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| K5L5628JT(B)M Document Title Multi-Chip Package MEMORY Preliminary Preliminary MCP MEMORY 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM Revision History Revision No. History 0.0 Initial Draft (256M NOR Flash A-die_rev0.3) (128M UtRAM M-die_rev0.1) Finalize Draft Date August 12, 2004 Remark Preliminary 1.0 November 10, 2004 Final Note : For more detailed features and specifications including FAQ, please refer to Samsung's web site. http://samsungelectronics.com/semiconductors/products/products_index.html The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you. 1 Revision 1.0 November 2004 K5L5628JT(B)M Multi-Chip Package MEMORY Preliminary Preliminary MCP MEMORY 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash / 128M Bit(8M x16) Synchronous Burst UtRAM FEATURES Internal TCSR * Supports Driver Strength Optimization for system environment power saving. * Supports Asynchronous 4-Page Read and Asynchronous Write Operation * Supports Synchronous Burst Read and Synchronous Burst Write Operation * Synchronous Burst(Read/Write) Operation - Supports 4 word / 8 word / 16 word and Full Page(256 word) burst - Supports Linear Burst type & Interleave Burst type - Latency support : Latency 3 @ 52.9MHz(tCD 12ns) - Supports Burst Read Suspend in No Clock toggling - Supports Burst Write Data Masking by /UB & /LB pin control - Supports WAIT pin function for indicating data availability. * Max. Burst Clock Frequency : 52.9MHz SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. 2 Revision 1.0 November 2004 K5L5628JT(B)M GENERAL DESCRIPTION Preliminary Preliminary MCP MEMORY The K5L5628JT(B)M is a Multi Chip Package Memory which combines 256Mbit Synchronous Burst Multi Bank NOR Flash Memory and 128Mbit Synchronous Burst UtRAM. 256Mbit Synchronous Burst Multi Bank NOR Flash Memory is organized as 16M x16 bits and 128Mbit Synchronous Burst UtRAM is organized as 8M x16 bits. In 256Mbit Synchronous Burst Multi Bank NOR Flash Memory, the memory architecture of the device is designed to divide its memory arrays into 519 blocks with independent hardware protection. This block architecture provides highly flexible erase and program capability. The NOR Flash consists of sixteen banks. This device is capable of reading data from one bank while programming or erasing in the other bank. Regarding read access time, the device provides an 14.5ns burst access time and an 88.5ns initial access time at 54MHz. At 66MHz, the device provides an 11ns burst access time and 70ns initial access time. The device performs a program operation in units of 16 bits (Word) and an erase operation in units of a block. Single or multiple blocks can be erased. The block erase operation is completed within typically 0.7 sec. The device requires 15mA as program/erase current. In 128Mbit Synchronous Burst UtRAM, the device is fabricated by SAMSUNGs advanced CMOS technology using one transistor memory cell. The device supports the traditional SRAM like asynchronous bus operation(asynchronous page read and asynchronous write), and the fully synchronous bus operation(synchronous burst read and synchronous burst write). These two bus operation modes are defined through the mode register setting. The device also supports the special features for the standby power saving. Those are the Partial Array Refresh(PAR) mode and internal Temperature Compensated Self Refresh(TCSR) mode. The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation. The K5L5628JT(B)M is suitable for use in data memory of mobile communication system to reduce not only mount area but also power consumption. This device is available in 115-ball FBGA Type. 3 Revision 1.0 November 2004 K5L5628JT(B)M PIN CONFIGURATION 1 2 3 4 5 6 7 8 9 10 Preliminary Preliminary MCP MEMORY A B C D E F G H J K L M N P DNU DNU DNU DNU DNU DNU DNU DNU ADVf NC CLKf NC Vccu ADVu CLKu NC DNU DNU WP A7 LB Vpp WE A8 A11 NC DNU DNU A3 A6 UB RESET MRS A19 A12 A15 DNU DNU A2 A5 A18 RDYf/ WAITu A20 A9 A13 A21 DNU DNU A1 A4 A17 NC NC A10 A14 A22 DNU DNU A0 Vss DQ1 Vccu NC DQ6 A23 A16 DNU DNU CEf OE DQ9 DQ3 DQ4 DQ13 DQ15 NC DNU DNU CSu DQ0 DQ10 Vccf Vccqu DQ12 DQ7 Vss DNU DNU NC DQ8 DQ2 DQ11 NC DQ5 DQ14 NC DNU DNU NC NC Vss Vccf NC NC NC NC DNU DNU DNU DNU DNU DNU DNU DNU DNU 115-FBGA: Top View (Ball Down) 4 Revision 1.0 November 2004 K5L5628JT(B)M PIN DESCRIPTION Ball Name A0 to A22 A23 DQ0 to DQ15 CEf CSu OE RESET VPP WE WP CLKf CLKu Description Address Input Balls (Common) Address Input Balls (Flash Memory) Data Input/Output Balls (Common) Chip Enable (Flash Memory) Chip Select (UtRAM) Output Enable (Common) Hardware Reset (Flash Memory) Accelerates Programming (Flash Memory) Write Enable (Common) Write Protection (Flash Memory) Clock (Flash Memory) Clock (UtRAM) Ball Name RDYf/WAITu ADVf ADVu MRS LB UB Vccf Vccu Vccqu Vss NC DNU Preliminary Preliminary MCP MEMORY Description Ready Output (Flash Memory)/Wait(UtRAM) Address Input Valid (Flash Memory) Address Input Valid (UtRAM) Mode Register Set (UtRAM) Lower Byte Enable (UtRAM) Upper Byte Enable (UtRAM) Power Supply (Flash Memory) Power Supply (UtRAM) Data Out Power (UtRAM) Ground (Common) No Connection Do Not Use ORDERING INFORMATION K 5 L 56 28 J T(B) M - D H 18 Samsung MCP Memory 2Chip MCP UtRAM Access Time 18.9ns Device Type Demuxed NOR Flash + Demuxed UtRAM Flash Access Time 14.5ns(CF 54MHz) NOR Flash Density 56 : 256Mbit, x16 Package D : FBGA(Lead Free) Version 1st Generation Block Architecture T = Top Boot Block B = Bottom Boot Block UtRAM Density, (Organization) 28 : 128Mbit, x16, Burst Operating Voltage J : 1.8V/1.8V(NOR), 2.6V/1.8V(UtRAM) 5 Revision 1.0 November 2004 K5L5628JT(B)M Figure 1. FUNCTIONAL BLOCK DIAGRAM Preliminary Preliminary MCP MEMORY Vccf Vss Address(A0 to A22) Address(A23) OE WE CEf RESET Vpp WP CLKf RDYf ADVf 256M bit Flash Memory DQ0 to DQ15 Vccu Vccqu Vss DQ0 to DQ15 CSu UB LB CLKu ADVu MRS WAITu 128M bit UtRAM DQ0 to DQ15 6 Revision 1.0 November 2004 K5L5628JT(B)M Preliminary Preliminary MCP MEMORY 256M Bit (16M x16) Synchronous Burst , Multi Bank NOR Flash A-die 7 Revision 1.0 November 2004 K5L5628JT(B)M Table 1. PRODUCT LINE-UP Synchronous/Burst Speed Option Max. Initial Access Time (tIAA, ns) VCC=1.7V-1.95V Max. Burst Access Time (tBA, ns) Max. OE Access Time (tOE, ns) 7B (54MHz) 88.5 14.5 20 7C (66MHz) 70 11 20 Preliminary Preliminary MCP MEMORY Asynchronous Speed Option Max Access Time (tAA, ns) Max CE Access Time (tCE, ns) Max OE Access Time (tOE, ns) 7B 7C (54MHz) (66MHz) 90 90 20 80 80 20 Table 2. DEVICE BANK DIVISIONS Bank 0 Mbit 16 Mbit Block Sizes Eight 4Kwords, Thirty-one 32Kwords Mbit 240 Mbit Bank 1 ~ Bank 15 Block Sizes Four hundred eighty 32Kwords 8 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Block BA518 BA517 BA516 BA515 BA514 BA513 BA512 BA511 BA510 BA509 BA508 BA507 BA506 BA505 BA504 BA503 BA502 BA501 BA500 Bank 0 BA499 BA498 BA497 BA496 BA495 BA494 BA493 BA492 BA491 BA490 BA489 BA488 BA487 BA486 BA485 BA484 BA483 BA482 BA481 BA480 BA479 BA478 Bank 1 BA477 BA476 BA475 Block Size 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range FFF000h-FFFFFFh FFE000h-FFEFFFh FFD000h-FFDFFFh FFC000h-FFCFFFh FFB000h-FFBFFFh FFA000h-FFAFFFh FF9000h-FF9FFFh FF8000h-FF8FFFh FF0000h-FF7FFFh FE8000h-FEFFFFh FE0000h-FE7FFFh FD8000h-FDFFFFh FD0000h-FD7FFFh FC8000h-FCFFFFh FC0000h-FC7FFFh FB8000h-FBFFFFh FB0000h-FB7FFFh FA8000h-FAFFFFh FA0000h-FA7FFFh F98000h-F9FFFFh F90000h-F97FFFh F88000h-F8FFFFh F80000h-F87FFFh F78000h-F7FFFFh F70000h-F77FFFh F68000h-F6FFFFh F60000h-F67FFFh F58000h-F5FFFFh F50000h-F57FFFh F48000h-F4FFFFh F40000h-F47FFFh F38000h-F3FFFFh F30000h-F37FFFh F28000h-F2FFFFh F20000h-F27FFFh F18000h-F1FFFFh F10000h-F17FFFh F08000h-F0FFFFh F00000h-F07FFFh EF8000h-EFFFFFh EF0000h-EF7FFFh EE8000h-EEFFFFh EE0000h-EE7FFFh ED8000h-EDFFFFh 9 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Block BA474 BA473 BA472 BA471 BA470 BA469 BA468 BA467 BA466 BA465 BA464 BA463 BA462 Bank 1 BA461 BA460 BA459 BA458 BA457 BA456 BA455 BA454 BA453 BA452 BA451 BA450 BA449 BA448 BA447 BA446 BA445 BA444 BA443 BA442 BA441 BA440 Bank 2 BA439 BA438 BA437 BA436 BA435 BA434 BA433 BA432 BA431 Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range ED0000h-ED7FFFh EC8000h-ECFFFFh EC0000h-EC7FFFh EB8000h-EBFFFFh EB0000h-EB7FFFh EA8000h-EAFFFFh EA0000h-EA7FFFh E98000h-E9FFFFh E90000h-E97FFFh E88000h-E8FFFFh E80000h-E87FFFh E78000h-E7FFFFh E70000h-E77FFFh E68000h-E6FFFFh E60000h-E67FFFh E58000h-E5FFFFh E50000h-E57FFFh E48000h-E4FFFFh E40000h-E47FFFh E38000h-E3FFFFh E30000h-E37FFFh E28000h-E2FFFFh E20000h-E27FFFh E18000h-E1FFFFh E10000h-E17FFFh E08000h-E0FFFFh E00000h-E07FFFh DF8000h-DFFFFFh DF0000h-DF7FFFh DE8000h-DEFFFFh DE0000h-DE7FFFh DD8000h-DDFFFFh DD0000h-DD7FFFh DC8000h-DCFFFFh DC0000h-DC7FFFh DB8000h-DBFFFFh DB0000h-DB7FFFh DA8000h-DAFFFFh DA0000h-DA7FFFh D98000h-D9FFFFh D90000h-D97FFFh D88000h-D8FFFFh D80000h-D87FFFh D78000h-D7FFFFh 10 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Block BA430 BA429 BA428 BA427 BA426 BA425 BA424 Bank 2 BA423 BA422 BA421 BA420 BA419 BA418 BA417 BA416 BA415 BA414 BA413 BA412 BA411 BA410 BA409 BA408 BA407 BA406 BA405 BA404 BA403 BA402 BA401 Bank 3 BA400 BA399 BA398 BA397 BA396 BA395 BA394 BA393 BA392 BA391 BA390 BA389 BA388 BA387 BA386 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range D70000h-D77FFFh D68000h-D6FFFFh D60000h-D67FFFh D58000h-D5FFFFh D50000h-D57FFFh D48000h-D4FFFFh D40000h-D47FFFh D38000h-D3FFFFh D30000h-D37FFFh D28000h-D2FFFFh D20000h-D27FFFh D18000h-D1FFFFh D10000h-D17FFFh D08000h-D0FFFFh D00000h-D07FFFh CF8000h-CFFFFFh CF0000h-CF7FFFh CE8000h-CEFFFFh CE0000h-CE7FFFh CD8000h-CDFFFFh CD0000h-CD7FFFh CC8000h-CCFFFFh CC0000h-CC7FFFh CB8000h-CBFFFFh CB0000h-CB7FFFh CA8000h-CAFFFFh CA0000h-CA7FFFh C98000h-C9FFFFh C90000h-C97FFFh C88000h-C8FFFFh C80000h-C87FFFh C78000h-C7FFFFh C70000h-C77FFFh C68000h-C6FFFFh C60000h-C67FFFh C58000h-C5FFFFh C50000h-C57FFFh C48000h-C4FFFFh C40000h-C47FFFh C38000h-C3FFFFh C30000h-C37FFFh C28000h-C2FFFFh C20000h-C27FFFh C18000h-C1FFFFh C10000h-C17FFFh 11 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Bank 3 BA384 BA383 BA382 BA381 BA380 BA379 BA378 BA377 BA376 BA375 BA374 BA373 BA372 BA371 BA370 BA369 BA368 Bank 4 BA367 BA366 BA365 BA364 BA363 BA362 BA361 BA360 BA359 BA358 BA357 BA356 BA355 BA354 BA353 BA352 BA351 BA350 BA349 BA348 BA347 Bank 5 BA346 BA345 BA344 BA343 BA342 BA341 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block BA385 Block Size 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range C08000h-C0FFFFh C00000h-C07FFFh BF8000h-BFFFFFh BF0000h-BF7FFFh BE8000h-BEFFFFh BE0000h-BE7FFFh BD8000h-BDFFFFh BD0000h-BD7FFFh BC8000h-BCFFFFh BC0000h-BC7FFFh BB8000h-BBFFFFh BB0000h-BB7FFFh BA8000h-BAFFFFh BA0000h-BA7FFFh B98000h-B9FFFFh B90000h-B97FFFh B88000h-B8FFFFh B80000h-B87FFFh B78000h-B7FFFFh B70000h-B77FFFh B68000h-B6FFFFh B60000h-B67FFFh B58000h-B5FFFFh B50000h-B57FFFh B48000h-B4FFFFh B40000h-B47FFFh B38000h-B3FFFFh B30000h-B37FFFh B28000h-B2FFFFh B20000h-B27FFFh B18000h-B1FFFFh B10000h-B17FFFh B08000h-B0FFFFh B00000h-B07FFFh AF8000h-AFFFFFh AF0000h-AF7FFFh AE8000h-AEFFFFh AE0000h-AE7FFFh AD8000h-ADFFFFh AD0000h-AD7FFFh AC8000h-ACFFFFh AC0000h-AC7FFFh AB8000h-ABFFFFh AB0000h-AB7FFFh AA8000h-AAFFFFh 12 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Block BA340 BA339 BA338 BA337 BA336 BA335 BA334 BA333 BA332 BA331 Bank 5 BA330 BA329 BA328 BA327 BA326 BA325 BA324 BA323 BA322 BA321 BA320 BA319 BA318 BA317 BA316 BA315 BA314 BA313 BA312 BA311 BA310 BA309 BA308 Bank 6 BA307 BA306 BA305 BA304 BA303 BA302 BA301 BA300 BA299 BA298 BA297 BA296 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range AA0000h-AA7FFFh A98000h-A9FFFFh A90000h-A97FFFh A88000h-A8FFFFh A80000h-A87FFFh A78000h-A7FFFFh A70000h-A77FFFh A68000h-A6FFFFh A60000h-A67FFFh A58000h-A5FFFFh A50000h-A57FFFh A48000h-A4FFFFh A40000h-A47FFFh A38000h-A3FFFFh A30000h-A37FFFh A28000h-A2FFFFh A20000h-A27FFFh A18000h-A1FFFFh A10000h-A17FFFh A08000h-A0FFFFh A00000h-A07FFFh 9F8000h-9FFFFFh 9F0000h-9F7FFFh 9E8000h-9EFFFFh 9E0000h-9E7FFFh 9D8000h-9DFFFFh 9D0000h-9D7FFFh 9C8000h-9CFFFFh 9C0000h-9C7FFFh 9B8000h-9BFFFFh 9B0000h-9B7FFFh 9A8000h-9AFFFFh 9A0000h-9A7FFFh 998000h-99FFFFh 990000h-997FFFh 988000h-98FFFFh 980000h-987FFFh 978000h-97FFFFh 970000h-977FFFh 968000h-96FFFFh 960000h-967FFFh 958000h-95FFFFh 950000h-957FFFh 948000h-94FFFFh 940000h-947FFFh 13 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Block BA295 BA294 BA293 BA292 Bank 6 BA291 BA290 BA289 BA288 BA287 BA286 BA285 BA284 BA283 BA282 BA281 BA280 BA279 BA278 BA277 BA276 BA275 BA274 BA273 Bank 7 BA272 BA271 BA270 BA269 BA268 BA267 BA266 BA265 BA264 BA263 BA262 BA261 BA260 BA259 BA258 BA257 BA256 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 938000h-93FFFFh 930000h-937FFFh 928000h-92FFFFh 920000h-927FFFh 918000h-91FFFFh 910000h-917FFFh 908000h-90FFFFh 900000h-907FFFh 8F8000h-8FFFFFh 8F0000h-8F7FFFh 8E8000h-8EFFFFh 8E0000h-8E7FFFh 8D8000h-8DFFFFh 8D0000h-8D7FFFh 8C8000h-8CFFFFh 8C0000h-8C7FFFh 8B8000h-8BFFFFh 8B0000h-8B7FFFh 8A8000h-8AFFFFh 8A0000h-8A7FFFh 898000h-89FFFFh 890000h-897FFFh 888000h-88FFFFh 880000h-887FFFh 878000h-87FFFFh 870000h-877FFFh 868000h-86FFFFh 860000h-867FFFh 858000h-85FFFFh 850000h-857FFFh 848000h-84FFFFh 840000h-847FFFh 838000h-83FFFFh 830000h-837FFFh 828000h-82FFFFh 820000h-827FFFh 818000h-81FFFFh 810000h-817FFFh 808000h-80FFFFh 800000h-807FFFh 14 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Boot Block Address Table Bank Block BA255 BA254 BA253 BA252 BA251 BA250 BA249 BA248 BA247 BA246 BA245 BA244 BA243 BA242 BA241 Bank 8 BA240 BA239 BA238 BA237 BA236 BA235 BA234 BA233 BA232 BA231 BA230 BA229 BA228 BA227 BA226 BA225 BA224 BA223 BA222 BA221 BA220 BA219 BA218 Bank 9 BA217 BA216 BA215 BA214 BA213 BA212 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 7F8000h-7FFFFFh 7F0000h-7F7FFFh 7E8000h-7EFFFFh 7E0000h-7E7FFFh 7D8000h-7DFFFFh 7D0000h-7D7FFFh 7C8000h-7CFFFFh 7C0000h-7C7FFFh 7B8000h-7BFFFFh 7B0000h-7B7FFFh 7A8000h-7AFFFFh 7A0000h-7A7FFFh 798000h-79FFFFh 790000h-797FFFh 788000h-78FFFFh 780000h-787FFFh 778000h-77FFFFh 770000h-777FFFh 768000h-76FFFFh 760000h-767FFFh 758000h-75FFFFh 750000h-757FFFh 748000h-74FFFFh 740000h-747FFFh 738000h-73FFFFh 730000h-737FFFh 728000h-72FFFFh 720000h-727FFFh 718000h-71FFFFh 710000h-717FFFh 708000h-70FFFFh 700000h-707FFFh 6F8000h-6FFFFFh 6F0000h-6F7FFFh 6E8000h-6EFFFFh 6E0000h-6E7FFFh 6D8000h-6DFFFFh 6D0000h-6D7FFFh 6C8000h-6CFFFFh 6C0000h-6C7FFFh 6B8000h-6BFFFFh 6B0000h-6B7FFFh 6A8000h-6AFFFFh 6A0000h-6A7FFFh 15 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Block BA211 BA210 BA209 BA208 BA207 BA206 BA205 BA204 BA203 BA202 Bank 9 BA201 BA200 BA199 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 BA190 BA189 BA188 BA187 BA186 BA185 BA184 BA183 BA182 BA181 BA180 Bank 10 BA179 BA178 BA177 BA176 BA175 BA174 BA173 BA172 BA171 BA170 BA169 BA168 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 698000h-69FFFFh 690000h-697FFFh 688000h-68FFFFh 680000h-687FFFh 678000h-67FFFFh 670000h-677FFFh 668000h-66FFFFh 660000h-667FFFh 658000h-65FFFFh 650000h-657FFFh 648000h-64FFFFh 640000h-647FFFh 638000h-63FFFFh 630000h-637FFFh 628000h-62FFFFh 620000h-627FFFh 618000h-61FFFFh 610000h-617FFFh 608000h-60FFFFh 600000h-607FFFh 5F8000h-5FFFFFh 5F0000h-5F7FFFh 5E8000h-5EFFFFh 5E0000h-5E7FFFh 5D8000h-5DFFFFh 5D0000h-5D7FFFh 5C8000h-5CFFFFh 5C0000h-5C7FFFh 5B8000h-5BFFFFh 5B0000h-5B7FFFh 5A8000h-5AFFFFh 5A0000h-5A7FFFh 598000h-59FFFFh 590000h-597FFFh 588000h-58FFFFh 580000h-587FFFh 578000h-57FFFFh 570000h-577FFFh 568000h-56FFFFh 560000h-567FFFh 558000h-55FFFFh 550000h-557FFFh 548000h-54FFFFh 540000h-547FFFh 16 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Block BA167 BA166 BA165 BA164 Bank 10 BA163 BA162 BA161 BA160 BA159 BA158 BA157 BA156 BA155 BA154 BA153 BA152 BA151 BA150 BA149 BA148 BA147 BA146 BA145 BA144 Bank 11 BA143 BA142 BA141 BA140 BA139 BA138 BA137 BA136 BA135 BA134 BA133 BA132 BA131 BA130 BA129 BA128 BA127 BA126 Bank 12 BA125 BA124 BA123 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 538000h-53FFFFh 530000h-537FFFh 528000h-52FFFFh 520000h-527FFFh 518000h-51FFFFh 510000h-517FFFh 508000h-50FFFFh 500000h-507FFFh 4F8000h-4FFFFFh 4F0000h-4F7FFFh 4E8000h-4EFFFFh 4E0000h-4E7FFFh 4D8000h-4DFFFFh 4D0000h-4D7FFFh 4C8000h-4CFFFFh 4C0000h-4C7FFFh 4B8000h-4BFFFFh 4B0000h-4B7FFFh 4A8000h-4AFFFFh 4A0000h-4A7FFFh 498000h-49FFFFh 490000h-497FFFh 488000h-48FFFFh 480000h-487FFFh 478000h-47FFFFh 470000h-477FFFh 468000h-46FFFFh 460000h-467FFFh 458000h-45FFFFh 450000h-457FFFh 448000h-44FFFFh 440000h-447FFFh 438000h-43FFFFh 430000h-437FFFh 428000h-42FFFFh 420000h-427FFFh 418000h-41FFFFh 410000h-417FFFh 408000h-40FFFFh 400000h-407FFFh 3F8000h-3FFFFFh 3F0000h-3F7FFFh 3E8000h-3EFFFFh 3E0000h-3E7FFFh 3D8000h-3DFFFFh 17 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Block BA122 BA121 BA120 BA119 BA118 BA117 BA116 BA115 BA114 BA113 BA112 BA111 BA110 Bank 12 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 BA93 BA92 BA91 BA90 BA89 BA88 BA87 Bank 13 BA86 BA85 BA84 BA83 BA82 BA81 BA80 BA79 BA78 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 3D0000h-3D7FFFh 3C8000h-3CFFFFh 3C0000h-3C7FFFh 3B8000h-3BFFFFh 3B0000h-3B7FFFh 3A8000h-3AFFFFh 3A0000h-3A7FFFh 398000h-39FFFFh 390000h-397FFFh 388000h-38FFFFh 380000h-387FFFh 378000h-37FFFFh 370000h-377FFFh 368000h-36FFFFh 360000h-367FFFh 358000h-35FFFFh 350000h-357FFFh 348000h-34FFFFh 340000h-347FFFh 338000h-33FFFFh 330000h-337FFFh 328000h-32FFFFh 320000h-327FFFh 318000h-31FFFFh 310000h-317FFFh 308000h-30FFFFh 300000h-307FFFh 2F8000h-2FFFFFh 2F0000h-2F7FFFh 2E8000h-2EFFFFh 2E0000h-2E7FFFh 2D8000h-2DFFFFh 2D0000h-2D7FFFh 2C8000h-2CFFFFh 2C0000h-2C7FFFh 2B8000h-2BFFFFh 2B0000h-2B7FFFh 2A8000h-2AFFFFh 2A0000h-2A7FFFh 298000h-29FFFFh 290000h-297FFFh 288000h-28FFFFh 280000h-287FFFh 278000h-27FFFFh 270000h-277FFFh 18 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Block BA77 BA76 BA75 BA74 BA73 BA72 BA71 Bank 13 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 BA54 BA53 BA52 BA51 BA50 BA49 BA48 Bank 14 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 BA38 BA37 BA36 BA35 BA34 BA33 BA32 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 268000h-26FFFFh 260000h-267FFFh 258000h-25FFFFh 250000h-257FFFh 248000h-24FFFFh 240000h-247FFFh 238000h-23FFFFh 230000h-237FFFh 228000h-22FFFFh 220000h-227FFFh 218000h-21FFFFh 210000h-217FFFh 208000h-20FFFFh 200000h-207FFFh 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 19 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Top Boot Block Address Table Bank Block BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 Bank 15 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 000000h-007FFFh Table 3-1-1. Top Boot Block OTP Addresses Table Block Address A23 ~ A8 Block Size 128words (x16) Address Range FFFF80h-FFFFFFh OTP FFFFh After entering OTP block, any issued addresses should be in the range of OTP block address 20 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Block BA518 BA517 BA516 BA515 BA514 BA513 BA512 BA511 BA510 BA509 BA508 BA507 BA506 BA505 BA504 Bank 15 BA503 BA502 BA501 BA500 BA499 BA498 BA497 BA496 BA495 BA494 BA493 BA492 BA491 BA490 BA489 BA488 BA487 BA486 BA485 Bank 14 BA484 BA483 BA482 Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range FF8000h-FFFFFFh FF0000h-FF7FFFh FE8000h-FEFFFFh FE0000h-FE7FFFh FD8000h-FDFFFFh FD0000h-FD7FFFh FC8000h-FCFFFFh FC0000h-FC7FFFh FB8000h-FBFFFFh FB0000h-FB7FFFh FA8000h-FAFFFFh FA0000h-FA7FFFh F98000h-F9FFFFh F90000h-F97FFFh F88000h-F8FFFFh F80000h-F87FFFh F78000h-F7FFFFh F70000h-F77FFFh F68000h-F6FFFFh F60000h-F67FFFh F58000h-F5FFFFh F50000h-F57FFFh F48000h-F4FFFFh F40000h-F47FFFh F38000h-F3FFFFh F30000h-F37FFFh F28000h-F2FFFFh F20000h-F27FFFh F18000h-F1FFFFh F10000h-F17FFFh F08000h-F0FFFFh F00000h-F07FFFh EF8000h-EFFFFFh EF0000h-EF7FFFh EE8000h-EEFFFFh EE0000h-EE7FFFh ED8000h-EDFFFFh 21 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Block BA481 BA480 BA479 BA478 BA477 BA476 BA475 BA474 BA473 BA472 BA471 BA470 BA469 Bank 14 BA468 BA467 BA466 BA465 BA464 BA463 BA462 BA461 BA460 BA459 BA458 BA457 BA456 BA455 BA454 BA453 BA452 BA451 BA450 BA449 BA448 BA447 Bank 13 BA446 BA445 BA444 BA443 BA442 BA441 BA440 BA439 BA438 Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range ED0000h-ED7FFFh EC8000h-ECFFFFh EC0000h-EC7FFFh EB8000h-EBFFFFh EB0000h-EB7FFFh EA8000h-EAFFFFh EA0000h-EA7FFFh E98000h-E9FFFFh E90000h-E97FFFh E88000h-E8FFFFh E80000h-E87FFFh E78000h-E7FFFFh E70000h-E77FFFh E68000h-E6FFFFh E60000h-E67FFFh E58000h-E5FFFFh E50000h-E57FFFh E48000h-E4FFFFh E40000h-E47FFFh E38000h-E3FFFFh E30000h-E37FFFh E28000h-E2FFFFh E20000h-E27FFFh E18000h-E1FFFFh E10000h-E17FFFh E08000h-E0FFFFh E00000h-E07FFFh DF8000h-DFFFFFh DF0000h-DF7FFFh DE8000h-DEFFFFh DE0000h-DE7FFFh DD8000h-DDFFFFh DD0000h-DD7FFFh DC8000h-DCFFFFh DC0000h-DC7FFFh DB8000h-DBFFFFh DB0000h-DB7FFFh DA8000h-DAFFFFh DA0000h-DA7FFFh D98000h-D9FFFFh D90000h-D97FFFh D88000h-D8FFFFh D80000h-D87FFFh D78000h-D7FFFFh 22 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Block BA437 BA436 BA435 BA434 BA433 BA432 BA431 Bank 13 BA430 BA429 BA428 BA427 BA426 BA425 BA424 BA423 BA422 BA421 BA420 BA419 BA418 BA417 BA416 BA415 BA414 BA413 BA412 BA411 BA410 BA409 BA408 Bank 12 BA407 BA406 BA405 BA404 BA403 BA402 BA401 BA400 BA399 BA398 BA397 BA396 BA395 BA394 BA393 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range D70000h-D77FFFh D68000h-D6FFFFh D60000h-D67FFFh D58000h-D5FFFFh D50000h-D57FFFh D48000h-D4FFFFh D40000h-D47FFFh D38000h-D3FFFFh D30000h-D37FFFh D28000h-D2FFFFh D20000h-D27FFFh D18000h-D1FFFFh D10000h-D17FFFh D08000h-D0FFFFh D00000h-D07FFFh CF8000h-CFFFFFh CF0000h-CF7FFFh CE8000h-CEFFFFh CE0000h-CE7FFFh CD8000h-CDFFFFh CD0000h-CD7FFFh CC8000h-CCFFFFh CC0000h-CC7FFFh CB8000h-CBFFFFh CB0000h-CB7FFFh CA8000h-CAFFFFh CA0000h-CA7FFFh C98000h-C9FFFFh C90000h-C97FFFh C88000h-C8FFFFh C80000h-C87FFFh C78000h-C7FFFFh C70000h-C77FFFh C68000h-C6FFFFh C60000h-C67FFFh C58000h-C5FFFFh C50000h-C57FFFh C48000h-C4FFFFh C40000h-C47FFFh C38000h-C3FFFFh C30000h-C37FFFh C28000h-C2FFFFh C20000h-C27FFFh C18000h-C1FFFFh C10000h-C17FFFh 23 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Bank 12 BA391 BA390 BA389 BA388 BA387 BA386 BA385 BA384 BA383 BA382 BA381 BA380 BA379 BA378 BA377 BA376 BA375 Bank 11 BA374 BA373 BA372 BA371 BA370 BA369 BA368 BA367 BA366 BA365 BA364 BA363 BA362 BA361 BA360 BA359 BA358 BA357 BA356 BA355 BA354 Bank 10 BA353 BA352 BA351 BA350 BA349 BA348 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block BA392 Block Size 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range C08000h-C0FFFFh C00000h-C07FFFh BF8000h-BFFFFFh BF0000h-BF7FFFh BE8000h-BEFFFFh BE0000h-BE7FFFh BD8000h-BDFFFFh BD0000h-BD7FFFh BC8000h-BCFFFFh BC0000h-BC7FFFh BB8000h-BBFFFFh BB0000h-BB7FFFh BA8000h-BAFFFFh BA0000h-BA7FFFh B98000h-B9FFFFh B90000h-B97FFFh B88000h-B8FFFFh B80000h-B87FFFh B78000h-B7FFFFh B70000h-B77FFFh B68000h-B6FFFFh B60000h-B67FFFh B58000h-B5FFFFh B50000h-B57FFFh B48000h-B4FFFFh B40000h-B47FFFh B38000h-B3FFFFh B30000h-B37FFFh B28000h-B2FFFFh B20000h-B27FFFh B18000h-B1FFFFh B10000h-B17FFFh B08000h-B0FFFFh B00000h-B07FFFh AF8000h-AFFFFFh AF0000h-AF7FFFh AE8000h-AEFFFFh AE0000h-AE7FFFh AD8000h-ADFFFFh AD0000h-AD7FFFh AC8000h-ACFFFFh AC0000h-AC7FFFh AB8000h-ABFFFFh AB0000h-AB7FFFh AA8000h-AAFFFFh 24 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Block BA347 BA346 BA345 BA344 BA343 BA342 BA341 BA340 BA339 BA338 Bank 10 BA337 BA336 BA335 BA334 BA333 BA332 BA331 BA330 BA329 BA328 BA327 BA326 BA325 BA324 BA323 BA322 BA321 BA320 BA319 BA318 BA317 BA316 BA315 Bank 9 BA314 BA313 BA312 BA311 BA310 BA309 BA308 BA307 BA306 BA305 BA304 BA303 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range AA0000h-AA7FFFh A98000h-A9FFFFh A90000h-A97FFFh A88000h-A8FFFFh A80000h-A87FFFh A78000h-A7FFFFh A70000h-A77FFFh A68000h-A6FFFFh A60000h-A67FFFh A58000h-A5FFFFh A50000h-A57FFFh A48000h-A4FFFFh A40000h-A47FFFh A38000h-A3FFFFh A30000h-A37FFFh A28000h-A2FFFFh A20000h-A27FFFh A18000h-A1FFFFh A10000h-A17FFFh A08000h-A0FFFFh A00000h-A07FFFh 9F8000h-9FFFFFh 9F0000h-9F7FFFh 9E8000h-9EFFFFh 9E0000h-9E7FFFh 9D8000h-9DFFFFh 9D0000h-9D7FFFh 9C8000h-9CFFFFh 9C0000h-9C7FFFh 9B8000h-9BFFFFh 9B0000h-9B7FFFh 9A8000h-9AFFFFh 9A0000h-9A7FFFh 998000h-99FFFFh 990000h-997FFFh 988000h-98FFFFh 980000h-987FFFh 978000h-97FFFFh 970000h-977FFFh 968000h-96FFFFh 960000h-967FFFh 958000h-95FFFFh 950000h-957FFFh 948000h-94FFFFh 940000h-947FFFh 25 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Block BA302 BA301 BA300 BA299 Bank 9 BA298 BA297 BA296 BA295 BA294 BA293 BA292 BA291 BA290 BA289 BA288 BA287 BA286 BA285 BA284 BA283 BA282 BA281 BA280 Bank 8 BA279 BA278 BA277 BA276 BA275 BA274 BA273 BA272 BA271 BA270 BA269 BA268 BA267 BA266 BA265 BA264 BA263 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 938000h-93FFFFh 930000h-937FFFh 928000h-92FFFFh 920000h-927FFFh 918000h-91FFFFh 910000h-917FFFh 908000h-90FFFFh 900000h-907FFFh 8F8000h-8FFFFFh 8F0000h-8F7FFFh 8E8000h-8EFFFFh 8E0000h-8E7FFFh 8D8000h-8DFFFFh 8D0000h-8D7FFFh 8C8000h-8CFFFFh 8C0000h-8C7FFFh 8B8000h-8BFFFFh 8B0000h-8B7FFFh 8A8000h-8AFFFFh 8A0000h-8A7FFFh 898000h-89FFFFh 890000h-897FFFh 888000h-88FFFFh 880000h-887FFFh 878000h-87FFFFh 870000h-877FFFh 868000h-86FFFFh 860000h-867FFFh 858000h-85FFFFh 850000h-857FFFh 848000h-84FFFFh 840000h-847FFFh 838000h-83FFFFh 830000h-837FFFh 828000h-82FFFFh 820000h-827FFFh 818000h-81FFFFh 810000h-817FFFh 808000h-80FFFFh 800000h-807FFFh 26 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Boot Block Address Table Bank Block BA262 BA261 BA260 BA259 BA258 BA257 BA256 BA255 BA254 BA253 BA252 BA251 BA250 BA249 BA248 Bank 7 BA247 BA246 BA245 BA244 BA243 BA242 BA241 BA240 BA239 BA238 BA237 BA236 BA235 BA234 BA233 BA232 BA231 BA230 BA229 BA228 BA227 BA226 BA225 Bank 6 BA224 BA223 BA222 BA221 BA220 BA219 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 7F8000h-7FFFFFh 7F0000h-7F7FFFh 7E8000h-7EFFFFh 7E0000h-7E7FFFh 7D8000h-7DFFFFh 7D0000h-7D7FFFh 7C8000h-7CFFFFh 7C0000h-7C7FFFh 7B8000h-7BFFFFh 7B0000h-7B7FFFh 7A8000h-7AFFFFh 7A0000h-7A7FFFh 798000h-79FFFFh 790000h-797FFFh 788000h-78FFFFh 780000h-787FFFh 778000h-77FFFFh 770000h-777FFFh 768000h-76FFFFh 760000h-767FFFh 758000h-75FFFFh 750000h-757FFFh 748000h-74FFFFh 740000h-747FFFh 738000h-73FFFFh 730000h-737FFFh 728000h-72FFFFh 720000h-727FFFh 718000h-71FFFFh 710000h-717FFFh 708000h-70FFFFh 700000h-707FFFh 6F8000h-6FFFFFh 6F0000h-6F7FFFh 6E8000h-6EFFFFh 6E0000h-6E7FFFh 6D8000h-6DFFFFh 6D0000h-6D7FFFh 6C8000h-6CFFFFh 6C0000h-6C7FFFh 6B8000h-6BFFFFh 6B0000h-6B7FFFh 6A8000h-6AFFFFh 6A0000h-6A7FFFh 27 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Block BA218 BA217 BA216 BA215 BA214 BA213 BA212 BA211 BA210 BA209 Bank 6 BA208 BA207 BA206 BA205 BA204 BA203 BA202 BA201 BA200 BA199 BA198 BA197 BA196 BA195 BA194 BA193 BA192 BA191 BA190 BA189 BA188 BA187 Bank 5 BA186 BA185 BA184 BA183 BA182 BA181 BA180 BA179 BA178 BA177 BA176 BA175 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 698000h-69FFFFh 690000h-697FFFh 688000h-68FFFFh 680000h-687FFFh 678000h-67FFFFh 670000h-677FFFh 668000h-66FFFFh 660000h-667FFFh 658000h-65FFFFh 650000h-657FFFh 648000h-64FFFFh 640000h-647FFFh 638000h-63FFFFh 630000h-637FFFh 628000h-62FFFFh 620000h-627FFFh 618000h-61FFFFh 610000h-617FFFh 608000h-60FFFFh 600000h-607FFFh 5F8000h-5FFFFFh 5F0000h-5F7FFFh 5E8000h-5EFFFFh 5E0000h-5E7FFFh 5D8000h-5DFFFFh 5D0000h-5D7FFFh 5C8000h-5CFFFFh 5C0000h-5C7FFFh 5B8000h-5BFFFFh 5B0000h-5B7FFFh 5A8000h-5AFFFFh 5A0000h-5A7FFFh 598000h-59FFFFh 590000h-597FFFh 588000h-58FFFFh 580000h-587FFFh 578000h-57FFFFh 570000h-577FFFh 568000h-56FFFFh 560000h-567FFFh 558000h-55FFFFh 550000h-557FFFh 548000h-54FFFFh 540000h-547FFFh 28 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Block BA174 BA173 BA172 BA171 Bank 5 BA170 BA169 BA168 BA167 BA166 BA165 BA164 BA163 BA162 BA161 BA160 BA159 BA158 BA157 BA156 BA155 BA154 BA153 BA152 BA151 Bank 4 BA150 BA149 BA148 BA147 BA146 BA145 BA144 BA143 BA142 BA141 BA140 BA139 BA138 BA137 BA136 BA135 BA134 BA133 Bank 3 BA132 BA131 BA130 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 538000h-53FFFFh 530000h-537FFFh 528000h-52FFFFh 520000h-527FFFh 518000h-51FFFFh 510000h-517FFFh 508000h-50FFFFh 500000h-507FFFh 4F8000h-4FFFFFh 4F0000h-4F7FFFh 4E8000h-4EFFFFh 4E0000h-4E7FFFh 4D8000h-4DFFFFh 4D0000h-4D7FFFh 4C8000h-4CFFFFh 4C0000h-4C7FFFh 4B8000h-4BFFFFh 4B0000h-4B7FFFh 4A8000h-4AFFFFh 4A0000h-4A7FFFh 498000h-49FFFFh 490000h-497FFFh 488000h-48FFFFh 480000h-487FFFh 478000h-47FFFFh 470000h-477FFFh 468000h-46FFFFh 460000h-467FFFh 458000h-45FFFFh 450000h-457FFFh 448000h-44FFFFh 440000h-447FFFh 438000h-43FFFFh 430000h-437FFFh 428000h-42FFFFh 420000h-427FFFh 418000h-41FFFFh 410000h-417FFFh 408000h-40FFFFh 400000h-407FFFh 3F8000h-3FFFFFh 3F0000h-3F7FFFh 3E8000h-3EFFFFh 3E0000h-3E7FFFh 3D8000h-3DFFFFh 29 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Block BA129 BA128 BA127 BA126 BA125 BA124 BA123 BA122 BA121 BA120 BA119 BA118 BA117 Bank 3 BA116 BA115 BA114 BA113 BA112 BA111 BA110 BA109 BA108 BA107 BA106 BA105 BA104 BA103 BA102 BA101 BA100 BA99 BA98 BA97 BA96 BA95 BA94 Bank 2 BA93 BA92 BA91 BA90 BA89 BA88 BA87 BA86 BA85 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 3D0000h-3D7FFFh 3C8000h-3CFFFFh 3C0000h-3C7FFFh 3B8000h-3BFFFFh 3B0000h-3B7FFFh 3A8000h-3AFFFFh 3A0000h-3A7FFFh 398000h-39FFFFh 390000h-397FFFh 388000h-38FFFFh 380000h-387FFFh 378000h-37FFFFh 370000h-377FFFh 368000h-36FFFFh 360000h-367FFFh 358000h-35FFFFh 350000h-357FFFh 348000h-34FFFFh 340000h-347FFFh 338000h-33FFFFh 330000h-337FFFh 328000h-32FFFFh 320000h-327FFFh 318000h-31FFFFh 310000h-317FFFh 308000h-30FFFFh 300000h-307FFFh 2F8000h-2FFFFFh 2F0000h-2F7FFFh 2E8000h-2EFFFFh 2E0000h-2E7FFFh 2D8000h-2DFFFFh 2D0000h-2D7FFFh 2C8000h-2CFFFFh 2C0000h-2C7FFFh 2B8000h-2BFFFFh 2B0000h-2B7FFFh 2A8000h-2AFFFFh 2A0000h-2A7FFFh 298000h-29FFFFh 290000h-297FFFh 288000h-28FFFFh 280000h-287FFFh 278000h-27FFFFh 270000h-277FFFh 30 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Block BA84 BA83 BA82 BA81 BA80 BA79 BA78 Bank 2 BA77 BA76 BA75 BA74 BA73 BA72 BA71 BA70 BA69 BA68 BA67 BA66 BA65 BA64 BA63 BA62 BA61 BA60 BA59 BA58 BA57 BA56 BA55 Bank 1 BA54 BA53 BA52 BA51 BA50 BA49 BA48 BA47 BA46 BA45 BA44 BA43 BA42 BA41 BA40 BA39 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 268000h-26FFFFh 260000h-267FFFh 258000h-25FFFFh 250000h-257FFFh 248000h-24FFFFh 240000h-247FFFh 238000h-23FFFFh 230000h-237FFFh 228000h-22FFFFh 220000h-227FFFh 218000h-21FFFFh 210000h-217FFFh 208000h-20FFFFh 200000h-207FFFh 1F8000h-1FFFFFh 1F0000h-1F7FFFh 1E8000h-1EFFFFh 1E0000h-1E7FFFh 1D8000h-1DFFFFh 1D0000h-1D7FFFh 1C8000h-1CFFFFh 1C0000h-1C7FFFh 1B8000h-1BFFFFh 1B0000h-1B7FFFh 1A8000h-1AFFFFh 1A0000h-1A7FFFh 198000h-19FFFFh 190000h-197FFFh 188000h-18FFFFh 180000h-187FFFh 178000h-17FFFFh 170000h-177FFFh 168000h-16FFFFh 160000h-167FFFh 158000h-15FFFFh 150000h-157FFFh 148000h-14FFFFh 140000h-147FFFh 138000h-13FFFFh 130000h-137FFFh 128000h-12FFFFh 120000h-127FFFh 118000h-11FFFFh 110000h-117FFFh 108000h-10FFFFh 100000h-107FFFh 31 Revision 1.0 November 2004 K5L5628JT(B)M Table 3-1. Bottom Boot Block Address Table Bank Block BA38 BA37 BA36 BA35 BA34 BA33 BA32 BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 Bank 0 BA19 BA18 BA17 BA16 BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8 BA7 BA6 BA5 BA4 BA3 BA2 BA1 BA0 Block Size 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 32 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords 4 Kwords Preliminary Preliminary MCP MEMORY (x16) Address Range 0F8000h-0FFFFFh 0F0000h-0F7FFFh 0E8000h-0EFFFFh 0E0000h-0E7FFFh 0D8000h-0DFFFFh 0D0000h-0D7FFFh 0C8000h-0CFFFFh 0C0000h-0C7FFFh 0B8000h-0BFFFFh 0B0000h-0B7FFFh 0A8000h-0AFFFFh 0A0000h-0A7FFFh 098000h-09FFFFh 090000h-097FFFh 088000h-08FFFFh 080000h-087FFFh 078000h-07FFFFh 070000h-077FFFh 068000h-06FFFFh 060000h-067FFFh 058000h-05FFFFh 050000h-057FFFh 048000h-04FFFFh 040000h-047FFFh 038000h-03FFFFh 030000h-037FFFh 028000h-02FFFFh 020000h-027FFFh 018000h-01FFFFh 010000h-017FFFh 008000h-00FFFFh 007000h-007FFFh 006000h-006FFFh 005000h-005FFFh 004000h-004FFFh 003000h-003FFFh 002000h-002FFFh 001000h-001FFFh 000000h-000FFFh Table 3-1-2. Bottom Boot Block OTP Block Addresses Block Address A23 ~ A8 Block Size 128words (x16) Address Range 000000h-00007Fh OTP 0000h After entering OTP block, any issued addresses should be in the range of OTP block address 32 Revision 1.0 November 2004 K5L5628JT(B)M PRODUCT INTRODUCTION Preliminary Preliminary MCP MEMORY The device is a 256Mbit (268,435,456 bits) NOR-type Burst Flash memory. The device features 1.8V single voltage power supply operating within the range of 1.7V to 1.95V. The device is programmed by using the Channel Hot Electron (CHE) injection mechanism which is used to program EPROMs. The device is erased electrically by using Fowler-Nordheim tunneling mechanism. To provide highly flexible erase and program capability, the device adopts a block memory architecture that divides its memory array into 519 blocks (32-Kword x 511 , 4-Kword x 8, ). Programming is done in units of 16 bits (Word). All bits of data in one or multiple blocks can be erased when the device executes the erase operation. To prevent the device from accidental erasing or over-writing the programmed data, 519 memory blocks can be hardware protected. Regarding read access time, at 54MHz, the device provides a burst access of 14.5ns with initial access times of 88.5ns at 30pF. At 66MHz, the device provides a burst access of 11ns with initial access times of 70ns at 30pF. The command set of device is compatible with standard Flash devices. The device uses Chip Enable (CE), Write Enable (WE), Address Valid(AVD) and Output Enable (OE) to control asynchronous read and write operation. For burst operations, the device additionally requires Ready (RDY) and Clock (CLK). Device operations are executed by selective command codes. The command codes to be combined with addresses and data are sequentially written to the command registers using microprocessor write timing. The command codes serve as inputs to an internal state machine which controls the program/erase circuitry. Register contents also internally latch addresses and data necessary to execute the program and erase operations. The device is implemented with Internal Program/Erase Routines to execute the program/erase operations. The Internal Program/Erase Routines are invoked by program/erase command sequences. The Internal Program Routine automatically programs and verifies data at specified addresses. The Internal Erase Routine automatically pre-programs the memory cell which is not programmed and then executes the erase operation. The device has means to indicate the status of completion of program/erase operations. The status can be indicated via Data polling of DQ7, or the Toggle bit (DQ6). Once the operations have been completed, the device automatically resets itself to the read mode. The device requires only 30mA as burst and asynchronous mode read current and 15 mA for program/erase operations. Table 4. Device Bus Operations Operation Asynchronous Read Operation CE L OE L WE H A0-22 Add In DQ0-15 I/O RESET H CLK L AVD L Write L H Add In I/O H L X Standby H X X X High-Z H X X Hardware Reset X X X X High-Z L X X Load Initial Burst Address L H H Add In X Burst DOUT High-Z H Burst Read Operation Terminate Burst Read Cycle L L H X H H H X X X H X X Terminate Burst Read Cycle via RESET X X X X High-Z L X X Terminate Current Burst Read Cycle and Start New Burst Read Cycle Note : L=VIL (Low), H=VIH (High), X=Don't Care. L H H Add In I/O H 33 Revision 1.0 November 2004 K5L5628JT(B)M COMMAND DEFINITIONS Preliminary Preliminary MCP MEMORY The device operates by selecting and executing its operational modes. Each operational mode has its own command set. In order to select a certain mode, a proper command with specific address and data sequences must be written into the command register. Writing incorrect information which include address and data or writing an improper command will reset the device to the read mode. The defined valid register command sequences are stated in Table 5. Table 5. Command Sequences Command Definitions Add Asynchronous Read Data Add Reset(Note 5) Data Autoselect Manufacturer ID(Note 6) Autoselect Device ID(Note 6) Autoselect Block Protection Verify(Note 7) Autoselect Handshaking(Note 6, 8) Program Data Add Unlock Bypass Data Add Unlock Bypass Program(Note 9) Data Add Unlock Bypass Block Erase(Note 9) Data Add Unlock Bypass Chip Erase(Note 9) Data Add Unlock Bypass Reset Data Add Quadruple word Accelerated Program(Note 10) Data Add Chip Erase Data Add Block Erase Data Add Erase Suspend (Note 11) Data Add Erase Resume (Note 12) Data Add Program Suspend (Note13) Data Add Program Resume (Note12) Data 1 30H 1 B0H (DA)XXXH 1 30H (DA)XXXH 1 B0H (DA)XXXH 6 AAH (DA)XXXH 55H 80H AAH 55H 30H 6 AAH 555H 55H 2AAH 80H 555H AAH 555H 55H 2AAH 10H BA 5 A5H 555H PD1 2AAH PD2 555H PD3 555H PD4 2AAH 555H 2 90H XXX 00H PA1 PA2 PA3 PA4 2 80H XXXH 10H XXXH 2 80H XXXH 30H XXXH 2 A0H XXX PD BA 3 AAH XXX 55H PA 20H Add 4 Data Add 4 Data Add 4 Data Add 4 Data Add 4 AAH 555H 55H 2AAH A0H 555H PD AAH 555H 55H 2AAH 90H 555H 0H/1H PA AAH 555H 55H 2AAH 90H (DA)555H 00H / 01H (DA)X03H AAH 555H 55H 2AAH 90H (BA)555H Note6 (BA)X02H AAH 555H 55H 2AAH 90H (DA)555H ECH (DA)X01H 1 F0H 555H 2AAH (DA)555H (DA)X00H 1 RD XXXH Cycle 1st Cycle RA 2nd Cycle 3rd Cycle 4th Cycle 5th Cycle 6th Cycle 34 Revision 1.0 November 2004 K5L5628JT(B)M Table 5. Command Sequences (Continued) Command Definitions Add Block Protection/Unprotection (Note 14) Data Add CFI Query (Note 15) Data Add Set Burst Mode Configuration Register (Note 16) Data Addr Enter OTP Block Region Data Addr Exit OTP Block Region Data Notes: 4 AAH 55H 75H 3 AAH 555H 55H 2AAH 70H 555H 3 60H 60H 60H (DA)X55H 98H 555H AAH 555H 2AAH 55H 2AAH (CR)555H C0H 555H Cycle 1st Cycle XXX 2nd Cycle XXX 3rd Cycle ABP Preliminary Preliminary MCP MEMORY 4th Cycle 5th Cycle 6th Cycle 1 3 XXX 00H 1. RA : Read Address , PA : Program Address, RD : Read Data, PD : Program Data , BA : Block Address (A23 ~ A12) DA : Bank Address (A23 ~ A20) , ABP : Address of the block to be protected or unprotected, CR : Configuration Register Setting 2. The 4th cycle data of autoselect mode and RD are output data. The others are input data. 3. Data bits DQ15-DQ8 are don't care in command sequences, except for RD, PD and Device ID. 4. Unless otherwise noted, address bits A23-A11 are don't cares. 5. The reset command is required to return to read mode. If a bank entered the autoselect mode during the erase suspend mode, writing the reset command returns that bank to the erase suspend mode. If a bank entered the autoselect mode during the program suspend mode, writing the reset command returns that bank to the program suspend mode. If DQ5 goes high during the program or erase operation, writing the reset command returns that bank to read mode or erase suspend mode if that bank was in erase suspend mode. 6. The 3rd and 4th cycle bank address of autoselect mode must be same. Device ID Data : "22FCH" for Top Boot Block Device, "22FDH" for Bottom Boot Block Device 7. 00H for an unprotected block and 01H for a protected block. 8. 0H for handshaking, 1H for non-handshaking 9. The unlock bypass command sequence is required prior to this command sequence. 10. Quadruple word accelerated program is invoked only at Vpp=VID ,Vpp setup is required prior to this command sequence. PA1, PA2, PA3, PA4 have the same A23~A2 address. 11. The system may read and program in non-erasing blocks when in the erase suspend mode. The system may enter the autoselect mode when in the erase suspend mode. The erase suspend command is valid only during a block erase operation, and requires the bank address. 12. The erase/program resume command is valid only during the erase/program suspend mode, and requires the bank address. 13. This mode is used only to enable Data Read by suspending the Program operation. 14. Set block address(BA) as either A6 = VIH, A1 = VIH and A0 = VIL for unprotected or A6 = VIL, A1 = VIH and A0 = VIL for protected. 15. Command is valid when the device is in Read mode or Autoselect mode. 16. See "Set Burst Mode Congiguration Register" for details. 35 Revision 1.0 November 2004 K5L5628JT(B)M DEVICE OPERATION Preliminary Preliminary MCP MEMORY To write a command or command sequence (which includes programming data to the device and erasing blocks of memory), the system must drive CLK, WE and CE to VIL and OE to VIH when providing address or data. The device provide the unlock bypass mode to save its program time for program operation. Unlike the standard program command sequence which is comprised of four bus cycles, only two program cycles are required to program a word in the unlock bypass mode. One block, multiple blocks, or the entire device can be erased. Table 3 indicates the address space that each block occupies. The device's address space is divided into sixteen banks: Bank 0 contains the boot/parameter blocks, and the other banks(from Bank 1 to 15) consist of uniform blocks. A "bank address" is the address bits required to uniquely select a bank. Similarly, a "block address" is the address bits required to uniquely select a block. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Read Mode The device automatically enters to asynchronous read mode after device power-up. No commands are required to retrieve data in asynchronous mode. After completing an Internal Program/Erase Routine, each bank is ready to read array data. The reset command is required to return a bank to the read(or erase-suspend-read)mode if DQ5 goes high during an active program/erase operation, or if the bank is in the autoselect mode. The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. That means device enters burst read mode from asynchronous read mode to burst read mode using CLK and AVD signal. When the burst read is finished(or terminated), the device return to asynchronous read mode automatically. Asynchronous Read Mode For the asynchronous read mode a valid address should be asserted on A0-A23, while driving AVD and CE to VIL. WE should remain at VIH . The data will appear on DQ0-DQ15. Since the memory array is divided into sixteen banks, each bank remains enabled for read access until the command register contents are altered. Address access time (tAA) is equal to the delay from valid addresses to valid output data. The chip enable access time(tCE) is the delay from the falling edge of CE to valid data at the outputs. The output enable access time(tOE) is the delay from the falling edge of OE to valid data at the output. To prevent the memory content from spurious altering during power transition, the initial state machine is set for reading array data upon device power-up, or after a hardware reset. Synchronous (Burst) Read Mode The device is capable of continuous linear burst operation and linear burst operation of a preset length. For the burst mode, the system should determine how many clock cycles are desired for the initial word(tIACC) of each burst access and what mode of burst operation is desired using "Burst Mode Configuration Register" command sequences. See "Set Burst Mode Configuration" for further details. The status data also can be read during burst read mode by using AVD signal with a bank address. To initiate the synchronous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase operation. Continuous Linear Burst Read The synchronous(burst) mode will automatically be enabled on the first rising edge on the CLK input while AVD is held low. Note that the device is enabled for asynchronous mode when it first powers up. The initial word is output tIAA after the rising edge of the first CLK cycle. Subsequent words are output tBA after the rising edge of each successive clock cycle, which automatically increments the internal address counter. Note that the device has internal address boundary that occurs every 16 words. When the device is crossing the first word boundary, additional clock cycles are needed before data appears for the next address. The number of addtional clock cycle can varies from zero to three cycles, and the exact number of additional clock cycle depends on the starting address of burst read.(Refer to Figure 13) The RDY output indicates this condition to the system by pulsing low. The device will continue to output sequential burst data, wrapping around to address 000000h after it reaches the highest addressable memory location until the system asserts CE high, RESET low or AVD low in conjunction with a new address.(See Table 4.) The reset command does not terminate the burst read operation. If the host system crosses the bank boundary while reading in burst mode, and the accessed bank is not programming or erasing, a additional clock cycles are needed as previously mentioned. If the host system crosses the bank boundary while the accessed bank is programming or erasing, that is busy bank, the synchronous read will be terminated. 36 Revision 1.0 November 2004 K5L5628JT(B)M Preliminary Preliminary MCP MEMORY 8-,16-Word Linear Burst Read As well as the Continuous Linear Burst Mode, there are two(8 & 16 word) linear wrap & no-wrap mode, in which a fixed number of words are read from consecutive addresses. In these modes, the addresses for burst read are determined by the group within which the starting address falls. The groups are sized according to the number of words read in a single burst sequence for a given mode.(See Table. 6) Table 6. Burst Address Groups(Wrap mode only) Burst Mode 8 word 16 word Group Size 8 words 16words Group Address Ranges 0-7h, 8-Fh, 10-17h, .... 0-Fh, 10-1Fh, 20-2Fh, .... As an example: In wrap mode case, if the starting address in the 8-word mode is 2h, the address range to be read would be 0-7h, and the wrap burst sequence would be 2-3-4-5-6-7-0-1h. The burst sequence begins with the starting address written to the device, but wraps back to the first address in the selected group. In a similar manner, 16-word wrap mode begin their burst sequence on the starting address written to the device, and then wrap back to the first address in the selected address group. In no-wrap mode case, if the starting address in the 8-word mode is 2h, the no-wrap burst sequence would be 2-3-4-5-6-7-8-9h. The burst sequence begins with the starting address written to the device, and continue to the 8th address from starting address. In a similar manner, 16-word no-wrap mode begin their burst sequence on the starting address written to the device, and continue to the 16th address from starting address. Also, when the address cross the word boundary in no-wrap mode, same number of additional clock cycles as continuous linear mode is needed. Programmable Wait State The programmable wait state feature indicates to the device the number of additional clock cycles that must elapse after AVD is driven active for burst read mode. Upon power up, the number of total initial access cycles defaults to seven. Handshaking The handshaking feature allows the host system to simply monitor the RDY signal from the device to determine when the initial word of burst data is ready to be read. To set the number of initial cycle for optimal burst mode, the host should use the programmable wait state configuration.(See "Set Burst Mode Configuration Register" for details.) The rising edge of RDY after OE goes low indicates the initial word of valid burst data. Using the autoselect command sequence the handshaking feature may be verified in the device. Set Burst Mode Configuration Register The device uses a configuration register to set the various burst parameters : the number of initial cycles for burst and burst read mode. The burst mode configuration register must be set before the device enter burst mode. The burst mode configuration register is loaded with a three-cycle command sequences. On the third cycle, the data should be C0h, address bits A11-A0 should be 555h, and address bits A18-A12 set the code to be latched. The device will power up or after a hardware reset with the default setting. Table 7. Burst Mode Configuration Register Table Address Bit A18 A17 A16 Burst Read Mode A15 A14 A13 Programmable Wait State A12 Function RDY Active Settings(Binary) 1 = RDY active one clock cycle before data 0 = RDY active with data(default) 000 = Continuous(default) 001 = 8-word linear with wrap 010 = 16-word linear with wrap 011 = 8-word linear with no-wrap 100 = 16-word linear with no-wrap 101 ~ 111 = Reserve 000 = Data is valid on the 4th active CLK edge after AVD transition to VIH 001 = Data is valid on the 5th active CLK edge after AVD transition to VIH 010 = Data is valid on the 6th active CLK edge after AVD transition to VIH 011 = Data is valid on the 7th active CLK edge after AVD transition to VIH (default) 100 = Reserve 101 = Reserve 110 = Reserve 111 = Reserve Programmable Wait State Configuration This feature informs the device of the number of clock cycles that must elapse after AVD# is driven active before data will be available. This value is determined by the input frequency of the device. Address bits A14-A12 determine the setting. (See Burst Mode Configuration Register Table) 37 Revision 1.0 November 2004 K5L5628JT(B)M Preliminary Preliminary MCP MEMORY The Programmable wait state setting instructs the device to set a particular number of clock cycles for the initial access in burst mode. Note that hardware reset will set the wait state to the default setting, that is 7 initial cycles. Burst Read Mode Setting The device supports five different burst read modes : continuous linear mode, 8 and 16 word linear burst modes with wrap and 8 and 16 word linear burst modes with no-wrap. RDY Configuration By default, the RDY pin will be high whenever there is valid data on the output. The device can be set so that RDY goes active one data cycle before active data. Address bit A18 determine this setting. Note that RDY always go high with valid data in case of word boundary crossing. Table 8. Burst Address Sequences Start Addr. 0 1 Wrap 2 . . 0 1 No-wrap 2 . . Burst Address Sequence(Decimal) Continuous Burst 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... . . 0-1-2-3-4-5-6... 1-2-3-4-5-6-7... 2-3-4-5-6-7-8... . . 8-word Burst 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 . . 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 . . 16-word Burst 0-1-2-3-4-....-13-14-15 1-2-3-4-5-....-14-15-0 2-3-4-5-6-....-15-0-1 . . 0-1-2-3-4-....-13-14-15 1-2-3-4-5-....-14-15-16 2-3-4-5-6-....-15-16-17 . . Autoselect Mode By writing the autoselect command sequences to the system, the device enters the autoselect mode. This mode can be read only by asynchronous read mode. The system can then read autoselect codes from the internal register(which is separate from the memory array). Standard asynchronous read cycle timings apply in this mode. The device offers the Autoselect mode to identify manufacturer and device type by reading a binary code. In addition, this mode allows the host system to verify the block protection or unprotection. Table 5 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is in the read mode, erase-suspend-read mode or program-suspend-read mode. The autoselect command may not be written while the device is actively programming or erasing in the device. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the address and the autoselect command. Note that the block address is needed for the verification of block protection. The system may read at any address within the same bank any number of times without initiating another autoselect command sequence. And the burst read should be prohibited during Autoselect Mode. To terminate the autoselect operation, write Reset command(F0H) into the command register. Table 9. Autoselct Mode Description Description Manufacturer ID Device ID Block Protection/Unprotection Handshaking Address (DA) + 00H (DA) + 01H (BA) + 02H (DA) + 03H Read Data ECH 22FCH(Top Boot Block), 22FDH(Bottom Boot Block) 01H (protected), 00H (unprotected) 0H : handshaking, 1H : non-handshaking Standby Mode When the CE and RESET inputs are both held at VCC 0.2V or the system is not reading or writing, the device enters Stand-by mode to minimize the power consumption. In this mode, the device outputs are placed in the high impedence state, independent of the OE input. When the device is in either of these standby modes, the device requires standard access time (tCE ) for read access before it is ready to read data. If the device is deselected during erasure or programming, the device draws active current until the operation is completed. ICC5 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The device features Automatic Sleep Mode to minimize the device power consumption during both asynchronous and burst mode. When addresses remain stable for tAA+60ns, the device automatically enables this mode. The automatic sleep mode is independent of the CE, WE, and OE control signals. In a sleep mode, output data is latched and always available to the system. When addresses are changed, the device provides new data without wait time. Automatic sleep mode current is equal to standby mode current. 38 Revision 1.0 November 2004 K5L5628JT(B)M Output Disable Mode Preliminary Preliminary MCP MEMORY When the OE input is at VIH , output from the device is disabled. The outputs are placed in the high impedance state. Block Protection & Unprotection To protect the block from accidental writes, the block protection/unprotection command sequence is used. On power up, all blocks in the device are protected. To unprotect a block, the system must write the block protection/unprotection command sequence. The first two cycles are written: addresses are don't care and data is 60h. Using the third cycle, the block address (ABP) and command (60h) is written, while specifying with addresses A6, A1 and A0 whether that block should be protected (A6 = VIL, A1 = VIH, A0 = VIL) or unprotected (A6 = VIH, A1 = VIH, A0 = VIL). After the third cycle, the system can continue to protect or unprotect additional cycles, or exit the sequence by writing F0h (reset command). The device offers three types of data protection at the block level: * The block protection/unprotection command sequence disables or re-enables both program and erase operations in any block. * When WP is at VIL, the two outermost blocks are protected. * When VPP is at VIL, all blocks are protected. Note that user never float the Vpp and WP, that is, Vpp is always connected with VIH, VIL or VID and WP is VIH or VIL. Hardware Reset The device features a hardware method of resetting the device by the RESET input. When the RESET pin is held low(VIL) for at least a period of tRP, the device immediately terminates any operation in progress, tristates all outputs, and ignores all read/write commands for the duration of the RESET pulse. The device also resets the internal state machine to asynchronous read mode. To ensure data integrity, the interrupted operation should be reinitiated once the device is ready to accept another command sequence. As previously noted, when RESET is held at VSS 0.2V, the device enters standby mode. The RESET pin may be tied to the system reset pin. If a system reset occurs during the Internal Program or Erase Routine, the device will be automatically reset to the asynchronous read mode; this will enable the systems microprocessor to read the boot-up firmware from the Flash memory. If RESET is asserted during a program or erase operation, the device requires a time of tREADY (during Internal Routines) before the device is ready to read data again. If RESET is asserted when a program or erase operation is not executing, the reset operation is completed within a time of tREADY (not during Internal Routines). tRH is needed to read data after RESET returns to VIH. Refer to the AC Characteristics tables for RESET parameters and to Figure 6 for the timing diagram. Software Reset The reset command provides that the bank is reseted to read mode, erase-suspend-read mode or program-suspend-read mode. The addresses are in Don't Care state. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins, or in a program command sequence before programming begins. If the device begins erasure or programming, the reset command is ignored until the operation is completed. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. The reset command is valid between the sequence cycles in an autoselect command sequence. In an autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Also, if a bank entered the autoselect mode while in the Program Suspend mode, writing the reset command returns that bank to the program-suspend-read mode. If DQ5 goes high during a program or an erase operation, writing the reset command returns the banks to the read mode. (or erase-suspend-read mode if the bank was in Erase Suspend) Program The device can be programmed in units of a word. Programming is writing 0's into the memory array by executing the Internal Program Routine. In order to perform the Internal Program Routine, a four-cycle command sequence is necessary. The first two cycles are unlock cycles. The third cycle is assigned for the program setup command. In the last cycle, the address of the memory location and the data to be programmed at that location are written. The device automatically generates adequate program pulses and verifies the programmed cell margin by the Internal Program Routine. During the execution of the Routine, the system is not required to provide further controls or timings. During the Internal Program Routine, commands written to the device will be ignored. Note that a hardware reset during a program operation will cause data corruption at the corresponding location. Accelerated Program Operation The device provides Single/Quadruple word accelerated program operations through the Vpp input. Using this mode, faster manufacturing throughput at the factory is possible. When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for program operations. By removing VID returns the device to normal operation mode. Note that Read while Accelerated Programm and Program suspend mode are not guaranteed 39 Revision 1.0 November 2004 K5L5628JT(B)M Preliminary Preliminary MCP MEMORY Single word accelerated program operation The system would use two-cycle program sequence (One-cycle (XXX - A0H) is for single word program command, and Next onecycle (PA - PD) is for program address and data ). Quadruple word accelerated program operation As well as Single word accelerated program, the system would use five-cycle program sequence (One-cycle (XXX - A5H) is for quadruple word program command, and four cycles are for program address and data). * Only four words programming is possible * Each program address must have the same A23~A2 address * The device automatically generates adequate program pulses and ignores other command after program command Unlock Bypass The device provides the unlock bypass mode to save its operation time. This mode is possible for program, block erase and chip erase operation. There are two methods to enter the unlock bypass mode. The mode is invoked by the unlock bypass command sequence or the assertion of VID on VPP pin. Unlike the standard program/erase command sequence that contains four/six bus cycles, the unlock bypass program/erase command sequence needs only two bus cycles. The unlock bypass mode is engaged by issuing the unlock bypass command sequence which is comprised of three bus cycles. Writing first two unlock cycles is followed by a third cycle containing the unlock bypass command (20H). Once the device is in the unlock bypass mode, the unlock bypass program/erase command sequence is necessary. The unlock bypass program command sequence is comprised of only two bus cycles; writing the unlock bypass program command (A0H) is followed by the program address and data. This command sequence is the only valid one for programming the device in the unlock bypass mode. Also, The unlock bypass erase command sequence is comprised of two bus cycles; writing the unlock bypass block erase command(80H-30H) or writing the unlock bypass chip erase command(80H-10H). This command sequences are the only valid ones for erasing the device in the unlock bypass mode. The unlock bypass reset command sequence is the only valid command sequence to exit the unlock bypass mode. The unlock bypass reset command sequence consists of two bus cycles. The first cycle must contain the data (90H). The second cycle contains only the data (00H). Then, the device returns to the read mode. To enter the unlock bypass mode in hardware level, the VID also can be used. By assertion VID on the VPP pin, the device enters the unlock bypass mode. Also, the all blocks are temporarily unprotected when the device using the VID for unlock bypass mode. To exit the unlock bypass mode, just remove the asserted VID from the VPP pin.(Note that user never float the Vpp, that is, Vpp is always connected with VIH, VIL or VID.). Chip Erase To erase a chip is to write 1s into the entire memory array by executing the Internal Erase Routine. The Chip Erase requires six bus cycles to write the command sequence. The erase set-up command is written after first two "unlock" cycles. Then, there are two more write cycles prior to writing the chip erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory for an all zero data pattern prior to erasing. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when DQ7 is "1". After that the device returns to the read mode. Block Erase To erase a block is to write 1s into the desired memory block by executing the Internal Erase Routine. The Block Erase requires six bus cycles to write the command sequence shown in Table 5. After the first two "unlock" cycles, the erase setup command (80H) is written at the third cycle. Then there are two more "unlock" cycles followed by the Block Erase command. The Internal Erase Routine automatically pre-programs and verifies the entire memory prior to erasing it. Multiple blocks can be erased sequentially by writing the sixth bus-cycle. Upon completion of the last cycle for the Block Erase, additional block address and the Block Erase command (30H) can be written to perform the Multi-Block Erase. For the Multi-Block Erase, only sixth cycle(block address and 30H) is needed.(Similarly, only second cycle is needed in unlock bypass block erase.) An 50us (typical) "time window" is required between the Block Erase command writes. The Block Erase command must be written within the 50us "time window", otherwise the Block Erase command will be ignored. The 50us "time window" is reset when the falling edge of the WE occurs within the 50us of "time window" to latch the Block Erase command. During the 50us of "time window", any command other than the Block Erase or the Erase Suspend command written to the device will reset the device to read mode. After the 50 us of "time window", the Block Erase command will initiate the Internal Erase Routine to erase the selected blocks. Any Block Erase address and command following the exceeded "time window" may or may not be accepted. No other commands will be recognized except the Erase Suspend command during Block Erase operation. The device provides accelerated erase operations through the Vpp input. When VID is asserted on the Vpp input, the device automatically enters the Unlock Bypass mode, temporarily unprotects any protected blocks, and uses the higher voltage on the input to reduce the time required for erase. By removing VID returns the device to normal operation mode. 40 Revision 1.0 November 2004 K5L5628JT(B)M Erase Suspend / Resume Preliminary Preliminary MCP MEMORY The Erase Suspend command interrupts the Block Erase to read or program data in a block that is not being erased. Also, it is possible to protect or unprotect of the block that is not being erased in erase suspend mode. The Erase Suspend command is only valid during the Block Erase operation including the time window of 50 us. The Erase Suspend command is not valid while the Chip Erase or the Internal Program Routine sequence is running. When the Erase Suspend command is written during a Block Erase operation, the device requires a maximum of 20 us(recovery time) to suspend the erase operation. Therefore system must wait for 20us(recovery time) to read the data from the bank which include the block being erased. Otherwise, system can read the data immediately from a bank which don't include the block being erased without recovery time(max. 20us) after Erase Suspend command. And, after the maximum 20us recovery time, the device is availble for programming data in a block that is not being erased. But, when the Erase Suspend command is written during the block erase time window (50 us) , the device immediately terminates the block erase time window and suspends the erase operation. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. When the Erase Resume command is executed, the Block Erase operation will resume. When the Erase Suspend or Erase Resume command is executed, the addresses are in Don't Care state. Program Suspend / Resume The device provides the Program Suspend/Resume mode. This mode is used to enable Data Read by suspending the Program operation. The device accepts a Program Suspend command in Program mode(including Program operations performed during Erase Suspend) but other commands are ignored. After input of the Program Suspend command, 2us is needed to enter the Program Suspend Read mode. Therefore system must wait for 2us(recovery time) to read the data from the bank which include the block being programmed. Othwewise, system can read the data immediately from a bank which don't include block being programmed without ecovery time(max. 2us) after Program Suspend command. Like an Erase Suspend mode, the device can be returned to Program mode by using a Program Resume command. Read While Write Operation The device is capable of reading data from one bank while writing in the other banks. This is so called the Read While Write operation. An erase operation may also be suspended to read from or program to another location within the same bank(except the block being erased). The Read While Write operation is prohibited during the chip erase operation. Figure 12 shows how read and write cycles may be initiated for simultaneous operation with zero latency. Refer to the DC Characteristics table for read-while-write current specifications. OTP Block Region The OTP Block feature provides a 256-byte Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The OTP Block is customer lockable and shipped with itself unlocked, allowing customers to untilize the that block in any manner they choose. The customer-lockable OTP Block has the Protection Verify Bit (DQ0) set to a "0" for Unlocked state or a "1" for Locked state. The system accesses the OTP Block through a command sequence (see "Enter OTP Block / Exit OTP Block Command sequence" at Table8). After the system has written the "Enter OTP Block" Command sequence, it may read the OTP Block by using the addresses (FFFF80h~FFFFFFh) normally and may check the Protection Verify Bit (DQ0) by using the "Autoselect Block Protection Verify" Command sequence with OTP Block address. This mode of operation continues until the system issues the "Exit OTP Block" Command suquence, a hardware reset or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to main blocks. Note that the Accelerated function and unlock bypass modes are not available when the OTP Block is enabled. Customer Lockable In a Customer lockable device, The OTP Block is one-time programmable and can be locked only once. Note that the Accelerated programming and Unlock bypass functions are not available when programming the OTP Block. Locking operation to the OTP Block is started by writing the "Enter OTP Block" Command sequence, and then the "Block Protection" Command sqeunce (Table 8) with an OTP Block address. Hardware reset terminates Locking operation, and then makes exiting from OTP Block. The Locking operation has to be above 100us. The OTP Block Lock operation must be used with caution since, once locked, there is no procedure available for unlocking and none of the bits in the OTP Block space can be modified in any way. Low VCC Write Inhibit To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than VLKO. If the Vcc < VLKO (Lock-Out Voltage), the command register and all internal program/erase circuits are disabled. Under this condition the device will reset itself to the read mode.Subsequent writes will be ignored until the Vcc level is greater than VLKO. It is the user's responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above VLKO. 41 Revision 1.0 November 2004 K5L5628JT(B)M Write Pulse "Glitch" Protection Noise pulses of less than 5ns (typical) on OE, CE, AVD or WE do not initiate a write cycle. Preliminary Preliminary MCP MEMORY Logical Inhibit Write cycles are inhibited by holding any one of OE = VIL , CE = VIH or WE = VIH. To initiate a write cycle, CE and WE must be a logical zero while OE is a logical one. Power-up Protection To avoid initiation of a write cycle during VCC power-up, RESET low must be asserted during Power-up. After RESET goes high. the device is reset to the read mode. FLASH MEMORY STATUS FLAGS The device has means to indicate its status of operation in the bank where a program or erase operation is in processes. Address must include bank address being executed internal routine operation. The status is indicated by raising the device status flag via corresponding DQ pins. This status read is supported in burst mode and asynchronous mode. The status data can be read during burst read mode by using AVD signal with a bank address. That means status read is supported in synchronous mode. If status read is performed, the data provided in the burst read is identical to the data in the initial access. To initiate the synchronous read again, a new address and AVD pulse is needed after the host has completed status reads or the device has completed the program or erase operation. The corresponding DQ pins are DQ7, DQ6, DQ5, DQ3 and DQ2. Table 10. Hardware Sequence Flags Status Programming Block Erase or Chip Erase Erase Suspend Read Erase Suspend Read In Progress Erase Suspend Program Program Suspend Read Program Suspend Read Programming Exceeded Time Limits Block Erase or Chip Erase Erase Suspend Program Erase Suspended Block Non-Erase Suspended Block Non-Erase Suspended Block Program Suspended Block Non- program Suspended Block DQ7 DQ7 0 1 Data DQ7 DQ7 Data DQ7 0 DQ7 DQ6 Toggle Toggle 1 Data Toggle 1 Data Toggle Toggle Toggle DQ5 0 0 0 Data 0 0 Data 1 1 1 DQ3 0 1 0 Data 0 0 Data 0 1 0 DQ2 1 Toggle Toggle (Note 1) Data 1 Toggle (Note 1) Data No Toggle (Note 2) No Toggle Notes : 1. DQ2 will toggle when the device performs successive read operations from the erase/program suspended block. 2. If DQ5 is High (exceeded timing limits), successive reads from a problem block will cause DQ2 to toggle. DQ7 : Data Polling When an attempt to read the device is made while executing the Internal Program, the complement of the data is written to DQ7 as an indication of the Routine in progress. When the Routine is completed an attempt to access to the device will produce the true data written to DQ7. When a user attempts to read the block being erased, DQ7 will be low. If the device is placed in the Erase/Program Suspend Mode, the status can be detected via the DQ7 pin. If the system tries to read an address which belongs to a block that is being erase suspended, DQ7 will be high. And, if the system tries to read an address which belongs to a block that is being program suspended, the output will be the true data of DQ7 itself. If a non-erase-suspended or non-program-suspended block address is read, the device will produce the true data to DQ7. If an attempt is made to program a protected block, DQ7 outputs complements the data for approximately 1s and the device then returns to the Read Mode without changing data in the block. If an attempt is made to erase a protected block, DQ7 outputs complement data in approximately 100us and the device then returns to the Read Mode without erasing the data in the block. 42 Revision 1.0 November 2004 K5L5628JT(B)M DQ6 : Toggle Bit Preliminary Preliminary MCP MEMORY Toggle bit is another option to detect whether an Internal Routine is in progress or completed. Once the device is at a busy state, DQ6 will toggle. Toggling DQ6 will stop after the device completes its Internal Routine. If the device is in the Erase/Program Suspend Mode, an attempt to read an address that belongs to a block that is being erased or programmed will produce a high output of DQ6. If an address belongs to a block that is not being erased or programmed, toggling is halted and valid data is produced at DQ6. If an attempt is made to program a protected block, DQ6 toggles for approximately 1us and the device then returns to the Read Mode without changing the data in the block. If an attempt is made to erase a protected block, DQ6 toggles for approximately 100s and the device then returns to the Read Mode without erasing the data in the block. DQ5 : Exceed Timing Limits If the Internal Program/Erase Routine extends beyond the timing limits, DQ5 will go High, indicating program/erase failure. DQ3 : Block Erase Timer The status of the multi-block erase operation can be detected via the DQ3 pin. DQ3 will go High if 50s of the block erase time window expires. In this case, the Internal Erase Routine will initiate the erase operation.Therefore, the device will not accept further write commands until the erase operation is completed. DQ3 is Low if the block erase time window is not expired. Within the block erase time window, an additional block erase command (30H) can be accepted. To confirm that the block erase command has been accepted, the software may check the status of DQ3 following each block erase command. DQ2 : Toggle Bit 2 The device generates a toggling pulse in DQ2 only if an Internal Erase Routine or an Erase/Program Suspend is in progress. When the device executes the Internal Erase Routine, DQ2 toggles only if an erasing block is read. Although the Internal Erase Routine is in the Exceeded Time Limits, DQ2 toggles only if an erasing block in the Exceeded Time Limits is read. When the device is in the Erase/Program Suspend mode, DQ2 toggles only if an address in the erasing or programming block is read. If a non-erasing or nonprogrammed block address is read during the Erase/Program Suspend mode, then DQ2 will produce valid data. DQ2 will go High if the user tries to program a non-erase suspend block while the device is in the Erase Suspend mode. RDY: Ready Normally the RDY signal is used to indicate if new burst data is available at the rising edge of the clock cycle or not. If RDY is low state, data is not valid at expected time, and if high state, data is valid. Note that, if CE is low and OE is high, the RDY is high state. Start Start DQ7 = Data ? No Yes DQ6 = Toggle ? No Yes No DQ5 = 1 ? No DQ5 = 1 ? Yes Yes Yes No DQ7 = Data ? DQ6 = Toggle ? No Yes Fail Pass Fail Pass Figure 1. Data Polling Algorithms Figure 2. Toggle Bit Algorithms 43 Revision 1.0 November 2004 K5L5628JT(B)M Commom Flash Memory Interface Preliminary Preliminary MCP MEMORY Common Flash Momory Interface is contrived to increase the compatibility of host system software. It provides the specific information of the device, such as memory size and electrical features. Once this information has been obtained, the system software will know which command sets to use to enable flash writes, block erases, and control the flash component. When the system writes the CFI command(98H) to address 55H , the device enters the CFI mode. And then if the system writes the address shown in Table 11, the system can read the CFI data. Query data are always presented on the lowest-order data outputs(DQ0-7) only. In word(x16) mode, the upper data outputs(DQ8-15) is 00h. To terminate this operation, the system must write the reset command. Table 11. Common Flash Memory Interface Code Description Addresses (Word Mode) 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH Data 0051H 0052H 0059H 0002H 0000H 0040H 0000H 0000H 0000H 0000H 0000H 0017H 0019H Query Unique ASCII string "QRY" Primary OEM Command Set Address for Primary Extended Table Alternate OEM Command Set (00h = none exists) Address for Alternate OEM Extended Table (00h = none exists) Vcc Min. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vcc Max. (write/erase) D7-D4: volt, D3-D0: 100 millivolt Vpp(Acceleration Program) Supply Minimum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV Vpp(Acceleration Program) Supply Maximum 00 = Not Supported, D7 - D4 : Volt, D3 - D0 : 100mV Typical timeout per single word write 2N us Typical timeout for Min. size buffer write 2 us(00H = not supported) Typical timeout per individual block erase 2N ms Typical timeout for full chip erase 2 ms(00H = not supported) Max. timeout for word write 2N times typical Max. timeout for buffer write 2N times typical Max. timeout per individual block erase 2N times typical Max. timeout for full chip erase 2N times typical(00H = not supported) Device Size = 2N byte Flash Device Interface description Max. number of byte in multi-byte write = 2N Number of Erase Block Regions within device N N 1DH 0085H 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 0095H 0004H 0000H 000AH 0013H 0005H 0000H 0004H 0000H 0019H 0000H 0000H 0000H 0000H 0002H 44 Revision 1.0 November 2004 K5L5628JT(B)M Table 11. Common Flash Memory Interface Code (Continued) Description Erase Block Region 1 Information Bits 0~15: y+1=block number Bits 16~31: block size= z x 256bytes Preliminary Preliminary MCP MEMORY Addresses (Word Mode) 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 40H 41H 42H 43H 44H 45H Data 0007H 0000H 0020H 0000H 00FEH 0001H 0000H 0001H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0050H 0052H 0049H 0031H 0030H 0000H Erase Block Region 2 Information Erase Block Region 3 Information Erase Block Region 4 Information Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address Sensitive Unlock(Bits 1-0) 0 = Required, 1= Not Required Silcon Revision Number(Bits 7-2) Erase Suspend 0 = Not Supported, 1 = To Read Only, 2 = To Read & Write Block Protect 00 = Not Supported, 01 = Supported Block Temporary Unprotect 00 = Not Supported, 01 = Supported Block Protect/Unprotect scheme 00 = Not Supported, 01 = Supported Simultaneous Operation 00 = Not Supported, 01 = Supported Burst Mode Type 00 = Not Supported, 01 = Supported Page Mode Type 00 = Not Supported, 01 = 4 Word Page 02 = 8 Word Page Max. Operating Clock Frequency (MHz ) RWW(Read While Write) Functionality Restriction (00H = non exists , 01H = exists) Handshaking 00 = Not Supported at both mode, 01 = Supported at Sync. Mode 10 = Supported at Async. Mode, 11 = Supported at both Mode 46H 47H 48H 49H 4AH 4BH 4CH 4EH 4FH 50H 0002H 0001H 0000H 0001H 0001H 0001H 0000H 0042H 0000H 0001H 45 Revision 1.0 November 2004 K5L5628JT(B)M ABSOLUTE MAXIMUM RATINGS Parameter Vcc Voltage on any pin relative to VSS VPP All Other Pins Temperature Under Bias Storage Temperature Short Circuit Output Current Operating Temperature Tbias Tstg IOS TA Symbol Vcc VIN Rating -0.5 to +2.5 -0.5 to +9.5 -0.5 to +2.5 -30 to +125 -65 to +150 5 -30 to + 85 Preliminary Preliminary MCP MEMORY Unit V C C mA C Notes : 1. Minimum DC voltage is -0.5V on Input/ Output pins. During transitions, this level may fall to -1.5V for periods <20ns. Maximum DC voltage is Vcc+0.6V on input / output pins which, during transitions, may overshoot to Vcc+1.5V for periods <20ns. 2. Minimum DC input voltage is -0.5V on VPP . During transitions, this level may fall to -1.5V for periods <20ns. Maximum DC input voltage is +9.5V on VPP which, during transitions, may overshoot to +11.0V for periods <20ns. 3. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED OPERATING CONDITIONS ( Voltage reference to GND ) Parameter Supply Voltage Supply Voltage Symbol VCC VSS Min 1.7 0 Typ. 1.8 0 Max 1.95 0 Unit V V DC CHARACTERISTICS Parameter Input Leakage Current VPP Leakage Current Output Leakage Current Active Burst Read Current Active Asynchronous Read Current Active Write Current (Note 2) Read While Write Current Accelerated Program Current Standby Current Standby Current During Reset Automatic Sleep Mode(Note 3) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Voltage for Accelerated Program Low VCC Lock-out Voltage Symbol ILI ILIP ILO ICCB1 ICC1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL VIH VOL VOH VID VLKO IOL = 100 A , VCC=VCCmin IOH = -100 A , VCC=VCCmin Test Conditions VIN=VSS to VCC, VCC=VCCmax VCC=VCCmax , VPP=9.5V VOUT=VSS to VCC, VCC=VCCmax, OE=VIH CE=VIL, OE=VIH CE=VIL, OE=VIH 10MHz 1MHz Min - 1.0 - 1.0 -0.5 VCC-0.4 VCC-0.1 8.5 1.0 Typ 30 30 3 15 40 15 25 25 25 9.0 Max + 1.0 35 + 1.0 45 45 5 30 70 30 70 70 70 0.4 VCC+0.4 0.1 9.5 1.3 Unit A A A mA mA mA mA mA mA A A A V V V V V V CE=VIL, OE=VIH, WE=VIL, VPP=VIH CE=VIL, OE=VIH CE=VIL, OE=VIH , VPP=9.5V CE= RESET=VCC 0.2V RESET = VSS 0.2V CE=VSS 0.2V, Other Pins=VIL or VIH VIL = VSS 0.2V, VIH = VCC 0.2V Notes: 1. Maximum ICC specifications are tested with VCC = VCCmax. 2. ICC active while Internal Erase or Internal Program is in progress. 3. Device enters automatic sleep mode when addresses are stable for tAA + 60ns. 46 Revision 1.0 November 2004 K5L5628JT(B)M CAPACITANCE(TA = 25 C, VCC = 1.8V, f = 1.0MHz) Item Input Capacitance Output Capacitance Control Pin Capacitance Symbol CIN COUT CIN2 Test Condition VIN=0V VOUT=0V Min - Preliminary Preliminary MCP MEMORY Max 10 10 10 Unit pF pF pF VIN=0V Note : Capacitance is periodically sampled and not 100% tested. AC TEST CONDITION Parameter Input Pulse Levels Input Rise and Fall Times Input and Output Timing Levels Output Load Value 0V to VCC 5ns VCC/2 CL = 30pF VCC VCC/2 Input & Output Test Point VCC/2 Device Under Test 0V * CL = 30pF including scope and Jig capacitance Input Pulse and Test Point Output Load AC CHARACTERISTICS Synchronous/Burst Read Parameter Initial Access Time Burst Access Time Valid Clock to Output Delay AVD Setup Time to CLK AVD Hold Time from CLK AVD High to OE Low Address Setup Time to CLK Address Hold Time from CLK Data Hold Time from Next Clock Cycle Output Enable to Data Output Enable to RDY valid CE Disable to High Z OE Disable to High Z CE Setup Time to CLK CLK to RDY Setup Time RDY Setup Time to CLK CLK High or Low Time CLK Fall or Rise Time Symbol Min tIAA tBA tAVDS tAVDH tAVDO tACS tACH tBDH tOE tOER tCEZ tOEZ tCES tRDYA tRDYS tCH/L tCHCL 5 7 0 5 7 4 7 4 4.5 7B (54 MHz) Max 88.5 14.5 20 14.5 20 15 14.5 3 Min 5 6 0 5 6 4 6 4 3.5 7C (66 MHz) Max 70 11 20 11 20 15 11 3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 47 Revision 1.0 November 2004 K5L5628JT(B)M SWITCHING WAVEFORMS 5 cycles for initial access shown. CR setting : A14=0, A13=0, A12=1 tCES CE 15.2 ns typ. Preliminary Preliminary MCP MEMORY tCEZ CLK tAVDS AVD tAVDH tACS A0-A23 tACH DQ0-DQ15 tIAA OE tOER Hi-Z RDY tRDYA tRDYS Da Da+1 Da+2 Da+3 tBA tBDH Hi-Z Da+n tOEZ Hi-Z Figure 3. Burst Mode Read (66 MHz) Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. 5 cycles for initial access shown. CR setting : A14=0, A13=0, A12=1 tCES CE 18.5 ns typ. tCEZ CLK tAVDS AVD tAVDH tACS A0-A23 tACH DQ0-DQ15 tIAA OE tOER Hi-Z RDY tRDYA tRDYS Da Da+1 Da+2 Da+3 tBA tBDH Hi-Z Da+n tOEZ Hi-Z Figure 4. Burst Mode Read (54 MHz) Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. 48 Revision 1.0 November 2004 K5L5628JT(B)M SWITCHING WAVEFORMS 5 cycles for initial access shown. CR setting : A14=0, A13=0, A12=1 tCES CE 15.2 ns typ. Preliminary Preliminary MCP MEMORY CLK tAVDS AVD tAVDH tACS A0-A23 tACH DQ0-DQ15 tIAA OE tOER Hi-Z RDY tRDYA tRDYS D6 D7 D0 D1 D2 D3 tBA tBDH Figure 5. 8 word Linear Burst Mode with Wrap Around (66 MHz) Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. D7 D0 5 cycles for initial access shown. CR setting : A14=0, A13=0, A12=1 tCES CE 15.2 ns typ.(66MHz) CLK tAVDS AVD tAVDH tACS A0-A23 tACH DQ0-DQ15 tIAA OE tOER Hi-Z RDY tRDYA tRDYS D6 D7 D0 D1 D2 D3 tBA tBDH Figure 6. 8 word Linear Burst with RDY Set One Cycle Before Data (CR setting : A18=1) Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. D7 D0 49 Revision 1.0 November 2004 K5L5628JT(B)M SWITCHING WAVEFORMS 5 cycles for initial access shown. CR setting : A14=0, A13=0, A12=1 tCES CE 15.2 ns typ(66MHz). Preliminary Preliminary MCP MEMORY tCEZ CLK tAVDS AVD tAVDH tACS A0-A23 tACH DQ0-DQ15 tIAA OE tOER Hi-Z RDY tRDYA tRDYS D6 D7 D8 D9 tBA tBDH Hi-Z D13 tOEZ Figure 7. 8 word Linear Burst Mode (No Wrap Case) Hi-Z Note: In order to avoid a bus conflict the OE signal is enabled on the next rising edge after AVD is going high. 50 Revision 1.0 November 2004 K5L5628JT(B)M AC CHARACTERISTICS Asynchronous Read Parameter Access Time from CE Low Asynchronous Access Time AVD Low Setup Time to CE Enable AVD Low Hold Time from CE Disable Output Enable to Output Valid Read Output Enable Hold Time Toggle and Data Polling tOEH Preliminary Preliminary MCP MEMORY Symbol tCE tAA tAVDCS tAVDCH tOE 7B 7C Min 0 0 0 10 - Max 90 90 20 15 Min 0 0 0 10 - Max 80 80 20 15 Unit ns ns ns ns ns ns ns ns Output Disable to High Z(Note 1) tOEZ Note: 1. Not 100% tested. SWITCHING WAVEFORMS Asynchronous Mode Read CLK VIL CE tAVDCS AVD tOE OE tOEH WE tAVDCH tCE Valid RD tAA tOEZ DQ0-DQ15 A0-A22 VA Figure 8. Asynchronous Mode Read Note: VA=Valid Read Address, RD=Read Data. 51 Revision 1.0 November 2004 K5L5628JT(B)M AC CHARACTERISTICS Hardware Reset(RESET) All Speed Options Preliminary Preliminary MCP MEMORY Parameter RESET Pin Low(During Internal Routines) to Read Mode (Note) RESET Pin Low(NOT During Internal Routines) to Read Mode (Note) RESET Pulse Width Reset High Time Before Read (Note) RESET Low to Standby Mode Symbol tReady tReady tRP tRH tRPD Min 200 200 20 Max 20 500 - Unit s ns ns ns s Note: Not 100% tested. SWITCHING WAVEFORMS CE, OE tRH RESET tRP tReady Reset Timings NOT during Internal Routines CE, OE tReady RESET tRP Reset Timings during Internal Routines Figure 9. Reset Timings 52 Revision 1.0 November 2004 K5L5628JT(B)M AC CHARACTERISTICS Erase/Program Operation Preliminary Preliminary MCP MEMORY 7B, 7C Parameter WE Cycle Time(Note 1) Address Setup Time(Note 2) Address Hold Time(Note 2) Data Setup Time Data Hold Time Read Recovery Time Before Write CE Setup Time CE Hold Time WE Pulse Width WE Pulse Width High Latency Between Read and Write Operations Word Programming Operation Accelerated Single word Programming Operation Accelerated Quad word Programming Operation Block Erase Operation (Note 3) VPP Rise and Fall Time VPP Setup Time (During Accelerated Programming) VCC Setup Time Symbol tWC tAS tAH tDS tDH tGHWL tCS tCH tWP tWPH tSR/W tPGM tACCPGM tACCPGM_QUAD tBERS tVPP tVPS tVCS Min 100 0 50 50 0 5 5 70 30 0 500 1 50 Typ 0 11.5 6.5 6.5 0.7 - Max - Unit ns ns ns ns ns ns ns ns ns ns ns s s s sec ns s s Notes: 1. Not 100% tested. 2. In write timing, addresses are latched on the falling edge of WE. 3. Include the preprogramming time. FLASH Erase/Program Performance Limits Parameter Min. 32 Kword Block Erase Time 4 Kword Chip Erase Time Word Programming Time Accelerated Sinlge Programming Time (@word) Accelerated Quad Programming Time (@word) Chip Programming Time Accelerated Single word Chip Programming Time Accelerated Quad word Chip Programming Time Erase/Program Endurance (Note 3) 100,000 0.2 360 11.5 6.5 1.6 193 109 27 4 210 120 30 Excludes system level overhead Cycles Minimum 100,000 cycles guaranteed in all Bank sec s sec Typ. 0.7 Max. 14 Unit Comments Includes 00h programming prior to erasure Notes: 1. 25C, VCC = 1.8V, 100,000 cycles, typical pattern. 2. System-level overhead is defined as the time required to execute the two or four bus cycle command necessary to program each word. In the preprogramming step of the Internal Erase Routine, all words are programmed to 00H before erasure. 3. 100K Program/Erase Cycle in all Bank 53 Revision 1.0 November 2004 K5L5628JT(B)M SWITCHING WAVEFORMS Program Operations Preliminary Preliminary MCP MEMORY Program Command Sequence (last two cycles) tAS A0:A23 tAH 555h PA VA Read Status Data VA DQ0-DQ15 A0h PD tDS tDH In Progress Complete CE OE tWP tCH WE tWPH tCS CLK VCC VIL tVCS tWC tPGM Notes: 1. PA = Program Address, PD = Program Data, VA = Valid Address for reading status bits. 2. "In progress" and "complete" refer to status of program operation. 3. A16-A23 are don't care during command sequence unlock cycles. 4. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. 5. AVD Setup/Hold Time to CE Enable are same to Asynchronous Mode Read Figure 10. Program Operation Timing 54 Revision 1.0 November 2004 K5L5628JT(B)M Preliminary Preliminary MCP MEMORY Start 555h/AAh 2AAh/55h 555h/A0h Program Address/Program Data DATA Polling or Toggle Bit Algorithm(See Below) NO Address = Address + 1 Last Address? YES Program Completed Program Command Sequence (address/data) Start Read(DQ0~DQ7) Valid Address Start Read(DQ0~DQ7) Valid Address Read(DQ0~DQ7) Valid Address DQ7 = Data ? Yes No No No DQ6 = Toggle ? No Yes DQ5 = 1 ? Yes DQ5 = 1 ? Yes Read(DQ0~DQ7) Valid Address Yes Read twice(DQ0~DQ7) Valid Address No DQ7 = Data ? No DQ6 = Toggle ? Yes Fail Pass Fail Pass Figure 1. Data Polling Algorithms Figure 2. Toggle Bit Algorithms Figure 11. Program Operation Flow Chart 55 Revision 1.0 November 2004 K5L5628JT(B)M SWITCHING WAVEFORMS Erase Operation Erase Command Sequence (last two cycles) tAS A0:A23 tAH 2AAh 555h for chip erase BA 10h for chip erase DQ0-DQ15 55h 30h tDS tDH CE VA Preliminary Preliminary MCP MEMORY Read Status Data VA In Progress Complete OE tWP tCH WE tWPH tCS CLK tVCS VCC VIL tWC tBERS Notes: 1. BA is the block address for Block Erase. 2. Address bits A16-A23 are don't cares during unlock cycles in the command sequence. 3. Status reads in this figure is asynchronous read, but status read in synchronous mode is also supported. 4. AVD Setup/Hold Time to CE Enable are same to Asynchronous Mode Read Figure 11. Chlp/Block Erase Operations 56 Revision 1.0 November 2004 K5L5628JT(B)M Start Preliminary Preliminary MCP MEMORY 555h/AAh 2AAh/55h 555h/80h 555h/AAh 2AAh/55h 555h/10h(Chip Erase) BA/30h(Block Erase) DATA Polling or Toggle Bit Algorithm(See Below) Erase Completed Figure 13. Erase Operation Flow Chart Start Read(DQ0~DQ7) Valid Address Start Read(DQ0~DQ7) Valid Address Read(DQ0~DQ7) Valid Address DQ7 = Data ? Yes No No No DQ6 = Toggle ? No Yes DQ5 = 1 ? Yes DQ5 = 1 ? Yes Read(DQ0~DQ7) Valid Address Yes Read twice(DQ0~DQ7) Valid Address No DQ7 = Data ? No DQ6 = Toggle ? Yes Fail Pass Fail Pass Figure 1. Data Polling Algorithms Figure 2. Toggle Bit Algorithms 57 Revision 1.0 November 2004 K5L5628JT(B)M SWITCHING WAVEFORMS Unlock Bypass Program Operations(Accelerated Program) Preliminary Preliminary MCP MEMORY CE WE A0:A23 PA DQ0-DQ15 Don't Care A0h Don't Care PD Don't Care OE 1us VID tVPS VPP VIL or VIH tVPP Unlock Bypass Block Erase Operations CE WE A0:A23 BA 555h for chip erase 10h for chip erase 30h Don't Care DQ0-DQ15 Don't Care 80h Don't Care OE 1us VID tVPS VPP VIL or VIH Notes: tVPP 1. VPP can be left high for subsequent programming pulses. 2. Use setup and hold times from conventional program operations. 3. Unlock Bypass Program/Erase commands can be used when the VID is applied to Vpp. 4. AVD Setup/Hold Time to CE Enable are same to Asynchronous Mode Read Figure 12. Unlock Bypass Operation Timings 58 Revision 1.0 November 2004 K5L5628JT(B)M Start Preliminary Preliminary MCP MEMORY Unlock Bypass Program Command Sequence (see below) DATA Polling or Toggle Bit Algorithm(See Below) NO Address = Address + 1 Last Address? YES Program Completed Unlock Bypass Program Command Sequence (address/data) 555h/AAh 2AAh/55h 555h/20h XXXh/A0h Unlock Bypass Reset Command Sequence (address/data) XXXh/90h XXXh/00h Figure 15. Unlock Bypass Operation Flow Chart Program Address/Program Data Start Read(DQ0~DQ7) Valid Address Start Read(DQ0~DQ7) Valid Address Read(DQ0~DQ7) Valid Address DQ7 = Data ? Yes No No No DQ6 = Toggle ? No Yes DQ5 = 1 ? Yes DQ5 = 1 ? Yes Read(DQ0~DQ7) Valid Address Yes Read twice(DQ0~DQ7) Valid Address No DQ7 = Data ? No DQ6 = Toggle ? Yes Fail Pass Fail Pass Figure 1. Data Polling Algorithms 59 Figure 2. Toggle Bit Algorithms Revision 1.0 November 2004 K5L5628JT(B)M SWITCHING WAVEFORMS Data Polling Operations tCES CE Preliminary Preliminary MCP MEMORY CLK tAVDS AVD tAVDH A0-A23 tACS VA tACH DQ0-DQ15 tIAA OE Hi-Z RDY Notes: 1. VA = Valid Address. When the Internal Routine operation is complete, and Data Polling will output true data. Figure 13. Data Polling Timings (During Internal Routine) Toggle Bit Operations tCES CE Status Data VA Status Data tRDYS CLK tAVDS AVD tAVDH A0-A23 tACS VA tACH DQ0-DQ15 tIAA OE Hi-Z RDY Notes: 1. VA = Valid Address. When the Internal Routine operation is complete, the toggle bits will stop toggling. Status Data VA Status Data tRDYS Figure 14. Toggle Bit Timings(During Internal Routine) 60 Revision 1.0 November 2004 K5L5628JT(B)M SWITCHING WAVEFORMS Read While Write Operations Preliminary Preliminary MCP MEMORY Last Cycle in Program or Block Erase Command Sequence Read status in same bank and/or array data from other bank Begin another Program or Erase Command Sequences tWC CE tRC tRC tWC OE tOE tOEH WE tWPH DQ0-DQ15 tWP tDS PD/30h tSR/W tAA tDH RD tOEH tGHWL RD AAh A0-A23 PA/BA RA RA 555h Figure 15. Read While Write Operation Note: Breakpoints in waveforms indicate that system may alternately read array data from the "non-busy bank" and checking the status of the program or erase operation in the "busy" bank. 61 Revision 1.0 November 2004 K5L5628JT(B)M Crossing of First Word Boundary in Burst Read Mode Preliminary Preliminary MCP MEMORY The additional clock insertion for word boundary is needed only at the first crossing of word boundary. This means that no addtional clock cycle is needed from 2nd word boundary crossing to the end of continuous burst read. Also, the number of addtional clock cycle for the first word boundary can varies from zero to three cycles, and the exact number of additional clock cycle depends on the starting address of burst read. The rule to determine the additional clock cycle is as follows. All addresses can be divided into 4 groups. The applied rule is "The residue obtained when the address is divided by 4" or "two LSB bits of address". Using this rule, all address can be divided by 4 different groups as shown in below table. For simplicity of terminology, "4N" stands for the address of which the residue is "0"(or the two LSB bits are "00") and "4N+1" for the address of which the residue is "1"(or the two LSB bits are "01"), etc. The additional clock cycles for first word boundary crossing are zero, one, two or three when the burst read start from "4N" address, "4N+1" address, "4N+2" address or "4N+3" address respectively. Starting Address vs. Additional Clock Cycles for first word boundary Srarting Address Group for Burst Read 4N 4N+1 4N+2 4N+3 The Residue of (Address/4) 0 1 2 3 LSB Bits of Address 00 01 10 11 Additional Clock Cycles for First Word Boundary Crossing 0 cycle 1 cycle 2 cycles 3 cycles Case 1 : Start from "4N" address group 5 cycle for initial access shown.(54MHz case) A0-A23 Data Bus C D E F 10 11 12 13 CLK C D E F 10 11 12 13 14 AVD No Additional Cycle for First Word Boundary CE tCEZ OE tOER tOEZ RDY Notes: 1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc. 2. Address 000000H is also a boundry crossing. 3. No additional clock cycles are needed except for 1st boundary crossing. Figure 16. Crossing of first word boundary in burst read mode. 62 Revision 1.0 November 2004 K5L5628JT(B)M Case2 : Start from "4N+1" address group Preliminary Preliminary MCP MEMORY 5 cycle for initial access shown.(54MHz case) A0-A23 Data Bus D E F 10 11 12 13 CLK D E F 10 11 12 13 14 AVD Additional 1 Cycle for First Word Boundary CE tCEZ OE tOER tOEZ RDY Case 3 : Start from "4N+2" address group 5 cycle for initial access shown.(54MHz case) A0-A23 Data Bus E F 10 11 12 13 CLK E F 10 11 12 13 14 AVD Additional 2 Cycle for First Word Boundary CE tCEZ OE tOER tOEZ RDY Notes: 1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc. 2. Address 000000H is also a boundry crossing. 3. No additional clock cycles are needed except for 1st boundary crossing. Figure 16. Crossing of first word boundary in burst read mode. 63 Revision 1.0 November 2004 K5L5628JT(B)M Preliminary Preliminary MCP MEMORY Case4 : Start from "4N+3" address group 5 cycle for initial access shown.(54MHz case) A0-A23 Data Bus F 10 1 12 13 CLK F 10 11 12 13 14 AVD Additional 3 Cycle for First Word Boundary CE tCEZ OE tOER tOEZ RDY Notes: 1. Address boundry occurs every 16 words beginning at address 00000FH , 00001FH , 00002FH , etc. 2. Address 000000H is also a boundry crossing. 3. No additional clock cycles are needed except for 1st boundary crossing. Figure 16. Crossing of first word boundary in burst read mode. 64 Revision 1.0 November 2004 K5L5628JT(B)M Preliminary Preliminary MCP MEMORY 128M Bit(8M x16) Synchronous Burst UtRAM M-die 65 Revision 1.0 November 2004 K5L5628JT(B)M POWER UP SEQUENCE Preliminary Preliminary MCP MEMORY After applying VCC upto minimum operating voltage(2.5V), drive CS High first and then drive MRS High. Then the device gets into the Power Up mode. Wait for minimum 200s to get into the normal operation mode. During the Power Up mode, the standby current can not be guaranteed. To get the stable standby current level, at least one cycle of active operation should be implemented regardless of wait time duration. To get the appropriate device operation, be sure to keep the following power up sequence. 1. Apply power. 2. Maintain stable power(Vcc min.=2.5V) for a minimum 200s with CS and MRS high. Fig.3 POWER UP TIMING 200s ~ VCC(Min) VCC VCCQ(Min) VCCQ Min. 0ns MRS Min. 200s CS Min. 0ns Power Up Mode Normal Operation Fig.4 STANDBY MODE STATE MACHINES CS=VIH MRS=VIH Power On Initial State (Wait 200s) CS=UB=LB=VIL, WE=VIL, MRS=VIL MRS Setting CS=VIL, UB or LB=VIL MRS=VIH Active CS=VIH MRS=VIH Standby Mode MRS=VIL PAR Mode MRS Setting CS=VIL, WE=VIL, MRS=VIL Default mode after power up is Asynchronous mode(4 Page Read and Asynchronous Write). But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up. For entry to PAR mode, drive MRS pin into VIL for over 0.5s(suspend period) during standby mode after MRS setting has been completed(A4=1, A3=0). If MRS pin is driven into VIH during PAR mode, the device gets back to the standby mode without wake up sequence. 66 Revision 1.0 November 2004 K5L5628JT(B)M FUNCTIONAL DESCRIPTION Preliminary Preliminary MCP MEMORY Table 3. ASYNCHRONOUS 4 PAGE READ & ASYNCHRONOUS WRITE MODE(A15/A14=0/0) CS H H L L L L L L L L L MRS H L H H H H H H H H L OE X 1) WE X 1) LB X 1) UB X 1) DQ0~7 High-Z High-Z High-Z High-Z Dout High-Z Dout Din High-Z Din High-Z DQ8~15 High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z Din Din High-Z Mode Deselected Deselected Output Disabled Output Disabled Lower Byte Read Upper Byte Read Word Read Lower Byte Write Upper Byte Write Word Write Mode Register Set Power Standby PAR Active Active Active Active Active Active Active Active Active X1) H X1) L L L H H H H X1) H X1) H H H L L L L X1) X 1) X1) X 1) H L H L L H L L H H L L H L L L 1. X must be low or high state. 2. In asynchronous mode, Clock and ADV are ignored. 3. /WAIT pin is High-Z in Asynchronous mode. Table 5. SYNCHRONOUS BURST READ & SYNCHRONOUS BURST WRITE MODE(A15/A14=1/0) CS H H L L L L L L L L L L L MRS H L H H H H H H H H H H L OE X1) X1) H X1) X1) L L L X 1) WE X1) X1) H X1) H H H H L or X1) X1) X1) L or LB X1) X1) X1) H X1) L H L X 1) UB X1) X1) X1) H X1) H L L X 1) DQ0~7 High-Z High-Z High-Z High-Z High-Z Dout High-Z Dout High-Z Din High-Z Din High-Z DQ8~15 High-Z High-Z High-Z High-Z High-Z High-Z Dout Dout High-Z High-Z Din Din High-Z CLK X2) X2) X2) X2) ADV X2) X2) H H Mode Deselected Deselected Output Disabled Output Disabled Read Command Power Standby PAR Active Active Active Active Active Active Active Active Active Active Active H H H Lower Byte Read Upper Byte Read Word Read Write Command H H H H L H L L H L L L H H H Lower Byte Write Upper Byte Write Word Write Mode Register Set 1. X must be low or high state. 2. X means "Don't care"(can be low, high or toggling). 3. /WAIT is device output signal so does not have any affect to the mode definition. Please refer to each timing diagram for /WAIT pin function. 4. The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. 5. The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous burst write operation to Asynchronous write operation is prohibited. 67 Revision 1.0 November 2004 K5L5628JT(B)M MODE REGISTER SETTING OPERATION Preliminary Preliminary MCP MEMORY The device has several modes : Asynchronous Page Read mode, Asynchronous Write mode, Synchronous Burst Read mode, Synchronous Burst Write mode, Standby mode and Partial Array Refresh(PAR) mode. Partial Array Refresh(PAR) mode is defined through Mode Register Set(MRS) option. Mode Register Set(MRS) option also defines Burst Length, Burst Type, Wait Polarity and Latency Count at Synchronous Burst Read/Write mode. Mode Register Set (MRS) The mode register stores the data for controlling the various operation modes of UtRAM. It programs Partial Array Refresh(PAR), Burst Length, Burst Type, Latency Count and various vendor specific options to make UtRAM useful for a variety of different applications. The default values of mode register are defined, therefore when the reserved address is input, the device runs at default modes. The mode register is written by driving CS, ADV, WE, UB, LB and MRS to VIL and driving OE to VIH during valid address. The mode register is divided into various fields depending on the fields of functions. The Partial Array Refresh(PAR) field uses A0~A4, Burst Length field uses A5~A7, Burst Type uses A8, Latency Count uses A9~A11, Wait Polarity uses A13, Operation Mode uses A14~A15 and Driver Strength uses A16~A17. Refer to the Table below for detailed Mode Register Setting. A18~A22 addresses are "Don't care" in Mode Register Setting. Table 6. Mode Register Setting according to field of function Address Function A17~A16 DS A15~A14 MS A13 WP A12 RFU A11~A9 Latency A8 BT A7~A5 BL A4~A3 PAR A2 PARA A1~A0 PARS NOTE : DS(Driver Strength), MS(Mode Select), WP(Wait Polarity), Latency(Latency Count), BT(Burst Type), BL(Burst Length), PAR(Partial Array Refresh), PARA(Partial Array Refresh Array), PARS(Partial Array Refresh Size), RFU(Reserved for Future Use) Table 7. Mode Register Set Driver Strength A17 0 0 1 A16 0 1 0 WAIT Polarity A13 0 1 WP Low Enable High Enable A12 0 1 DS Full Drive 1/2 Drive 1/4 Drive RFU RFU Must A11 0 0 0 0 Partial Array Refresh A4 1 1 A3 0 1 PAR PAR Enable PAR Disable A2 0 1 PAR Array PARA Bottom Array Top Array A1 0 0 1 1 A15 0 0 1 A14 0 1 0 Mode Select MS Async. 4 Page Read / Async. Write Not Support Sync. Burst Read / Sync. Burst Write** Latency Count A10 0 0 1 1 A9 0 1 0 1 PAR Size A0 0 1 0 1 PARS Full Array 3/4 Array 1/2 Array 1/4 Array Latency 3* 4 5 6 A8 0 1 Burst Type BT Linear Interleave A7 0 0 1 1 A6 1 1 0 1 Burst Length A5 0 1 0 1 BL 4 word 8 word 16 word Full(256 word) NOTE : The address bits other than those listed in the table above are reserved for future use. Each field has its own default mode and these default modes are written in blue-bold in the table above. But this default mode is not 100% guaranteed so MRS setting sequence is highly recommended after power up. A12 is a reserved bit for future use. A12 must be set as "0". Not all the mode settings are tested. Per the mode settings to be tested, please contact Samsung Product Planning team. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. * Latency 3 is supported in 52.9MHz with tCD 12ns. ** The last data written in the previous Asynchronous write mode is not valid. To make the lastly written data valid, then implement at least one dummy write cycle before change mode into synchronous burst read and synchronous burst write mode. ** The data written in Synchronous burst write operation can be corrupted by the next Asynchronous write operation. So the transition from Synchronous burst write operation to Asynchronous write operation is prohibited. 68 Revision 1.0 November 2004 K5L5628JT(B)M MRS pin Control Type Mode Register Setting Timing Preliminary Preliminary MCP MEMORY In this device, MRS pin is used for two purposes. One is to get into the mode register setting and the other one is to execute Partial Array Refresh mode. To get into the Mode Register Setting, the system must drive MRS pin to VIL and immediately(within 0.5s) issue a write command(drive CS, ADV, UB, LB and WE to VIL and drive OE to VIH during valid address). If the subsequent write command(WE signal input) is not issued within 0.5s, then the device might get into the PAR mode. Fig.5 MODE REGISTER SETTING TIMING(OE=VIH) 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 ADV tWC Address tCW CS tAW tBW UB, LB tWP WE tAS tMW tWU MRS Register Update Complete Register Write Start (MRS SETTING TIMING) 1. Clock input is ignored. Register Write Complete Table 8. MRS AC CHARACTERISTICS (VCC=2.5~2.7V, VCCQ=1.7~2.0V TA=-30 to 85C, Maximum Main Clock Frequency = 52.9MHz) Parameter List MRS Enable to Register Write Start End of Write to MRS Disable Symbol Min MRS tMW tWU 0 0 Speed Max 500 ns ns Units 69 Revision 1.0 November 2004 K5L5628JT(B)M ASYNCHRONOUS OPERATION Asynchronous 4 Page Read Operation Asynchronous normal read operation starts when CS, OE and UB or LB are driven to VIL under the valid address without toggling page addresses(A0, A1). If the page addresses(A0, A1) are toggled under the other valid address, the first data will be out with the normal read cycle time(tRC) and the second, the third and the fourth data will be out with the page cycle time(tPC). (MRS and WE should be driven to VIH during the asynchronous (page) read operation) Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation. Preliminary Preliminary MCP MEMORY SYNCHRONOUS BURST OPERATION Burst mode operations enable the system to get high performance read and write operation. The address to be accessed is latched on the rising edge of clock or ADV(whichever occurs first). CS should be setup before the address latch. During this first clock rising edge, WE indicates whether the operation is going to be a Read(WE High) or a Write(WE Low). For the optimized Burst Mode to each system, the system should determine how many clock cycles are required for the first data of each burst access(Latency Count), how many words the device outputs at an access(Burst Length) and which type of burst operation(Burst Type : Linear or Interleave) is needed. The Wait Polarity should also be determined.(See Table "Mode Register Set") Asynchronous Write Operation Asynchronous write operation starts when CS, WE and UB or LB are driven to VIL under the valid address.(MRS and OE should be driven to VIH during the asynchronous write operation.) Clock, ADV, WAIT signals are ignored during the asynchronous (page) read operation. Synchronous Burst Read Operation The Synchronous Burst Read command is implemented when the clock rising is detected during the ADV low pulse. ADV and CS should be set up before the clock rising. During Read command, WE should be held in VIH. The multiple clock risings(during low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be out with Latency count and tCD. Synchronous Burst Write Operation The Synchronous Burst Write command is implemented when the clock rising is detected during the ADV and WE low pulse. ADV, WE and CS should be set up before the clock rising. The multiple clock risings(during low ADV period) are allowed but the burst operation starts from the first clock rising. The first data will be written in the Latency clock with tDS. Fig.6 ASYNCHRONOUS 4-PAGE READ A22~A2 Fig.8 SYNCHRONOUS BURST READ(Latency 5, BL 4, WP : Low Enable) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK ADV A1~A0 Addr. CS CS UB, LB OE OE Data out Data out WAIT UB, LB Fig.7 ASYNCHRONOUS WRITE Address Fig.9 SYNCHRONOUS BURST WRITE(Latency 5, BL 4, WP : Low Enable) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK ADV CS Addr. UB, LB CS UB, LB WE Data in High-Z WE Data in Data out High-Z High-Z WAIT 70 Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST OPERATION TERMINOLOGY Clock(CLK) Preliminary Preliminary MCP MEMORY The clock input is used as the reference for synchronous burst read and write operation of UtRAM. The synchronous burst read and write operation is synchronized to the rising edge of the clock. The clock transitions must swing between VIL and VIH. Latency Count The Latency Count configuration tells the device how many clocks must elapse from the burst command before the first data should be available on its data pins. This value depends on the input clock frequency. The supported Latency Count is as follows. Table 9. Latency Count support : 3, 4, 5 Clock Frequency Latency Count Table 10. Number of Clocks for 1st Data Set Latency # of Clocks for 1st data(Read) # of Clocks for 1st data(Write) Fig.10 Latency Configuration(Read) T Upto 66MHz 5 Upto 54MHz 4 Upto 52.9MHz 3 Latency 3 4 2 Latency 4 5 3 Latency 5 6 4 Clock ADV Address Latency 3 Data out Latency 4 Data out Latency 5 Data out Latency 6 Data out DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 NOTE : The first data will always keep the Latency. From the second data, some period of wait time might be caused by WAIT pin. Burst Length Burst Length identifies how many data the device outputs at an access. The device supports 4 word, 8 word, 16 word and 256 word burst read or write. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. The first data will be out with the set Latency + tCD. From the second data, the data will be out with tCD from each clock. Burst Stop Burst stop is used when the system wants to stop burst operation on special purpose. If driving CS to VIH during the burst read operation, then the burst operation will be stopped. During the burst read operation, the new burst operation can not be issued. The new burst operation can be issued only after the previous burst operation is finished. The burst stop feature is very useful because it enables the user to utilize the un-supported burst length such as 1 burst or 2 burst which accounts for big portion in usage for the mobile handset application environment. 71 Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST OPERATION TERMINOLOGY WAIT Control(WAIT) Preliminary Preliminary MCP MEMORY The WAIT signal is the device's output signal which indicates to the host system when the device's data-out or data-in is valid. To be compatible with the Flash interfaces of various microprocessor types, the WAIT polarity(WP) can be configured. The polarity can be programmed to be either low enable or high enable. For the timing of WAIT signal, the WAIT signal should be set active one clock prior to the data regardless of Read or Write cycle. Fig.11 WAIT Control and Read/Write Latency Control(LATENCY : 5, Burst Length : 4, WP : Low Enable) 0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 ADV Latency 5 CS Read Data out WAIT Write Data in WAIT DQ0 DQ1 DQ2 DQ3 High-Z Latency 5 D0 D1 D2 D3 High-Z Burst Type The device supports Linear type burst sequence and Interleave type burst sequence. Linear type burst sequentially increments the burst address from the starting address. The detailed Linear and Interleave type burst address sequence is shown in burst sequence table in next page. 72 Revision 1.0 November 2004 K5L5628JT(B)M Table 11. Burst Sequence Burst Address Sequence(Decimal) Start Addr. Wrap1) 4 word Burst Linear 0 1 2 3 4 5 6 7 ~ 14 15 ~ 255 1. Wrap : Burst Address wraps within word boundary and ends after fulfilled the burst length. 2. 256 word Full page burst mode needs to meet tBC(Burst Cycle time) parameter as max. 2500ns. 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 Interleave 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 8 word Burst Linear 0-1-...-5-6-7 1-2-...-6-7-0 2-3-...-7-0-1 3-4-...-0-1-2 4-5-...-1-2-3 5-6-...-2-3-4 6-7-...-3-4-5 7-0-...-4-5-6 Interleave 0-1-2-...-6-7 1-0-3-...-7-6 2-3-0-...-4-5 3-2-1-...-5-4 4-5-6-...-2-3 5-4-7-...-3-2 6-7-4-...-0-1 7-6-5-...-1-0 16 word Burst Linear 0-1-2-...-14-15 1-2-3-...-15-0 2-3-4-...-0-1 3-4-5-...-1-2 4-5-6-...-2-3 5-6-7-...-3-4 6-7-8-...-4-5 7-8-9-...-5-6 ~ 14-15-0-...-12-13 15-0-1-...-13-14 Interleave Preliminary Preliminary MCP MEMORY Full Page(256 word) Linear 0-1-2-...-254-255 1-2-3-...-255-0 2-3-4-...-255-0-1 3-4-5-...-255-0-1-2 4-5-6-...-255-0-1-2-3 5-6-7-...-255-...-3-4 6-7-8-...-255-...-4-5 7-8-9-...-255-...-5-6 ~ 14-15-...-255-...-12-13 15-16-...-255-...-13-14 ~ 255-0-1-...-253-254 0-1-2-3-4...14-15 1-0-3-2-5...15-14 2-3-0-1-6...12-13 3-2-1-0-7...13-12 4-5-6-7-0...10-11 5-4-7-6-1...11-10 6-7-4-5-2...8-9 7-6-5-4-3...9-8 ~ 14-15-12-...-0-1 15-14-13-...-1-0 73 Revision 1.0 November 2004 K5L5628JT(B)M LOW POWER FEATURES Internal TCSR The internal Temperature Compensated Self Refresh(TCSR) feature is a very useful tool for reducing standby current in room temperature(below 40C). DRAM cell has weak refresh characteristics in higher temperature. So high temperature requires more refresh cycles, which lead to standby current increase. Without internal TCSR, the refresh cycle should be set as worst condition so as to cover high temperature(85C) refresh characteristics. But with internal TCSR, the refresh cycle below 40C can be optimized, so the standby current in room temperature can be highly reduced. This feature is really beneficial to mobile phone because most of mobile phones are used at below 40C in the phone standby mode. Fig.13 PAR MODE EXECUTION and EXIT 0.5s MRS Preliminary Preliminary MCP MEMORY Driver Strength Optimization The optimization of output driver strength is possible through the mode register setting to adjust for the different data loadings. Through this driver strength optimization, the device can minimize the noise generated on the data bus during read operation. The device supports full drive, 1/2 drive and 1/4 drive. Partial Array Refresh(PAR) mode The PAR mode enables the user to specify the active memory array size. UtRAM consists of 4 blocks and user can select 1 block, 2 blocks, 3 blocks or all blocks as active memory array through Mode Register Setting. The active memory array is periodically refreshed whereas the disabled array is not going to be refreshed and so the previously stored data will get lost. Even though PAR mode is enabled through the Mode Register Setting, PAR mode execution by MRS pin is still needed. The normal operation can be executed even in refresh-disabled array as long as MRS pin is not driven to low for over 0.5s. Driving MRS pin to high makes the device to get back to the normal operation mode from PAR executed mode, Refer to Fig.13 and Table 12 for PAR operation and PAR address mapping. Normal Operation MODE Suspend PAR mode Normal Operation CS Table 12. PAR MODE CHARACTERISTIC Power Mode Standby(Full Array) Partial Refresh(3/4 Block) Partial Refresh(1/2 Block) Partial Refresh(1/4 Block) Address (Bottom Array)2) 000000h ~ 7FFFFFh 000000h ~ 5FFFFFh 000000h ~ 3FFFFFh 000000h ~ 1FFFFFh Address (Top Array)2) 000000h ~ 7FFFFFh 200000h ~ 7FFFFFh 400000h ~ 7FFFFFh 600000h ~ 7FFFFFh Memory Standby3) Standby3) Cell Data (ISB1, <40C) (ISB1, <85C) Valid1) Valid1) Valid1) Valid1) 130A 125A 120A 115A 250A 235A 220A 205A Wait Time(s) 0 0 0 0 1. Only the data in the refreshed block are valid 2. PAR Array can be selected through Mode Register Set(See Page 66) 3. Standby mode is supposed to be set up after at least one active operation.after power up. ISB1 is measured after 60ms from the time when standby mode is set up. 74 Revision 1.0 November 2004 K5L5628JT(B)M Table 14. ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Power supply voltage relative to Vss Output power supply voltage relative to Vss Power Dissipation Storage temperature Operating Temperature Symbol VIN, VOUT VCC VCCQ PD TSTG TA Ratings Preliminary Preliminary MCP MEMORY Unit V V V W C C -0.2 to VCC+0.3V -0.2 to 3.0V -0.2 to 2.5V 1.0 -65 to 150 -30 to 85 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to be used under recommended operating condition. Exposure to absolute maximum rating conditions longer than 1 second may affect reliability. Table 15. RECOMMENDED DC OPERATING CONDITIONS1) Item Power supply voltage I/O power supply voltage Ground Input high voltage Input low voltage 1. TA=-30 to 85C, otherwise specified. 2. Overshoot: VCC+1.0V in case of pulse width 20ns. 3. Undershoot: -1.0V in case of pulse width 20ns. 4. Overshoot and undershoot are sampled, not 100% tested. Symbol VCC VCCQ Vss VIH VIL Min 2.5 1.7 0 0.8 x VCCQ -0.23) Typ 2.6 1.85 0 - Max 2.7 2.0 0 VCCQ+0.22) 0.4 Unit V V V V V 75 Revision 1.0 November 2004 K5L5628JT(B)M Table 16. CAPACITANCE1)(f=1MHz, TA=25C) Item Input capacitance Input/Output capacitance 1. Capacitance is sampled, not 100% tested. Preliminary Preliminary MCP MEMORY Symbol CIN CIO Test Condition VIN=0V VIO=0V Min - Max 8 10 Unit pF pF Table 17. DC AND OPERATING CHARACTERISTICS Item Input Leakage Current Output Leakage Current Average Operating Current(Async) Average Operating Current(Sync) Output Low Voltage Output High Voltage Standby Current(CMOS) Symbol Test Conditions VIN=Vss to VCCQ CS=VIH, MRS=VIH, OE=VIH or WE=VIL, VIO=Vss to VCCQ Cycle time=tRC+3tPC, IIO=0mA, 100% duty, CS=VIL, MRS=VIH, VIN=VIL or VIH Burst Length 4, Latency 3, 52.9MHz, IIO=0mA, Address transition 1 time, CS=VIL, MRS=VIH, VIN=VIL or VIH IOL=0.1mA IOH=-0.1mA CSVCCQ-0.2V, MRSVCCQ-0.2V, Other inputs=Vss to VCCQ < 40C < 85C 3/4 Block < 40C 1/2 Block 1/4 Block 3/4 Block < 85C 1/2 Block 1/4 Block Min -1 -1 1.4 - Typ - Max 1 1 40 40 0.2 130 250 125 120 115 235 220 205 Unit A A mA mA V V A A A ILI ILO ICC2 ICC3 VOL VOH ISB12) Partial Refresh Current ISBP1) MRS0.2V, CSVCCQ-0.2V Other inputs=Vss to VCCQ A 1. Full Array Partial Refresh Current(ISBP) is same as Standby Current(ISB1). 2. Standby mode is supposed to be set up after at least one active operation.after power up. ISB1 is measured after 60ms from the time when standby mode is set up. 76 Revision 1.0 November 2004 K5L5628JT(B)M AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) Input pulse level: 0.2 to VCCQ-0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCCQ Output load: CL=30pF Preliminary Preliminary MCP MEMORY Figure 14. AC Output Load Circuit Vtt=0.5 x VCCQ 50 Dout Z0=50 30pF Table 18. ASYNCHRONOUS AC CHARACTERISTICS (VCC=2.5~2.7V, VCCQ=1.7~2.0V, TA=-30 to 85C) Parameter List Common CS High Pulse Width Read Cycle Time Page Read Cycle Time Address Access Time Page Access Time Chip Select to Output Output Enable to Valid Output Async. (Page) Read UB, LB Access Time Chip Select to Low-Z Output UB, LB Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output UB, LB Disable to High-Z Output Output Disable to High-Z Output Output Hold Write Cycle Time Chip Select to End of Write ADV Minimum Low Pulse Width Address Set-up Time to Beginning of Write Async. Write Address Valid to End of Write UB, LB Valid to End of Write Write Pulse Width WE High Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from Write Time 1. tWP(min)=70ns for continuous write operation over 50 times. Symbol Min tCSHP(A) tRC tPC tAA tPA tCO tOE tBA tLZ tBLZ tOLZ tCHZ tBHZ tOHZ tOH tWC tCW tADV tAS tAW tBW tWP tWHP tWR tDW tDH 10 70 25 10 5 5 0 0 0 3 70 60 7 0 60 60 551) 5 0 30 0 Speed Max 70 20 70 35 35 12 12 12 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 77 Revision 1.0 November 2004 K5L5628JT(B)M ASYNCHRONOUS READ TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.15 TIMING WAVEFORM OF ASYNCHRONOUS READ CYCLE (MRS=VIH, WE=VIH, WAIT=High-Z) tRC Address tCSHP(A) CS tAA tCO tOH tCHZ tBA UB, LB tBHZ tOE OE Data out High-Z tOLZ tBLZ tLZ Data Valid tOHZ (ASYNCHRONOUS READ CYCLE) 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. In asynchronous read cycle, Clock, ADV and WAIT signals are ignored. Table 19. ASYNCHRONOUS READ AC CHARACTERISTICS Symbol Min tRC tAA tCO tBA tOE tOH tCSHP(A) 70 3 10 Speed Max 70 70 35 35 ns ns ns ns ns ns ns tOLZ tBLZ tLZ tCHZ tBHZ tOHZ Units Symbol Min 5 5 10 0 0 0 Speed Max 12 12 12 ns ns ns ns ns ns Units 78 Revision 1.0 November 2004 K5L5628JT(B)M ASYNCHRONOUS READ TIMING WAVEFORM Fig.16 TIMING WAVEFORM OF PAGE READ CYCLE(MRS=VIH, WE=VIH, WAIT=High-Z) tRC A22~A2 tAA A1~A0 Valid Address Valid Address Valid Address Valid Address Preliminary Preliminary MCP MEMORY tOH Valid Address tPC tCO CS tBA UB, LB tBHZ tOE OE tLZ High Z tOLZ tBLZ tPA Data Valid Data Valid Data Valid Data Valid tCHZ tOHZ Data out (ASYNCHRONOUS 4 PAGE READ CYCLE) 1. tCHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tCHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. In asynchronous 4 page read cycle, Clock, ADV and WAIT signals are ignored. Table 20. ASYNCHRONOUS PAGE READ AC CHARACTERISTICS Symbol Min tRC tAA tPC tPA tCO tBA tOE 70 25 Speed Max 70 20 70 35 35 ns ns ns ns ns ns ns tOH tOLZ tBLZ tLZ tCHZ tBHZ tOHZ Units Symbol Min 3 5 5 10 0 0 0 Speed Max 12 12 12 ns ns ns ns ns ns ns Units 79 Revision 1.0 November 2004 K5L5628JT(B)M ASYNCHRONOUS WRITE TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.17 TIMING WAVEFORM OF WRITE CYCLE(1)(MRS=VIH, OE=VIH, WAIT=High-Z, WE Controlled) tWC Address tAW tCW CS tBW UB, LB tWP WE tAS tDH tDW Data Valid tWHP tAS tDH tDW Data Valid tWP tBW tWR tCSHP(A) tAW tCW tWR tWC Data in Data out High-Z High-Z (ASYNCHRONOUS WRITE CYCLE - WE Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored. 6. Condition for continuous write operation over 50 times : tWP(min)=70ns Table 21. ASYNCHRONOUS WRITE AC CHARACTERISTICS(WE Controlled) Symbol Min tWC tCW tAW tBW tWP 70 60 60 60 55 1) Speed Max - Units ns ns ns ns ns Symbol Min tAS tWR tDW tDH tCSHP(A) 0 0 30 0 10 Speed Max - Units ns ns ns ns ns 1. tWP(min)=70ns for continuous write operation over 50 times. 80 Revision 1.0 November 2004 K5L5628JT(B)M ASYNCHRONOUS WRITE TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.18 TIMING WAVEFORM OF WRITE CYCLE(2)(MRS=VIH, OE=VIH, WAIT=High-Z, UB & LB Controlled) tWC Address tCW CS tAW tBW UB, LB tAS tWP WE tDW Data in Data Valid tDH tWR Data out High-Z High-Z (ASYNCHRONOUS WRITE CYCLE - UB & LB Controlled) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high or WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR is applied in case a write ends with CS or WE going high. 5. In asynchronous write cycle, Clock, ADV and WAIT signals are ignored. Table 22. ASYNCHRONOUS WRITE AC CHARACTERISTICS(UB & LB Controlled) Symbol Min tWC tCW tAW tBW tWP 70 60 60 60 55 1) Speed Max - Units ns ns ns ns ns Symbol Min tAS tWR tDW tDH 0 0 30 0 Speed Max - Units ns ns ns ns 1. tWP(min)=70ns for continuous write operation over 50 times. 81 Revision 1.0 November 2004 K5L5628JT(B)M AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) Input pulse level: 0.2 to VCCQ-0.2V Input rising and falling time: 3ns Input and output reference voltage: 0.5 x VCCQ Output load: CL=30pF Preliminary Preliminary MCP MEMORY Figure 24. AC Output Load Circuit Vtt=0.5 x VCCQ 50 Dout Z0=50 30pF Table 28. SYNCHRONOUS AC CHARACTERISTICS (VCC=2.5~2.7V, VCCQ=1.7~2.0V, TA=-30 to 85C, Maximum Main Clock Frequency=52.9MHz) Parameter List Clock Cycle Time Burst Cycle Time Address Set-up Time to ADV Falling(Burst) Address Hold Time from ADV Rising(Burst) ADV Setup Time ADV Hold Time CS Setup Time to Clock Rising(Burst) Burst Operation (Common) Burst End to New ADV Falling Burst Stop to New ADV Falling CS Low Hold Time from Clock CS High Pulse Width ADV High Pulse Width Chip Select to WAIT Low ADV Falling to WAIT Low Clock to WAIT High Chip De-select to WAIT High-Z UB, LB Enable to End of Latency Clock Output Enable to End of Latency Clock UB, LB Valid to Low-Z Output Output Enable to Low-Z Output Burst Read Operation Latency Clock Rising Edge to Data Output Output Hold Burst End Clock to Output High-Z Chip De-select to Output High-Z Output Disable to Output High-Z UB, LB Disable to Output High-Z WE Set-up Time to Command Clock WE Hold Time from Command Clock WE High Pulse Width Burst Write Operation UB, LB Set-up Time to Clock UB, LB Hold Time from Clock Byte Masking Set-up Time to Clock Byte Masking Hold Time from Clock Data Set-up Time to Clock Data Hold Time from Clock Symbol Min T tBC tAS(B) tAH(B) tADVS tADVH tCSS(B) tBEADV tBSADV tCSLH tCSHP tADHP tWL tAWL tWH tWZ tBEL tOEL tBLZ tOLZ tCD tOH tHZ tCHZ tOHZ tBHZ tWES tWEH tWHP tBS tBH tBMS tBMH tDS tDHC 18.9 0 7 5 7 5 7 12 7 5 5 1 1 5 5 3 5 5 5 5 5 7 7 5 3 Speed Max 200 2500 10 10 12 12 12 12 12 12 12 - Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Clock Clock ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 82 Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST OPERATION TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.25 TIMING WAVEFORM OF BASIC BURST OPERATION [Latency=5,Burst Length=4](MRS=VIH) 0 T CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tADVH tADVS ADV tBEADV tAS(B) tAH(B) tBEADV Address Valid Don't Care tCSS(B) CS tBC Data out Undefined DQ0 DQ1 DQ2 DQ3 Data in D0 D1 D2 D3 Burst Command Clock Burst Read End Clock Burst Write End Clock Table 29. BURST OPERATION AC CHARACTERISTICS Symbol Min T tBC tADVS tADVH 18.9 5 7 Speed Max 200 2500 ns ns ns ns tAS(B) tAH(B) tCSS(B) tBEADV Units Symbol Min 0 7 5 7 Speed Max ns ns ns ns Units 83 Valid D0 Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST READ TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.26 TIMING WAVEFORM OF BURST READ CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - CS Toggling Consecutive Burst Read 0 T CLK tADVH tADVS ADV tAS(B) Address Valid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tBEADV tAH(B) Don't Care Valid tCSS(B) CS tBC tCSHP tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 Data out tWL WAIT High-Z tWH tCD Undefined tOH DQ0 DQ1 DQ2 DQ3 tWZ (SYNCHRONOUS BURST READ CYCLE - CS Toggling Consecutive Burst Read) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s. Table 30. BURST READ AC CHARACTERISTICS(CS Toggling Consecutive Burst) Symbol Min tCSHP tBEL tOEL tBLZ tOLZ tHZ tCHZ 5 1 1 5 5 Speed Max 12 12 ns clock clock ns ns ns ns tOHZ tBHZ tCD tOH tWL tWH tWZ Units Symbol Min 3 Speed Max 12 12 12 10 12 12 ns ns ns ns ns ns ns Units 84 tBHZ tOHZ tCHZ tHZ tWL tWH Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST READ TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.27 TIMING WAVEFORM OF BURST READ CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - CS Low Holding Consecutive Burst Read 0 T CLK tADVH tADVS ADV tBEADV tAS(B) Address Valid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tAH(B) Don't Care Valid tCSS(B) CS tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 Data out tWL WAIT High-Z tBC tCD Undefined tOH DQ0 DQ1 DQ2 DQ3 tWH (SYNCHRONOUS BURST READ CYCLE - CS Low Holding Consecutive Burst Read) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address. 5. Burst Cycle Time(tBC) should not be over 2.5s. Table 31. BURST READ AC CHARACTERISTICS(CS Low Holding Consecutive Burst) Symbol Min tBEL tOEL tBLZ tOLZ tHZ 1 1 5 5 Speed Max 12 clock clock ns ns ns tCD tOH tWL tAWL tWH Units Symbol Min 3 Speed Max 12 10 10 12 ns ns ns ns ns Units 85 tHZ tAWL tWH Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST READ TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.28 TIMING WAVEFORM OF BURST READ CYCLE(3) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) - Last Data Sustaining 0 T CLK tADVH tADVS ADV tAS(B) Address Valid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tAH(B) Don't Care tCSS(B) CS tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 Data out tWL WAIT High-Z tBC tCD Undefined tOH DQ0 DQ1 DQ2 DQ3 tWH (SYNCHRONOUS BURST READ CYCLE - Last Data Sustaining) 1. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 3. Burst Cycle Time(tBC) should not be over 2.5s. Table 32. BURST READ AC CHARACTERISTICS(Last Data Sustaining) Symbol Min tBEL tOEL tBLZ tOLZ 1 1 5 5 Speed Max clock clock ns ns tCD tOH tWL tWH Units Symbol Min 3 Speed Max 12 10 12 ns ns ns ns Units 86 Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST WRITE TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.29 TIMING WAVEFORM OF BURST WRITE CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH) - CS Toggling Consecutive Burst Write 0 T CLK tADVH tADVS ADV tBEADV tAS(B) Address tCSS(B) CS tBS tBH LB, UB tWEH WE tWES tDS Latency 5 Data in tWL WAIT High-Z tWH tDHC D0 D1 D2 tDHC D3 tWZ tWL tWH Latency 5 D0 tWHP tBMS tBMH Valid 1 2 3 4 5 6 7 8 9 10 11 12 13 tAH(B) Don't Care Valid tBC tCSHP (SYNCHRONOUS BURST WRITE CYCLE - CS Toggling Consecutive Burst Write) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 4. D2 is masked by UB and LB. 5. Burst Cycle Time(tBC) should not be over 2.5s. Table 33. BURST WRITE AC CHARACTERISTICS(CS Toggling Consecutive Burst) Symbol Min tCSHP tBS tBH tBMS tBMH tWES tWEH 5 5 5 7 7 5 5 Speed Max ns ns ns ns ns ns ns tWHP tDS tDHC tWL tWH tWZ Units Symbol Min 5 5 3 Speed Max 10 12 12 ns ns ns ns ns ns Units 87 Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST WRITE TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.30 TIMING WAVEFORM OF BURST WRITE CYCLE(2) [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH) - CS Low Holding Consecutive Burst Write 0 T CLK tADVH tADVS ADV tBEADV tAS(B) Address Valid 1 2 3 4 5 6 7 8 9 10 11 12 13 tAH(B) Don't Care Valid tCSS(B) CS tBC tBS tBH tBMS tBMH LB, UB tWEH WE tWES tDS Latency 5 Data in tWL WAIT High-Z tWH tDHC D0 D1 D2 tDHC D3 tAWL tWH Latency 5 D0 tWHP (SYNCHRONOUS BURST WRITE CYCLE - CS Low Holding Consecutive Burst Write) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 3. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 4. D2 is masked by UB and LB. 5. The consecutive multiple burst read operation with holding CS low is possible through issuing only new ADV and address. 6. Burst Cycle Time(tBC) should not be over 2.5s. Table 34. BURST WRITE AC CHARACTERISTICS(CS Low Holding Consecutive Burst) Symbol Min tBS tBH tBMS tBMH tWES tWEH 5 5 7 7 5 5 Speed Max ns ns ns ns ns ns tWHP tDS tDHC tWL tAWL tWH Units Symbol Min 5 5 3 Speed Max 10 10 12 ns ns ns ns ns ns Units 88 Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST READ STOP TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.31 TIMING WAVEFORM OF BURST READ STOP by CS [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) 0 T CLK tADVH tADVS ADV tBSADV tAS(B) Address Valid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 tAH(B) Don't Care Valid tCSS(B) CS tBEL LB, UB tBLZ OE tOLZ Latency 5 Data tWL tWH WAIT High-Z tOEL tCD Undefined tCSHP tCSLH tOH DQ0 DQ1 tCHZ tWZ High-Z (SYNCHRONOUS BURST READ STOP TIMING) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBSADV should be met 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. The burst stop operation should not be repeated for over 2.5s. Table 35. BURST READ STOP AC CHARACTERISTICS Symbol Min tBSADV tCSLH tCSHP tBEL tOEL tBLZ tOLZ 12 7 5 1 1 5 5 Speed Max ns ns ns clock clock ns ns tCD tOH tCHZ tWL tWH tWZ Units Symbol Min 3 Speed Max 12 12 10 12 12 ns ns ns ns ns ns Units 89 tWL Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST WRITE STOP TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.32 TIMING WAVEFORM OF BURST WRITE STOP by CS [Latency=5,Burst Length=4,WP=Low enable](OE=VIH, MRS=VIH) 0 T CLK tADVH tADVS ADV tAS(B) Address Valid 1 2 3 4 5 6 7 8 9 10 11 12 13 tAH(B) Don't Care tBSADV Valid tCSS(B) CS tBS tBH LB, UB tWEH tWES tDS Latency 5 Data in tWL tWH WAIT High-Z D0 tCSLH tCSHP tWHP WE tDHC D1 tWZ tWL High-Z (SYNCHRONOUS BURST WRITE STOP TIMING) 1. The new burst operation can be issued only after the previous burst operation is finished. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. The burst stop operation should not be repeated for over 2.5s. Table 36. BURST WRITE STOP AC CHARACTERISTICS Symbol Min tBSADV tCSLH tCSHP tBS tBH tWES tWEH 12 7 5 5 5 5 5 Speed Max ns ns ns ns ns ns ns tWHP tDS tDHC tWL tWH tWZ Units Symbol Min 5 5 3 Speed Max 10 12 12 ns ns ns ns ns ns Units 90 Latency 5 D0 tWH D1 D2 Revision 1.0 November 2004 K5L5628JT(B)M SYNCHRONOUS BURST READ SUSPEND TIMING WAVEFORM Preliminary Preliminary MCP MEMORY Fig.33 TIMING WAVEFORM OF BURST READ SUSPEND CYCLE(1) [Latency=5,Burst Length=4,WP=Low enable](WE=VIH, MRS=VIH) 0 T CLK tADVH tADVS ADV tAS(B) Address Valid 1 2 3 4 5 6 7 8 9 10 11 tAH(B) Don't Care tCSS(B) CS tBEL LB, UB tBLZ tOEL OE tOLZ Latency 5 Data out tWL WAIT High-Z tWH tBC tCD Undefined tOHZ DQ0 DQ1 tOLZ High-Z DQ1 tOH tHZ DQ2 DQ3 tWZ (SYNCHRONOUS BURST READ SUSPEND CYCLE) 1. If clock input is halted during burst read operation, the data out will be suspended. During the burst read suspend period, OE high drives data out to high-Z. If clock input is resumed, the suspended data will be out first. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. During suspend period, OE high drives DQ to High-Z and OE low drives DQ to Low-Z. If OE stays low during suspend period, the previous data will be sustained. 4. Burst Cycle Time(tBC) should not be over 2.5s. Table 37. BURST READ SUSPEND AC CHARACTERISTICS Symbol Min tBEL tOEL tBLZ tOLZ tCD tOH 1 1 5 5 3 Speed Max 12 clock clock ns ns ns ns tHZ tOHZ tWL tWH tWZ Units Symbol Min Speed Max 12 12 10 12 12 ns ns ns ns ns Units 91 Revision 1.0 November 2004 K5L5628JT(B)M TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Preliminary Preliminary MCP MEMORY Fig.34 SYNCH. BURST READ to ASYNCH. WRITE(Address Latch Type) TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 0 T CLK tADVS ADV tBEADV tAS(B) Address Valid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 tADVH tADV tAH(A) tAH(B) Don't Care tAS(A) Valid tCSS(B) CS tBC tCSS(A) tWLRL tAW tCW tWP WE tAS tOEL OE tBEL LB, UB tDW Data in Latency 5 Data out High-Z tWL tWH WAIT High-Z High-Z Read Latency 5 (SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s. (ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation. tBW tDH Data Valid tCD tOH DQ0 DQ1 DQ2 DQ3 tHZ High-Z tWZ Table 38. BURST READ to ASYNCH. WRITE(Address Latch Type) AC CHARACTERISTICS Symbol Min tBEADV 7 Speed Max ns tWLRL Units Symbol Min 1 Speed Max clock Units 92 Revision 1.0 November 2004 K5L5628JT(B)M TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Preliminary Preliminary MCP MEMORY Fig.35 SYNCH. BURST READ to ASYNCH. WRITE(Low ADV Type) TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 1 T CLK tADVS ADV tAH(B) Don't Care 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 tADVH tBEADV tAS(B) Address Valid Valid Address tCSS(B) CS tBC tAW tCW tWLRL tWR tWP WE tOEL OE tBEL LB, UB tAS tBW tDW Data in Latency 5 Data out High-Z tWL tWH WAIT High-Z High-Z Read Latency 5 (SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s. tDH Data Valid tCD tOH DQ0 DQ1 DQ2 DQ3 tHZ High-Z tWZ (LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation. Table 39. BURST READ to ASYNCH. WRITE(Low ADV Type) AC CHARACTERISTICS Symbol Min tBEADV 7 Speed Max ns tWLRL Units Symbol Min 1 Speed Max clock Units 93 Revision 1.0 November 2004 K5L5628JT(B)M TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Preliminary Preliminary MCP MEMORY Fig.36 ASYNCH. WRITE(Address Latch Type) to SYNCH. BURST READ TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 0 CLK tADVS ADV tAS(A) Address Valid 1 2 3 4 5 6 7 8 9 10 11 T 12 13 14 15 16 17 18 19 20 tADVH tADV tAH(A) Don't Care tAH(B) tAS(B) Valid Don't Care tAW tCSS(A) CS tCW tWLRL WE tAS tWP tCSS(B) tBC tOEL OE tBW LB, UB tDW Data in tDH tBEL Data Valid Latency 5 tCD tOH DQ0 DQ1 DQ2 DQ3 tHZ Data out High-Z Read Latency 5 High-Z tWL tWH tWZ WAIT (SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s. (ADDRESS LATCH TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation. Table 40. ASYNCH. WRITE(Address Latch Type) to BURST READ AC CHARACTERISTICS Symbol Min tWLRL 1 Speed Max clock Units Symbol Min Speed Max Units 94 Revision 1.0 November 2004 K5L5628JT(B)M TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Preliminary Preliminary MCP MEMORY Fig.37 ASYNCH. WRITE(Low ADV Type) to SYNCH. BURST READ TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 0 CLK tADVS tADHP ADV tWC Address Valid 1 2 3 4 5 6 7 8 9 10 11 T 12 13 14 15 16 17 18 19 20 tADVH tAH(B) tAS(B) Valid Don't Care tAW tCW CS tWLRL tWP WE tAS tWR tCSS(B) tBC tOEL OE tBW LB, UB tDW Data in tDH tBEL Data Valid Latency 5 tCD tOH DQ0 DQ1 DQ2 DQ3 tHZ Data out High-Z tWL tWH tWZ WAIT High-Z Read Latency 5 (SYNCHRONOUS BURST READ CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s. (LOW ADV TYPE ASYNCHRONOUS WRITE CYCLE - WE controlled) 1. Clock input does not have any affect to the write operation if WE is driven to low before Read Latency-1 clock. Read Latency-1 clock in write timing is just a reference to WE low going for proper write operation. Table 41. ASYNCH. WRITE(Low ADV Type) to BURST READ AC CHARACTERISTICS Symbol Min tWLRL 1 Speed Max clock tADHP Units Symbol Min 5 Speed Max ns Units 95 Revision 1.0 November 2004 K5L5628JT(B)M TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Preliminary Preliminary MCP MEMORY Fig.38 SYNCH. BURST READ to SYNCH. BURST WRITE TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 0 T CLK tADVS ADV tAS(B) Address Valid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 tADVH tBEADV tAH(B) Don't Care tAS(B) Valid tAH(B) tCSS(B) CS tBC tWES tCSS(B) tBC tWEH WE tOEL OE tBEL LB, UB Latency 5 Data in Latency 5 Data out tWL WAIT High-Z High-Z tWH tCD High-Z tOH DQ0 DQ1 DQ2 DQ3 D0 D1 D2 tBS tBH tDS tDHC D3 tHZ High-Z tWL tWH tWZ tWZ (SYNCHRONOUS BURST READ & WRITE CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s. Table 42. BURST READ to BURST WRITE AC CHARACTERISTICS Symbol Min tBEADV 7 Speed Max ns Units Symbol Min Speed Max Units 96 Revision 1.0 November 2004 K5L5628JT(B)M TRANSITION TIMING WAVEFORM BETWEEN READ AND WRITE Preliminary Preliminary MCP MEMORY Fig.39 SYNCH. BURST WRITE to SYNCH. BURST READ TIMING WAVEFORM [Latency=5, Burst Length=4](MRS=VIH) 0 T CLK tADVS ADV tAS(B) Address Valid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 tADVH tBEADV tAH(B) Don't Care tAS(B) Valid tAH(B) tCSS(B) CS tWES tWEH WE tBC tCSS(B) tBC tOEL OE tBS tBH LB, UB Latency 5 Data in D0 D1 D2 tBEL tDS tDHC D3 High-Z Latency 5 tCD tOH DQ0 DQ1 DQ2 DQ3 tHZ Data out tWL WAIT High-Z tWH High-Z tWZ tWL tWH (SYNCHRONOUS BURST READ & WRITE CYCLE) 1. The new burst operation can be issued only after the previous burst operation is finished. For the new burst operation, tBEADV should be met. 2. /WAIT Low(tWL or tAWL) : Data not available(driven by CS low going edge or ADV low going edge) /WAIT High(tWH) : Data available(driven by Latency-1 clock) /WAIT High-Z(tWZ) : Data don't care(driven by CS high going edge) 3. Multiple clock risings are allowed during low ADV period. The burst operation starts from the first clock rising. 4. Burst Cycle Time(tBC) should not be over 2.5s. Table 43. BURST WRITE to BURST READ AC CHARACTERISTICS Symbol Min tBEADV 7 Speed Max ns Units Symbol Min Speed Max Units 97 Revision 1.0 November 2004 K5L5628JT(B)M PACKAGE DIMENSION 115-Ball FINE PITCH BGA Package (measured in millimeters) Preliminary Preliminary MCP MEMORY #A1 INDEX MARK 0.10 MAX 8.000.10 (Datum A) 10 9 A #A1 0.450.05 B C D E (Datum B) F G H J 5.20 K L M N P 0.320.05 1.300.10 115- 0.450.05 TOP VIEW 0.20 M A B 8.000.10 0.80x9=7.20 8 76 5 43 0.80 A 2 1 B 0.80 0.80x13=10.40 3.60 BOTTOM VIEW 12.000.10 12.000.10 98 Revision 1.0 November 2004 12.000.10 |
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