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Ordering number : EN5760
CMOS IC
LC7535M
Electronic Volume/Loudness Control with Serial Data Control and High Voltage-Handling Capacity
Overview
The LC7535M is an electronic volume and loudness control IC that provides volume, balance, and loudness functions with a minimal number of external components and that can be controlled electronically.
Feature
* High voltage-handling capacity: 16 V.
Package Dimensions
unit: mm 3216A-MFP30S
[LC7535M]
Functions
* Volume: Provides 81 positions from 0 dB to -79 dB in 1-dB steps and -. A balance function can be implemented by controlling the left and right volume levels independently. * Loudness: A loudness function can be implemented by attaching external capacitors at the output tap provided at the -20-dB position in the 5-dB step volume control. * S (select) pin: Up to two LC7535M chips can be used on the same bus. * Serial data input: The LC7535M supports communication with the controller in the CCB format.
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
SANYO: MFP30S
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol VDD max Maximum supply voltage VEE max VCC max VIN max1 Maximum input voltage VIN max2 VIN max3 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg Conditions VEE VSS < VCC < VDD VEE VSS < VCC < VDD VEE VSS < VCC < VDD CL, DI, CE L5dBIN, R5dBIN, L1dBIN, R1dBIN S Ta 75C Ratings VSS to VSS + 18 VSS - 18 to VSS VSS to VSS + 7 0 to VCC + 0.3 VEE - 0.3 to VDD + 0.3 VCC - 0.3 to VDD + 0.3 250 -30 to +75 -40 to +125 Unit V V V V V V mW C C
Allowable Operating Ranges at Ta = 25C, VSS = 0 V
Parameter Symbol VDD Supply voltage VEE VCC Input high-level voltage VIH1 VIH2 VIL1 VIL2 VDD VEE VCC CL, DI, CE S CL, DI, CE S Conditions Ratings min VCC + 4.5 -16 4.5 0.8 VCC 0.8 x (VDD - VCC) + VCC VSS VCC 5 typ max 16 0 5.5 VCC VDD 0.2 VCC 0.2 x (VDD - VCC) + VCC Unit V V V V V V V
Input low-level voltage
Continued on next page.
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
53098RM (OT) No. 5760-1/9
LC7535M
Continued from preceding page.
Parameter Input voltage amplitude Input pulse width Setup time Hold time Operating frequency Symbol VIN tow tset up thold topg Conditions L5dBIN, R5dBIN, L1dBIN, R1dBIN CL CL, DI, CE CL, DI, CE CL Ratings min VEE 1 1 1 500 typ max VDD Unit Vp-p s s s kHz
Electrical Characteristics at Ta = 25C, VSS = 0 V
Parameter Total harmonic distortion Symbol THD Conditions VIN = 1 Vrms, f = 1 kHz, With all tone control settings flat, VDD - VEE = 30 V VIN = 1 Vrms, f = 1 kHz, With all tone control settings flat, RG = 1 k, VDD - VEE = 30 V VIN = 1 V rms, f = 1 kHz, with the volume set at -, VDD - VEE = 30 V With all tone control settings flat, Rg = 1 k IHF-A, VDD - VEE = 30 V 5-dB volume control block 1-dB volume control block L5dBIN, R5dBIN, LCT1, RCT1, LCT2, RCT2, L5dBOUT, R5dBOUT, L1dBIN, R1dBIN, L1dBOUT, R1dBOUT, LVM, RVM CL, DI, CE : VIN = VCC CL, DI, CE : VIN = VSS VDD = 16 V VCC = 5.5 V -10 1 1 -10 Ratings min typ 0.002 max Unit %
Crosstalk
CT
70
dB
Output at maximum attenuation Output noise voltage Total resistance
VOmin VN Rvol1 Rvol2 IOFF IIH IIL IDD ICC
-95 2 75 20 +10 10 10
dB V k k A A A mA mA
Output off leakage current Input high-level current Input low-level current Current drain
Equivalent Circuit
No. 5760-2/9
LC7535M Sample Application Circuit
Test Circuit Total Harmonic Distortion
With an identical circuit for the right channel
No. 5760-3/9
LC7535M Output Noise Voltage
With an identical circuit for the right channel
Crosstalk
Pin Assignment
No. 5760-4/9
LC7535M Pin Descriptions
Pin No. 2 Pin L5dBIN * 5-dB step attenuator inputs These inputs must be driven by low-impedance circuits. 29 R5dBIN Function Equivalent circuit
3
LCT1
28
RCT1
4
LCT2
* Loudness circuit connections Connect the high-band compensation capacitors between the CT1 and 5dBIN pins, and connect the low band compensation capacitors between the CT2 and the VM pins.
27
RCT2
5
L5dBOUT * 5-dB step attenuator outputs These outputs must be accepted by circuits with an impedance of between 47 k and 1 M.
26
R5dBOUT
7
L1dBIN * 1-dB step attenuator inputs These inputs must be driven by low-impedance circuits.
24
R1dBIN
8
L1dBOUT * 1-dB step attenuator outputs These outputs must be accepted by circuits with an impedance of between 47 k and 1 M.
23
R1dBOUT
9
LVM
22
RVM
* Common connections for the volume control circuit. The impedance of the printed circuit board pattern connected to these pins must be kept as low as possible. Since the LVM, RVM, and VSS pins are not connected internally, they must be connected externally as required by the various specifications. When a single-sided power supply is used, the capacitors between VM and VSS become the residual resistance when the volume control is set at its maximum attenuation. This means that care is required in selecting the values of these capacitors.
12
S
* Selection input for the address code in the data format. If this pin is connected to VDD, data will be accepted when the address code is 9, and if connected to VCC, data will be accepted when the address code is 8.
17 18 19 10 13 14 21 1, 6, 11, 15, 16, 20, 25, 30
CL DI CE VEE VDD VSS VCC
* Input pins for the serial data used to control the device. These inputs must have an amplitude of 0 to 5 V. In applications in which any of microcontroller CL, DI, or CE may go high in backup mode (when VDD = VCC = 0 V), the signal lines must have series resistors of at least 2 k inserted.
* Power supply connections. All these pins must be connected to the corresponding power supply voltage. When power is first applied, the VCC voltage must not rise before VDD.
NC
* Unconnected (NC) pins Do not connect any signals or devices to these pins.
No. 5760-5/9
LC7535M Control System Timing and Data Format The stipulated serial data must be input to the CL, DI, and CE pins to control the LC7535M. The data consists of a total of 20 bits, of which 4 bits are address and 16 bits are data.
Left channel 1-dB step control (identical to the right channel) Left channel 5-dB step control (identical to the right channel) Address code S pin Right channel 5-dB step control Set state Loudness 1: On 0: Off
Right channel 1-dB step control Set state
Dummy *
Note *: To minimize switching noise, applications should input dummy data in the following sequence: -79 dB dummy -
No. 5760-6/9
LC7535M Loudness Characteristics
VSS = VM = 0 V, loudness on
Volume Step Characteristics
Volume attenuation -- dB
Output level -- dB
Overall
Frequency, f -- Hz
Step -- dB
THD - Frequency Characteristics (1)
Total harmonic distortion, THD -- % Total harmonic distortion, THD -- %
THD - Frequency Characteristics (2)
80-kHz low-pass weighting
80-kHz low-pass weighting
Volume control set to -20 dB
Volume control set to -10 dB
Volume control set to 0 dB
Volume control set to 0 dB
Frequency, f -- Hz
Frequency, f -- Hz
No. 5760-7/9
LC7535M THD - Power-Supply Voltage Characteristics (1)
Total harmonic distortion, THD -- % Total harmonic distortion, THD -- %
THD - Power-Supply Voltage Characteristics (2)
80-kHz low-pass weighting Flat overall
Volume control set to -20 dB 80-kHz low-pass weighting
Power-supply voltage, VDD - VEE -- V
Power-supply voltage, VDD - VEE -- V
THD - Input Level Characteristics (1)
Total harmonic distortion, THD -- % Total harmonic distortion, THD -- %
THD - Input Level Characteristics (2)
80-kHz low-pass weighting Flat overall
80-kHz low-pass weighting Volume control set to -20 dB
Input level, VIN - dBV
Input level, VIN - dBV
No. 5760-8/9
LC7535M
THD - Output Level Characteristics (1)
Total harmonic distortion, THD -- % Total harmonic distortion, THD -- %
THD - Output Level Characteristics (2)
80-kHz low-pass weighting Flat overall
80-kHz low-pass weighting Volume control set to -20 dB
Output level, VO - dBV
Output level, VO - dBV
Usage Notes * The state of the internal analog switches are undefined when power is first applied. Applications should apply external muting to the output signal until the control data has been set up. * To prevent the high-frequency digital signals transmitted over the CL, DI, and CE pin lines from entering the analog signal system, these lines should either be covered by the ground pattern or shielded cables should be used.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of May, 1998. Specifications and information herein are subject to change without notice. PS No. 5760-9/9

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