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Advance Data Sheet March 26, 2004
LCK4972 Low-Voltage PLL Clock Driver
1 Features
s s s s s s s
2 Description
Agere Systems' LCK4972 is a 3.3 V/2.5 V, PLL-based clock driver designed for high-performance RISC or CISC processor-based systems. The LCK4972 has output frequencies of up to 240 MHz and skews of less than 250 ps, making it ideal for synchronous systems. The LCK4972 contains 12 low-skew outputs and a feedback/sync output for flexibility and simple implementation. There is a robust level of frequency programmability between the 12 low-skew outputs in addition to the input/ output relationships. This allows for very flexible programming of the input reference versus the output frequency. The LCK4972 contains a flexible output enable and disable scheme. This helps execute system debug as well as offer multiple powerdown schemes, which meet green-class machine requirements. The LCK4972 features a power-on reset function, which automatically resets the device on powerup, providing automatic synchronization between QFB and other outputs. The LCK4972 is 3.3 V/2.5 V compatible and requires no external loop filters. It has the capability of driving 50 transmission lines. Series terminated lines have the ability of driving two 50 lines in parallel, effectively doubling the fanout.
Fully integrated PLL Output frequency up to 240 MHz 150 ps typical cycle-to-cycle jitter Output skews of less than 250 ps Single 3.3 V/2.5 V 5% supply 52-pin TQFPT Compatible with PowerPC (R) and Pentium (R) microprocessors Pin compatible with 972 type devices
s
LCK4972 Low-Voltage PLL Clock Driver
Advance Data Sheet March 26, 2004
Table of Contents Contents Page
1 Features .............................................................................................................................................................................1 2 Description ..........................................................................................................................................................................1 3 Pin Information ...................................................................................................................................................................4 3.1 Pin Diagram .................................................................................................................................................................4 4 Functional Description ........................................................................................................................................................7 4.1 Device Programming ...................................................................................................................................................8 4.2 Application Examples ..................................................................................................................................................9 4.3 Typical Skew Example ................................................................................................................................................9 4.4 SYNC Output .............................................................................................................................................................10 4.5 Output Freeze Circuitry .............................................................................................................................................12 4.6 On-Board Crystal Oscillator .......................................................................................................................................12 4.7 Power Supply Filtering ...............................................................................................................................................13 4.8 Driving Transmission Lines .......................................................................................................................................14 5 Absolute Maximum Ratings ..............................................................................................................................................15 5.1 Handling Precautions ................................................................................................................................................15 5.2 Thermal Parameters (Definitions and Values) ...........................................................................................................15 6 Electrical Characteristics ..................................................................................................................................................17 6.1 dc Characteristics ......................................................................................................................................................17 6.2 ac Characteristics ......................................................................................................................................................18 7 Outline Diagram ................................................................................................................................................................19 8 Ordering Information .........................................................................................................................................................20
Figures
Page
Figure 2-1. Logic Diagram ......................................................................................................................................................4 Figure 3-1. 52-Pin TQFPT ......................................................................................................................................................5 Figure 4-1. 100 MHz from 50 MHz Example ........................................................................................................................10 Figure 4-2. Pentium Compatible Clocks Example ................................................................................................................10 Figure 4-3. 20 MHz Source Example ...................................................................................................................................10 Figure 4-4. Skew Relative to Qa...........................................................................................................................................10 Figure 4-5. Phase Delay Example Using Two LCK4972s ....................................................................................................11 Figure 4-6. LCK4972 Timing ................................................................................................................................................12 Figure 4-7. Freeze Data Input Protocol ................................................................................................................................13 Figure 4-8. Power Supply Filter ............................................................................................................................................14 Figure 4-9. Dual Transmission Lines....................................................................................................................................15 Figure 4-10. Single vs. Dual Waveforms ..............................................................................................................................15 Figure 4-11. Optimized Dual Transmission Lines.................................................................................................................15
Tables
Page
Table 3-1. Pin Description.......................................................................................................................................................5 Table 4-1. Function Table for Qa, Qb, and Qc ........................................................................................................................7 Table 4-2. Function Table for QFB..........................................................................................................................................7 Table 4-3. Function Table for Logic Selection.........................................................................................................................7 Table 4-4. Programmable Output Frequency Relationships for Qa, Qb, and Qc (VCO_Sel = 1) ...........................................8 Table 4-5. Programmable Output Frequency Relationships for QFB (VCO_Sel = 1).............................................................8 Table 4-6. Crystal Recommendations...................................................................................................................................12 Table 5-1. Absolute Maximum Ratings .................................................................................................................................15 Table 5-2. ESD Tolerance.....................................................................................................................................................15 Table 5-3. Thermal Parameter Values ..................................................................................................................................16 Table 6-1. PLL Input Reference Characteristics (TA = -40 C to +85 C) ............................................................................17 Table 6-2. dc Characteristics (TA = -40 C to+85 C, VDD = 3.3 V 5%) ...........................................................................17 Table 6-3. dc Characteristics (TA = -40 C to +85 C, VDD = 2.5 V 5%) ..........................................................................17 Table 6-4. ac Characteristics (TA = -40 C to +85 C, VDD = 3.3 V/2.5 V 5%).................................................................18 Table 8-1. LCK4972 Ordering Information............................................................................................................................20 2 Agere Systems Inc.
Advance Data Sheet March 26, 2004
LCK4972 Low-Voltage PLL Clock Driver
xtal1 xtal2 VCO_Sel PLL_EN REF_SEL
DQ
TCLK0 TCLK1 TCLK_Sel Ext_FB
0 1 PHASE DETECTOR LPF VCO
0 1
SYNC Frz
Qa0 Qa1 Qa2 Qa3
DQ
SYNC Frz
Qb0 Qb1 Qb2 Qb3
fselFB2
MR/OE
POWER-ON RESET /4, /6, /8, /12 /4, /6, /8, /10 /2, /4, /6, /8
DQ SYNC Frz DQ SYNC Frz
Qc0 Qc1 Qc2 Qc3 QFB
fsela0:1 fselb0:1 fselc0:1 fselFB0:1
2 /4, /6, /8, /10 2 2 2 SYNC PULSE DATA GENERATOR /2
0 DQ 1
DQ
SYNC Frz
QSync
Frz_Clk
OUTPUT DISABLE CIRCUITRY
Frz_Data Inv_Clk
12
2332 (F)
Figure 2-1. Logic Diagram
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LCK4972 Low-Voltage PLL Clock Driver
Advance Data Sheet March 26, 2004
3 Pin Information
3.1 Pin Diagram
VCO_Sel
fsela0
fsela1
fselb0 41
52 VSS MROEB Frz_Clk Frz_Data fselFB2 PLL_EN Ref_Sel TCLK_Sel TCLK0 TCLK1 xtal1 xtal2 VDDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Inv_Clk
51
50
49
48
47
46
45
44
43
42
40 39 38 37 36 35 34 VSS Qb0 VDDO Qb1 VSS Qb2 VDDO Qb3 Ext_FB VSS QFB VDDI fselFB0
LCK4972
15 VSS
16 Qc3
17 VDDO
18 Qc2
19 fselc1
20 fselc0
21 Qc1
22 VDDO
23 Qc0
24 VSS
25 QSync
26 fselFB1
fselb1 33 32 31 30 29 28 27
VDDO
VDDO
Qa0
Qa1
Qa2
Qa3
VSS
VSS
2331 (F)
Figure 3-1. 52-Pin TQFPT
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Advance Data Sheet March 26, 2004
Table 3-1. Pin Description Pin 1, 15, 24, 30, 35, 39, 47, 51 2 Symbol VSS MROEB Type Ground LVTTL I/O* -- Ground.
LCK4972 Low-Voltage PLL Clock Driver
Description
3 4 5
Frz_Clk Frz_Data fselFB2
LVTTL LVTTL LVTTL
6
PLL_EN
LVTTL
7
Ref_Sel
LVTTL
8
TCLK_Sel
LVTTL
9, 10 11 12 13 14
TCLK[0:1] xtal1 xtal2 VDDA Inv_Clk
LVTTL Analog Analog Power LVTTL
16, 18, 21, 23
Qc[3:0]
LVTTL
17, 22, 33, 37, 45, 49 19, 20
VDDO fselc[1:0]
Power LVTTL
Master Reset and Output Enable Input. 0 = Outputs disabled (high-impedance state). During this condition the PLL loop is open and the VCO will run at an indeterminate frequency. 1 = Normal operation (outputs active). I Freeze Mode. I Freeze Mode. Iu Feedback Output Divider Function Select. This input, along with pins fselFB0 and fselFB1, controls the divider function of the feedback bank of outputs. See Table 4-2 for more details. Iu PLL Bypass Select. 0 = The internal PLL is bypassed and the selected reference input provides the clocks to operate the device. 1 = The internal PLL provides the internal clocks to operate the device. Iu Reference Select Input. The Ref_Sel input controls the reference input to the PLL. 0 = The input is selected by the TCLK_Sel input. 1 = The XTAL is selected. Iu TCLK Select Input. The TCLK_Sel input controls which TCLK input will be used as the reference input if Ref_Sel is set to 0. 0 = TCLK0 is selected. 1 = TCLK1 is selected. I LVTLL Reference Input. These inputs provide the reference frequency for the internal PLL when selected by Ref_Sel and TCLK_Sel. I Xtal Reference Input. This input provides the reference frequency for the internal PLL when selected by Ref_Sel. I Xtal Reference Input. This input provides the reference frequency for the internal PLL when selected by Ref_Sel. -- PLL Power. Iu Invert Mode. This input only affects the Qc bank. 0 = All outputs of the Qc bank are in the normal phase alignment. 1 = Qc2 and Qc3 are inverted from the normal phase of Qc0 and Qc1. O Clock Output. These outputs, along with the Qa[0:3], Qb[0:3], and QFB outputs, provide numerous divide functions determined by the fsela[0:3], fselb[0:3], and the fselFB[0:2] See Table 4-1 and Table 4-2 for more details. -- Output Buffer Power. Iu Output Divider Function Select. Each pair controls the divider function of the respective bank of outputs. See Table 4-1 for more details.
Iu
* U = Internal pull-up resistors (50 k).
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LCK4972 Low-Voltage PLL Clock Driver
Table 3-1. Pin Description (continued) Pin 25 26 Symbol QSync fselFB1 Type LVTTL LVTTL I/O* O Description
Advance Data Sheet March 26, 2004
27
fselFB0
LVTTL
28 29
VDDI QFB
Power LVTTL
31 32, 34, 36, 38
Ext_FB Qb[3:0]
LVTTL LVTTL
40, 41 42, 43 44, 46, 48, 50
fselb[1:0] fsela[1:0] Qa[3:0]
LVTTL LVTTL LVTTL
52
VCO_Sel
LVTTL
Synchronous Pulse Output. This output is used for system synchronization. See Section 4.4 on page 10. u Feedback Output Divider Function Select. This input, along with pins I fselFB1 and fselFB2, controls the divider function of the feedback bank of outputs. See Table 4-2 for more details. Iu Feedback Output Divider Function Select. This input, along with pins fselFB0 and fselFB2, controls the divider function of the feedback bank of outputs. See Table 4-2 for more details. -- PLL Power. O Clock Output. This output, along with the Qa[0:3] and Qc[0:3] outputs, provides numerous divide functions determined by the fsela[0:3], fselb[0:3], and the fselFB[0:2]. See Table 4-1 and Table 4-2 for more details. I PLL Feedback Input. This input is used to connect one of the clock outputs (usually QFB) to the feedback input of the PLL. O Clock Output. These outputs, along with the Qa[0:3], Qc[0:3], and QFB outputs, provide numerous divide functions determined by the fsela[0:3], fselb[0:3], and the fselFB[0:2]. See Table 4-1 and Table 4-2 for more details. I Output Divider Function Select. Each pair controls the divider function of the respective bank of outputs. See Table 4-1 for more details. I Output Divider Function Select. Each pair controls the divider function of the respective bank of outputs. See Table 4-1 for more details. O Clock Output. These outputs, along with the Qb[0:3], Qc[0:3], and QFB outputs, provide numerous divide functions determined by the fsela[0:3], fselb[0:3], and the fselFB[0:2]. See Table 4-1 and Table 4-2 for more details. Iu VCO Frequency Select Input. This input selects the nominal operating range of the VCO used in the PLL. 0 = The VCO range is 150 MHz--240 MHz. 1 = The VCO range is 200 MHz--480 MHz.
* U = Internal pull-up resistors (50 k).
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Advance Data Sheet March 26, 2004
LCK4972 Low-Voltage PLL Clock Driver
4 Functional Description
Using the select lines (fsela[1:0], fselb[1:0], fselc[1:0], and fselFB[2:0]), the following output frequency ratios between outputs can be obtained: 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1, and 6:5 These ratios can be achieved by forcing the control signal low one clock edge before the coincident edges of outputs Qa and Qc. The synchronization output indicates when these rising edges will occur. Selectability of feedback frequency is independent of the output frequencies. Output frequencies can be odd or even multiples of the input reference clock, as well as being less than the input frequency. The power-on reset function is designed to reset the system after powerup for synchronization between QFB and other outputs. The LCK4972 has the ability to independently enable/disable each output through a serial input port. When disabled (frozen), the outputs will freeze to the low state while internal state machines remain unaffected. When re-enabled, the outputs initialize synchronously and in phase with those not reactivated. Freezing only happens when the outputs are in the low state, preventing runt pulse generation, see Section 4.5 Output Freeze Circuitry on page 12. Table 4-1. Function Table for Qa, Qb, and Qc fsela1 0 0 1 1 fsela0 0 1 0 1 Qa /4 /6 /8 /12 fselb1 0 0 1 1 fselb0 0 1 0 1 Qb /4 /6 /8 /10 fselc1 0 0 1 1 fselc0 0 1 0 1 Qc /2 /4 /6 /8
Table 4-2. Function Table for QFB fselFB21 0 0 0 0 1 1 1 1 fselFB1 0 0 1 1 0 0 1 1 fselFB0 0 1 0 1 0 1 0 1 QFB /4 /6 /8 /10 /8 /12 /16 /20
1. If fselFB2 is set to 1, it may be necessary to apply a reset pulse after powerup in order to ensure synchronization between the QFB and other inputs.
Table 4-3. Function Table for Logic Selection Control Pin VCO_Sel Ref_Sel TCLK_Sel PLL_EN MR/OE Inv_Clk Logic 0 VCO/2 TCLK TCLK0 Bypass PLL Master reset/output high-Z Noninverted Qc2, Qc3 Logic 1 VCO Xtal TCLK1 Enable PLL Enable outputs Inverted Qc2, Qc3
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LCK4972 Low-Voltage PLL Clock Driver
4.1 Device Programming
Advance Data Sheet March 26, 2004
The LCK4972 contains three independent banks of four outputs as well as an independent PLL feedback output. The possible configurations make Agere Systems' LCK4972 one of the most versatile frequency programming devices. Table 4-4 shows various selection possibilities. Table 4-4. Programmable Output Frequency Relationships for Qa, Qb, and Qc (VCO_Sel = 1) fselb1 fselb0 fsela1 fsela0 fselc1 Qa VCO/4 VCO/6 VCO/8 VCO/12 Qb VCO/4 VCO/6 VCO/8 VCO/10 fselc0 Qc VCO/2 VCO/4 VCO/6 VCO/8
0 0 1 1
0 1 0 1
0 0 1 1
0 1 0 1
0 0 1 1
0 1 0 1
Table 4-5. Programmable Output Frequency Relationships for QFB (VCO_Sel = 1) fselFB2 0 0 0 0 1 1 1 1 fselFB1 0 0 1 1 0 0 1 1 fselFB0 0 1 0 1 0 1 0 1 QFB VCO/4 VCO/6 VCO/8 VCO/10 VCO/8 VCO/12 VCO/16 VCO/20
To determine the relationship between the three banks, compare their divide ratios. For example, if a ratio of 5:3:2 is desired, set Qa to /10, Qb to /6, and Qc to /4. These selections would yield a 5:3:2 ratio. For low frequency circumstances, the VCO_Sel pin allows the option of an additional /2 to be added to the clock path. This pin maintains the output relationships, but provides an extended clock range for the PLL. The feedback output is matched to the input reference frequency after the output frequency relationship is set and VCO is in a stable range. If, in the previous example, the input reference frequency were equal to the lowest output frequency, the output would be set to /10 mode. The fselFB2 input could be asserted to half the frequency if the needed feedback frequency is half of the lowest frequency output. This multiplies the output frequencies by a factor of two, relative to the input reference frequency. Assume the previously mentioned 5:3:2 ratio with the highest output frequency of 100 MHz. If the only available reference frequency is 50 MHz, the setup of Figure 4-1 can be used. The device provides 100 MHz, 66 MHz, and 40 MHz outputs, all generated from the 50 MHz source. Figure 4-2 and Figure 4-3 also show possible configurations of the LCK4972.
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Advance Data Sheet March 26, 2004
4.2 Application Examples
0 0 1 1 0 1 0 1 0 50 MHz fsela0 LCK4972 fsela1 Qa fselb0 fselb1 Qb fselc0 fselc1 Qc fselFB0 fselFB1 QFB fselFB2 Input Ref Ext_FB 4 4 4 0 0 0 0 1 1 1 1 0 24 MHz
LCK4972 Low-Voltage PLL Clock Driver
100 MHz 40 MHz 66.66 MHz 50 MHz
fsela0 LCK4972 fsela1 Qa fselb0 fselb1 Qb fselc0 fselc1 Qc fselFB0 fselFB1 QFB fselFB2 Input Ref Ext_FB
4 4 4
60 MHz (PROCESSOR) 60 MHz (PROCESSOR) 30 MHz (PCI) 24 MHz (FLOPPY DISK CLK)
VCO = 400 MHz
VCO = 240 MHz
Figure 4-1. 100 MHz from 50 MHz Example
Figure 4-2. Pentium Compatible Clocks Example
1 1 0 1 1 1 1 1 1 20 MHz
fsela0 LCK4972 fsela1 Qa fselb0 fselb1 Qb fselc0 fselc1 Qc fselFB0 fselFB1 QFB fselFB2 Input Ref Ext_FB
4 4 4
33 MHz (PCI) 50 MHz (PROCESSOR) 50 MHz (PROCESSOR) 20 MHz (ETHERNET)
VCO = 400 MHz
Figure 4-3. 20 MHz Source Example
4.3 Typical Skew Example
100 75 50 25 ps 0 -25 -50 -75 -100 Qc3 Qc2 Qc1 Qc0 Qb3 Qb2 Qb1 Qb0 Qa3 Qa2 Qa1 Qa0 QFB
Figure 4-4. Skew Relative to Qa
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LCK4972 Low-Voltage PLL Clock Driver
Advance Data Sheet March 26, 2004
The Inv_Clk input pin, when asserted, will invert the Qc2 and Qc3 outputs. This inversion does not affect the output-output skew of the device and allows for the development of 180 phase-shifted clocks. This output can also be used as a feedback output or routed to a second PLL to generate early/late clocks. Figure 4-5 shows a 90 phase-shift configuration.
LCK4972 fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2 Inv_Clk LCK4972 fsela0 fsela1 fselb0 fselb1 fselc0 fselc1 fselFB0 fselFB1 fselFB2 Inv_Clk
0 0 0 0 1 0 0 0 0 1
Qa Qb Qc Qc QFB
4 4 2 2
66 MHz 66 MHz 66 MHz 66 MHz
0 1 0 1 1 1 0 0 0 0
Qa Qb Qc QFB
4 4 4
33 MHz SHIFTED 90 33 MHz SHIFTED 90 33 MHz SHIFTED 90 66 MHz 66 MHz 66 MHz 33 MHz SHIFTED 90
2337 (F)
66 MHz
Input Ref Ext_FB
Input Ref Ext_FB
Figure 4-5. Phase Delay Example Using Two LCK4972s
4.4 SYNC Output
When the output frequencies are not integer multiples of each other, there is a need for a signal for synchronization purposes. The SYNC output is designed to address this need. The Qa and Qc banks of outputs are monitored by the device, and a low-going pulse (one period in duration, one period before the coincident rising edges of Qa and Qc) is provided. The duration and placement of the pulse is dependent on the highest of Qa and Qc output frequencies. The timing diagram, (Figure 4-6) shows the various waveforms for SYNC. Note: SYNC is defined for all possible combinations of Qa and Qc, even though the lower frequency clock should be used as a synchronizing signal in most cases.
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Advance Data Sheet March 26, 2004
fVCO 1:1 MODE Qa Qc Sync 2:1 MODE Qa Qc Sync 3:1 MODE Qc(/2) Qa(/6) Sync 3:2 MODE Qa(/4) Qc(/6) Sync 4:1 MODE Qc(/2) Qa(/8) Sync 4:3 MODE Qa(/6) Qc(/8) Sync 6:1 MODE Qa(/12) Qc(/2) Sync
LCK4972 Low-Voltage PLL Clock Driver
2333 (F)
Figure 4-6. LCK4972 Timing
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LCK4972 Low-Voltage PLL Clock Driver
4.5 Output Freeze Circuitry
Advance Data Sheet March 26, 2004
The new green classification for computers requires unique power management. The LCK4972's individual output enable control allows software to implement unique power management. A serial interface was created to eliminate individual output control at the cost of one pin per output. The freeze control logic provides a mechanism for the LCK4972's clock outputs to be stopped in the logic 0 state. The freeze mechanism allows serial loading of the 12-bit serial input register. This register contains one programmable freeze enable bit for 12 of the 14 output clocks. The Qc0 and QFB outputs cannot be frozen with the serial port, which prevents possible lock-up situations if there is an error in the serial input register. The user can also program a freeze by writing 0 to the respective freeze bit. Likewise, it can be programmed unfrozen by writing a 1 to that same bit. Freeze logic cannot force a recently frozen clock to a logic 0 state before the time which it would normally transition to that state. The logic will only maintain the frozen clock in logic 0. Similarly, the logic will not force a recently frozen clock to logic 1 before the time it would normally transition there. When the clock would normally be in a logic 0 state, the logic re-enables the unfrozen clock, eliminating the possibility of runt clock pulses. The user may write to the serial input register by supplying a logic 0 start bit followed (serially) by 12 NRZ freeze bits through Frz_Data. The period of the Frz_Clk signal equals the period of each Frz_Data bit. The timing should be such that the LCK4972 is able to sample each Frz_Data bit with the rising edge of the Frz_Clk (free running) signal.
Frz_Clk Frz_Data
START
QA0
QA1 QA2
QA3 QB0 QB1
QB2 QB3 QC1
QC2 QC3 QSYNC
Figure 4-7. Freeze Data Input Protocol
4.6 On-Board Crystal Oscillator
The LCK4972 features an on-board crystal oscillator for seed clock generation. The oscillator is self-contained. The only external component required is the crystal. The circuit is a series resonant circuit, eliminating the need for large on-board capacitors. This series resonant design calls for a series resonant crystal, but most crystals are characterized in parallel resonant mode. Physically, a parallel resonant crystal is no different from a series resonant crystal. Overall, a parallel crystal can be used with this device with a small frequency error due to the actual series resonant frequency of the parallel resonant crystal. A parallel specified crystal will exhibit an oscillatory frequency 100 ppm lower than the specified value. This translates to ineffectual kHz inaccuracies, which will not effect the device. Table 4-6. Crystal Recommendations Parameter Crystal Cut Resonance Frequency Tolerance Frequency/Temperature Stability Operating Range Shunt Capacitance Equivalent Series Resistance (ESR) Correlation Drive Level Aging Functional AT cut Series resonance 75 ppm at 25 C 150 ppm at 0 C--70 C 0 C--70 C 5 pF--7 pF 50 --80 max 100 W 5 ppm/year (first 3 years) Value
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Advance Data Sheet March 26, 2004
4.7 Power Supply Filtering
LCK4972 Low-Voltage PLL Clock Driver
The LCK4972 is a mixed-signal product which is susceptible to random noise, especially when this noise is on the power supply pins. To isolate the output buffer switching from the internal phase-locked loop, the LCK4972 provides separate power supplies for the internal PLL (VDDA) and for the output buffers (VDDO). In a digital system environment, besides this isolation technique, it is highly recommended that both VDDA and VDD power supplies be filtered to reduce the random noise as much as possible. Figure 4-8 illustrates a typical power supply filter scheme. Due to its susceptibility to noise with spectral content in this range, a filter for the LCK4972 should be designed to target noise in the 100 kHz to 10 MHz range. The RC filter in Figure 4-8 will provide a broadband filter with approximately 100:1 attenuation for noise with spectral content above 20 kHz. More elaborate power supply schemes may be used to achieve increased power supply noise filtering.
3.3 V
RS = 5 --10
VDDA 0.01 F LCK4972 VDD 0.01 F 22 F
2344 (F)
Figure 4-8. Power Supply Filter
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LCK4972 Low-Voltage PLL Clock Driver
4.8 Driving Transmission Lines
Advance Data Sheet March 26, 2004
The output drivers of the LCK4972 were designed for the lowest impedance possible for maximum flexibility. With the LCK4972's 7 impedance, the drivers can accommodate either parallel or series terminated transmission lines. Point-to-point distribution of signals is the preferred method in today's high-performance clock networks. Series-terminated or parallel-terminated lines can be used in a point-to-point scheme. The parallel configuration terminates the signal at the end of the line with a 50 resistance to VDD/2. Only one terminated line can be driven by each output of the LCK4972 due to the high level of dc current drawn. In a series-terminated case, there is no dc current draw; the outputs can drive multiple series-terminated lines, see below.
LCK4972 OUTPUT BUFFER
IN
7
RS = 43
ZO = 50 OUTA
LCK4972 OUTPUT BUFFER IN
RS = 43 OUTB0 7 ZO = 50 ZO = 50 RS = 43 OUTB1
2340 (F)
Figure 4-9. Dual Transmission Lines The waveform plots of Figure 4-10 show the simulated results of a single output versus a two-line output. A 43 ps delta exists between the two differently loaded outputs that can be seen in the figure. This implies that dual-line driving need not be used in order to maintain tight output-to-output skew. The step in the figure shows an impedance mismatch caused when looking into the driver. The parallel combination in Figure 4-9 plus the output resistance do not equal the parallel combination of the line impedances. The voltage wave down the lines will equal the following: VL = VS (Z0/RS + R0 + Z0) = 3.0 (25/53.5) = 1.4 V The voltage will double at the load-end to 2.8 V, due to the near-unity reflection coefficient. It then continues to increment towards 3.0 V in one-round trip delay steps (4 ps). This step will not cause any false clock triggering, but some users may not want these reflections on the line. Figure 4-11 shows a possible configuration to eliminate these reflections. In this scenario, the series terminating resistors are reduced so the line impedance is matched when the parallel combination is added to the output buffer.
3.0 OUTA tD = 3.8956
2.5
OUTB tD = 3.9386
VOLTAGE (V)
2.0 IN 1.5
LCK4972 OUTPUT BUFFER 7
RS = 36
ZO = 50
ZO = 50 RS = 36 7 + 36 36 = 50 50 25 = 25
2 4 6 8 10 12 14 TIME (ns)
1.0
0.5
0
Figure 4-10. Single vs. Dual Waveforms 14
Figure 4-11. Optimized Dual Transmission Lines Agere Systems Inc.
Advance Data Sheet March 26, 2004
LCK4972 Low-Voltage PLL Clock Driver
5 Absolute Maximum Ratings
Stresses which exceed the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods of time can adversely affect device reliability. Table 5-1. Absolute Maximum Ratings Parameter Supply Voltage Input Voltage Input Current Storage Temperature Range Symbol VDD VI IIN Tstg Min -0.3 -0.3 -- -40 Max 4.6 VDD + 0.3 20 125 Unit V V mA C
5.1 Handling Precautions
Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification requirement in order to determine ESD-susceptibility limits and protection design evaluation. ESD voltage thresholds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114 (HBM) and JESD22-C101 (CDM) standards. Table 5-2. ESD Tolerance Device LCK4972 HBM >2500 V Minimum Threshold CDM >1000 V
5.2 Thermal Parameters (Definitions and Values)
System and circuit board level performance depends not only on device electrical characteristics, but also on device thermal characteristics. The thermal characteristics frequently determine the limits of circuit board or system performance, and they can be a major cost adder or cost avoidance factor. When the die temperature is kept below 125 C, temperature activated failure mechanisms are minimized. The thermal parameters that Agere provides for its packages help the chip and system designer choose the best package for their applications, including allowing the system designer to thermally design and integrate their systems. It should be noted that all the parameters listed below are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. JA - Junction to Air Thermal Resistance JA is a number used to express the thermal performance of a part under JEDEC standard natural convection conditions. JA is calculated using the following formula: JA = (TJ - Tamb) / P; where P = power JMA - Junction to Moving Air Thermal Resistance JMA is effectively identical to JA but represents performance of a part mounted on a JEDEC four layer board inside a wind tunnel with forced air convection. JMA is reported at airflows of 200 LFPM and 500 LFPM (linear feet per minute), which roughly correspond to 1 m/s and 2.5 m/s (respectively). JMA is calculated using the following formula: JMA = (TJ - Tamb) / P Agere Systems Inc. 15
LCK4972 Low-Voltage PLL Clock Driver
JC - Junction to Case Thermal Resistance
Advance Data Sheet March 26, 2004
JC is the thermal resistance from junction to the top of the case. This number is determined by forcing nearly 100% of the heat generated in the die out the top of the package by lowering the top case temperature. This is done by placing the top of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit. JC is calculated using the following formula: JC = (TJ - TC) / P JB - Junction to Board Thermal Resistance JB is the thermal resistance from junction to board. This number is determined by forcing the heat generated in the die out of the package through the leads or balls by lowering the board temperature and insulating the package top. This is done using a special fixture, that keeps the board in contact with a water chilled copper slug around the perimeter of the package while insulating the package top. JB is calculated using the following formula: JB = (TJ - TB) / P JT JT correlates the junction temperature to the case temperature. It is generally used by the customer to infer the junction temperature while the part is operating in their system. It is not considered a true thermal resistance. JT is calculated using the following formula: JT = (TJ - TC) / P Table 5-3. Thermal Parameter Values Parameter JA JMA (1 m/s) JMA (2.5 m/s) JC JB JT 51.11 TBD TBD 14.81 40.23 1 Temperature C/Watt
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Advance Data Sheet March 26, 2004
LCK4972 Low-Voltage PLL Clock Driver
6 Electrical Characteristics
Table 6-1. PLL Input Reference Characteristics (TA = -40 C to +85 C) Parameter TCLK Input Rise/Fall Reference Input Frequency Reference Input Duty Cycle Crystal Oscillator Frequency Symbol tr, tf fref trefDC txtal Condition -- -- -- --2 Min -- --1 25 10 Max 3.0 --1 75 25 Unit ns MHz % MHz
1. Maximum input reference frequency is limited by VCO lock range and the feedback driver or 100 MHz. Minimum input reference frequency is limited by the VCO lock range and the feedback divider. 2. See Section On-Board Crystal Oscillator, on page 12 for more crystal information.
6.1 dc Characteristics
Table 6-2. dc Characteristics (TA = -40 C to+85 C, VDD = 3.3 V 5%) Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Current Maximum Supply Current Analog VDD Current Input Capacitance Power Dissipation Capacitance Symbol VIH VIL VOH VOL IIN IDD IDDA CIN Cpd Condition -- -- IOH = -24 IOL = 24 --2 All VDD pins VDDA pin -- Per output only3 mA1 mA1 Min 2.0 -- 2.4 -- -- -- -- -- -- Typ -- -- -- -- -- 130 60 -- 25 Max 3.6 0.8 -- 0.5 Unit V V V V A mA mA pF pF
120
160 85 4 --
1. The LCK4972 inputs can drive a series of parallel terminated transmission lines on the incident edge. 2. Inputs have pull-up/pull-down resistors, which affect input current. 3. Qa = Qb = Qc = 50 MHz, unloaded outputs.
Table 6-3. dc Characteristics (TA = -40 C to +85 C, VDD = 2.5 V 5%) Parameter PLL Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Impedance Input Current Analog VDD Current Maximum Supply Current Input Capacitance Power Dissipation Capacitance Symbol VDD_PLL VIH VIL VOH VOL ZOUT IIN IDDA IDD CIN Cpd Condition LVCMOS LVCMOS LVCMOS IOH = -15 mAS* IOL = 15 mA -- VIN = VDD or GND VDDA pin only All VDD Pins -- Per output
Min 2.325 1.7 -0.3 1.8 -- 17 -- -- -- -- --
Typ -- -- -- -- -- -- -- 60 130 -- 25
Max VDD VDD + 0.3 0.7 -- 0.6 20 120 85 160 4 --
Unit V V V V V W A mA mA pF pF
* The LCK4972 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines per output. Qa = Qb = Qc = 50 MHz, unloaded outputs.
Agere Systems Inc.
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LCK4972 Low-Voltage PLL Clock Driver
6.2 ac Characteristics
Table 6-4. ac Characteristics (TA = -40 C to +85 C, VDD = 3.3 V/2.5 V 5%)1 Parameter Input Reference Frequency: /4 feedback /6 feedback /8 feedback /10 feedback /12 feedback /16 feedback /20 feedback Input Reference Frequency in PLL Bypass Mode2 VCO Frequency Range3 Crystal Internal Frequency Range4 Output Frequency: /2 output /4 output /6 output /8 output /10 output /12 output Serial Interface Clock Frequency Reference Input Duty Cycle CCLKx Input Rise/Fall Time Propagation Delay (static phase offset) CCLKx or FB_IN Output-to-Output Skew Output Duty Cycle Output Rise/Fall Time Output Disable Time Output Enable Time Cycle-to-Cycle Period Jitter I/O Phase Jitter Maximum PLL Lock Time Jitter5 Symbol fREF Condition PLL locked Min
Advance Data Sheet March 26, 2004
Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 50 -- -- -- 150 -- -- 10
Max 120.0 80.0 60.0 48.0 40.0 30.0 24.0 250 480 25 240.0 120.0 80.0 60.0 48.0 40.0 20 75 1.0 150 250 53 1.0 8 8 200 150 150 --
Unit MHz
37.5 25.0 18.75 15.0 12.5 9.4 7.5 fREF fVCO fXTAL fMAX PLL bypass -- -- PLL locked 75.0 37.5 25.0 18.75 15.0 12.5 fSTOP_CLK fREFDC tR, tF t() tSK(O) DC tR, tF tPLZ, HZ tPZL, LZ tJIT(CC) tJIT(PER) tJIT() tLOCK -- -- 20% to 80% PLL locked -- -- 20% to 80% -- -- -- -- -- -- -- 25 -- -- -- 47 0.1 -- -- -- -- -- -- -- 150 10
MHz MHz MHz MHz
MHz % ns ps ps % ns ns ns ps ps ps ms
1. ac characteristics apply for parallel output termination of 50 to VTT. 2. In bypass mode, the LCK4972 divides the input reference clock. 3. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fREF = fVCO / (M x VCO_SEL). 4. The crystal frequency range must meet the interface frequency range and the VCO lock range divided by the feedback divider ratio: fXTAL (min, max) = fVCO (min, max) / (M x VCO_SEL) and 10 MHz fXTAL 25 MHz. 5. tJIT (CC) is valid for a VCO frequency of 400 MHz with QFB = to divide by 4.
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Agere Systems Inc.
Advance Data Sheet March 26, 2004
LCK4972 Low-Voltage PLL Clock Driver
7 Outline Diagram
52-pin TQFPT package outline. All dimensions are in millimeters.
12.00 10.00 PIN #1 IDENTIFIER ZONE
52 40
1.00 REF
1
39
0.25 GAGE PLANE SEATING PLANE 10.00 12.00 DETAIL A 0.45/0.75
13
27
14
26
0.09/0.20 DETAIL A DETAIL B 1.00 0.05 0.22/0.38 1.20 MAX SEATING PLANE 0.08 0.65 TYP 0.05/0.15 DETAIL B 0.08
M
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8 Ordering Information
Table 8-1. LCK4972 Ordering Information Device LCK4972 Package Type TQFPT Comcode 700010364 Delivery Tray
For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-54614688 (Shanghai), (86) 755 25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344 296 400
Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. Agere is a registered trademark of Agere Systems Inc. Agere Systems and the Agere logo are trademarks of Agere Systems Inc.
Copyright (c) 2004 Agere Systems Inc. All Rights Reserved
March 26, 2004 DS04-066LCK (Replaces DS03-014LCK)

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