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RJ21P3AA0PT
RJ21P3AA0PT
DESCRIPTION
The RJ21P3AA0PT is a 1/1.8-type (8.93 mm) solidstate image sensor that consists of PN photodiodes and CCDs (charge-coupled devices). With approximately 3 370 000 pixels (2 152 horizontal x 1 567 vertical), the sensor provides a stable highresolution color image.
1/1.8-type Interline Color CCD Area Sensor with 3 370 k Pixels
* Package : 20-pin half-pitch DIP [Plastic] (P-DIP020-0500) Row space : 12.20 mm
PIN CONNECTIONS
20-PIN HALF-PITCH WDIP TOP VIEW
FEATURES
* Optical size : 8.93 mm (aspect ratio 4 : 3)
3 210 k effective pixels OD 1 GND 2 OFD 3 PW 4 ORS 5 NC1 6 NC2 7 OH1 8 NC3 9 OH2 10 20 OS 19 GND 18 NC5 17 NC4 16 OV1A 15 OV1B 14 OV2 13 OV3A 12 OV3B 11 OV4
8.93 mm
2 080
* * * * *
*
* * * * * * * * *
Interline scan format Square pixel Number of image pixels : 2 096 (H) x 1 560 (V) Number of effective pixels : 2 080 (H) x 1 544 (V) Number of optical black pixels - Horizontal : 2 front and 54 rear - Vertical : 5 front and 2 rear Number of dummy bits - Horizontal : 24 - Vertical : 2 Pixel pitch : 3.45 m (H) x 3.45 m (V) R, G, and B primary color mosaic filters Supports monitoring mode Low fixed-pattern noise and lag No burn-in and no image distortion Blooming suppression structure Built-in output amplifier Built-in overflow drain voltage circuit and reset gate voltage circuit Variable electronic shutter
1 544
(P-DIP020-0500)
PRECAUTIONS
* The exit pupil position of lens should be 30 to 55 mm from the top surface of the CCD. * Refer to "PRECAUTIONS FOR CCD AREA SENSORS" for details.
In the absence of confirmation by device specification sheets, SHARP takes no responsibility for any defects that may occur in equipment using any SHARP devices shown in catalogs, data books, etc. Contact SHARP in order to obtain the latest device specification sheets before using any SHARP device.
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RJ21P3AA0PT
PIN DESCRIPTION
SYMBOL OD OS ORS OV1A, OV1B, OV2, OV3A, OV3B, OV4 OH1, OH2 OFD PW GND NC1, NC2, NC3, NC4, NC5 PIN NAME Output transistor drain Output signals Reset transistor clock Vertical shift register clock Horizontal shift register clock Overflow drain P-well Ground No connection
ABSOLUTE MAXIMUM RATINGS
PARAMETER Output transistor drain voltage Overflow drain voltage Reset gate clock voltage Vertical shift register clock voltage Horizontal shift register clock voltage Voltage difference between P-well and vertical clock Voltage difference between vertical clocks Storage temperature Ambient operating temperature SYMBOL VOD VOFD VORS VOV VOH VPW-VOV VOV-VOV TSTG TOPR RATING 0 to +18 Internal output Internal output VPW to +18 -0.3 to +12 -27 to 0 0 to +18 -40 to +85 -20 to +70
(TA = +25C)
UNIT V V V V V V V C C 3 NOTE 1 2
NOTES :
1. Do not connect to DC voltage directly. When OFD is connected to GND, connect VOD to GND. Overflow drain clock is applied below 24 Vp-p. 2. Do not connect to DC voltage directly. When ORS is connected to GND, connect VOD to GND. Reset gate clock is applied below 8 Vp-p. 3. When clock width is below 10 s, and clock duty factor is below 0.1%, voltage difference between vertical clocks will be below 26 V.
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RJ21P3AA0PT
RECOMMENDED OPERATING CONDITIONS
PARAMETER Ambient operating temperature Output transistor drain voltage Overflow drain clock p-p level Ground P-well voltage LOW level Vertical shift register clock INTERMEDIATE level HIGH level Horizontal shift register clock LOW level HIGH level SYMBOL TOPR VOD VOOFD GND VPW VOV1AL, VOV1BL, VOV2L VOV3AL, VOV3BL, VOV4L VOV1AI, VOV1BI, VOV2I VOV3AI, VOV3BI, VOV4I VOV1AH, VOV1BH VOV3AH, VOV3BH VOH1L, VOH2L VOH1H, VOH2H VORS fOV1A, fOV1B, fOV2 fOV3A, fOV3B, fOV4 fOH1, fOH2 fORS MIN. 14.55 20.7 -8.0 -7.35 -7.0 0.0 14.55 -0.05 4.5 4.5 15.0 0.0 4.8 4.8 7.50 18.00 18.00 15.45 +0.05 5.5 5.5 TYP. 25.0 15.0 21.5 0.0 VOVL -6.65 MAX. 15.45 22.8 UNIT C V V V V V V V V V V kHz MHz MHz 1 1 2 NOTE
Reset gate clock p-p level Vertical shift register clock frequency Horizontal shift register clock frequency Reset gate clock frequency
NOTES :
1. Use the circuit parameter indicated in "SYSTEM CONFIGURATION EXAMPLE", and do not connect to DC voltage directly. 2. VPW is set below VOVL that is low level of vertical shift register clock, or is used with the same power supply that is connected to VL of V driver IC. * To apply power, first connect GND and then turn on VOD. After turning on VOD, turn on VPW first and then turn on other powers and pulses. Do not connect the device to or disconnect it from the plug socket while power is being applied.
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RJ21P3AA0PT
CHARACTERISTICS (Drive method : 1/30 s frame accumulation)
(TA = +25C, Operating conditions : The typical values specified in "RECOMMENDED OPERATING CONDITIONS". Color temperature of light source : 3 200 K, IR cut-off filter (CM-500, 1 mmt) is used.)
PARAMETER Standard output voltage Photo response non-uniformity Saturation output voltage Dark output voltage Dark signal non-uniformity Sensitivity (green channel) Smear ratio Image lag Blooming suppression ratio Output transistor drain current SYMBOL VO PRNU VSAT VDARK DSNU R (G) SMR AI ABL IOD 1 000 4.0 8.0 mA 130 450 320 530 400 0.5 0.5 160 -90 3.0 2.0 -82 1.0 MIN. TYP. 150 MAX. 10 UNIT mV % mV mV mV mV mV dB % NOTE 2 3 4 5 1, 6 1, 7 8 9 10 11
NOTES :
* Within the recommended operating conditions of VOD, VOFD of the internal output satisfies with ABL larger than 1 000 times exposure of the standard exposure conditions, and VSAT larger than 320 mV. 1. TA = +60C 2. The average output voltage of G signal under uniform illumination. The standard exposure conditions are defined as when Vo is 150 mV. 3. The image area is divided into 10 x 10 segments under the standard exposure conditions. Each segment's voltage is the average output voltage of all pixels within the segment. PRNU is defined by (Vmax - Vmin)/Vo, where Vmax and Vmin are the maximum and minimum values of each segment's voltage respectively. 4. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. VSAT is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. The operation of OFDC is high. (for still image capturing) 5. The image area is divided into 10 x 10 segments. Each segment's voltage is the average output voltage of all pixels within the segment. VSAT is the minimum segment's voltage under 10 times exposure of the standard exposure conditions. The operation of OFDC is low. 6. The average output voltage under non-exposure conditions. 7. The image area is divided into 10 x 10 segments under non-exposure conditions. DSNU is defined by (Vdmax - Vdmin), where Vdmax and Vdmin are the maximum and minimum values of each segment's voltage respectively. 8. The average output voltage of G signal when a 1 000 lux light source with a 90% reflector is imaged by a lens of F4, f50 mm. 9. The sensor is exposed only in the central area of V/10 square with a lens at F4, where V is the vertical image size. SMR is defined by the ratio of the output voltage detected during the vertical blanking period to the maximum output voltage in the V/10 square. 10. The sensor is exposed at the exposure level corresponding to the standard conditions. AI is defined by the ratio of the output voltage measured at the 1st field during the non-exposure period to the standard output voltage. 11. The sensor is exposed only in the central area of V/10 square, where V is the vertical image size. ABL is defined by the ratio of the exposure at the standard conditions to the exposure at a point where blooming is observed.
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RJ21P3AA0PT
PIXEL STRUCTURE
OPTICAL BLACK (2 PIXELS)
OPTICAL BLACK (2 PIXELS)
2 096 (H) x 1 560 (V)
OPTICAL BLACK (54 PIXELS)
1 pin
OPTICAL BLACK (5 PIXELS)
COLOR FILTER ARRAY
(1, 1 560) (2 096, 1 560) G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R G R B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G B G (2 096, 1)
Pin arrangement of the vertical readout clock
OV3B OV1A OV3B OV1B OV3B OV1B OV3B OV1B OV3A OV1B OV3B OV1B OV3B OV1B OV3B OV1A OV3B OV1B OV3B OV1B OV3B OV1B OV3B OV1B OV3A OV1B OV3B OV1B OV3B OV1B OV3B OV1A OV3B OV1B OV3B OV1B (1, 1)
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RJ21P3AA0PT
TIMING CHART
TIMING CHART EXAMPLE
Pulse diagram in more detail is shown in the figure q to r after next page. Field accumulation mode q q' At first frame Frame accumulation accumulation mode mode w e At first field Field accumulation mode accumulation mode r q q' q q'
VD OV1A
227.5
455 1
227.5
455 1
848 1
848 1
227.5
455 1
227.5
455 1
OV1B OV2 OV3A OV3B OV4 OOFD
(at OFD shutter operation)
OFDC OS
(Number of vertical line)
; ; ; ; ; ;
(1, 3, 5, 7, 9...)
; ; ; ; ; ;
Frame accumulation mode
(2, 4, 6, 8, 10...)
Field accumulation Not for use Not for use (NOTE 1) (NOTE 1) mode (5, 12, 19...)
Not for use
(NOTE 2)
Field accumulation mode
(5, 12, 19..) (5, 12, 19..) (5, 12, 19..)
NOTES :
1. Do not use these signals immediately after field accumulation mode is transferred to frame accumulation mode for still image capturing. 2. Do not use these signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring image. * Start the exposure period after 10 ms later that OFDC is high, and finish before change swept transfer. * Apply at least an OFD shutter pulse to OFD in each field accumulation mode.
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RJ21P3AA0PT
q VERTICAL TRANSFER TIMING FIELD ACCUMULATION MODE
2 640 clk/H 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 HD VD OV1A OV1B OV2 OV3A OV3B OV4 OFDC OOFD
1475 1489 1503 1517 1531 1545 1559 1482 1496 1510 1524 1538 1552 RG GB RG GB RG GB RG GB RG GB RG GB RG OB3 5 12 19 26 33 40 47 54 61 68 RG GB RG GB RG GB RG GB RG GB
OS
q' VERTICAL TRANSFER TIMING FIELD ACCUMULATION MODE
444 445 446 447 448 449 450 451 452 453 454 455 1 HD VD OV1A OV1B OV2 OV3A OV3B OV4 OFDC OOFD
1475 1489 1503 1517 1531 1545 1559 1468 1482 1496 1510 1524 1538 1552 GB RG GB RG GB RG GB RG GB RG GB RG GB RG OB3 5 12 19 26 33 40 47 54 61 68 RG GB RG GB RG GB RG GB RG GB
2
3
4
5
6
7
8
9
2 640 clk/H 10 11 12 13 14 15 16
OS
7
RJ21P3AA0PT
w VERTICAL TRANSFER TIMING AT FIRST FRAME ACCUMULATION MODE
451 452 453 454 455 1 HD VD OV1A OV1B OV2 OV3A OV3B OV4 Charge swept transfer (2 112 stages) OFDC OOFD
OB2 OB4 1 3 5 7 RG RG RG RG
2
3
4
5
6
7
8
9
2 640 clk/H ... 61 62 63 64 65 66 67 68 69 70 71 72 73
OS Not for use
* Do not use the frame signals immediately after field accumulation mode is transferred to frame accumulation mode.
e VERTICAL TRANSFER TIMING FRAME ACCUMULATION MODE
844 845 846 847 848 1 HD VD OV1A OV1B OV2 OV3A OV3B OV4 Charge swept transfer (2 112 stages) OFDC OOFD
1549 1553 1557 1551 1555 1559 RG RG RG RG RG RG
2
3
4
5
6
7
8
9
2 640 clk/H ... 61 62 63 64 65 66 67 68 69 70 71 72 73
OB1 OB3 OB5
OS
2 4 6 GB GB GB
Not for use
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RJ21P3AA0PT
r VERTICAL TRANSFER TIMING AT FIRST FIELD ACCUMULATION MODE
837 838 839 840 841 842 843 844 845 846 847 848 1 HD VD OV1A OV1B OV2 OV3A OV3B OV4 OFDC OOFD
1534 1538 1542 1546 1550 1554 1558 OB2 1536 1540 1544 1548 1552 1556 1560 GB GB GB GB GB GB GB GB GB GB GB GB GB GB
2
3
4
5
6
7
8
9
2 640 clk/H 10 11 12 13 14 15 16
OS
Not for use
* Do not use the field signals immediately after frame accumulation mode is transferred to field accumulation mode for monitoring image.
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RJ21P3AA0PT
READOUT TIMING FIELD ACCUMULATION MODE
2640 (0) HD OV1A OV1B 992 OV2 1034 1160 OV3A OV3B 950 OV4 38.9 s (698 bits) 57.6 s (1 034 bits) 7.02 s (126 bits) 250 866 194 222 698 824 908 166 260 2640 (0) 260
7.02 s
(126 bits)
READOUT TIMING FRAME ACCUMULATION MODE w
HD OV1A OV1B OV2 OV3A OV3B OV4 38.9 s (698 bits) 7.02 s (126 bits) 2640 (0) 908 992 1034 1160 OV3A OV3B 36 OV4 57.6 s (1 034 bits) 7.02 s (126 bits) 866 950 194 250 166 222 260 16 36 866 950 194 250 16 36 698 824 908 992 166 222 2640 (0) 260 2640 (0) 260
e
HD OV1A OV1B OV2
2640 (0) 16 36
260
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RJ21P3AA0PT
HORIZONTAL TRANSFER TIMING FIELD ACCUMULATION MODE-1
2640 (0) 54 HD OH1 OH2 ORS OS 2096 OB (54) 82 110 138 166 194 1 clk = 55.7 ns (= 1/18.0 MHz) 222 250 260 278
28 clk
(= 1.56 s)
4-stage transfer
OV1A OV1B OV2 OV3A OV3B OV4
3-stage transfer
OV1A OV1B OV2 OV3A OV3B
OV4
152
OFD
208
* Keep over 1.56 s when vertical transfer clock pulse is overlapping.
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RJ21P3AA0PT
HORIZONTAL TRANSFER TIMING FIELD ACCUMULATION MODE-2
278 HD OH1 OH2 ORS OS PRE SCAN (24) OB (2) OUTPUT (2 096) 1 306 334 362 390 418 446 1 clk = 55.7 ns (= 1/18.0 MHz) 518 474
4-stage transfer
OV1A OV1B OV2 OV3A OV3B OV4
3-stage transfer
OV1A OV1B OV2 OV3A OV3B
OV4 OFD
* Keep over 1.56 s when vertical transfer clock pulse is overlapping.
12
RJ21P3AA0PT
HORIZONTAL TRANSFER TIMING FRAME ACCUMULATION MODE-1
2640 (0) 54 HD OH1 OH2 ORS OS 2096 OV1A OV1B OV2 OV3A OV3B OV4 152 OFD 208 OB (54) 82 110 138 166 194 1 clk = 55.7 ns (= 1/18.0 MHz) 222 250 260 278
56 clk
(= 3.11 s)
* Keep over 3.11 s when vertical clock pulse is overlapping.
HORIZONTAL TRANSFER TIMING FRAME ACCUMULATION MODE-2
278 HD OH1 OH2 ORS OS PRE SCAN (24) OB (2) OUTPUT (2 096) 1 306 334 362 390 418 446 1 clk = 55.7 ns (= 1/18.0 MHz) 474 508
OV1A OV1B OV2 OV3A OV3B OV4 OFD
* Keep over 3.11 s when vertical transfer clock pulse is overlapping.
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RJ21P3AA0PT
CHARGE SWEPT TRANSFER TIMING FRAME ACCUMULATION MODE
w, e 2H 0 HD OV1A OV1B OV2 OV3A OV3B OV4 1 2 3
*******
3H 260
4H
5H
*******
65H 2640
66H
56
96
136
176
216
2616 16
76
116
156
196
2636 36
56
96
136
176
216
2616 16
76
116
156
196
2636 36
2110
2111
2112
* Keep over 1.56 s when vertical transfer clock pulse of charge swept transfer is overlapping.
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VOD + 47 k$ 47 F 33 k$ 1 M$ 100 $ 100 k$ 270 pF 1.0 F 0. 1 F +
OFDC
5.6 k$
VL (VPW) ORS OH1 0.01 F 1 M$
OH2
SYSTEM CONFIGURATION EXAMPLE
VH
ORS
PW
V1A
V1B
V3A
V3B
OH2
OH1
NC
GND
OFD
NC3
NC2
NC1
POFD
VMa V4 V2 VL
VMb
OD
VH
+
15
9 8 7 6 5 4 3 2 1 10 9
12 11 10
8
7
6
5
(*1)
4
3
(*1)
2
1
LR36685
V4X V3X V1X V2X VDD GND VOFDH VH3AX VH1AX VH3BX OFDX
RJ21P3AA0PT
11 12 13 14 15 16 17 18 19 20
OS OV2 OV4 NC4 NC5 OV3B OV3A OV1B OV1A GND
13 14 15 16 17 18 19 20 21 22 23 24
VH1BX
VH1BX +
V4X VH3AX
CCD OUT
+VDD V3X VH1AX V1X V2X OFDX VH3BX
RJ21P3AA0PT
Be sure to use the parameter indicated in this circuit example. (*1) ORS, OFD : Do not connect to DC voltage directly.
RJ21P3AA0PT
PACKAGE OUTLINES 20 DIP (P-DIP020-0500)
6.90.075 0.40.4 20 60.075 0.40.4 11 Center of effective imaging area and center of package
(Unit : mm)
11.20.1 (2) 120.1
CCD
Rotation error of die : = 1.0MAX. ( 1 : Effective imaging area) ( 2 : Lid's size)
1 130.1 (2) 13.8 2.40.1
0.1
10
12.20.1 Refractive index : nd = 1.5 0.02 (1) A 3.50.1
Glass Lid ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; CCD ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; Package ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
A
2.90.1
0.50.05 (2) 1.410.025
A' 0.04 0.02 (1)
+0.3
20-0.3TYP. 20-0.64TYP.
A'
P-1.27TYP. 0.2 M
0.250.1 12.2 -0
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RJ21P3AA0PT
PRECAUTIONS FOR CCD AREA SENSORS 1. Package Breakage
In order to prevent the package from being broken, observe the following instructions : 1) The CCD is a precise optical component and the package material is ceramic or plastic. Therefore, o Take care not to drop the device when mounting, handling, or transporting. o Avoid giving a shock to the package. Especially when leads are fixed to the socket or the circuit board, small shock could break the package more easily than when the package isn't fixed. 2) When applying force for mounting the device or any other purposes, fix the leads between a joint and a stand-off, so that no stress will be given to the jointed part of the lead. In addition, when applying force, do it at a point below the stand-off part. (In the case of ceramic packages) - The leads of the package are fixed with low melting point glass, so stress added to a lead could cause a crack in the low melting point glass in the jointed part of the lead.
Low melting point glass Lead
(In the case of plastic packages) - The leads of the package are fixed with package body (plastic), so stress added to a lead could cause a crack in the package body (plastic) in the jointed part of the lead.
Glass cap Package Lead Fixed
Stand-off
3) When mounting the package on the housing, be sure that the package is not bent. - If a bent package is forced into place between a hard plate or the like, the package may be broken. 4) If any damage or breakage occurs on the surface of the glass cap, its characteristics could deteriorate. Therefore, o Do not hit the glass cap. o Do not give a shock large enough to cause distortion. o Do not scrub or scratch the glass surface. - Even a soft cloth or applicator, if dry, could cause flaws to scratch the glass.
2. Electrostatic Damage
As compared with general MOS-LSI, CCD has lower ESD. Therefore, take the following antistatic measures when handling the CCD : 1) Always discharge static electricity by grounding the human body and the instrument to be used. To ground the human body, provide resistance of about 1 M$ between the human body and the ground to be on the safe side. 2) When directly handling the device with the fingers, hold the part without leads and do not touch any lead.
Fixed
Stand-off
17
RJ21P3AA0PT
3) To avoid generating static electricity, a. do not scrub the glass surface with cloth or plastic. b. do not attach any tape or labels. c. do not clean the glass surface with dustcleaning tape. 4) When storing or transporting the device, put it in a container of conductive material.
4. Other
1) Soldering should be manually performed within 5 seconds at 350C maximum at the tip of soldering iron. 2) Avoid using or storing the CCD at high temperature or high humidity as it is a precise optical component. Do not give a mechanical shock to the CCD. 3)* Do not expose the device to strong light. For the color device, long exposure to strong light will fade the color of the color filters.
* Only for color devices
3. Dust and Contamination
Dust or contamination on the glass surface could deteriorate the output characteristics or cause a scar. In order to minimize dust or contamination on the glass surface, take the following precautions : 1) Handle the CCD in a clean environment such as a cleaned booth. (The cleanliness level should be, if possible, class 1 000 at least.) 2) Do not touch the glass surface with the fingers. If dust or contamination gets on the glass surface, the following cleaning method is recommended : o Dust from static electricity should be blown off with an ionized air blower. For antielectrostatic measures, however, ground all the leads on the device before blowing off the dust. o The contamination on the glass surface should be wiped off with a clean applicator soaked in isopropyl alcohol. Wipe slowly and gently in one direction only. - Frequently replace the applicator and do not use the same applicator to clean more than one device. Note : In most cases, dust and contamination are unavoidable, even before the device is first used. It is, therefore, recommended that the above procedures should be taken to wipe out dust and contamination before using the device.
18

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