View M39P0R9070E0ZADF_1269560.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

M39P0R9070E0
512 Mbit (x16, Multiple Bank, Multi-Level, Burst) Flash Memory 128 Mbit Low Power SDRAM, 1.8V Supply, Multi-Chip Package
PRELIMINARY DATA
Features summary
Multi-chip package - 1die of 512 Mbit (32Mb x 16, Multiple Bank, Multi-Level, Burst) Flash memory - 1 die of 128 Mbit (4 Banks of 2Mb x16) Low Power Synchronous Dynamic RAM Supply voltage - VDDF = VCCP = VDDQ = 1.7 to 1.95V - VPPF = 9V for fast program (12V tolerant) Electronic signature - Manufacturer Code: 20h - Device Code: 8819 Package - ECOPACK(R) (RoHS compliant) Synchronous / asynchronous read - Synchronous Burst Read mode:
108MHz, 66MHz
FBGA
TFBGA105 (ZAD) 9 x 11mm
100,000 program/erase cycles per block Block locking - All Blocks locked at power-up - Any combination of Blocks can be locked with zero latency - WPF for Block Lock-Down - Absolute Write Protection with VPPF = VSS Common Flash Interface (CFI) 128Mbit synchronous dynamic RAM - Organized as 4 Banks of 2 MWords, each 16 bits wide Synchronous burst read and write - Fixed Burst Lengths: 1, 2, 4, 8 words or Full Page - Burst Types: Sequential and Interleaved. - Maximum Clock Frequency: 104MHz - CAS Latency 2, 3 Automatic precharge Low power features: - PASR (Partial Array Self Refresh), - Automatic TCSR (Temperature Compensated Self Refresh) - Driver Strength (DS) - Deep Power-Down Mode Auto Refresh and Self Refresh
Flash memory

LPSDRAM
- Asynchronous Page Read mode - Random Access: 93ns
Programming time - 4s typical Word program time using Buffer Enhanced Factory Program command Memory organization - Multiple Bank Memory Array: 64 Mbit Banks - Four Extended Flash Array (EFA) Blocks of 64 Kbits Dual operations - program/erase in one Bank while read in others - No delay between read and write operations Security - 64-bit unique device number - 2112-bit user programmable OTP Cells

November 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 1 1/26
www.st.com 1
M39P0R9070E0
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 2.18 2.19 2.20 2.21 2.22 2.23 2.24 Address inputs (A0-A24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 LPSDRAM Bank Select Address Inputs (BA0-BA1) . . . . . . . . . . . . . . . . . . . . 9 Data Inputs/Outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Memory Chip Enable Input (EF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Flash Memory Output Enable (GF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Memory Write Enable (WF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Memory Write Protect Input (WPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Memory Reset (RPF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Deep Power-Down (DPDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Flash Memory Latch Enable (LF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash Memory Clock (KF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Flash Memory Wait (WAITF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LPSDRAM Chip Select (ES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LPSDRAM Column Address Strobe (CASS) . . . . . . . . . . . . . . . . . . . . . . . . . 11 LPSDRAM Row Address Strobe (RASS) . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LPSDRAM Write Enable (WS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 LPSDRAM Clock Input (KS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Clock Enable (KES) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM Lower/Upper Data Input/Output Mask (LDQMS/UDQMS) . . . . . 12 Flash Memory VDDF Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 LPSDRAM VDDS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VDDQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Flash Memory VPPF Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . 13 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 4
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2/26
M39P0R9070E0
5 6 7 8
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3/26
M39P0R9070E0
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Flash Memory DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Flash Memory DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 LPSDRAM DC Characteristics 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 LPSDRAM DC Characteristics 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, mechanical data . . . . . . . . . . 23 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4/26
M39P0R9070E0
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline . . . . . . . . . . . 22
5/26
1 Summary description
M39P0R9070E0
1
Summary description
The M39P0R9070E0 combines two memory devices in one Multi-Chip Package:

512-Mbit Multiple Bank Flash memory (the M58PR512J) 128-Mbit Low Power Synchronous DRAM (the M65KA128AL)
This datasheet should be read in conjunction with the M58PR512J and M65KA128AL datasheets, available from www.st.com. Recommended operating conditions do not allow more than one memory to be active at the same time. The memory is offered in a Stacked TFBGA105 package. It is supplied with all the bits erased (set to `1'). Figure 1. Logic Diagram
VDDF VDDQ 25 A0-A24 BA0-BA1 EF GF WF RPF WPF LF KF DPDF ES WS KES KS RASS CASS UDQMS LDQMS VSS M39P0R9070E0 WAITF 2 VDDS
VPPF 16 DQ0-DQ15
Ai11735b
6/26
M39P0R9070E0
Table 1.
A0-A24(1) DQ0-DQ15 VDDQ VPPF VDDF
1 Summary description
Signal Names
Address Inputs Common Data Input/Output Common Flash and LPSDRAM Power Supply for I/O Buffers Flash Memory Optional Supply Voltage for Fast Program & Erase Flash Memory Power Supply LPSDRAM Power Supply Ground Not Connected Internally Do Not Use as Internally Connected
VDDS
VSS NC DU Flash Memory EF GF WF RPF WPF LF KF WAITF DPDF Low Power SDRAM ES WS KS KES CASS RASS BA0, BA1 UDQMS LDQMS
Chip Enable input Output Enable Input Write Enable input Reset input Write Protect input Latch Enable input Burst Clock Wait Output Deep Power-Down
Chip Enable Input Write Enable input LPSDRAM Clock input LPSDRAM Clock Enable input Column Address Strobe Input Row Address Strobe Input Bank Select Inputs Upper Data Input/Output Mask Lower Data Input/Output Mask
Note: 1 A12-A24 are Address Inputs for the Flash memory component only.
7/26
1 Summary description
M39P0R9070E0
Figure 2.
TFBGA Connections (Top view through package)
1 2 3 4 5 6 7 8 9
A
DU
A4
A6
A7
A19
A23
A24
NC
DU
B
A2
A3
A5
A17
A18
DPDF
A22
NC
A16
C
A1
VSS
VSS
VSS
VDDS
VSS
VSS
VSS
A15
D
A0
NC
VDDS
VDDF
LF
VDDF
VDDS
NC
A14
E
WPF
WF
NC
NC
NC
A21
A10
A13
F
NC
ES
CASS
RASS
NC
A20
A9
A12
G
NC
NC
EF
BA0
KES
RPF
A8
A11
H
NC
NC
NC
BA1
NC
WS
GF
UDQMS
LDQMS
J
VPPF
VDDQ
VDDQ
VDDF
KS
VDDF
VDDQ
VDDQ
WAITF
K
DQ2
VSS
VSS
VSS
KF
VSS
VSS
VSS
DQ13
L
DQ1
DQ3
DQ5
DQ6
DQ7
DQ9
DQ11
DQ12
DQ14
M
DU
DQ0
NC
DQ4
DQ8
DQ10
NC
DQ15
DU
AI10961
8/26
M39P0R9070E0
2 Signal descriptions
2
Signal descriptions
See Figure 1., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connect-ed to this device.
2.1
Address inputs (A0-A24)
A0-A11 are common to the Flash memory and LPSDRAM components. A12-A24 are Address Inputs for the Flash memory component only. In the Flash memory, the Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the Program/Erase Controller. In the LPSDRAM, the A0-A11 Address Inputs are used to select the row or column to be made active. If a row is selected, all A0-A11 Address Inputs are used. If a column is selected, only the nine least significant Address Inputs, A0-A8, are used. In this latter case, A10 determines whether Auto Precharge is used. If A10 is High (set to `1') during Read or Write, the Read or Write operation includes an Auto Precharge cycle. If A10 is Low (set to `0') during Read or Write, the Read or Write cycle does not include an Auto Precharge cycle.
2.2
LPSDRAM Bank Select Address Inputs (BA0-BA1)
The BA0 and BA1 Bank Select Address Inputs are used by the LPSDRAM to select the bank to be made active. The LPSDRAM must be enabled, the Row Address Strobe, RASS, must be Low, VIL, the Column Address Strobe, CASS, and W must be High, VIH, when selecting the addresses. The address inputs are latched on the rising edge of the clock signal, KS.
2.3
Data Inputs/Outputs (DQ0-DQ15)
In the Flash memory, the Data I/O output the data stored at the selected address during a Bus Read operation or input a command or the data to be programmed during a Bus Write operation. In the LPSDRAM, the Data Inputs/Outputs are common to all memory components. They output the data stored at the selected address during a Read operation, or are used to input the data during a write operation.
2.4
Flash Memory Chip Enable Input (EF)
The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VIL and Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to have EF and ES all at VIL at the same time, only one memory component should be enabled at a time.
9/26
2 Signal descriptions
M39P0R9070E0
2.5
Flash Memory Output Enable (GF)
The Output Enable input controls data outputs during the Bus Read operation of the memory.
2.6
Flash Memory Write Enable (WF)
The Write Enable input controls the Bus Write operation of the Flash memory's Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first.
2.7
Flash Memory Write Protect Input (WPF)
Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See M58PR512J datasheet for details).
2.8
Flash Memory Reset (RPF)
The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 6., Flash Memory DC Characteristics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 7., Flash Memory DC Characteristics - Voltages).
2.9
Deep Power-Down (DPDF)
The Deep Power-Down input is used to put the Flash memory in Deep Power-Down mode. When the Flash memory is in Standby mode and the Enhanced Configuration Register bit ECR15 is set, asserting the Deep Power-Down input will cause the memory to enter the Deep Power-Down mode. When the device is in the Deep Power-Down mode, the memory cannot be modified and the data is protected. The polarity of the DPDF pin is determined by ECR14. The Deep Power-Down input is active Low by default.
10/26
M39P0R9070E0
2 Signal descriptions
2.10
Flash Memory Latch Enable (LF)
The Latch Enable input latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported.
2.11
Flash Memory Clock (KF)
The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations.
2.12
Flash Memory Wait (WAITF)
Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH, Output Enable is at VIH, or Reset is at VIL. It can be configured to be active during the wait cycle or one data cycle in advance.
2.13
LPSDRAM Chip Select (ES)
The Chip Select input ES activates the LPSDRAM state machine, address buffers and decoders when driven Low, VIL. When High, VIH, the device is not selected.
2.14
LPSDRAM Column Address Strobe (CASS)
The Column Address Strobe, CASS, is used in conjunction with Address Inputs A8-A0 and BA1-BA0, to select the starting column location prior to a Read or Write.
2.15
LPSDRAM Row Address Strobe (RASS)
The Row Address Strobe, RASS, is used in conjunction with Address Inputs A11-A0 and BA1BA0, to select the starting address location prior to a Read or Write.
2.16
LPSDRAM Write Enable (WS)
The Write Enable input, WS, controls writing to the LPSDRAM.
11/26
2 Signal descriptions
M39P0R9070E0
2.17
LPSDRAM Clock Input (KS)
The Clock signal, KS, is used to clock the Read and Write cycles. During normal operation, the Clock Enable pin, KES, is High, VIH. The clock signal KS can be suspended to switch the device to the Self Refresh, Power-Down or Deep Power-Down mode by driving KES Low, VIL.
2.18
LPSDRAM Clock Enable (KES)
The Clock Enable, KES, pin is used to control the synchronizing of the signals to Clock signal KS. The signals are clocked when KES is High, VIH When KES is Low, VIL, the signals are no longer clocked and data Read and Write cycles are extended. KES is also involved in switching the device to the Self Refresh, Power-Down and Deep Power-Down modes.
2.19
LPSDRAM Lower/Upper Data Input/Output Mask (LDQMS/ UDQMS)
Lower Data Input/Output Mask and Upper Data Input/Output Mask pins are input signals used to mask the Read or Write data.
2.20
Flash Memory VDDF Supply Voltage
VDDF provides the power supply to the internal core of the Flash memory component. It is the main power supply for all operations (Read, Program and Erase).
2.21
LPSDRAM VDDS Supply Voltage
VDDS provides the power supply to the internal core of the LPSDRAM component. It is the main power supply for all operations (Read and Write).
2.22
VDDQ Supply Voltage
VDDQ is common to the Flash memory and LPSDRAM memory components. It provides the power supply to the I/O pins and enables all Outputs to be powered independently of VDDF for the Flash memory, or VDDS for the LPSDRAM. VDDQ can be tied to VDDF or VDDS, or can use a separate supply.
12/26
M39P0R9070E0
2 Signal descriptions
2.23
Flash Memory VPPF Program Supply Voltage
VPPF is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while VPP > VPP1 enables these functions (see Tables 6 and 7, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed.
2.24
VSS Ground
VSS ground is common to the LPSDRAM and Flash memory components. It is the reference for the core supply. It must be connected to the system ground.
Note:
Each device in a system should have VDDF,VDDS, VDDQ and VPPH decoupled with a 0.1F ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 5., AC Measurement Load Circuit The PCB track widths should be sufficient to carry the required VPPF program and erase currents.
13/26
3 Functional description
M39P0R9070E0
3
Functional description
The LPSDRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by two Chip Enable inputs: EF for Flash and ES for the LPSDRAM. Recommended operating conditions do not allow more than one device to be active at a time. The most common example is a simultaneous read operations on the Flash memory and the LPSDRAM which would result in a data bus contention. Therefore it is recommended to put the other devices in the high impedance state when reading the selected device.
Figure 3.
Functional Block Diagram
VPPF VDDF A12-A24
EF WPF WF A0-A11 KF GF RPF LF DPDF VDDS VDDQ DQ0-DQ15 512 Mbit Flash Memory WAITF
BA0-BA1 ES WS KS KES CASS RASS UDQMS LDQMS 128 Mbit LPSDRAM
VSS
Ai11736c
14/26
M39P0R9070E0
Table 2.
Operation(1) Bus Read
3 Functional description
Bus Operations
EF GF WF LF RPF WAITF(2) KESn-1 KESn ES RASS CASS WS A10 A9, A0-A7 BA0- DQ15-DQ0 A11 BA1
VIL VIL VIH
VIL
(4)
VIH
Data Output The SDRAM must be disabled. Data Input Data Output or Hi-Z
(5)
Bus Write Flash memory(3)
(4 VIL VIH VIL VIL VIH )
Address Latch
VIL X VIH VIL VIH VIL VIH VIH VIH X X X VIH X X X X X X X X VIH VIH VIL VIH Hi-Z Hi-Z Hi-Z Hi-Z VIH The Flash memory must be disabled. VIH VIH VIH VIH VIH Any Flash memory operation mode is allowed. VIH VIH VIH X X VIL VIH VIL VIH VIL VIH VIL VIL VIL VIL V V X X X X X X X SCA BS
(6) (7)
Output Disable Standby Reset Deep PowerDown Burst Read
Hi-Z Hi-Z Any SDRAM operation mode is allowed. Hi-Z Hi-Z Data Output Data Input - - - - - - -
Burst Write Self Refresh LPSDRAM(3) Auto Refresh Power-Up Power-Down Deep PowerDown Device Deselect No Operation
SCA( BS(7
6) )
VIL VIL VIL VIH VIL VIL VIL VIL VIH VIL VIL VIH VIH X
VIL VIH VIL VIH VIH VIL VIH VIH X X VIH VIL X X VIH VIH
X X X X X X X
VIL VIL VIH X X VIH X VIL VIH
1. X = Don't care, V = Valid. 2. WAITF signal polarity is configured using the Set Configuration Register command. 3. For further details, refer to the M58PR512J and M65KA128AL datasheets. 4. LF can be tied to VIH if the valid address has been previously latched. 5. Depends on GF 6. SCA = Start Column Address. 7. BS = Bank Select.
15/26
4 Maximum rating
M39P0R9070E0
4
Maximum rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 3.
Symbol TA TJ TBIAS TSTG VIO VDDF VDDS VDDQ VPPF IO tVPPH
Absolute Maximum Ratings
Value Parameter Min Ambient Operating Temperature SDRAM Junction Temperature Temperature Under Bias Storage Temperature Input or Output Voltage Supply Voltage LPSDRAM Supply Voltage Input/Output Supply Voltage Program Voltage Output Short Circuit Current Time for VPP at VPPH -25 -25 -25 -55 -0.5 -1.0 -0.5 -0.5 -1.0 Max 85 90 85 125 2.6 3.0 2.6 2.6 12.6 100 100 C C C C V V V V V mA hours Unit
16/26
M39P0R9070E0
5 DC and AC parameters
5
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 4., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 4.
Operating and AC Measurement Conditions
Flash memory Parameter(1)(2) Min Max 1.95 - 1.95 9.5 VDDQ+0.4 85 30 50 50 3 0 to VDDQ VDDQ/2 1 - VDDQ/2 Min - 1.7 1.7 - - -25 Typ - 1.8 1.8 - - - 30 Max - 1.95 1.95 - - 85 V V V V V C pF ns V V LPSDRAM Unit 1.7 - 1.7 8.5 -0.4 -25
VDDF Supply Voltage VDDS Supply Voltage VDDQ Supply Voltage(3) VPPF Supply Voltage (Factory environment) VPPF Supply Voltage (Application environment) Ambient Operating Temperature Load Capacitance (CL) Impedance Output (Z0) Output Circuit Protection Resistance (R) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages
1. All voltages are referenced to VSS = 0V. 2. TJ = -25 to 90C, f = 1MHz 3. VDDQ must not exceed the level of VDDS.
Figure 4.
AC Measurement I/O Waveform
VDDQ VDDQ/2 0V
AI06161
17/26
5 DC and AC parameters
M39P0R9070E0
Figure 5.
AC Measurement Load Circuit
VCCQ/2
R DEVICE UNDER TEST
OUT Z0 CL
AI06162a
Table 5.
Symbol CIN COUT
Capacitance
Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min - - Max 12 15 Unit pF pF
1. Sampled only, not 100% tested.
18/26
M39P0R9070E0
Table 6.
Symbol ILI ILO
5 DC and AC parameters
Flash Memory DC Characteristics - Currents
Parameter Input Leakage Current Output Leakage Current Supply Current Asynchronous Read (f=5MHz) Supply Current Page Read (f=13MHz) Test Condition 0V VIN VDDQ 0V VOUT VDDQ EF = VIL, GF = VIH 25 11 8 Word 16 Word Continuous 8 Word 16 Word Continuous RPF = VSS 0.2V 512 Mbit EF = VDDF 0.2V EF = VIL, GF = VIH VPPF = VPPH VPPF = VDDF VPPF = VPPH VPPF = VDDF VPPF = VPPH VPPF = VDDF Program/Erase in one Bank, Asynchronous Read in another Bank Program/Erase in one Bank, Synchronous Read (Continuous f=66MHz) in another Bank EF = VDDF 0.2V VPPF = VPPH VPPF = VDDF VPPF = VPPH VPPF = VDD VPP VDDF VPP VDDF VPPF = VPPH VPPF = VPP1 512 Mbit 512 Mbit 512 Mbit 22 19 25 26 23 30 50 50 50 2 35 35 35 35 35 35 60 65 50 8 0.05 8 0.05 2 0.2 0.05 0.05 Typ Max 1 1 30 15 32 26 34 36 30 42 120 120 120 30 50 50 50 50 50 50 80 92 120 22 0.1 22 0.1 15 5 0.1 0.1 Unit A A mA mA mA mA mA mA mA mA A A A A mA mA mA mA mA mA mA mA A mA A mA A A A mA mA
IDD1
Supply Current Synchronous Read (f=66MHz) Supply Current Synchronous Read (f = 108MHz)
IDD2 IDD3 IDD4 IDD5(1)
Supply Current (Reset) Supply Current (Standby) Supply Current (Automatic Standby) Supply Current (Deep Power Down) Supply Current (Program)
IDD6 (2)
Supply Current (Erase) Supply Current (Blank Check)
IDD7
(2)(3)
Supply Current (Dual Operations)
IDD8(2)
Supply Current Program/ Erase Suspended (Standby) VPPF Supply Current (Program)
IPP1(2) VPPF Supply Current (Erase) IPP2 IPP3(2) IPP4 VPPF Supply Current (Read) VPPF Supply Current (Standby, Program/Erase Suspend) VPPF Supply Current (Blank Check)
1. The DPD current is measured 40s after entering the Deep Power Down mode. 2. Sampled only, not 100% tested. 3. VDDF Dual Operation current is the sum of read and program or erase currents.
19/26
5 DC and AC parameters
M39P0R9070E0
Table 7.
Symbol VIL VIH VOL VOH VPP1 VPPH VPPLK VLKO VRPH VLKOQ
Flash Memory DC Characteristics - Voltages
Parameter Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage VPPF Program Voltage-Logic VPPF Program Voltage Factory Program or Erase Lockout VDDF Lock Voltage RPF pin Extended High Voltage VDDQ Lock Voltage 0.9 1 3.3 IOL = 100A IOH = -100A Program, Erase Program, Erase VDDQ -0.1 1.1 8.5 1.8 9.0 3.3 9.5 0.4 Test Condition Min 0 VDDQ -0.4 Typ Max 0.4 VDDQ + 0.4 0.1 Unit V V V V V V V V V V
Table 8.
Symbol ILI ILO(2) VIL(3) VIH(3) VOL VOH
LPSDRAM DC Characteristics 1
Parameter Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Test Condition(1) 0VVIN 1.8V 1.8V 0V VOUT VIN = 0V VIN = 0V IOUT = 100A, VIN = 0V IOUT = -100A, VIN = 0V VDDQ -0.2 Min -1 -1.5 -0.3(4) 0.8VDDQ Max 1 1.5 0.3 VDDQ + 0.3(5) 0.2 Unit A A V V V V
1. TJ = -25 to 90C. 2. Data outputs are disabled. 3. VDDQ must not exceed the level of VDDS. 4. VIL may undershoot to -1.0V for less that 5ns. 5. VIH may overshoot to 2.6V for less that 5ns.
20/26
M39P0R9070E0
Table 9.
Symbol IDD1(2) IDD2P IDD2PS
5 DC and AC parameters
LPSDRAM DC Characteristics 2
Parameter Operating Current Test Condition(1) Burst length = 1, one bank active tRC tRC(min), IOL = 0mA KES VIL(max), tCK = 15ns Standby Current in Power-Down Mode KES VIL(max), tCK = Input signal stable KES VIH (min), ES VIH (min), tCK = 15ns Input signals are changed once in 30ns KES VIH (min), tCK = Input signals are stable Active Standby Current in PowerDown Mode KES VIL(max), tCK = 15ns KES VIL(max), tCK = Typ 36 0.6 mA 0.5 Unit mA
IDD2N Standby Current in Non Power-Down Mode IDD2NS IDD3P IDD3PS IDD3N
3 mA 1 1 mA 0.8 15 mA 5 35 52 65 See M65KA128AL datasheet mA mA mA
IDD3NS IDD4(2) IDD5(3),
(4)
KES VIH (min), ES VIH (min), tCK = 15ns Active Standby Current in Non Power- Input signals are changed once in 30ns Down Mode KES VIH (min), tCK = Input signals are stable Burst Mode Current, CL=2 Burst Mode Current, CL=3 Auto Refresh Current, CL=2 Auto Refresh Current, CL=3 Self Refresh Current tCK tCK (min), IOL = 0mA All banks active tRC1 tRC1(min)
IDD6
KES 0.2V
A
IDD7
See Deep Power-Down Entry AC Standby Current in Deep Power-down Waveforms, and Deep Power-Down Exit Mode AC Waveforms Figures in M65KA128AL datasheet.
10
A
1. TJ = -25 to 90C. 2. IDD1 and IDD4 depend on the output loading and cycle rates. All measurements are made with the output open and on condition that the addresses are changed only once during tCK (min.). 3. The minimum value of tRC (RASS cycle time for Refresh operation) is shown in the Asynchronous AC Characteristics Table in M65KA128AL datasheet. 4. IDD5 is measured on condition that the addresses are changed only once during tCK (min.).
21/26
6 Package mechanical
M39P0R9070E0
6
Package mechanical
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 6.
TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, package outline
D D1 FD
e
E
E1
SE
ddd
BALL "A1"
FE A e b A1 A2
BGA-Z79
Drawing is not to scale.
22/26
M39P0R9070E0
Table 10.
Symbol Typ A A1 A2 b D D1 ddd E E1 e FD FE SE 11.00 8.80 0.80 1.30 1.10 0.40 - - 10.90 0.80 0.35 9.00 6.40 0.10 11.10 0.433 0.346 0.031 0.051 0.043 0.016 - 0.30 8.90 0.40 9.10 0.20 0.031 0.014 0.354 0.252 Min Max 1.20 Typ Min
6 Package mechanical
TFBGA105 9x11mm - 9x12 active ball array, 0.8mm pitch, mechanical data
millimeters inches Max 0.047 0.008
0.012 0.350
0.016 0.358
0.004 0.429 0.437
-
23/26
7 Part numbering
M39P0R9070E0
7
Table 11.
Example:
Part numbering
Ordering Information Scheme
M39 P 0 R 9 0 7 0 E 0 ZAD E
Device Type M39 = Multi-Chip Package (Flash + LPSDRAM) Flash 1 Architecture P = Multi-Level, Multiple Bank, Large Buffer Flash 2 Architecture 0 = No Die Operating Voltage R = VDDF = VDDS = VDDQ = 1.7 to 1.95V Flash 1 Density 9 = 512 Mbits Flash 2 Density 0 = No Die RAM 1 Density 7 = 128 Mbit RAM 0 Density 0 = No Die Parameter Blocks Location E = Even Block Flash Memory Configuration Product Version 0 = 90nm Flash technology, 93ns speed; LPSDRAM Package ZAD= stacked TFBGA105 D stacked footprint. Option Blank = Standard Packing E = ECOPACK(R) Package, Standard packing F = ECOPACK(R) Package, Tape & Reel packing
Note:
Devices are shipped from the factory with the memory content bits erased to '1'. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
24/26
M39P0R9070E0
8 Revision history
8
Revision history
Date 29-Nov-2005 Version 1 Initial release. Revision Details
25/26
M39P0R9070E0
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
26/26

▲Up To Search▲

Price & Availability of M39P0R9070E0ZADF

	To Download M39P0R9070E0ZADF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .