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M69KB096AB
64 Mbit (4 Mb x16), 104MHz Clock Rate, 1.8V Supply, Bare Die, Burst PSRAM
PRELIMINARY DATA
Features summary
Supply Voltage - VCC = 1.7 to 1.95V core supply voltage - VCCQ = 1.7 to 1.95V for I/O buffers User-selectable Operating Modes - Asynchronous Modes: Random Read, and Write, Page Read - Synchronous Modes: NOR-Flash, Full Synchronous (Burst Read and Write) Asynchronous Random Read - Access Time: 70ns Asynchronous Page Read - Page Size: 4, 8 or 16 Words - Subsequent Read Within Page: 20ns Burst Read - Fixed Length (4, 8, 16 or 32 Words) or Continuous - Maximum Clock Frequency: 104MHz - Output delay: 7ns at 104MHz Low Power Consumption - Active Current: < 25mA - Standby Current: 140A - Deep Power-Down Current: < 10A Low Power Features - Partial Array Self-Refresh (PASR) - Deep Power-Down (DPD) Mode - Automatic Temperature-compensated SelfRefresh Operating Temperature - -30C to +85C
Wafer

The M69KB096AB is only available as part of a multi-chip package Product.
November 2005
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev 1 1/73
www.st.com 1
M69KB096AB
Contents
1 2 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 Address Inputs (A0-A21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Inputs/Outputs (DQ8-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Upper Byte Enable (UB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Lower Byte Enable (LB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clock Input (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Configuration Register Enable (CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VCCQ Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 VSSQ Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3 4
Power-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.1 4.2 4.3 4.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Deep Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Automatic Temperature Compensated Self Refresh . . . . . . . . . . . . . . . . . . . 14
5
Standard Asynchronous operating modes . . . . . . . . . . . . . . . . . . . . . . . . 15
5.1 5.2 5.3 Asynchronous Read and Write modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Asynchronous Page Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Configuration Registers Asynchronous Read and Write . . . . . . . . . . . . . . . . 16
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6
Synchronous Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1 6.2 6.3 NOR-Flash Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Full Synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Synchronous Burst Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.3.1 6.3.2 6.3.3 Variable Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Fixed Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Row Boundary Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.4 6.5 6.6
Synchronous Burst Read Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Synchronous Burst Write Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Synchronous Burst Read and Write Suspend . . . . . . . . . . . . . . . . . . . . . . . 21
7
Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1 Programming and Reading Registers using the CR Controlled Method . . . . 26
7.1.1 7.1.2 Read Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Program Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.2 7.3
Programming and Reading the Registers using the Software Method . . . . . 27 Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 7.3.7 7.3.8 Operating Mode Bit (BCR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Latency Type (BCR14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Latency Counter Bits (BCR13-BCR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 WAIT Polarity Bit (BCR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 WAIT Configuration Bit (BCR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Driver Strength Bits (BCR5-BCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Burst Wrap Bit (BCR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Burst Length Bits (BCR2-BCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4
Refresh Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.4.1 7.4.2 7.4.3 Page Mode Operation Bit (RCR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Deep Power-Down Bit (RCR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Partial Array Refresh Bits (RCR2-RCR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
7.5
Device ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8 9 10
Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Wafer and die specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
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Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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M69KB096AB
List of tables
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Page Mode Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Standard Asynchronous Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating Frequency versus Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Asynchronous Write Operations (NOR-Flash Synchronous Mode) . . . . . . . . . . . . . . . . . . 22 Synchronous Read Operations (NOR-Flash Synchronous Mode) . . . . . . . . . . . . . . . . . . . 22 Full Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Register Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Bus Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Refresh Configuration Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Device ID Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Asynchronous Read AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Asynchronous Page Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Asynchronous Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Clock Related AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Synchronous Burst Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Synchronous Burst Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Power-Up and Deep Power-Down AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Bond Pad Location and Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Ordering Information Scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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M69KB096AB
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Latency Configuration (Variable Latency Mode, No Refresh Collision) . . . . . . . . . . . . . . . 24 Latency Configuration (Fixed Latency Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Switching from Asynchronous to Synchronous Write Operation . . . . . . . . . . . . . . . . . . . . 25 Refresh Collision during Synchronous Burst Read in Variable Latency Mode . . . . . . . . . . 25 Set Configuration Register (Software Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Configuration Register (Software Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WAIT Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 WAIT Polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 AC Measurement I/O Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC Input Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Asynchronous Random Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Latch Enable Controlled, Asynchronous Random Read AC Waveforms . . . . . . . . . . . . . 43 Asynchronous Page Read AC Waveforms (4 Words) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 CR Controlled Configuration Register Read Followed by Read, Asynchronous Mode . . . 45 Chip Enable Controlled, Asynchronous Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . 47 Upper/Lower Byte Enable Controlled, Asynchronous Write AC Waveforms . . . . . . . . . . . 48 Write Enable Controlled, Asynchronous Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . 49 L Controlled, Asynchronous Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 CR Controlled Configuration Register Program, Asynchronous Mode . . . . . . . . . . . . . . . . 51 Clock input AC Waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 4-Word Synchronous Burst Read AC Waveforms (Variable Latency Mode) . . . . . . . . . . . 54 Synchronous Burst Read Suspend and Resume AC Waveforms . . . . . . . . . . . . . . . . . . . 55 Burst Read Showing End-of-Row Condition AC Waveforms (No Wrap) . . . . . . . . . . . . . . 56 Burst Read Interrupted by Burst Read or Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . 57 CR Controlled Configuration Register Read Followed by Read, Synchronous Mode . . . . 58 4-Word Synchronous Burst Write AC Waveforms (Variable Latency Mode) . . . . . . . . . . . 60 Burst Write Showing End-of-Row Condition AC Waveforms (No Wrap) . . . . . . . . . . . . . . 61 Synchronous Burst Write Followed by Read AC Waveforms (4 Words) . . . . . . . . . . . . . . 62 Burst Write Interrupted by Burst Write or Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . 63 CR Controlled Configuration Register Program, Synchronous Mode. . . . . . . . . . . . . . . . . 64 Power-Up AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Deep Power-Down Entry and Exit AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Die Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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M69KB096AB
1 Summary description
1
Summary description
The M69KB096AB is a 64 Mbit (67,108,864 bit) PSRAM, organized as 4,194,304 Words by 16 bits. It uses a high-speed CMOS DRAM technology implemented using a one transistor-per-cell topology that achieves bigger array sizes. It provides a high-density solution for low-power handheld applications. The M69KB096AB is supplied by a 1.7 to 1.95V supply voltage range. The PSRAM interface supports various operating modes: Asynchronous Random Read and Write, Asynchronous Page Read and Synchronous mode that increases read/write speed. In Asynchronous Random Read mode, the M69KB096AB is compatible with low power SRAMs. In Asynchronous Page mode the device has much shorter access times within the page that make it is compatible with the industry standard PSRAMs. Two types of Synchronous modes are available:

Flash-NOR: the device operates in Synchronous mode for read operations and Asynchronous mode for write operations. Full Synchronous: the device supports Synchronous transfers for both read and write operations. Two user-programmable registers used to define the device operation: the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR). A read-only Device ID Register (DIDR) containing device identification.
The M69KB096AB features three configuration registers:

The Bus Configuration Register (BCR) indicates how the device interacts with the system memory bus. The Refresh Configuration Register (RCR) is used to control how the memory array refresh is performed. At Power-Up, these registers are automatically loaded with default settings and can be updated any time during normal operation. PSRAMs are based on the DRAM technology, but have a transparent internal self-refresh mechanism that requires no additional support from the system memory microcontroller. To minimize the value of the Standby current during self-refresh operations, the M69KB096AB includes three system-accessible mechanisms configured via the Refresh Configuration Register (RCR):

Partial Array Self Refresh (PASR) performs a limited refresh of the part of the PSRAM array that contains essential data. Deep Power-Down (DPD) mode completely halts the refresh operation. It is used when no essential data is being held in the device. Automatic Temperature Compensated Self Refresh (TCSR) adjusts the refresh rate according to the operating temperature.
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1 Summary description
M69KB096AB
Figure 1.
Logic Diagram
VCC VCCQ
22 A0-A21 W E CR G UB LB K L M69KB096AB
16 DQ0-DQ15
WAIT
VSS
VSSQ
AI11565
Table 1.
A0-A21 DQ0-DQ15 E CR G W UB LB K L WAIT VCC VCCQ VSS VSSQ
Signal Names
Address Inputs Data Inputs/Outputs Chip Enable Input Configuration Register Enable Input Output Enable Input Write Enable Input Upper Byte Enable Input Lower Byte Enable Input Clock Input Latch Enable Input Wait Output Core Supply Voltage Input/Output Buffers Supply Voltage Ground Input/Output Buffers Ground
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1 Summary description
Figure 2.
Block Diagram
A21-A0
Address Decoder
E W CR Bus Configuration Register (BCR)
Column Decoder
DQ0-DQ15 Synchronous/ Asynchronous Logic Row Decoder 4,096K x 16 Memory Array I/O Buffers WAIT
K
E W G L CR LB UB Control Logic
AI11299
1. This functional block diagram illustrates simplified device operation.
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2 Signal descriptions
M69KB096AB
2
Signal descriptions
The signals are summarized in Figure 1: Logic Diagram, and Table 1: Signal Names.
2.1
Address Inputs (A0-A21)
The Address Inputs select the cells in the memory array to access during read and write operations.
2.2
Data Inputs/Outputs (DQ8-DQ15)
The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a write or read operation, when Upper Byte Enable (UB) is driven Low. When disabled, the Data Inputs/Outputs are high impedance.
2.3
Data Inputs/Outputs (DQ0-DQ7)
The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a write or read operation, when Lower Byte Enable (LB) is driven Low. When disabled, the Data Inputs/Outputs are high impedance.
2.4
Chip Enable (E)
Chip Enable, E, activates the device when driven Low (asserted). When de-asserted (VIH), the device is disabled and goes automatically in low-power Standby mode or Deep Power-Down mode, according to the RCR settings.
2.5
Output Enable (G)
When held Low, VIL, the Output Enable, G, enables the Bus Read operations of the memory.
2.6
Write Enable (W)
Write Enable, W, controls the Bus Write operation of the memory. When asserted (VIL), the device is in write mode and write operations can be performed either to the configuration registers or to the memory array.
2.7
Upper Byte Enable (UB)
The Upper Byte Enable, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8DQ15) to or from the upper part of the selected address during a write or read operation.
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2 Signal descriptions
2.8
Lower Byte Enable (LB)
The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a write or read operation. If both LB and UB are disabled (High), the device will disable the data bus from receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as E remains Low.
2.9
Clock Input (K)
The Clock, K, is an input signal to synchronize the memory to the microcontroller or system bus frequency during Synchronous Burst Read and Write operations. The Clock input signal increments the device internal address counter. The addresses are latched on the rising edge of the Clock K, when L is Low during Synchronous Bus operations. Latency counts are defined from the first Clock rising edge after L falling edge to the first data input latched or the first data output valid. The Clock input is required during all synchronous operations and must be kept Low during asynchronous operations.
2.10
Configuration Register Enable (CR)
When this signal is driven High, VIH, bus read or write operations access either the value of the Refresh Configuration Register (RCR) or the Bus Configuration Register (BCR) according to the value of A19.
2.11
Latch Enable (L)
In Synchronous mode, addresses are latched on the rising edge of the Clock K when the Latch Enable input, L is Low. In Asynchronous mode, addresses are latched on L rising edge.
2.12
Wait (WAIT)
The WAIT output signal provides data-valid feedback during Synchronous Burst Read and Write operations. The signal is gated by E. Driving E High while WAIT is asserted may cause data corruption. Once a read or write operation has been initiated, the WAIT signal goes active to indicate that the M69KB096AB device requires additional time before data can be transferred. The WAIT signal also is used for arbitration when a Read or Write operation is launched while an on-chip refresh is in progress (see Figure 6: Refresh Collision during Synchronous Burst Read in Variable Latency Mode). Typically, the WAIT pin of the M69KB096AB can be connected to a shared WAIT signal used by the processor to coordinate transactions with multiple memories on the synchronous bus. See Section 3: Power-up for details on the WAIT signal operation.
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2 Signal descriptions
M69KB096AB
2.13
VCC Supply Voltage
The VCC Supply Voltage is the core supply voltage.
2.14
VCCQ Supply Voltage
VCCQ provides the power supply for the I/O pins. This allows all Outputs to be powered independently from the core power supply, VCC.
2.15
VSS Ground.
The VSS Ground is the reference for all voltage measurements.
2.16
VSSQ Ground
VSSQ ground is the reference for the input/output circuitry driven by VCCQ. VSSQ must be connected to VSS.
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M69KB096AB
3 Power-up
3
Power-up
To guarantee correct operation, a specific Power-Up sequence must be followed to initialize the M69KB096AB. Power must be applied simultaneously to VCC and VCCQ. Once VCC and VCCQ have reached a stable level (see Figure 35: Deep Power-Down Entry and Exit AC Waveforms and Figure 34: Power-Up AC Waveforms), the device will require tVCHEL to complete its selfinitialization process. During the initialization period, the E signal must remain High. Once initialization has completed, the device is ready for normal operation. Initialization will load the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) with their default settings (see Table 9: Bus Configuration Register Definition, and Table 11: Refresh Configuration Register Definition).
4
4.1
Low-power modes
Standby
When the device is in Standby, the current consumption is reduced to the level necessary to perform the memory array refresh operation. The device will enter Standby when a read or write operation is completed, depending on the operating mode (Asynchronous, NOR-Flash Synchronous or Full Synchronous). For details on how to enter Standby, refer to Table 3: Standard Asynchronous Operating Modes, Table 5: Asynchronous Write Operations (NOR-Flash Synchronous Mode) and Table 6: Synchronous Read Operations (NOR-Flash Synchronous Mode).
4.2
Deep Power-Down
Deep Power-Down (DPD) is used by the system memory microcontroller to disable the PSRAM device when its storage capabilities are not needed. All refresh operations are then disabled. For the device to enter Deep Power-Down, bit 4 of the RCR must be set to `0' and Chip Enable, E, must go High, VIH. When the Deep Power-Down is enabled, the data stored in the device may be corrupted and BCR, RCR and DIDR content are saved. For the device exits Deep Power-Down by driving Chip Enable, E, Low, VIL. Bit 4 of the RCR will be automatically set to `1'. Once the Deep Power-Down is exited, the device will be available for normal operations after tVCHEL (time to perform an initialization sequence) During this delay, the current consumption will be higher than the specified Standby levels, but considerably lower than the active current. The content of the registers will be restored after Deep Power-Down. For details on how to enter Deep Power-Down, refer to Table 3: Standard Asynchronous Operating Modes, Table 5: Asynchronous Write Operations (NOR-Flash Synchronous Mode) and Table 6: Synchronous Read Operations (NOR-Flash Synchronous Mode).
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4 Low-power modes
M69KB096AB
4.3
Partial Array Self Refresh
The Partial Array Self Refresh (PASR) performs a limited refresh of part of the PSRAM array. This mechanism enables the device to reduce the Standby current by refreshing only the part of the memory array that contains essential data. Different refresh options can be defined by setting the RCR0 to RCR2 bits of the RCR:

Full array One eighth of the array One half of the array One quarter of the array None of the array.
These memory areas can be located either at the top or bottom of the memory array. The WAIT signal is used for arbitration when a read/write operation is launched while an onchip refresh is in progress. If locations are addressed while they are undergoing refresh, the WAIT signal will be asserted for additional clock cycles, until the refresh has completed (see Figure 6: Refresh Collision during Synchronous Burst Read in Variable Latency Mode). When the refresh operation is completed, the read or write operation will be allowed to continue normally.
4.4
Automatic Temperature Compensated Self Refresh
The leakage current of DRAM capacitive storage elements increases with the temperature. At lower temperatures, the refresh rate can be decreased to minimize the Standby current. The M69KB096AB is based on DRAM architecture, consequently it requires increasingly frequent refresh operations to maintain data integrity as the temperature increases. The Automatic Temperature Compensated Self Refresh mechanism (TCSR) that the devices feature, automatically adjusts the refresh rate depending on the operating temperature.
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M69KB096AB
5 Standard Asynchronous operating modes
5
Standard Asynchronous operating modes
The M69KB096AB supports Asynchronous Read and Write modes (Random Read, Page Read, Asynchronous Write). The device is put in Asynchronous mode by setting bit 15 (BCR15) of the BCR to `1'. The Page mode is controlled by the Refresh Configuration Register (bit RCR7). During asynchronous operations, the WAIT signal should be ignored and the Clock input signal K should be held Low, VIL. Refer to Table 3: Standard Asynchronous Operating Modes for a detailed description of asynchronous operating modes.
5.1
Asynchronous Read and Write modes
At Power-Up, the device defaults to Asynchronous Random Read mode (bit BCR15 set to `1'). This mode uses the industry standard control bus (E, G, W, LB, UB). Read operations are initiated by bringing E and G Low, VIL, while keeping W High, VIH. Valid data will be gated through the output buffers after the specific access time tELQV has elapsed. Write operations occur when E and W are Low. During Asynchronous Random Write operations, the G signal is `don't care' and W will override G. The data to be written is latched on the rising edge of E, W, LB or UB (whichever occurs first). The write operation is terminated by de-asserting E, W, LB or UB. The L input can either be used to latch the address or kept Low, VIL, during the entire read/write operation. See Figures 14 and 15, and Table 17 for details on Asynchronous Read AC waveforms and characteristics and Figures 18, 19, 20, and Table 19 for details of Asynchronous Write AC waveforms and characteristics.
5.2
Asynchronous Page Read mode
Asynchronous Page Read mode is enabled by setting RCR7 to `1'. The Latch Enable, L, and the Chip enable E must be held Low, VIL during Asynchronous Page Read operations. A Page of data is internally read. A memory page may consist of 4, 8 or 16 Words. During a 4Word page access, all the address bits except A0 to A1 should be fixed. During a 8-Word and 16-Word page access, all address bits are fixed except A0 to A2 and A0 to A3, respectively (see Table 2: Page Mode Characteristics). The first read operation within the Page has the normal access time (tAVQV), subsequent reads within the same Page have much shorter access times (tAVQV1). If the Page changes then the normal, longer timings apply again. The Page mode is not available for write operations. See Figure 16 and Table 17 for details of the Asynchronous Page Read timing requirements.
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5 Standard Asynchronous operating modes
M69KB096AB
Table 2.
Page Mode Characteristics
Page Read Address A0-A1 A0-A2 A0-A3 Page Read Start Address Don't Care Don't Care Don't Care Page Read Direction Don't Care Don't Care Don't Care
Page Size 4 Words 8 Words 16 Words
5.3
Configuration Registers Asynchronous Read and Write
Programming the registers (BCR and RCR) and reading the registers (BCR, RCR and DIDR) can be performed using the CR controlled method in standard Asynchronous mode.
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M69KB096AB
Table 3. Standard Asynchronous Operating Modes
Power E W G VIL VIH VIL VIL X VIL VIL X X UB VIL VIH VIL VIL VIH VIL LB VIL VIL VIH VIL VIL VIH CR VIL VIL VIL VIL VIL VIL
5 Standard Asynchronous operating modes
Asynchronous Modes(1)(2) Word Read Lower Byte Read Upper Byte Read Word Write Lower Byte Write Upper Byte Write Read Configuration Register (CR Controlled Method) Program Configuration Register (CR Controlled)(3) Output Disable/ No Operation Deep Power-Down(5)
A19 A18
A0-A17 A20-A21
DQ0-DQ7 DQ8-DQ15 Output Valid Output Valid High-Z Input Valid Input Valid Invalid Output Valid High-Z Output Valid Input Valid Invalid Input Valid
Valid Valid Valid Valid Valid Valid
Active (ICC)
VIH
VIL
X
X VIH
00(RCR) 10(BCR) X1(DIDR) 00(RCR) 10(BCR)
(4)
X
BCR/ RCR/DIDR Content
VIL
X
X
X
BCR/ RCR Data
X
Active (ICC) Deep PowerDown (ICCPD) Standby (IPASR)
VIH VIH
X
X
VIL
X
X
X
High-Z
VIH
X
X
X
X
X
X
X
X
High-Z
Standby
VIH
X
X
X
X
X
X
X
X
High-Z
1. The Clock signal, K, must remain Low in asynchronous operating mode, and to achieve standby power in Standby and Deep Power-Down modes. 2. The device must have been configured to operate in asynchronous mode by setting BCR15 to `1' (default value). 3. BCR and RCR only. 4. A18 and A19 are used to select the BCR, RCR or DIDR registers. 5. Bit 4 of the Refresh Configuration Register must be set to `0' and E must be maintained High, VIH, during Deep PowerDown mode.
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6 Synchronous Operating modes
M69KB096AB
6
Synchronous Operating modes
The synchronous modes allow high-speed read and write operations synchronized with the clock. The M69KB096AB supports two types of synchronous modes:

NOR-Flash:- this mode greatly simplifies the interfacing with traditional burst-mode Flash memory microcontrollers. Full Synchronous: both read and write are performed in Synchronous mode.
All the options related to the synchronous modes can be configured through the Bus Configuration Register, BCR. In particular, the device is put in Synchronous mode, either NORFlash or Full Synchronous, by setting bit BCR15 of the Bus Configuration Register to `0'. The device will automatically detect whether the NOR-Flash or the Full Synchronous mode is being used by monitoring the Clock, K, and the Latch Enable, L, signals. If a rising edge of the Clock K is detected while L is held Low, VIL (active), the device operates in Full Synchronous mode.
6.1
NOR-Flash Synchronous mode
In this mode, the device operates in synchronous mode for read operations, and in asynchronous mode for write operations. Asynchronous write operations are performed at Word level, with LB and UB Low. The data is latched on E, W, LB, UB, whichever occurs first. RCR and BCR registers can be programmed in NOR-Flash Asynchronous Write mode, using the CR controlled method (see Section 7.1: Programming and Reading Registers using the CR Controlled Method). A Program Configuration Register operation can only be issued if the device is in idle state and no burst operations are in progress. NOR-Flash Asynchronous Write operations are described in Table 5: Asynchronous Write Operations (NOR-Flash Synchronous Mode). Synchronous read operations are also performed at Word level. They are controlled by the state of E, L, G, W, LB and UB signals when a rising edge of the clock signal, K, occurs. The initial Burst Read access latches the Burst start address. The number of Words to be output is controlled by bits 0 to 2 of the BCR. The first data will be output after a number of clock cycles, also called Latency. NOR-Flash Synchronous Burst Read operations are described in Table 6: Synchronous Read Operations (NOR-Flash Synchronous Mode). When a Burst Write operation is initiated or when switching from NOR-Flash mode to Full Synchronous mode, the delay from E Low to Clock High, tELKH, should not exceed 20ns. However, when it is not possible to meet these specifications, special care must be taken to keep addresses stable after driving the Write Enable signal, W, Low. Write operations are considered as Asynchronous operations until the device detects a valid clock edge and hence the address setup time of tAVWL must be satisfied (see Figure 5: Switching from Asynchronous to Synchronous Write Operation).
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M69KB096AB
6 Synchronous Operating modes
6.2
Full Synchronous mode
In Full Synchronous mode, the device performs read and write operations synchronously. Synchronous Read and Write operations are performed at Word level. The initial Burst Read and Write access latches the Burst start address. The number of Words to be output or input during Synchronous Read and Write operations is controlled by bits 0 to 2 of the BCR. During Burst Read and Write operations, the first data will be output after a number of clock cycles defined by the Latency value. Programming the registers (BCR and RCR) and reading the registers (BCR, RCR and DIDR) can be performed using the CR controlled method in Full Synchronous mode. Full Synchronous operations are described in Table 7: Full Synchronous Mode.
6.3
Synchronous Burst Read and Write
During Synchronous Burst Read or Write operations, addresses are latched on the rising edge of the Clock K when L is Low and data are latched on the rising edge of K. The Write Enable, W, signal indicates whether the operation is going to be a read (W=VIH) or a write (W=VIL). The WAIT output will be asserted as soon as a Synchronous Burst operation is initiated and will be de-asserted to indicate when data are to be transferred to (or from) the memory array. The Burst Length is the number of Words to be output or input during a Synchronous Burst Read or Write operation. It can be configured as 4, 8, 16 or 32 Words or continuous through bit BCR0 to BCR2 or the Burst Configuration Register. The Latency defines the number of clock cycles between the beginning of a Burst Read operation and the first data output (counting from the first Clock edge where L was detected Low) or between the beginning of a Burst Write operation and the first data input. The Latency can be set through bits BCR13 to BCR11 of the Bus Configuration Register (see Table 4: Operating Frequency versus Latency). The latency can also be configured to fixed or variable by programming bit BCR14. By default, the Latency Type is set to variable. Synchronous Read operations are performed in both fixed and variable latency mode while Synchronous Write operations are only performed with fixed latency. See Figures 24, 26, and Figures 30, 31, for details on Synchronous Read and Write AC waveforms, respectively.
6.3.1
Variable Latency
In Variable Latency mode, the latency programmed in the BCR is not guaranteed and is maintained only if there is no conflict with a refresh operation. The Latency set in the BCR is applicable only for an initial burst read access, when no refresh request is pending. For a given latency value, the Variable Latency mode allows higher operating frequencies than the Fixed Latency mode (see Table 4: Operating Frequency versus Latency and Figure 3: Latency Configuration (Variable Latency Mode, No Refresh Collision)). Burst Write operations are always performed at fixed latency, even if BCR14 is configured to Variable Latency (see Section 6.3.2: Fixed Latency). Monitoring of the WAIT signal is recommended for reliable operation in this mode. See Figure 24. and 31 for details on Synchronous Burst Read and Write AC waveforms in Variable Latency mode.
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6 Synchronous Operating modes
M69KB096AB
6.3.2
Fixed Latency
The latency programmed in the BCR is the real latency. The number of clock cycles is calculated by taking into account the time necessary for a refresh operation and the time necessary for an initial Burst access. This limits the operating frequency for a given latency value (see Table 4: Operating Frequency versus Latency and Figure 4: Latency Configuration (Fixed Latency Mode)). It is recommended to use the Fixed Latency mode if the microcontroller cannot monitor the WAIT signal.
6.3.3
Row Boundary Crossing
The M69KB096AB features 128-Word rows. Row boundary crossings between adjacent rows may occur during Burst Read and Write operations. Row boundary crossings are not handled automatically by the PSRAM. The microcontroller must stop the Burst operation at the row boundary and restart it at the beginning of the next row. Burst operations must be stopped by driving the Chip Enable signal, E, High, after the WAIT signal falling edge. E must transition:

before the third Clock cycle after the WAIT signal goes Low if BCR[8] = 0, before the fourth Clock cycle after WAIT signal goes Low if BCR[8] = 1.
Refer to Figure 26 and Figure 30 for details on how to manage row boundary crossings during burst operations.
6.4
Synchronous Burst Read Interrupt
Ongoing Burst Read operations can be interrupted to start a new Burst cycle by either of the following means:
Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended). If necessary, refresh cycles will be added during the new Burst operation to schedule any outstanding refresh. If Variable Latency mode is set, additional wait cycles will be added if a refresh operation is scheduled during the Synchronous Burst Read Interrupt. WAIT monitoring is mandatory for proper system operation. Starting a new Synchronous Burst Read operation without toggling E.
An ongoing Burst Read operation can be interrupted only after the first valid data is output. When a new Burst access starts, I/O signals immediately become high impedance.
6.5
Synchronous Burst Write Interrupt
Ongoing Burst Write operations can be interrupted to start a new Burst cycle by either of the following means:

Driving E High, VIH, and then Low, VIL on the next clock cycle (recommended), Starting a new Synchronous Burst Write without toggling E. Considering that Burst Writes are always performed in Fixed Latency mode, refresh is never scheduled. A maximum Chip Enable, E, low time (tELEH) must be respected for proper device operation.
An ongoing Burst Write can be interrupted only after the first data is input. When a new Burst access starts, I/O signals immediately become high impedance.
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M69KB096AB
6 Synchronous Operating modes
See Figure 27: Burst Read Interrupted by Burst Read or Write AC Waveforms and Figure 32: Burst Write Interrupted by Burst Write or Read AC Waveforms for details on Burst Read and Burst Write interrupt AC waveforms, respectively.
6.6
Synchronous Burst Read and Write Suspend
Synchronous Burst Read and Write operations can be suspended by halting the Clock K holding it either High or Low. The status of the I/O signals will depend on the status of Output enable input, G. The device internal address counter is suspended and data outputs become high impedance tGHQZ after the rising edge of the Output Enable signal, G. It is prohibited to suspend the first data output at the beginning of a Synchronous Burst Read. See Figure 25 for details on the Synchronous Burst Read and Write Suspend mechanisms. During Synchronous Burst Read and Synchronous Burst Write Suspend operations, the WAIT output will be asserted. Bit BCR8 of the Bus Configuration Register is used to configure when the transition of the WAIT output signal between the asserted and the de-asserted state occurs with respect to valid data available on the data bus.
Table 4.
Latency Mode
Operating Frequency versus Latency
Latency (Clock Cycles) Configured Latency (Clock Cycles) Normal 3 4 3 4 5 6 7 If Refresh Collision 5 7 Max Input Clock Frequency (MHz) 104 MHz 66 104 33 52 66 75 104 80 MHz 52 80 33 52 66 75 80 -
Variable Latency BCR14 = 0 (Default)
2 (3 clock cycles) 3 (4 clock cycles) (default) All Others 2 (3 clock cycles) 3 (4 clock cycles) (default)
Fixed Latency BCR14 = 1
4 (5 clock cycles) 5 (6 clock cycles) 6 (7 clock cycles) All Others
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M69KB096AB
Table 5.
Asynchronous Write Operations (NOR-Flash Synchronous Mode)
Power E VIL Active (ICC) VIL L VIL VIL W VIL VIL G X X UB, LB VIL X CR A19 A18 VIL VIH A0-A21 DQ0DQ15 Input Valid RCR/ BCR Data X
Asynchronous Operations(1)(2) Word Write Program Configuration Register (CR Controlled)(3) Output Disable/ No Operation Standby Deep Power-Down
Valid 00(RCR) 10(BCR) VIL X X
Active (ICC) Standby (IPASR)
VIL VIH
VIH X X
VIH X X
VIH X X
VIL X X
VIL VIL X
High-Z High-Z High-Z
Deep Power-Down VIH (ICCPD)
1. The device must have been configured to operate in asynchronous mode by setting BCR15 to `1' (default value). 2. The Clock signal, K, must remain Low, during asynchronous Write operations and to achieve standby power during Standby and Deep Power-Down modes. 3. BCR and RCR only.
Table 6.
Synchronous Read Operations (NOR-Flash Synchronous Mode)
Power K E L W G LB, UB VIL VIL CR A19 A18 A0A21(2) Valid DQ15DQ0 X DataOut RCR/ BCR/ DIDR Content
Synchronous Operations(1) Initial Burst Read Subsequent Burst Read(3) Read Configuration Register (CR Controlled Method) Output Disable/No Operation Standby
! ! Active (ICC) !
VIL VIL
VIL VIH
VIH X
X VIL
VIL VIL
Valid
Valid
X
VIL
VIL
VIH
VIL
X
VIH
00(RCR) 10(BCR) X1(DIDR)
X
Active (ICC) Standby (IPASR) Deep PowerDown (ICCPD)
!
VIL
VIH
VIH
VIH
X
VIL
X
High-Z
!
VIH
X
X
X
X
X
X
High-Z
Deep PowerDown
VIL
VIH
X
X
X
X
X
X
High-Z
1. The device must have been configured to operate in synchronous mode by setting BCR15 to `0' (default value). 2. Except A18 and A19. 3. Burst Read Interrupt and Suspend are described in dedicated paragraph of the Section 6: Synchronous Operating modes.
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M69KB096AB
Table 7. Full Synchronous Mode
Power K ! ! ! ! Active (ICC) ! VIL VIL VIL VIH X E VIL VIL VIL VIL L VIL VIH VIL VIH W VIH X VIL X G LB, UB VIL VIL X VIL WAIT CR VIL VIL VIL X
6 Synchronous Operating modes
Synchronous Mode Initial Burst Read Subsequent Burst Read(2) Initial Burst Write Subsequent Burst Write Program Configuration Register (CR Controlled) Read Configuration Register (CR Controlled Method) No Operation Standby
A19
A18
A0A22(1) Valid X
DQ15DQ0 X Output Valid
X VIL VIH VIH
Valid X Valid X
Valid
Valid X
Valid X
Input Valid Input Valid
Low-Z
VIH
00(RCR) 10(BCR)
RCR/ BCR Data
X
!
VIL
VIL
VIH
VIL
VIL
VIH
00(RCR) 10(BCR) X1(DIDR)
X
RCR/ BCR/ DIDR Content
Active (ICC)
!
VIL
VIH X
VIH X
VIH X
X X High-Z
VIL VIL
X X
High-Z High-Z
Standby VIL VIH (IPASR) Deep PowerDown (ICCPD)
Deep PowerDown
VIL VIH
X
X
X
X
X
X
High-Z
1. Except A18 and A19. 2. Burst Read Interrupt, Suspend, Terminate and Burst Write Interrupt, Suspend and Terminate are described in dedicated paragraph of the Section 6: Synchronous Operating modes.
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6 Synchronous Operating modes
M69KB096AB
Figure 3.
Latency Configuration (Variable Latency Mode, No Refresh Collision)
K 0 Addr. Address Valid 1 2 3 4 5 6 7
ADV Latency = 3 Clock Cycles DQ0-DQ15 Hi Z
Q1 Q2 Q3 Q4 Q5
Latency = 4 Clock Cycles DQ0-DQ15 Hi Z
Q1 Q2 Q3 Q4
AI11280
Figure 4.
Latency Configuration (Fixed Latency Mode)
N-1 Cycle N Cycle
K tAVQV Addr. Address Valid tLLQV ADV tELQV E tKHQV2 DQ0-DQ15 OUT Hi Z
Q1 Q2 Q3 Q4 Q5
AI11281b
1. See Table 21: Synchronous Burst Read AC Characteristics for details on the synchronous read AC Characteristics shown in the above waveforms.
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M69KB096AB
Figure 5.
6 Synchronous Operating modes
Switching from Asynchronous to Synchronous Write Operation
K VALID tAVWL L tELKH E
Addr.
W
AI10203
Figure 6.
K
Refresh Collision during Synchronous Burst Read in Variable Latency Mode
A0-A22
Address Valid
L
E G
W
LB/UB Hi Z Hi Z
WAIT
DQ0-DQ15 Additional WAIT states inserted to allow Refresh completion
Q0
Q1
Q2
Q3
AI11275b
1. Additional Wait states are inserted to allow Refresh completion. The latency is set to 3 clock cycles (BCR13-BCR11 = 010). The WAIT must be active Low, VIL, (BCR10 = 0) and asserted during delay (BCR8= 0).
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7 Configuration Registers
M69KB096AB
7
Configuration Registers
The M69KB096AB features three registers:

The Bus Configuration Register (BCR) The Refresh Configuration Register (RCR) The Device ID Register (DIDR).
BCR and RCR are user-programmable registers that define the device operating mode. They are automatically loaded with default settings during Power-Up, and selected by address bits A18 and A19 (see Table 8: Register Selection). DIDR is a read-only register that contains information about the device identification. It is selected by setting address bit A18 to `1' with A19 `don't care'. The configuration registers (only BCR and RCR) can be programmed and read using two methods:

The CR Controlled Method (or Hardware Method) The Software Method.
7.1
Programming and Reading Registers using the CR Controlled Method
Read Configuration Register
The content of a register is read by issuing a read operation with Configuration Register Enable signal, CR, High, VIH. Address bits A18 and A19 select the register to be read (see Table 8: Register Selection). The value contained in the register is then available on data bits DQ0 to DQ15. The BCR, RCR and DIDR can be read either in normal asynchronous or synchronous mode. The CR pin has to be driven high prior to any access. See Tables 6 and 7 for a detailed description of Configuration register Read by the CR Controlled methods and Figures 17 and 28, CR Controlled Configuration Register Read waveforms in asynchronous and synchronous mode.
7.1.1
7.1.2
Program Configuration Register
BCR and RCR registers can be programmed by issuing a bus write operation, in asynchronous or synchronous mode (NOR-Flash or Full Synchronous), with Configuration Register Enable signal, CR, High, VIH. Address bits A18 and A19 allow to select between BCR and RCR (see Table 8: Register Selection). In synchronous mode, the values placed on address lines A0 to A15 are latched on the rising edge of L, E, or W, whichever occurs first. In asynchronous mode, a register is programmed by toggling L signal. LB and UB are `don't care'. The CR pin has to be driven high prior to any access.
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M69KB096AB
7 Configuration Registers
Refer to Tables 5 and 7 for a detailed description of Configuration Register Program by the CR Controlled method and to Figures 22 and 33, showing CR controlled Configuration Register Program waveforms in asynchronous and synchronous mode. Table 8. Register Selection
Read or Write Operation Read/Write Read/Write Read-Only A18 0 0 1 A19 0 1 X
Register RCR BCR DIDR
7.2
Programming and Reading the Registers using the Software Method
All registers (BCR, RCR, DIDR) can be read by issuing a Read Configuration Register sequence (see Figure 8: Read Configuration Register (Software Method). BCR and RCR can be programmed by issuing a Set Configuration Register sequence (see Figure 7: Set Configuration Register (Software Method). The timings will be identical to those described in Table 17: Asynchronous Read AC Characteristics. The Configuration Register Enable input, CR, is `don't care'. Read Configuration Register and Set Configuration Register sequences both require 4 read and write cycles. These cycles are performed in asynchronous mode, whatever the device operating mode: 1. 2 bus read and one bus write cycles to a unique address location, 7FFFFFh, indicate that the next operation will read or write to a configuration register. The data written during the third cycle must be `0000h' to access the RCR, `0001h' to access the BCR and `0002h' to access the DIDR during the next cycle. The fourth cycle reads from or writes to the configuration register.
2.
The timings for programming and reading the registers by the software method are identical to the asynchronous write and read timings.
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7 Configuration Registers
M69KB096AB
Figure 7.
Set Configuration Register (Software Method)
Addr. 7FFFFFh 7FFFFFh 7FFFFFh 7FFFFFh
E tEHEL2 G tEHEL2 tEHEL2
W
LB, UB
DQ0-DQ15
(2)
Configuration Register Data
AI09469f
1. Only the Bus Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified. 2. To program the BCR or the RCR on last bus write cycle, DQ0-DQ15 must be set to `0001h' and `0000' respectively. 3. The highest order address location is not modified during this operation. 4. The control signals E, G, W, LB and UB, must be toggled as shown in the above figure.
Figure 8.
Read Configuration Register (Software Method)
Addr. 7FFFFFh 7FFFFFh 7FFFFFh 7FFFFFh
E tEHEL2 G tEHEL2 tEHEL2
W
LB, UB
DQ0-DQ15
(1)
Configuration Register Data
AI09470f
1. To read the BCR, RCR or DIDR on last bus read cycle, DQ0-DQ15 must be set to `0001h', `0000' and `0002' respectively. 2. The highest order address location is not modified during this operation. 3. The control signals E, G, W, LB and UB, must be toggled as shown in the above figure.
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M69KB096AB
7 Configuration Registers
7.3
Bus Configuration Register
The Bus Configuration Register (BCR) defines how the PSRAM interacts with the system memory bus. All the device operating modes are configured through the BCR, except the Page mode which is configured through the RCR. Refer to Table 9 for the description of the Bus Configuration Register Bits.
7.3.1
Operating Mode Bit (BCR15)
The Operating Mode bit allows the Synchronous mode or the Asynchronous mode (default setting) to be selected. Selecting the Synchronous mode will allow the device to operate either in NOR Flash mode or in full Synchronous Burst mode. The device will automatically detect that the NOR Flash mode is being used by monitoring a rising edge of the Clock signal, K, when L is Low. If this should not be the case, the device operates in full Synchronous mode.
7.3.2
Latency Type (BCR14)
The Latency Type bit is used to configure the latency type. When the Latency Type bit is set to `0', the device operates in variable latency mode (only available for Synchronous Read mode). When it is `1', the fixed latency mode is selected and the latency is defined by the values of bits BCR13 to BCR11. Refer to Figures 3 and 4 for examples of fixed and variable latency configuration.
7.3.3
Latency Counter Bits (BCR13-BCR11)
The Latency Counter bits are used to set the number of clock cycles between the beginning of a read or write operation and the first data output or input. The Latency Counter bits can only assume the values shown in Table 9: Bus Configuration Register Definition (see also Figures 3 and 4).
7.3.4
WAIT Polarity Bit (BCR10)
The WAIT Polarity bit indicates whether the WAIT output signal is active High or Low. As a consequence, it also determines whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state (see Figure 10: WAIT Polarity). By default, the WAIT output signal is active High.
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7.3.5
WAIT Configuration Bit (BCR8)
The system memory microcontroller uses the WAIT signal to control data transfer during Synchronous Burst Read and Write operations. The WAIT Configuration bit is used to determine when the transition of the WAIT output signal between the asserted and the de-asserted state occurs with respect to valid data available on the data bus. When the Wait Configuration bit is set to `0', data is valid or invalid on the first Clock rising edge immediately after the WAIT signal transition to the de-asserted or asserted state. When the Wait Configuration bit is set to `1' (default settings), the WAIT signal transition occurs one clock cycle prior to the data bus going valid or invalid. See Figure 9: WAIT Configuration Example for an example of WAIT configuration.
7.3.6
Driver Strength Bits (BCR5-BCR4)
The Driver Strength bits allow to set the output drive strength to adjust to different data bus loading. Normal driver strength (full drive) and reduced driver strength (half drive and a quarter drive) are available. By default, outputs are configured at `half drive" strength.
7.3.7
Burst Wrap Bit (BCR3)
Burst Read operations can be confined inside the 4, 8, 16 or 32 Word boundary (wrap mode). If the wrap mode is not enabled, the device outputs data sequentially up to the end of the row, regardless of burst boundaries. The Burst Wrap bit is used to select between `wrap' and `no wrap' mode.
7.3.8
Burst Length Bits (BCR2-BCR0)
The Burst Length bits set the number of Words to be output or input during a Synchronous Burst Read or Write operation. They can be set for 4 Words, 8 Words, 16 Words, 32 Words or Continuous Burst (default settings), where all the Words are output or input sequentially regardless of address boundaries (see also Table 10: Burst Type Definition).
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Table 9.
Address Bits
7 Configuration Registers
Bus Configuration Register Definition
Bus Configuration Register Bits Name Value Description Synchronous Mode (NOR Flash or Full Synchronous Mode) Asynchronous Mode (Default) Variable Latency (Default) Fixed Latency 3 Clock Cycles 4 Clock Cycles (Default) 5 Clock Cycles 6 Clock Cycles 7 Clock Cycles
A15
BCR15
Operating Mode Bit
0 1 0
A14
BCR14
Latency Type 1 010 011
A13-A11
BCR13BCR11
Latency Counter 100 Bits 101 110
Other Configurations Reserved(1) 0 A10 BCR10 WAIT Polarity Bit 1 A9 WAIT Active Low WAIT Active High (default).See Figure 10: WAIT Polarity.
Must be set to `0' Reserved(1) 0 WAIT Asserted During Delay (see Figure 9: WAIT Configuration Example). WAIT Asserted One Clock Cycle Before Delay (Default)
A8
BCR8
Wait Configuration Bit 1
A7-A6
-
-
Must be set to `0' Reserved(1) 00 Full Drive 1/2 Drive (Default) 1/4 Drive Reserved(1) Wrap No Wrap (default) 4 Words 8 Words 16 Words 32 Words Continuous Burst (default)
A5-A4
BCR5-BCR4
Driver Strength Bits
01 10 11 0
A3
BCR3
Burst Wrap Bit 1 001 010 011
A2-A0
BCR2-BCR0
Burst Length Bit
100 111
Other Configurations Reserved(1)
1. Programming the BCR with reserved value will force the device to use the default register settings.
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Table 10.
Mode Start Add
Burst Type Definition
4 Words (Sequential) BCR2BCR0=001b 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 8 Words (Sequential) BCR2-BCR0=010b 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 ... ... 16 Words (Sequential) BCR2-BCR0=011b 0-1-2-3-...-14-15 1-2-3-4-...-14-15-0 2-3-4-5-...-15-0-1 3-4-5-...-15-0-1-2 4-5-...-15-0-1-2-3 5-6-7-...-15-0-1-...-4 6-7-8-...-15-0-1-...-5 7-8-9-...15-0-1-...-6 ... 14-15-0-1-2-...-13 15-0-1-2-...-14 ... ... ... 32 Words (Sequential) BCR2BCR0=100b 0-1-2-3-...-30-31 1-2-3-...-30-31-0 2-3-4-...-31-0-1 3-4-5-...-31-0-1-2 4-5-6-...-31-0-1-2-3 5-6-7-..-31-0-1-..-4 6-7-8-...-31-0-1-...-5 7-8-9-...-31-0-1-...-6 ... 14-15-...-31-0-...-13 15-0-1-...-31-0-...-14 ... 30-31-0-...-28-29 31-0-1-...-29-30 0-1-2-3 1-2-3-4 2-3-4-5 3-4-5-6 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-8 2-3-4-5-6-7-8-9 3-4-5-6-7-8-9-10 4-5-6-7-8-9-10-11 5-6-7-8-9-10-11-12 6-7-8-9-10-11-12-13 7-8-9-10-11-12-1314 ... 14-15-...-29 15-16-17-...-30 ... 30-31-0-...-28-62 31-0-1-...-29-63 14-15-16-...-46 15-16-17-...-47 0-1-2-3-...-14-15 1-2-3-..-15-16 2-3-4-...-17 3-4-5-...-18 4-5-6-...-19 5-6-7-...-20 6-7-8-...-21 7-8-9-...-22 0-1-2-3-...-30-31 1-2-3-4-...-32 2-3-4-...-33 3-4-5-...-34 4-5-6-...-35 5-6-7-...-36 6-7-8-...-37 7-8-9-...-38 Continuous Burst BCR2-BCR0=111b
0 1 2 3 4 Wrap (BCR3='0') 5 6 7 ... 14 15 ... 30 31 0 1 2 3 4 No Wrap (BCR3='1') 5 6 7 ... 14 15 ... 30 31
0-1-2-3-..-511-. 1-2-3-4-...-510-5112-3-4-5-6-...-5113-4-5-...-5114-5-...-5115-6-7-...-5116-7-8-...-5117-8-9-...-511... 14-...51115-...511... 30-...-51131-...-5110-1-2-3-..-511-. 1-2-3-4-...-5122-3-4-5-...-5133-4-5-...-5144-5-6-...-5155-6-7-...-5166-7-8-...-5177-8-9-...-518... 14-...-52515-...-526... 30-...-54131-...-542-
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Figure 9. WAIT Configuration Example
7 Configuration Registers
K
WAIT DQ0-DQ15 BCR8='0', BCR10='1' Data Valid During Current Cycle DQ0-DQ15 BCR8='1', BCR10='1' Data Valid During Next Cycle Hi-Z
Data[0] Data[1]
Hi-Z
Data[0]
AI06795b
Figure 10. WAIT Polarity
K
BCR8='0' BCR10='1'
WAIT DQ0-DQ15 Hi-Z Data[0] Data[1]
BCR8='0' BCR10='0'
WAIT DQ0-DQ15 Hi-Z Data[0] Data[1]
AI09963
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7.4
Refresh Configuration Register
The role of the Refresh Configuration Register (RCR) is:

to define how the self refresh of the PSRAM array is performed, to select the Deep Power-Down mode, to enable Page Read operations.
Refer to Table 11 for the description of the Refresh Configuration Register Bits.
7.4.1
Page Mode Operation Bit (RCR7)
The Page Mode operation bit determines whether the Asynchronous Page Read mode is enabled. At power-up, the RCR7 bit is set to `0', and the Asynchronous Page Read mode is disabled.
7.4.2
Deep Power-Down Bit (RCR4)
The Deep Power-Down bit enables or disables all refresh-related operations. Deep PowerDown mode is enabled when the RCR4 bit is set to `0', and remains enabled until this bit is set to `1'. When E goes high, the device enters Deep-Power Down mode and remains in this mode until the E mean time goes low and stays low for at least 10s. At power-up, the Deep PowerDown mode is disabled. See the Section 4.2: Deep Power-Down for more details.
7.4.3
Partial Array Refresh Bits (RCR2-RCR0)
The Partial Array Refresh bits allow refresh operations to be restricted to a portion of the total PSRAM array. The refresh options can be full array, one half, one quarter, one eighth or none of the array. These memory areas can be located either at the top or bottom of the memory array. By default, the full memory array is refreshed.
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Table 11.
Address Bits A15-A8 A7 A6-A5 A4 A3
7 Configuration Registers
Refresh Configuration Register Definition
Refresh Configuration Register Bits RCR7 RCR4 Name Page Mode Operation Bit Deep PowerDown Bit Value Must be set to `0' Reserved 0 1 Page Read Mode Disabled (Default) Page Read Mode Enabled Description
Must be set to `0' Reserved 0 1 Deep Power-Down Enabled Deep Power-Down Disabled (Default)
Must be set to `0' Reserved 000 001 010 Full Array Refresh (Default) Refresh of the Bottom Half of the Array Refresh of the Bottom Quarter of the Array Refresh of the Bottom Eighth of the Array None of the Array Refresh of the Top Half of the Array Refresh of the Top Quarter of the Array Refresh of the Top Eighth of the Array
A2-A0
RCR2-RCR0
Partial Array Refresh Bits
011 100 101 110 111
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7.5
Device ID Register
The Device ID Register (DIDR) is a read-only register that contains the Manufacturer code. It is preprogrammed by STMicroelectronics and cannot be modified by the user. Refer to Table 12 for the description of the Bus Configuration Register Bits.
Table 12.
Address Bits A15
Device ID Register Definition
Device ID Register Bits DIDR15 Name Row Length 0 0000 0001 0010 Value 128 Words A B C D P Description
A14-A11
DIDR14-DIDR11
Design Version 0011 1111
Other Configurations Reserved 000 001 010 A10-A8 DIDR10-DIDR8 Device Density 011 100 128 Mbits 256 Mbits 16 Mbits 32 Mbits 64 Mbits
Other Configurations Reserved 001 010 A7-A5 DIDR7-DIDR5 PSRAM Generation 011 2.0 Other Configurations Reserved 00001 00010 00011 A4-A0 DIDR4-DIDR0 Device ID 00100 01111 Renesas STMicroelectronics Cypress Infineon Micron 1.0 1.5
Other Configurations Reserved
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8 Maximum Rating
8
Maximum Rating
Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Table 13.
Symbol TA TSTG VCC VCCQ VIO
Absolute Maximum Ratings
Parameter Ambient Operating Temperature Storage Temperature Core Supply Voltage Input/Output Buffer Supply Voltage Input or Output Voltage Min -30 -55 -0.2 -0.2 -0.2 Max +85 150 2.45 2.45 2.45 Unit C C V V V
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9 DC and AC parameters
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9
DC and AC parameters
This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 14: Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters.
Table 14.
Operating and AC Measurement Conditions
M69KB096AB Parameter(1) Min Max 1.95 1.95 30 50 0 VCC/2 1 VCC V V pF V V V/ns Unit 1.7 1.7
VCC Supply Voltage VCCQ Input/Output Buffer Supply Voltage Load Capacitance (CL) Output Circuit Protection Resistance (R) Input Pulse Voltages(2)(3) Input and Output Timing Ref. Voltages(2)(3) Input Rise Time tr and Fall Time tf(2)(3)
1. All voltages are referenced to VSS. 2. Referenced to VSS. 3. VCC=VCCQ
Figure 11. AC Measurement I/O Waveform
I/O Timing Reference Voltage VCCQ VCCQ/2 VSSQ
AI09484c
1. Logic states `1' and `0' correspond to AC test inputs driven at VCCQ and VSS respectively. Input timings begin at VCCQ/2 and output timings end at VCCQ/2.
Figure 12. AC Input Transitions
VCCTyp 10% tr tf
ai10122
90%
90% 10%
VSS
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M69KB096AB
Figure 13. AC Measurement Load Circuit
VCCQ/2
9 DC and AC parameters
R
DEVICE UNDER TEST CL
OUT
AI11289
Table 15.
Symbol CIN CIO
Capacitance
Parameter Input Capacitance Data Input/Output Capacitance Test Condition TA = 25C, f = 1MHz, VIN = 0V Min 2 3.5 Max 6 6 Unit pF pF
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M69KB096AB
Table 16.
Symbol VOH(1) VOL(1) VIH(2) VIL(3) ILI ILO ICC1(4) ICC2(4) ICC3(4)
DC Characteristics
Parameter Refreshed Array Test Conditions IOH = -0.2mA IOL = 0.2mA VCCQ -0.4 - 0.2 VIN = 0 to VCCQ G = VIH or E = VIH VIN = 0V or VCCQ, IOUT = 0mA, E = VIL VIN = 0V or VCCQ IOUT = 0mA, E = VIL VIN = 0V or VCCQ IOUT = 0mA, E = VIL VIN = 0V or VCCQ IOUT = 0mA, E = VIL VIN = 0V or VCCQ IOUT = 0mA, E = VIL 104MHz 80MHz 104MHz 80MHz 104MHz 80MHz Min. 0.8VCCQ 0.2VCCQ VCCQ + 0.2 0.4 1 1 25 Typ Max. Unit V V V V A A mA
Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Asynchronous Read/Write Random at tRC min Asynchronous Page Read Burst, Initial Read/Write Access
15 35 30 30 25 35 30 140 120
mA mA mA mA mA mA mA A A A A A A
ICC4R(4) Continuous Burst Read ICC4W(4) Continuous Burst Write Full Array 1/2 Array Partial Array Refresh Standby 1/4 Array Current 1/8 Array None ISB(5) ICCPD Standby Current
IPASR(4)
VIN = 0V or VCCQ E = VCCQ
110 105 95
VIN = 0V or VCCQ E = VCCQ VIN = 0V or VCCQ, VCC, VCCQ = 1.95V; TA= +85C 3
140
Deep-Power Down Current
10
A
1. BCR5-BCR4 = 01 (default settings). 2. Input signals may overshoot to VCCQ+ 1.0V for periods of less than 2ns during transitions. 3. Output signals may undershoot to VSS - 1.0V for periods of less than 2ns during transitions. 4. This parameter is specified with all outputs disabled to avoid external loading effects. The user must add the current required to drive output capacitance expected for the actual system. 5. ISB maximum value is measured at +85C with PAR set to Full Array. In order to achieve low standby current, all inputs must be driven either to VCCQ or VSSQ. ISB might be slightly higher for up to 500ms after Power-up, or when entering Standby mode.
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Table 17.
Symbol tAVQV tLLQV tLHAX tLHRL tAVLH tRHLH tBLQV tBHQZ(2) tBLQX(3) tELTV tELQV tELLH tEHEL tEHQZ(2) tELQX(3) tGLQV tGHQZ(2) tGLQX(3) tAVAX tLLLH
9 DC and AC parameters
Asynchronous Read AC Characteristics
Alt. tAA tAADV tAVH Parameter(1) Address Valid to Output Valid Latch Enable Low to Output Valid Latch Enable High to Address Transition Latch Enable High to Configuration Register Low Address Valid to L High Configuration Register High to L High Upper/Lower Byte Enable Low to Output Valid Upper/Lower Byte Enable High to Output Hi-Z Upper/Lower Byte Enable Low to Output Transition Chip Enable Low to WAIT Valid Chip Enable Low to Output Valid Chip Enable Low to L High Chip Enable High between Subsequent Asynchronous Operations Output Enable High to Output Hi-Z Chip Enable High to Output Hi-Z Chip Enable Low to Output Transition Output Enable Low to Output Valid Output Enable Low to Output Hi-Z Output Enable Low to Output Transition Read Cycle Time Latch Enable Low Pulse Width 3 70 5 10 20 8 7 5 8 10 1 7.5 70 2 Min Max 70 70 Unit ns ns ns
tAVS tBA tBHZ tBLZ tCEW tCO tCVS tCPH tHZ tLZ tOE tOHZ tOLZ tRC tVP
5 70 8
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement Conditions and Figure 13: AC Measurement Load Circuit. 2. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2. 3. The Low-Z timings measure a 100mV transition from the Hi-Z (VCCQ/2) level to either VOH or VOL.
Table 18.
Symbol tAVQV1 tAVAV tELEH tAVQX
Asynchronous Page Read AC Characteristics
Alt. tAPA tPC tCEM tOH Page Access Time Page Cycle Time Maximum Chip Enable Pulse Width Data Hold from Address Change 5 Parameter(1) Min 20 20 4 Max Unit ns ns s ns
1. These timings have been obtained in the measurement conditions described in Figure 14: Operating and AC Measurement Conditions and Figure 13: AC Measurement Load Circuit.
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M69KB096AB
Figure 14. Asynchronous Random Read AC Waveforms
tAVAX Addr. VALID ADDRESS tAVQV L tEHEL E tELQV LB/UB tBLQV G tGLQV W Hi-Z tGLQX tBLQX
VALID OUTPUT
tEHQZ
tBHQZ
tGHQZ
DQ0-DQ15
Hi-Z
tELQX tELTV WAIT Hi-Z Hi-Z
AI11276c
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9 DC and AC parameters
Figure 15. Latch Enable Controlled, Asynchronous Random Read AC Waveforms
Addr.
VALID ADDRESS
tAVQV tAVLH L tLLQV tLLLH E tELQV tELLH G tGLQV tGLQX LB/UB tBLQV tGHQZ tEHQZ tEHEL tLHAX
tBLQX DQ0-DQ15 Hi-Z tELQX
VALID OUTPUT
tBHQZ Hi-Z
AI11567
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9 DC and AC parameters
M69KB096AB
Figure 16. Asynchronous Page Read AC Waveforms (4 Words)
tAVAX A2-A22 VALID ADDRESS
Page Address A0-A1
X
Y tAVAV
Z tAVAV
A tAVAV
L tELEH E tELQV tGLQV, tBLQV G, LB,UB tAVQV DQ0-DQ15 Hi-Z
DQN+X
tBHQZ, tEHQZ, tGHQZ tAVQV1
DQN+Y DQN+Z DQN+A
tAVQX
AI11568
1. Any address can be used as starting address.
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9 DC and AC parameters
Figure 17. CR Controlled Configuration Register Read Followed by Read, Asynchronous Mode
Addr. (Except A18-A19) tRHLH A18-19 Select Configuration Register tLHRL tAVQV CR ADDRESS ADDRESS
L tLLLH tLLQV E tELQV G Initiate Configuration Register Access tEHQZ tEHEL
W tGLQX LB/UB tELQX DQ0-DQ15 Configuration Register Data Valid Data Valid
AI11566
1. A18-A19 must be set to `00b' to select RCR, `01b' to select the BCR and `1Xb' to select the DIDR.
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M69KB096AB
Table 19.
Symbol tAVBL tAVEL tAVWL tLLWL tLHAX tLHRL tAVLH tRHLH tAVWH tAVEH tAVBH tBLBH tBLEH tBLWH tELTV tEHEL tELLH tELWH tELEH tELBH tEHDX tWHDX tBHDX tELWH tDVBH tDVEH tDVWH tEHTZ tBHTZ(2) tLLWH tAVAX tWHQZ tWLBH tWLEH tWLWH(3)
Asynchronous Write AC Characteristics
Alt. Parameter(1) Min Max Unit
tAS
Address Set-up to Beginning of Write Operation
0
ns
tAVH
Latch Enable High to Address Transition or Latch Enable High to Configuration Register Low Address Valid to Latch Enable High Configuration Register High to Latch Enable High
2
ns
tAVS
5
ns
tAW
Address Set-up to End of Write Operation
70
ns
tBW
Upper/Lower Byte Enable Low to End of Write Operation
70
ns
tCEW Chip Enable Low to WAIT Valid tCPH tCVS Chip Enable High between Subsequent Asynchronous Operations Chip Enable Low to L High
1 5 7
7.5
ns ns ns
tCW
Chip Enable Low to End of Write Operation
70
ns
tDH
Input Hold from Write
0
ns
tDW
Input Valid to Write Setup Time
20
ns
tHZ tVS tWC tOW
Chip Enable High to WAIT Hi-Z LB/UB High to WAIT Hi-Z Write Enable High to WAIT Hi-Z Latch Enable Low to Write Enable High Write Cycle Time End of Write to Input Low-Z 70 70 5
8
ns
ns ns ns
tWP
Write Pulse Width
45
ns
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9 DC and AC parameters
Symbol tWHWL tWHAX tEHAX tBHAX
Alt.
Parameter(1)
Min 10
Max
Unit ns
tWPH Write Enable Pulse Width High
tWR
Write Recovery Time
0
ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement Conditions and Figure 13: AC Measurement Load Circuit. 2. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2. The Low-Z timings measure a 100mV transition from the Hi-Z (VCCQ/2) level to either VOH or VOL. 3. W Low time must be limited to tEHEL.
Figure 18. Chip Enable Controlled, Asynchronous Write AC Waveforms
tAVAX Addr.
VALID ADDRESS
tAVEH L tAVEL, tAVBL E tBLEH LB/UB tELEH
tEHAX
tEHEL
G tWHWL W tWLEH
tLLWL tDVEH Hi-Z tELTV
VALID INPUT
DQ0-DQ15
tEHDX
tEHTZ Hi-Z
AI11284b
WAIT
Hi-Z
1. Data Inputs are Hi-Z if E is High, VIH.
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M69KB096AB
Figure 19. Upper/Lower Byte Enable Controlled, Asynchronous Write AC Waveforms
tAVAX Addr.
VALID ADDRESS
tAVBH L tELBH E tBLBH LB/UB
tBHAX
G tWHWL W tLLWL tDVBH DQ0-DQ15 IN Hi-Z tELQX DQ0-DQ15 OUT Hi-Z
DON'T CARE VALID INPUT
tWLBH
tBHDX
tWLQZ
tELTV WAIT Hi-Z
tBHTZ Hi-Z
AI11285b
1. Data Inputs are Hi-Z if E is High, VIH.
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Figure 20. Write Enable Controlled, Asynchronous Write AC Waveforms
tAVAX Addr.
VALID ADDRESS
9 DC and AC parameters
tAVWH L tELWH E tBLWH LB/UB
tWHAX
G tWHWL W tAVWL DQ0-DQ15 tLLWL Hi-Z tELTV Hi-Z tDVWH
VALID INPUT
tWLWH
tWHDZ tWHDX
WAIT
Hi-Z
AI11569
1. Data Inputs are Hi-Z if E is High, VIH.
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M69KB096AB
Figure 21. L Controlled, Asynchronous Write AC Waveforms
Addr. tAVLH tLLWH tLLLH L tAVWH tELWH E tBLWH LB/UB
VALID ADDRESS
tLHAX
G tWLWH W tLLWL DQ0-DQ15 Hi-Z tELTV WAIT Hi-Z Hi-Z
AI11570
tWHWL
tDVWH
VALID INPUT
tEHDX
1. Data Inputs are Hi-Z if E is High, VIH.
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9 DC and AC parameters
Figure 22. CR Controlled Configuration Register Program, Asynchronous Mode
OPCODE(3) tAVLH A18-A19 tLHAX 00(RCR), 01 (BCR)
Addr. (Except A18-A19)
L
tLLLH E Access to Configuration Register
G
W tWLWH A0-A15 Latched into Register CR tRHLH LB, UB
AI11571
tLHRL
1. Only the content of the Bus Configuration Register (BCR) and Refresh Configuration Register (RCR) can be modified. 2. Data Inputs/Outputs are not used. 3. The Opcode is the value to be written the configuration register. 4. W must go High after L goes High 5. CR is latched on the rising edge of L. There is no setup requirement of CR with respect to E.
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M69KB096AB
Table 20.
Symbol
Clock Related AC Timings
104MHz Alt. Parameter Min Max 104 9.62 1.6 12.5 1.8 Min Max 80 MHz ns ns 80MHz Unit
fCLk tKHKH tR tF tKHKL tKLKH
fCLk tCLK tKHKL
Clock frequency Clock Period Clock Rise Time Clock Fall Time Clock High to Clock Low Clock Low to Clock High 3
tKP
4
ns
Table 21.
Symbol tAVQV tLLQV tKHQV1 tKHQV2 tGLQV tEHEL(2) tELEH(2) tELTV tLLTV tELQV tELKH tKHAX tKHBH tKHWL tKHEH tKHLH tKHQX tEHQZ tEHTZ(3) tKHTX tKHTV tGHQZ(3)
Synchronous Burst Read AC Characteristics
104MHz Alt. tAA tAADV tABA tACLK tBOE tCBPH tCEM tCEW tCO tCSP Parameter(1) Min Address Valid to Output Valid (Fixed Latency) Latch Enable Low to Output Valid (Fixed Latency) Burst to Read Access Time (Variable Latency) Clock High to Output Delay Delay From Output Enable Low to Output Valid in Burst mode Chip Enable High between Subsequent Operations in Full-Synchronous or NOR-Flash mode. Chip Enable Pulse Width Chip Enable Low to WAIT Valid Latch Enable Low to WAIT Valid Chip Enable Low to Output Valid Chip Enable Low to Clock High 3 1 5 4 7.5 70 4 1 Max 70 70 35 7 20 6 4 7.5 70 Min Max 70 70 46 9 20 ns ns ns ns ns ns s ns ns ns 80MHz Unit
tHD
Hold Time From Active Clock Edge
2
2
ns
tHZ
Chip Enable High to Output Hi-Z or WAIT Hi-Z
8
8
ns
tKHTL tOHZ
Clock High to WAIT Valid Output Enable High to Output Hi-Z
7 8
9 8
ns ns
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M69KB096AB
9 DC and AC parameters
104MHz Symbol tGLQX(4) tAVKH tRHKH tQVKH tLLKH tBLKH tWHKH tSP Set-up Time to Active Clock Edge 3 3 Alt. tOLZ Parameter(1) Min Output Enable Low to Output Transition 3 Max
80MHz Unit Min 3 Max ns
ns
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement Conditions and Figure 13: AC Measurement Load Circuit. 2. A refresh opportunity must be offered every tELEH. A refresh opportunity is possible either if E is High during the rising edge of K; or if E is High for longer than 15ns. 3. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2. 4. The Low-Z timings measure a 100mV transition from the Hi-Z (VCCQ/2) level to either VOH or VOL.
Figure 23. Clock input AC Waveform
tKHKL tKHKH
tf tKLKH
tr
AI06981
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9 DC and AC parameters
M69KB096AB
Figure 24. 4-Word Synchronous Burst Read AC Waveforms (Variable Latency Mode)
tKHKH tKHKL
K tAVKH tKHAX Addr.
VALID ADDRESS
tKHLH tLLKH L tELEH tELKH E tGLQV G tWHKH W tBLKH LB/UB tELTV WAIT Hi-Z tKHQV2 D0-D15 Hi-Z READ Burst Identified (W = High) tKHQX
VALID OUTPUT VALID OUTPUT VALID OUTPUT VALID OUTPUT
tKHQV1
tKHEH
tEHEL
tEHQZ
tKHWL
tGLQX
tGHQZ
tKHBH
tKHTX Hi-Z
AI11573
1. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0).
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M69KB096AB
Figure 25. Synchronous Burst Read Suspend and Resume AC Waveforms
tKHKL K tAVKH Addr. tAVLH L tLLKH tELKH E tGLQX G tWHKH W tBLKH LB/UB tKHTX WAIT Hi-Z tKHWL tGLQV DON'T CARE tGHQZ tGLQV tKHLH Valid Address tKHAX
9 DC and AC parameters
Valid Address
tEHQZ tEHEL
tGHQZ
DON'T CARE
Hi-Z
D0-D15
Hi-Z tKHQV1
Valid Output
Valid Output tKHQX
Valid Output
Valid Output
Valid Output
Valid Output
AI11287e
1. The latency Type (BCR14) can be set to fixed or variable during Burst Read Suspend operations.The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 2. During Burst Read Suspend operations, the Clock signal must be stable (High or Low). 3. G can be held Low, VIL, during Burst Suspend operations. If so, data output remain valid.
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9 DC and AC parameters
M69KB096AB
Figure 26. Burst Read Showing End-of-Row Condition AC Waveforms (No Wrap)
tKLKH, tKHKL K tKHKH Addr. High L Low tF DON'T CARE
LB/UB
E
Low
Note 2
G
Low
W tKHTV WAIT
DON'T CARE tEHTZ tEHTZ High-Z
DQ0-DQ15
VALID OUTPUT
VALID OUTPUT
End of Row
AI11574
1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to 1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low.
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M69KB096AB
Figure 27. Burst Read Interrupted by Burst Read or Write AC Waveforms
Hi-Z
9 DC and AC parameters
tGHQZ
VALID OUTPUT
tKHEH
Burst Read Interrupted by New Burst Read or Write (2)
VALID OUTPUT
VALID OUTPUT
tKHQV2
VALID OUTPUT
tGLQV
tKHQX
High
tDVKH
tKHWL
tKHAX
tKHTV
tKHLH
Hi-Z
tELEH(3)
LB/UB 2nd Write Cycle
VALID ADDRESS
tLLTV
Note 4
tWHKH
tGHQZ
tKHQX
tKHKH
tAVKH
tKHAX
tKHLH
VALID ADDRESS
tELKH
tWHKH
tLLKH
tKHWL
Hi-Z
tGLQV
tKHQV2
1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). All Burst operations are given for variable latency and no refresh collision. 2. The Burst Read is interrupted during the first allowable clock cycle, i.e. after the first data is received by the microcontroller. 3. The Chip Enable signal, E, can remain Low, between burst operations, but it must not remain Low for longer than tELEH. 4. If the latency is variable, WAIT is asserted tKHTV after L is clocked Low. If the latency is fixed, WAIT is asserted tLLTV after L falling edge.
D0-D15 2nd Read Cycle
tAVKH
G 2nd Read Cycle
WAIT
Addr.
W
K
L
E
LB/UB 2nd Read Cycle
Hi-Z
VALID OUTPUT
tLLKH
D0-D15 2nd Write Cycle
G 2nd Write Cycle
Hi-Z
VALID INPUT
VALID INPUT
VALID INPUT
VALID INPUT
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AI11572
9 DC and AC parameters
M69KB096AB
Figure 28. CR Controlled Configuration Register Read Followed by Read, Synchronous Mode
K
Addr. (except A18-A19) tAVKH A18-A19 tRHKH CR tLLKH L tELKH E tKHQV1 tEHEL tKHLH tKHRL tKHAX
ADDRESS
ADDRESS
tLLKH
tEHQZ G High W High-Z tBLKH UB, LB tELTV WAIT tGLQX DQ0-DQ15 tKHQV2 CR VALID tKHQX
ai10132f
tGLQV
tGHQZ
tGLQV
tBLKH
DATA VALID
1. A18-A19 must be set to `00b' to select RCR, `01b' to select BCR and `1Xb' to select the DIDR.
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Table 22.
Symbol tAVWL tLLWL(2) tLHAX tEHEL(3) tELEH(3) tELTV tLLTV tELKH tKHAX tKHRL tKHLH tKHDX tKHEH tKHBH tKHWH tKHLL tEHDZ tEHTZ(4) tKHTV
tKHTX
9 DC and AC parameters
Synchronous Burst Write AC Characteristics
104MHz Alt. Parameter(1) Min tAS tAVH tCBPH tCEM tCEW tCSP Address Set-up to Beginning of Write Operation Latch Enable High to Address Transition (Fixed Latency) Chip Enable High between Subsequent Operations in Full-Synchronous or NOR-Flash mode. Maximum Chip Enable Low Pulse Chip Enable Low to WAIT Valid Chip Enable Low to Clock High 1 3 0 2 5 4 7.5 1 4 Max Min 0 2 6 4 7.5 Max ns ns ns s ns ns 80MHz Unit
tHD
Hold Time From Active Clock Edge
2
2
ns
tKADV tHZ
Last Clock Rising Edge to Latch Enable Low (Fixed Latency) Chip Enable High to Input Hi-Z or WAIT Hi-Z
4
6
ns
8
8
ns
tKHTL
Clock High to WAIT Valid or Low
7
9
ns
tAVKH tDVKH tWLKH tLLKH tBLKH tWHKH tWHWL
1. These timings have been obtained in the measurement conditions described in Table 14: Operating and AC Measurement Conditions and Figure 13: AC Measurement Load Circuit. 2. tAVWL and tLLWL, are required if tELKH> 20ns. 3. A refresh opportunity must be offered every tELEH. A refresh opportunity is possible either if E is High during the rising edge of K; or if E is High for longer than 15ns. 4. The Hi-Z timings measure a 100mV transition from either VOH or VOL to VCCQ/2.
tSP
Set-up Time to Active Clock Edge
3
3
ns
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9 DC and AC parameters
M69KB096AB
Figure 29. 4-Word Synchronous Burst Write AC Waveforms (Variable Latency Mode)
tKHKH
K
Addr. tAVKH tAVWL tLLWL L tLLKH
VALID ADDRESS
tKHAX tKHLL
tKHLH tBLKH tKHBH
LB/UB tELKH E High G tWLKH W tKHTX tELTV WAIT Hi-Z Note 2 tDVKH D0-D15 Hi-Z WRITE Burst Identified (W = Low)
ai11288 VALID INPUT
tELEH
tEHEL
tKHEH
tKHWH
tEHTZ Hi-Z tKHDX
VALID INPUT VALID INPUT VALID INPUT
1. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and asserted during delay (BCR8=0). 2. The WAIT signal must remain asserted for LC clock cycles (LC Latency code), whatever the Latency mode (fixed or variable). 3. tAVLL and tLLWL, are required if tELKH> 20ns.
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9 DC and AC parameters
Figure 30. Burst Write Showing End-of-Row Condition AC Waveforms (No Wrap)
tKLKH K tKHKH Addr. tF DON'T CARE
L
LB/UB Note 2 High G
E
W tKHTV WAIT tDVKH DQ0-DQ15
VALID INPUT D[n]
DON'T CARE tEHTZ tEHTZ High-Z tKHDX
VALID INPUT D[n+1]
End of Row (A6-A0 = 7Fh)
ai11575
1. The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 2. The Chip Enable signal, E, must go High before the third Clock cycle after the WAIT signal goes Low. If BCR8 were set to 1, E would have to go Low before the fourth Clock cycle after WAIT signal goes Low.
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9 DC and AC parameters
M69KB096AB
Figure 31. Synchronous Burst Write Followed by Read AC Waveforms (4 Words)
tGHQZ
ai11291c
tKHEH
tKHQX tGLQX tKHTX (2) tELKH tWHKH tKHWL tKHDX tKHTX tKHWH tDVKH WAIT UB, LB W tWLKH E G
tKHLH
tKLKH
tKHAX
tAVKH
tEHEL
tKHLL
tKHEH
tKHKH
tKHAX
tKHLH
tAVKH
tLLKH
tELKH
1. The Latency type can set to fixed or variable mode. The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). 2. E can remain Low between the Burst Read and Burst Write operation, but it must not be held Low for longer than tELEH.
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DQ0DQ15
Addr.
K
L
DIN0
DIN1 DIN2
tKHKL
DIN3
DO0
DO1
DO2
DO3
M69KB096AB
Figure 32. Burst Write Interrupted by Burst Write or Read AC Waveforms
9 DC and AC parameters
VALID INPUT
tKHEH
tGHQZ
VALID INPUT
tKHBH
Burst Write Interrupted by New Burst Write or Read (2)
tKHDX
tKHQX
tDVKH
VALID INPUT
tKHWL
tKHAX
tKHLH
tKHTV
tGLQV
VALID ADDRESS
tELEH(3)
tKHDX
tGLKH
tKHQV2
tAVKH
tWHKH
tLLKH
tKHKH
tKHLH
VALID ADDRESS
tELKH
tAVKH
tWHKH
tLLKH
tKHWH
tKHAX
High
Hi-Z
tDVKH
1. The latency Type (BCR14) can be set to fixed or variable.The Latency is set to 3 clock cycles (BCR13-BCR11 = 101). The WAIT signal is active Low (BCR10=0), and is asserted during delay (BCR8=0). All Burst operations are given for variable latency and no refresh collision. 2. The Burst Write is interrupted during the first allowable clock cycle, i.e. after the first Word written to the memory. 3. The Chip Enable signal, E, can remain Low, VIL, between burst operations, but it must not remain Low for longer than tELEH.
Hi-Z D0-D15 2nd WriteCycle
G 2nd Write Cycle
WAIT
Addr.
W
K
L
E
LB/UB 2nd Write Cycle
VALID INPUT
D0-D15 Hi-Z 2nd Read Cycle
G 2nd Read Cycle
LB/UB 2nd Read Cycle
VALID OUTPUT
VALID OUTPUT
VALID INPUT
VALID OUTPUT
VALID OUTPUT
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AI11293b
Hi-Z
9 DC and AC parameters
M69KB096AB
Figure 33. CR Controlled Configuration Register Program, Synchronous Mode
K
Addr.(3) tAVKH A18-A19(4) tRHKH CR(5) tLLKH L tELEH E
Opcode
tKHAX 00 (RCR) 01 (BCR) tKHRL
tKHLH
G tWLKH W tKHWH
UB, LB
DQ0-DQ15(2) tELTV WAIT Hi-Z
AI10131d
1. Only the Configuration Register (BCR) and the Refresh Configuration Register (RCR) can be modified. 2. Data Inputs/Outputs are not used. 3. The Opcode is the value to be written in the Configuration Register. 4. A19 gives the Configuration Register address. 5. CR initiates the Configuration Register Access.
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M69KB096AB
Table 23.
Symbol tPU tEHEL(DP) tELEH(DP)
9 DC and AC parameters
Power-Up and Deep Power-Down AC Characteristics
Alt. tPU tDPD tDPDX Parameter Initialization delay after Power-Up or Deep Power-Down Exit Deep Power-Down Entry to Deep Power-Down Exit Chip Enable Low to Deep Power-Down Exit Min 150 10 10 Max Unit s s s
Figure 34. Power-Up AC Waveforms
E tPU VCC, VCCQ 1.7V Device Initialization Device Ready for Normal Operation
AI09465d
1. Power must be applied to VCC prior to or at the same time as VCCQ.
Figure 35. Deep Power-Down Entry and Exit AC Waveforms
E tEHEL(DP) Deep Power-Down Entry (RCR4= 0) Deep Power-Down Mode tELEH (DP) tPU
Deep Power-Down Device Initialization Device Ready Exit for Normal Operation
AI11306
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10 Wafer and die specifications
M69KB096AB
10
Table 24.
Wafer and die specifications
Dimensions
200mm (8") 750 25m (29.51.0mil) 5,009.365m x 5,005.795m
Wafer Diameter Wafer Thickness Die Size (stepping interval)
Street Width Along X-Axis (dsw_X) 102m Street Width Along Y-Axis (dsw_Y) 102m Center of Street (COS) (relative to X = -222.98m, Y = 160.08m (X = -8.779mil, Y = 6.303mil) Bond Pad 1) Bond Pad Size Passivation Openings (MIN) Minimum Bond Pad Pitch Pad Count 85m x 100m (3.35mil x 3.94mil) 75m x 90m (2.95mil x 3.54mil) 119.00m (4.685mil) 71
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M69KB096AB
Figure 36. Die Outline
dsw_X dsw_Y COS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 y -x x Center of Die -y 20
10 Wafer and die specifications
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Die Orientation with Respect to Wafer Notch
71 70 69 68 67 66 65 64 62 61 60 59 58 57 56 55
54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38
37
Ai11630
1. Die streets are not to scale.
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10 Wafer and die specifications
M69KB096AB
Table 25.
Pad 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
Bond Pad Location and Identification
Pad Coordinates from Center of Die Signal X (m)(1) A0 A1 A2 A3 A4 A5 VCCQ VSSQ A6 A7 A17 A18 A19 E LB UB CR L W K VCC VSS A20 A21 DNU(2) A8 A9 VSSQ VCCQ A10 A11 A12 A13 -2,281.70 -2,162.70 -2,043.70 -1,924.70 -1,805.70 -1,686.70 -1,567.70 -1,448.70 -1,329.70 -1,210.70 -1,091.70 -972.70 -853.70 -734.70 -615.70 -496.70 -377.70 -258.70 -139.70 135.79 376.17 495.17 614.17 733.17 852.17 971.17 1,090.17 1,209.17 1,328.17 1,447.17 1,566.17 1,685.17 1,804.17 Y (m)(1) 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 2,342.81 X (inches) (1) -0.0898306 -0.0851456 -0.0804605 -0.0757755 -0.0710905 -0.0664054 -0.0617204 -0.0570353 -0.0523503 -0.0476653 -0.0429802 -0.0382952 -0.0336101 -0.0289251 -0.0242401 -0.0195550 -0.0148700 -0.0101849 -0.0054999 0.0053460 0.0148097 0.0194948 0.0241798 0.0288649 0.0335499 0.0382349 0.0429200 0.0476050 0.0522901 0.0569751 0.0616601 0.0663452 0.0710302 Y (inches)(1) 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367 0.0922367
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M69KB096AB
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 A14 A15 A16 WAIT DQ15 DQ7 VCCQ VSSQ DQ14 DQ6 DQ13 DQ5 VCCQ VSSQ DQ12 DQ4 NC DNU(2) DNU(2) DNU(2) VSS VCC DNU(2) DNU(2) DNU(2) G DQ11 DQ3 VSSQ VCCQ DQ10 DQ2 DQ9 DQ1 VSSQ 1,923.17 2,042.17 2,161.17 2,139.96 1,961.46 1,842.46 1,723.46 1,604.46 1,485.46 1,366.46 1,247.46 1,128.46 1,009.46 890.46 771.46 652.46 533.46 414.46 295.46 176.46 57.46 -180.54 -299.54 -418.54 -537.54 -656.54 -775.54 -894.54 -1,013.54 -1,132.54 -1,251.54 -1,370.54 -1,489.54 -1,608.54 -1,727.54 2,342.81 2,342.81 2,342.81 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02 -2,317.02
10 Wafer and die specifications
0.0757153 0.0804003 0.0850853 0.0842504 0.0772228 0.0725378 0.0678528 0.0631677 0.0584827 0.0537976 0.0491126 0.0444276 0.0397425 0.0350575 0.0303724 0.0256874 0.0210024 0.0163173 0.0116323 0.0069472 0.0022622 -0.0071079 -0.0117929 -0.0164780 -0.0211630 -0.0258480 -0.0305331 -0.0352181 -0.0399031 -0.0445882 -0.0492732 -0.0539583 -0.0586433 -0.0633283 -0.0680134
0.0922367 0.0922367 0.0922367 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211 -0.0912211
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10 Wafer and die specifications
M69KB096AB
-1,846.54 -1,965.54 -2,084.54 -2,317.02 -2,317.02 -2,317.02 -0.0726984 -0.0773835 -0.0820685 -0.0912211 -0.0912211 -0.0912211
69 70 71
VCCQ DQ8 DQ0
1. Reference from the center of each bond pad to the center of the die (0,0). 2. DNU stands for `do not use'.
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M69KB096AB
11 Part numbering
11
Table 26.
Example:
Part numbering
Ordering Information Scheme
M69KB096AB 80 C W 8
Device Type M69 = PSRAM Mode K = Bare Die Operating Voltage B = VCC = 1.7 to 1.95V, Burst, Address/Data bus standard x16 Array Organization 096 = 64 Mbit (4 Mbit x16) Option 1 A = 1 Chip Enable Silicon Revision B = B Die Speed Class 80 = 80ns Maximum clock frequency C = 80MHz D = 104MHz Package W = Unsawn Wafer Operating Temperature 8 = -30 to 85 C
The notation used for the device number is as shown in Table 26. Not all combinations are necessarily available. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest STMicroelectronics Sales Office.
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12 Revision history
M69KB096AB
12
Table 27.
Revision history
Document Revision History
Rev. 1 First Issue Revision Details
Date 29-Nov-2005
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M69KB096AB
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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