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19-2144; Rev 1; 7/04
+3.3V, 2.5Gbps Quad Limiting Amplifier
General Description
The MAX3822 quad limiting amplifier is ideal for multichannel systems with data rates up to 2.5Gbps. The MAX3822 operates from a single +3.3V supply, over temperatures ranging from 0C to +85C. A channelselect (CS) pin is provided to program single-, dual-, or quad-channel operation. The disabled channels are shut down to reduce power consumption. The output interface for all four channels is CML. The input can be driven from 20mVp-p to 1000mVp-p differentially. The threshold voltage control is common for all four channels and is programmable by an external resistor. Four separate power detectors are incorporated to monitor the received signal level for each channel. Individual TTL-compatible loss-of-power (LOP) indicators assert low if the channel signal input is below the programmed threshold. Typically 4dB LOP hysteresis (2dB optical) is provided to prevent chattering when the input signal level is close to the threshold. A general LOP indicator is also provided which asserts low if one or more of the four inputs is in the LOP condition. o Single +3.3V Supply o Single-, Dual-, or Quad-Channel Operation at 2.5Gbps o 700mW Total Power Dissipation (Quad-Channel Operation) o 120ps Maximum Output Edge Speed o Overall and Individual Channel Loss-of-Power (LOP) Indicator o Differential CML Outputs with On-Chip Back Termination Resistors o 30ps Maximum Deterministic Jitter o 2ps Random Jitter o Power-Down Feature Shuts Down Unused Channels o Operating Temperature Range: 0C to +85C
Features
MAX3822
Ordering Information
PART MAX3822UCM MAX3822UCM+ MAX3822U/D TEMP RANGE 0C to +85C 0C to +85C 0C to +85C PIN-PACKAGE 48 TQFP-EP* 48 TQFP-EP* Dice**
Applications
Optical System Interconnects Multichannel Receiver Modules Dense Digital Cross-Connects ATM Switch Networks High-Speed Parallel Links
*Exposed pad. **Contact factory for availability. Dice are designed to operate from TA = 0C to TA = +85C, but are tested and guaranteed only at TA = +25C. +Denotes lead-free package.
Pin Configuration
GND CZ1+ CZ1GND CZ2+ CZ2GND CS GND GND VTH GND
48 47 46 45 44 43 42 41 40 39 38 37
TOP VIEW
Typical Operating Circuit appears at end of data sheet.
IN1+ IN1VCC IN2+ IN2VCC VCC IN3+ IN3VCC IN4+ IN41 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 36 35 34 33 32 31 30 29 28 27 26 25
MAX3822
OUT1+ OUT1VCC OUT2+ OUT2VCC VCC OUT3+ OUT3VCC OUT4+ OUT4-
________________________________________________________________ Maxim Integrated Products
GND CZ4CZ4+ GND CZ3CZ3+ GND LOP LOP1 LOP2 LOP3 LOP4
TQFP-EP
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
+3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) ........................................... -0.5V to +6.0V Differential Input Voltage Swing (IN1+ - IN1-), (IN2+ - IN2-), (IN3+ - IN3-), (IN4+ - IN4-) ..............................................2Vp-p Voltage at LOP1, LOP2, LOP3, LOP4, LOP, CS........................................-0.5V to (VCC + 0.5V) Voltage at IN1+, IN1-, IN2+, IN2-, IN3+, IN3-, IN4+, IN4- .............................(VCC - 1V) to (VCC + 0.5V) Voltage at VTH .....................................................+0.5V to +2.3V Voltage at CZ1+, CZ1-, CZ2+, CZ2-, CZ3+, CZ3-, CZ4+, CZ4- ........................-0.5V to (VCC + 0.5V) Current into OUT1+, OUT1-, OUT2+, OUT2-, OUT3+, OUT3-, OUT4+, OUT4-, ..................................22mA Continuous Power Dissipation (TA = +85C) 48-Pin TQFP-EP (derate 29.4mW/C above +85C) ......2.35W Operating Junction Temperature Range(die) ...-55C to +150C Processing Temperature (die) .........................................+400C Storage Temperature Range .............................-55C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25C.) (Note 1)
PARAMETER Power-Supply Current Single-Ended Data Input Voltage Range Single-Ended Data Input Resistance Data Input Voltage for LOP Assert RTH = 1k RTH = 649 RTH = 400 RTH = 1k LOP Hysteresis CML Differential Output Single-Ended Data Output Resistance CML Output Common-Mode Voltage TTL Output High TTL Output Low VOH VOL Sourcing 200A Sinking 2mA 2.4 VOD RTH = 649 RTH = 400 RL = 50 to VCC 640 40 3.0 3.4 740 50 VCC 0.2 VCC 0.4 1000 60 mVp-p V V V 11.5 SYMBOL ICC CONDITIONS Single channel (Note 2) Dual channel (Note 2) Quad channel VIS VCC 0.5 40 50 14 18.5 34 4.5 6.0 dB 32.5 mVp-p MIN TYP 60 110 210 MAX 72 137 265 VCC + 0.25 60 V mA UNITS
2
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+3.3V, 2.5Gbps Quad Limiting Amplifier
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25C.) (Notes 1, 3)
PARAMETER Data Input Voltage Range Random Jitter Deterministic Jitter Data Output Edge Speed LOP Assert/Deassert Time Input-Referred Noise Offset Correction LowFrequency Cutoff Channel-to-Channel Skew (Note 7) CZ1 = CZ2 = CZ3 = CZ4 = 0.033F (Note 8) SYMBOL VIN (Note 4) VIN = 20mVp-p (Notes 5, 6) VIN = 1000mVp-p to 1000mVp-p (Notes 5, 6) (20% to 80%) 100 105 150 20 70 594 CONDITIONS MIN 20 2 8 4 90 30 120 TYP MAX 1000 9.5 UNITS mVp-p psRMS psp-p ps ns VRMS kHz ps
MAX3822
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
Characteristics at 0C are guaranteed by design and characterization. Dice are tested at TA = +25C. When power is first applied, all four channels are briefly active. AC characteristics are guaranteed by design and characterization. Input data edge speed of 150ps (20% to 80%). Data rate = 2.5Gbps. Measured with 213 -1 PRBS plus 100 consecutive identical digits. Deterministic jitter (p-p) equals total jitter (p-p) minus random jitter (p-p). Input-referred noise is specified (differential output noise)/(small-signal gain). Measured by applying the same input signal to all channels. Skew measurements are made at 50% point of the transition.
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+3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822
Typical Operating Characteristics
(VCC = +3.3V, TA = +25C, unless otherwise noted.)
DETERMINISTIC JITTER vs. DIFFERENTIAL INPUT VOLTAGE
PEAK-TO-PEAK DETERMINISTIC JITTER (psp-p)
MAX3822 toc01
RANDOM JITTER vs. DIFFERENTIAL INPUT VOLTAGE
MAX3822 toc02
8 7 6 5 4 3 2 1 0
9 8 RANDOM JITTER (psRMS) 7 6 5 4 3 2 1 0
100mV/div
0 100 200 300 400 500 600 700 800 900 1000 DIFFERENTIAL INPUT VOLTAGE (mV)
0 100 200 300 400 500 600 700 800 900 1000 DIFFERENTIAL INPUT VOLTAGE (mVp-p)
75ps/div
ELECTRICAL EYE DIAGRAM (VIN = 20mV DIFFERENTIAL)
MAX3822 toc04
ELECTRICAL EYE DIAGRAM (VIN = 100mV DIFFERENTIAL)
MAX3822 toc05
POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO (dB) -10 -20 -30 -40 -50 -60 -70 -80 -90 1 10 100 1000
MAX3822 toc06
0
100mV/div
100mV/div
75ps/div
75ps/div
FREQUENCY (MHz)
COMMON-MODE REJECTION RATIO vs. FREQUENCY
MAX3822 toc07
LOSS-OF-POWER THRESHOLD LEVEL vs. THRESHOLD RESISTANCE
DIFFERENTIAL INPUT VOLTAGE (mVp-p)
MAX3822 toc08
15 COMMON-MODE REJECTION RATIO (dB) 10 5 0 -5 -10 -15 -20 -25 1 10 FREQUENCY (MHz)
70 60 50 40 DEASSERT THRESHOLD 30 20 10 0 ASSERT THRESHOLD
100
0
400
800
1200
1600
2000
RTH ()
4
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MAX3822 toc03
9
10
ELECTRICAL EYE DIAGRAM (VIN = 1V DIFFERENTIAL)
+3.3V, 2.5Gbps Quad Limiting Amplifier
Pin Description
PIN 1 2 3, 6, 7, 10, 27, 30, 31, 34 4 5 8 9 11 12 13, 16, 19, 37, 39, 40, 42, 45, 48 14 15 17 18 20 21 22 23 24 25 NAME IN1+ IN1VCC IN2+ IN2IN3+ IN3IN4+ IN4GND Noninverted Data Input for Channel 1 Inverted Data Input for Channel 1 +3.3V Supply Voltage Noninverted Data Input for Channel 2 Inverted Data Input for Channel 2 Noninverted Data Input for Channel 3 Inverted Data Input for Channel 3 Noninverted Data Input for Channel 4 Inverted Data Input for Channel 4 Supply Ground A capacitor connected between this pin and CZ4+ extends the time constant for the offsetcorrection loop associated with channel 4. Maxim recommends a capacitor value of 0.033F. A capacitor connected between this pin and CZ4- extends the time constant for the offsetcorrection loop associated with channel 4. Maxim recommends a capacitor value of 0.033F. A capacitor connected between this pin and CZ3+ extends the time constant for the offsetcorrection loop associated with channel 3. Maxim recommends a capacitor value of 0.033F. A capacitor connected between this pin and CZ3- extends the time constant for the offsetcorrection loop associated with channel 3. Maxim recommends a capacitor value of 0.033F. LOP is low when any of the individual power detectors (LOP1, LOP2, LOP3, LOP4) are low. LOP1 asserts low when the data input signal level to channel 1 drops below the programmed threshold. LOP2 asserts low when the data input signal level to channel 2 drops below the programmed threshold. LOP3 asserts low when the data input signal level to channel 3 drops below the programmed threshold. LOP4 asserts low when the data input signal level to channel 4 drops below the programmed threshold. Inverted Data Output for Channel 4 DESCRIPTION
MAX3822
CZ4CZ4+ CZ3CZ3+ LOP LOP1 LOP2 LOP3 LOP4 OUT4-
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5
+3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822
Pin Description (continued)
PIN 26 28 29 32 33 35 36 38 41 43 44 46 47 EP NAME OUT4+ OUT3OUT3+ OUT2OUT2+ OUT1OUT1+ VTH CS CZ2CZ2+ CZ1CZ1+ Exposed Pad Noninverted Data Output for Channel 4 Inverted Data Output for Channel 3 Noninverted Data Output for Channel 3 Inverted Data Output for Channel 2 Noninverted Data Output for Channel 2 Inverted Data Output for Channel 1 Noninverted Data Output for Channel 1 A resistor connected from this pin to ground sets the data input signal level at which the loss-ofpower outputs will be asserted. Channel-Select Input. To enable channel 1 only, leave CS open. To enable channels 1 and 2, connect CS to VCC. To enable all four channels, connect CS to GND. A capacitor connected between this pin and CZ2+ extends the time constant for the offsetcorrection loop associated with channel 2. Maxim recommends a capacitor value of 0.033F. A capacitor connected between this pin and CZ2- extends the time constant for the offsetcorrection loop associated with channel 2. Maxim recommends a capacitor value of 0.033F. A capacitor connected between this pin and CZ1+ extends the time constant for the offsetcorrection loop associated with channel 1. Maxim recommends a capacitor value of 0.033F. A capacitor connected between this pin and CZ1- extends the time constant for the offsetcorrection loop associated with channel 1. Maxim recommends a capacitor value of 0.033F. Ground. This must be soldered to a circuit board for proper thermal and electrical performance (see Exposed Pad (EP) Package). DESCRIPTION
Detailed Description
The MAX3822 is a 2.5Gbps quad limiting amplifier designed for fiber applications with input sensitivities as low as 20mVp-p. This device has internally terminated CML inputs with loss-of-power circuitry for each channel, as well as a general loss-of-power indicator valid for the whole part. Offset correction ensures low pulse-width distortion (PWD) and reduced patterndependent jitter (PDJ). A channel-select (CS) pin is used to control the device's mode of operation as single, dual, or quad. The inputs of the MAX3822 are typically connected to a transimpedance amplifier (TIA) (MAX3825) found within a fiber-optic link. The output signal from a TIA can contain significant amounts of noise, and may vary in amplitude over time. The MAX3822 limiting amplifier quantizes the input signal, and outputs a voltage-limited waveform over a 40dB input dynamic range. Signal input to this device passes through a buffer to a lineargain amplifier. This linear-gain amplifier (Figure 1) drives the power-detection circuitry and a chain of limiting amplifiers leading to the CML output buffer.
6
The power-detection circuitry is used to indicate that the data input voltage has fallen below the programmed threshold level. Each individual channel has a power detector output (LOP1, LOP2, LOP3, LOP4). The LOP output is low when any of the individual powerdetector outputs are low. A threshold adjustment pin (VTH) programs the signal-detect threshold for all four channels with a single external resistor. The offset-correction loop adjusts the input buffer bias until the CML output buffer has a zero offset. This offset-correction loop acts as a high-pass filter where signal components below 150kHz are attenuated.
Input Buffer and Gain Stages
The MAX3822's inputs are terminated with 50 to VCC (Figure 2). The inputs do not need to be AC-coupled if the upstream TIA has CML outputs, but should be ACcoupled if the differential logic levels are in any other format. The differential input signal is passed through a buffer, and then continues through two sets of differential amplifiers, each with an emitter-follower output stage. The first differential amplifier provides approximately 10dB gain and a linear output for input signals
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+3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822
CZ1+
CZ1-
LOW PASS OFFSET CORRECTION IN1+ BUFF IN1GAIN GAIN
LIMITING AMPLIFIER #1
OUT1+ CML LOSS-OF-POWER LOGIC R RECTIFIER AND LOW-PASS FILTER VTH RTH LOSS OF POWER S THRESHOLD CONTROL Q LOP1 OUT1-
LOP
CS
CHANNEL SELECT LIMITING AMPLIFIER #2 LIMITING AMPLIFIER #3 LIMITING AMPLIFIER #4
MAX3822
CZ2+ IN2+ IN2-
LOP2 CZ2CZ3+ OUT2+ OUT2- IN3+ IN3-
LOP3 CZ3CZ4+ OUT3+ OUT3IN4+ IN4-
LOP4 CZ4OUT4+ OUT4-
Figure 1. Functional Diagram
up to 80mVp-p. This differential amplifier is designed to work with the power-detect circuitry. The next high-gain amplifier provides an additional gain of approximately 22dB. This gain stage functions similarly to the input-gain stage. The output signal from this gain stage is applied to the CML output buffer shown in Figure 3, and is used in the offset-correction loop. The input voltage range is limited to VCC + 0.5V by the ESD structure, and to a minimum of VCC - 1V by the internal resistor. Figure 2 shows a model of the input stage of the MAX3822, including the package capacitance and the bond wire inductance. The additional 0.4pF capacitance on the inputs represents the ESD diode's junction capacitance and a small contribution by the bond pad. For more information about the CML electrical specifications and interfacing to other proto-
cols, refer to Application Note HFAN-1.0, Introduction to LVDS, PECL, and CML. Be sure the MAX3822 is placed as close as possible to the TIA when using this device near sensitivity. If you are using a TIA with CML outputs, such as the MAX3825, AC-coupling capacitors are not required. Taking these precautions will ensure the best possible sensitivity.
Output Buffer
The MAX3822's CML output buffer is designed to drive 50 lines that are used to feed the input of a clock- and data-recovery device (CDR). Figure 3 shows a model of the output stage showing some important details. The outputs of the device are terminated internally with 50 to VCC. ESD diode structures are connected to VCC and GND. Figure 3 also shows the model of the output
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+3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822
PACKAGE DIE
VCC ESD DIODES
1.5nH IN+ 0.2pF 0.4pF 1.5nH 0.2pF 0.4pF
50
50
IN-
GND
Figure 2. Input Structure
ESD DIODES
VCC
and may cause deterministic jitter through an increase of PWD. Each of the MAX3822's integrated limiting amplifiers includes a DC cancellation loop that provides offset correction to the CML output signal in addition to lowfrequency power-supply noise rejection. The DC cancellation loop consists of a low-pass filter and a high-gain amplifier. The input voltage difference of the CML output buffer is amplified, sent through a low-pass filter, inverted, and summed up with the input signal that drives the high-gain input stage. This removes from the output signal all frequency components between the cutoff frequency and DC. The low-frequency cutoff of the DC cancellation loop is set by an external capacitor connected between CZ_+ and CZ_-.
50
50 1.5nH 0.4pF 1.5nH OUT0.4pF 0.2pF OUT+ 0.2pF
DIE GND
PACKAGE
Power Detection and Threshold Control
The MAX3822 incorporates a chatter-free loss-of-power function that is used to determine if the input signal has dropped below the programmed threshold level. The power detector is implemented by comparing the DCrectified output of the first gain stage to the programmed loss-of-power threshold. The threshold control circuitry enables programming of LOP_ assert and deassert reference voltages by using one external resistor, RTH (Figure 4). An internal amplifier guarantees a voltage at VTH of approximately 0.5V. The external resistor (RTH) connected to GND converts this voltage into a current. The current through this resistor sets the power threshold level for the device (see Typical Operating Characteristics, Loss-of-Power Threshold Level vs. RTH).
Figure 3. Output Structure
stage of the MAX3822, including package capacitance and bond-wire inductance. The additional 0.4pF capacitance on the output represents the ESD diode's junction capacitance and a small contribution by the bond pad. For more information about the CML electrical specifications and interfacing to other protocols, refer to Application Note HFAN-1.0, Introduction to LVDS, PECL, and CML.
Offset Correction
Each limiting amplifier on the MAX3822 provides approximately 50dB of gain. An input offset as small as 1mV reduces the power-detection circuitry's accuracy
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+3.3V, 2.5Gbps Quad Limiting Amplifier
Loss-Of-Power Logic (LOP)
The loss-of-power logic circuitry is asserted anytime the input power of one of the limiting amplifiers is observed below the threshold set by R TH. The logic of this is comprised of two comparators and an S-R flip-flop to compare the outputs of the threshold-control and power-detect circuitry for each of the limiting amplifiers on the MAX3822. The LOP_ output corresponding to a given input is asserted if the input power is too low. A general LOP output is also given for the whole part; if any LOP_ signal is low, the LOP output will also go low. Once a LOP_ signal has been asserted, the input power must rise above the threshold before resetting. This prevents the LOP_ output from turning on and off when the input signal is near the programmed threshold level, an effect called chatter. The LOP_ indicator will return to its unasserted state when the input power level is increased (4dB typ). Figure 5 shows the output structure. device is placed into single-mode operation with channel 1 enabled, and channels 2, 3, and 4 disabled. Dualmode operation is programmed by connecting CS directly to VCC. In dual-mode operation, channels 1 and 2 are enabled and channels 3 and 4 are disabled. Quadmode operation is programmed by connecting CS directly to GND. In quad-mode operation, all four channels are enabled. Figure 6 shows the input circuitry of the CS pin.
MAX3822
Applications Information
Set Up the DC Cancellation Loop
The value of the offset-correction capacitor (CZ_) affects the maximum speed at which the DC cancellation loop can adjust to changes in DC offset at the input. PWD and pattern-dependent jitter (PDJ) are both error sources that can be minimized by the proper selection of CZ_. Therefore, the loop should be as slow as possible to reduce PDJ while performing its DC cancellation function. Select the CZ_ capacitor to set the bandwidth of the DC cancellation loop. The input impedance between CZ+ and CZ- is approximately 10k. This impedance is in series with CZ_. Therefore, the low-frequency cutoff (foc) associated with the DC offset-correction loop is computed as follows:
Channel Select
The channel-select circuitry controls the operating mode of the MAX3822 by shutting down unused amplifiers. Single-, dual-, and quad-mode operation is programmed by the channel-select (CS) pin. When CS is left open, the
VCC VCC VREF ICTAL 2k ESD DIODES 4k VTH LOP ESD DIODES
RTH
18k
GND
GND GND
Figure 4. Threshold Set Structure
Figure 5. TTL Output Structure _______________________________________________________________________________________ 9
+3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822
VCC
ESD DIODES
In an optical receiver, the dB change at the MAX3822 will equal twice the optical dB change. The MAX3822's typical voltage hysteresis is 4dB. This provides an optical hysteresis of 2dB.
30k
Exposed-Pad (EP) Package
The exposed-pad, 48-pin TQFP-EP incorporates features that provide a very low thermal resistance path for heat removal from the IC. The pad is electrical ground on the MAX3822 and should be soldered to the circuit board for proper thermal and electrical performance.
CS
40k 20k
Chip Information
TRANSISTOR COUNT: 813 SUBSTRATE CONNECTED TO GND PROCESS: Bipolar DIE SIZE: 90mil 102mil
GND
Figure 6. Channel-Select Interface
50dB
10 20 foc = 2 x 10k x Cz _
(125.2, 2090.8)
Bond Pad Information
(1804.6, 1966.6)
where 50dB is the gain of the offset-correction loop. Maxim recommends a value of 0.033F for the filter capacitor. This value will set the lower cutoff frequency of the DC cancellation loop to approximately 150kHz.
(46.9, 1804.6)
B
HF65Z
(1947.6, 1804.6)
Optical Hysteresis
Power and hysteresis are often expressed in decibels. By definition, decibels are always 10log (ratio power). At the inputs to the MAX3822 limiting amplifier, the power is VIN2 / R. If a receiver's optical input power (x) increases by a factor of two, and the preamplifier is linear, then the voltage input to the MAX3822 will also increase by a factor of two. The optical power change is: 2x 10log = 10log(2) = + 3dB x At the MAX3822, the voltage change is: 10log
A MAX3822 C
INDEX PAD
Y (46.9, 46.9)
(1947.6, 46.9)
D
(125.5, -215) X (1985.5, -215) *ORIENT PLOT, USING HF65Z AS A KEY. * ALL DIMENSIONS ARE IN MICRONS * GST2 PROCESS * PAD DIMENSIONS: (BONDING AREA) H = 93.8MICRONS W = 93.8MICRONS * ALL MEASUREMENTS SPECIFY THE CENTER OF THE PAD. * ORIGIN IS DEFINED AS THE BOTTOM LEFT CORNER OF THE INDEX PAD
(2VIN )
2
/R
VIN2 / R
= 10log 22 = 20log(2) = + 6dB
()
10
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+3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822
Bond Pad Information (continued)
MAX3822 (HF65Z) DIMENSIONS SIDE A 46.9 46.9 46.9 46.9 46.9 46.9 46.9 46.9 46.9 46.9 46.9 46.9 46.9 206.2 365.5 524.8 684.1 846.1 1005.4 1167.4 1326.7 1486.0 1645.3 1804.6 125.2 292.6 460.0 627.4 794.8 962.2 1129.6 1297.0 1464.4 1631.8 1799.2 1966.6 SIDE B 2090.8 2090.8 2090.8 2090.8 2090.8 2090.8 2090.8 2090.8 2090.8 2090.8 2090.8 2090.8 1947.6 1947.6 1947.6 1947.6 1947.6 1947.6 1947.6 1947.6 1947.6 1947.6 1947.6 1947.6 SIDE C 46.9 206.2 365.5 524.8 684.1 846.1 1005.4 1167.4 1326.7 1486.0 1645.3 1804.6 125.2 279.1 433.0 586.9 740.8 894.7 1048.6 1202.5 1356.4 1510.3 1664.2 1818.1 1985.5 SIDE D -215 -215 -215 -215 -215 -215 -215 -215 -215 -215 -215 -215 -215
Typical Operating Circuit
CZ1 VCC CS CZ1 IN1+ 50 VCC 50 IN2+ 50 VCC 50 IN3+ 50 VCC 50 IN4+ 50 PHOTODIODE ARRAY 50 IN4VTH OUT4+ OUT450 IN450 IN3IN2OUT2+ OUT250 IN250 QUAD CDR WITH CML INPUTS IN1CZ2 CZ3 CZ4 OUT1+ OUT150 IN150 IN2+ IN1+ CZ2 CZ3 CZ4 VCC
MAX3822
OUT3+ OUT350
IN3+ IN350
MAX3827*
IN4+
MAX3825
RTH LOP1 LOP2 LOP3 LOP4 LOP GND
*FUTURE PRODUCT
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11
+3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822
Chip Topography
(90mil)
CZ1+
CZ2+
CZ1-
CZ2-
GND
GND
GND
GND
GND
GND OUT1+ OUT1VCC OUT2+ OUT2VCC VCC OUT3+ OUT3VCC OUT4+ OUT4(102mil)
IN1+ IN1VCC IN2+ IN2VCC VCC IN3+ IN3VCC IN4+ IN4-
CZ4-
GND
VTH LOP4
CS
12
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EPGND
CZ3+
GND
LOP1
GND
CZ3-
CZ4+
LOP
LOP2
LOP3
+3.3V, 2.5Gbps Quad Limiting Amplifier
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX3822
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.0mm EP OPTION
21-0065
F
1 2
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48L,TQFP.EPS 13
+3.3V, 2.5Gbps Quad Limiting Amplifier MAX3822
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 32/48L TQFP, 7x7x1.0mm EP OPTION
21-0065
F
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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