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Freescale Semiconductor Advance Information
Document Number: MC33888 Rev. 6.0, 2/2007
Quad High-Side and Octal Low-Side Switch for Automotive
The 33888 is a single-package combination of a power die with four discrete high-side MOSFETs (two 10 m and two 40 m) and an integrated IC control die consisting of eight low-side drivers (600 m each) with appropriate control, protection, and diagnostic features. Programming, control, and diagnostics are accomplished using a 16-bit SPI interface. Additionally, each high-side output has its own parallel input for pulse-width modulation (PWM) control if desired. The low sides share a single configurable direct input. Features * Dual 10 m High Side, Dual 40 m High Side, Octal 600 m Low Side * Full Operating Voltage of 6.0 V to 27 V * SPI Control of High-Side Overcurrent Limit, High-Side Current Sense, Output OFF Open Load Detection, Output ON/OFF Control, Watchdog Timeout * SPI Reporting of Program Status and Fault * High-Side Analog Current Feedback with Selectable Ratio * Enhanced 16 V Reverse Polarity VPWR Protection
33888 33888A
HIGH-SIDE/LOW-SIDE SWITCH
Bottom View PNB SUFFIX 98ARL10544D 36-PIN PQFN
Top View FB SUFFIX 98ARH99043A 64-PIN PQFP
ORDERING INFORMATION
Device MC33888APNB/R2 MC33888FB/R2 -40C to 125C 64 PQFP Temperature Range (TA) Package 36 PQFN
VPWR +5.0 V +5.0 V 8 x Relay or LED
33888 4 MCU A/D A/D VPWR FS VDD IHS0:IHS3 LS4:LS11 ILS RST HS3 SPI HS2 WDIN HS1 CSNS2-3 HS0 CSNS0-1 FSI GND Loads
4
Figure 1. 33888 Simplified Application Diagram
* This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2007. All rights reserved.
DEVICE VARIATIONS
DEVICE VARIATIONS
Table 1. Features Comparison: 33888 and 33888A
Parameter Undervoltage Low-Side Output Shutdown Low-Side Drain-to-Source ON Resistance Recommended Frequency of SPI Operation Symbol VPWRUV RDS(ON) Condition - VPWR = 4.5 V; VDD = 3.5 V Extended Mode, VDD = 3.4 V 33888 5.0 V Not specified Not specified 33888A 3.0 V 8.0 2.1 MHz (max) For details, see page 10 13 16
f SPI
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Analog Integrated Circuit Device Data Freescale Semiconductor
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VDD VPWR
VIC
IUP CS SCLK IDWN SO SI RST WAKE FS IN0 IN1 IN2 IN3 ILS
SPI 3.0 MHz
Internal Regulator
Over/Undervoltage Protection
10 m
Gate Driver
Selectable Current Limit Open Load
HS0
Detection
Logic Overtemperature Detection
HS0
Selectable Output Current Recopy (Analog MUX)
CSNS0-1 HS1
Gate Control and Fault 10 m
HS1
Gate Control and Fault 40 m
HS2 RDWN IDWN
Selectable Output Current Recopy (Analog MUX)
HS2 CSNS2-3
Gate Control and Fault 40 m
HS3
VIC
HS3
WDIN
Watchdog
Gate Control
Clamp Overtemperature ILIM Open Load x8
FSI
LS4 LS5 LS6 LS7 LS8 LS9 LS10 LS11
GND
Figure 2. 33888 Simplified Internal Block Diagram
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PIN CONNECTIONS
PIN CONNECTIONS
Transparent Top View of Package
VPWR 2 LS11 LS10 GND GND VDD LS9 LS8 LS7 LS6 LS5 LS4 SO FS 1 36 GND 35 WDIN FSI RST WAKE GND IHS1 IHS0 CSNS0-1 34 33 32 31 30 29 28 HS2
14 CS SCLK SI ILS GND IHS3 IHS2 CSNS2-3 16
13
12
11
10
9
8
7
6
5
4
3
15 17 18 19 20 21 22 23
(Control Die)
Internally Connected to VPWR
24
VPWR
(Power Die)
25 HS3
26 HS1
27 HS0
Figure 3. 33888 Pin Connections for PQFN Table 2. 33888 Pin Definitions for PQFN A functional description of each pin can be found in the Functional Pin Description section beginning on page 18.
Pin Number 1 2, 24 Pin Name FS VPWR Pin Function Output Input Formal Name Fault Status (Active Low) Definition This output pin is an open drain indication that goes active low when a fault mode is detected by the device.
Positive Power Supply These pin connects to the positive power supply and are the source input of operational power for the device. Pins 2 and 24 must be shorted together on the board. Low-Side Output 4 Low-Side Output 6 Low-Side Output 8 Low-Side Output 10 Power Ground These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 500 mA.
3 6 8 10 4, 11, 15, 20, 32 5 7 9 12
LS4 LS6 LS8 LS10 GND
Output
Ground
These pins serve as the ground for the source of the low-side output transistors as well as the logic portion of the device. Pins 4, 11, 15, 20, and 32 must be shorted together on the board These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 800 mA.
LS5 LS7 LS9 LS11
Output
Low-Side Output 5 Low-Side Output 7 Low-Side Output 9 Low-Side Output 11
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Analog Integrated Circuit Device Data Freescale Semiconductor
PIN CONNECTIONS
Table 2. 33888 Pin Definitions for PQFN (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 18.
Pin Number 13 14 16 17 18 19 21 22 30 31 23 29 25 28 26 27 33 34 35 36 Pin Name VDD SO CS SCLK SI ILS IHS3 IHS2 IHS0 IHS1 CSNS2 - 3 CSNS0 - 1 HS3 HS2 HS1 HS0 WAKE RST FSI WDIN Pin Function Input Output Input Input Input Input Input Formal Name Digital Drain Voltage (Power) Serial Output Chip Select (Active Low) Serial Clock Serial Input Low-Side Input High-Side Input 3 High-Side Input 2 High-Side Input 0 High-Side Input 1 Current Sense 2-3 Current Sense 0-1 High-Side Output 3 High-Side Output 2 High-Side Output 1 High-Side Output 0 Wake Reset (Active Low) Fail-Safe Input Watchdog Input Definition This is an external input pin used to supply power to the SPI circuit. This is an output pin connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device in a daisy chain. This is an input pin connected to a chip select output of a microcontroller (MCU). This input pin is connected to the SCLK pin of the master MCU, which is a bit (shift) clock for the SPI port. This input pin is connected to the SPI Serial Data Output pin of the MCU from which it receives output command data. This input pin is used to directly control a number of the low-side devices as configured by SPI. These inputs may or may not be activated depending on the configured state of the internal logic.
Output
These pins deliver a metered amount of the high-side output current that can be used to generate signal ground referenced output voltages for use by the MCU. Each pin is the source of a 40 m MOSFET high-side driver, which delivers current through the connected loads. Each pin is the source of a 10 m MOSFET high-side driver, which delivers current through the connected loads. This pin is used to input a logic [1] signal in order to enable the watchdog timer function. This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low current standby mode. The Fail-Safe input pin level determines the state of the outputs after a watchdog timeout occurs. This pin has an internal pullup. This input pin is a CMOS logic level input that is used to monitor system operation.
Output Output Input Input Input Input
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Analog Integrated Circuit Device Data Freescale Semiconductor
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RST WAKE IHS1 IHS0 CSNS0-1 VPWR
64 63 62 61 60 59
58 57 56 55 54 53
VPWR HS2 HS2 NC NC NC
FSI WDIN FS VPWR LS4 GND LS5 LS6 GND LS7 LS8 GND LS9 LS10 GND LS11 VDD SO CS SCLK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC NC NC HS0 HS0 HS0 HS0 HS0 HS0 HS0 HS1 HS1 HS1 HS1 HS1 HS1 HS1 NC NC NC
21 22 23 24 25 26
SI ILS IHS3 IHS2 CSNS2-3 VPWR
Figure 4. 33888 Pin Connections for PQFP Table 3. 33888 Pin Definitions for PQFP A functional description of each pin can be found in the Functional Pin Description section beginning on page 18.
Pin Number 1 2 3 4, 26, 27, 58, 59 5 8 11 14 6, 9, 12, 15 Pin Name FSI WDIN FS VPWR Pin Function Input Input Output Input Formal Name Fail-Safe Input Watchdog Input Fault Status (Active Low) Definition The Fail-Safe input pin level determines the state of the outputs after a watchdog timeout occurs. This pin has an internal pullup. This input pin is a CMOS logic level input that is used to monitor system operation. This output pin is an open drain indication that goes active low when a fault mode is detected by the device.
Positive Power Supply These pin connects to the positive power supply and are the source input of operational power for the device. Pins 4, 26, 27, 58 and 59 must be shorted together on the board. Low-Side Output 4 Low-Side Output 6 Low-Side Output 8 Low-Side Output 10 Power Ground These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 500 mA.
LS4 LS6 LS8 LS10 GND
Output
Ground
These pins serve as the ground for the source of the low-side output transistors as well as the logic portion of the device. Pins 6, 9, 12 and 15 must be shorted together on the board.
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VPWR HS3 HS3 NC NC NC
27 28 29 30 31 32
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Analog Integrated Circuit Device Data Freescale Semiconductor
Table 3. 33888 Pin Definitions for PQFP (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on page 18.
Pin Number 7 10 13 16 17 18 19 20 21 22 23 24 61 62 25 60 28, 29 56, 57 30 - 35, 50 - 55 36 - 42 43 - 49 63 64 Pin Name LS5 LS7 LS9 LS11 VDD SO CS SCLK SI ILS IHS3 IHS2 IHS0 IHS1 CSNS2 - 3 CSNS0 - 1 HS3 HS2 NC HS1 HS0 WAKE RST Pin Function Output Formal Name Low-Side Output 5 Low-Side Output 7 Low-Side Output 9 Low-Side Output 11 Digital Drain Voltage (Power) Serial Output Chip Select (Active Low) Serial Clock Serial Input Low-Side Input High-Side Input 3 High-Side Input 2 High-Side Input 0 High-Side Input 1 Current Sense 2-3 Current Sense 0-1 High-Side Output 3 High-Side Output 2 Not Connected High-Side Output 1 High-Side Output 0 Wake Reset (Active Low) Definition These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 800 mA.
Input Output Input Input Input Input Input
This is an external input pin used to supply power to the SPI circuit. This is an output pin connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device in a daisy chain. This is an input pin connected to a chip select output of a microcontroller (MCU). This input pin is connected to the SCLK pin of the master MCU, which is a bit (shift) clock for the SPI port. This input pin is connected to the SPI Serial Data Output pin of the MCU from which it receives output command data. This input pin is used to directly control a number of the low-side devices as configured by SPI. Each high-side input pin is used to directly control only one designated high-side output.
Output
These pins deliver a metered amount of the high-side output current that can be used to generate signal ground referenced output voltages for use by the MCU. Each pin is the source of a 40 m MOSFET high-side driver, which delivers current through the connected loads. These pins are not connected internally. Each pin is the source of a 10 m MOSFET high-side driver, which delivers current through the connected loads. This pin is used to input a logic [1] signal in order to enable the watchdog timer function. This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low current standby mode.
Output N/A Output Input Input
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ELECTRICAL CONNECTIONS MAXIMUM RATINGS
ELECTRICAL CONNECTIONS
MAXIMUM RATINGS
Table 4. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings ELECTRICAL RATINGS Power Supply Voltage Steady State Input Pin Voltage (1) WAKE Input Pin Clamp Current Continuous per Output Current (2) Low-Sides 4, 6, 8, 10 Low-Sides 5, 7, 9, 11 Continuous per Output Current High-Sides 0, 1 High-Sides 2, 3 Output Clamp Energy High-Sides 0, 1 (4) High-Sides 2, 3 (5) Low-Sides
(6) (3)
Symbol
Value
Unit
VPWR
-16 to 41 VIN IWICI IOUTLS 500 800 IOUTHS 10 5.0 - 0.3 to 7.0 2.5
V
V mA mA
A
mJ EHS EHS ELS 450 120 50 V VESD1 VESD2 2000 200
ESD Voltage (7) Human Body Model Machine Model
Notes 1. Exceeding voltage limits on SCLK, SI, CS, WDIN, RST, IHS, FSI, or ILS pins may cause a malfunction or permanent damage to the device. 2. Continuous low-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125C ambient temperature will require calculation of maximum output current using package thermal resistance. 3. Continuous high-side output current rating so long as maximum junction temperature is not exceeded. Operation at 125C ambient temperature will require calculation of maximum output current using package thermal resistance. 4. Active HS0 and HS1 clamp energy using the following conditions: single nonrepetitive pulse, VPWR = 16.0 V, L = 40 mH, TJ = 150C. 5. 6. 7. Active HS2 and HS3 clamp energy using the following conditions: single nonrepetitive pulse, VPWR = 16.0 V, L = 10 mH, TJ = 150C. Active low-side clamp energy using the following conditions: single nonrepetitive pulse, 450 mA, TJ = 150C. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 ), ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 ).
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CONNECTIONS MAXIMUM RATINGS
Table 4. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.
Ratings THERMAL RATINGS Operating Temperature Ambient Junction Storage Temperature Control Die Thermal Resistance PQFP One Low-Side ON Two Low-Side ON Three Low-Side ON Four Low Side ON All Low-Sides ON PQFN One Low-Side ON Two Low-Side ON Three Low-Side ON Four Low Side ON All Low-Sides ON Power Die Thermal Resistance (8) PQFP One High-Side 2, 3 ON All High-Sides ON PQFN One High-Side 2, 3 ON All High-Sides ON Thermal Resistance, Junction to Ambient, Natural Convection, Four-Layer Board (8) PQFP PQFN Peak Package Reflow Temperature During Reflow Notes 8. 9. 10. Board dimensions are 8.0 cm x 8.0 cm x 1.5 mm with a 300 mm2 copper area on the bottom layer. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), > Go to www.freescale.com > Search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx)] > Locate your Part Number and in the Details column, select "View" > Select "Environmental and Compliance Information"
(9), (10) (8)
Symbol
Value
Unit
C
TA TJ TSTG RCJC 12.5 9.3 7.3 5.9 3.2 8.6 6.0 4.6 3.8 2.0 RPJC 0.5 0.15 0.5 0.1 RJA 33 37 TPPRT Note 10 C C/W C/W - 40 to 125 - 40 to 150 - 55 to 150 C C/W
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Analog Integrated Circuit Device Data Freescale Semiconductor
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ELECTRICAL CONNECTIONS STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER INPUT Supply Voltage Range Fully Operational VPWR Supply Current TJ > 125C TJ 125C VPWR Standby Current (All Outputs OFF, Open Load Detection Disabled, WAKE = H, RST = H) TJ > 125C TJ 125C Sleep State Supply Current (VPWR < 12.6 V, RST < 0.5 V, WAKE < 0.5 V, HS[0 :3] = 0 V) (11) TJ = 85C TJ = 25C Logic Supply Voltage Range Logic Supply Current TJ > 125C TJ 125C Logic Supply Sleep State Current Sleep State Low-Side Output Leakage Current (per Low-Side Output, RST = LOW) TJ = 85C TJ = 25C Overvoltage Shutdown Threshold Overvoltage Shutdown Hysteresis Undervoltage High-Side Output Shutdown (12) Undervoltage Low-Side Output Shutdown APNB Suffix Only (12) PNB and FB Suffixes Undervoltage High-Side Shutdown Hysteresis VPWRUV(HYS) VPWROV VPWROV(HYS) VPWRUV VPWRUV 3.0 5.0 0.1 4.0 5.6 0.3 4.4 6.0 0.5 V IDD(SS) ISLK(SS) - - 28.5 0.2 5.0 - - 32 0.6 5.6 3.0 1.0 36 1.5 6.0 V V V V VDD IDD(ON) - - - 4.2 2.9 - 7.0 5.0 5.0 A A IPWR(SS) - - 4.5 - 1.0 5.0 80 25 5.5 V mA IPWR(SBY) - - 4.2 2.9 7.0 5.0 A IPWR(ON) - - 17 - 25 20 mA VPWR 6.0 - 27 mA V Symbol Min Typ Max Unit
Notes 11. This parameter is tested at 125C with a maximum value of 10 A. 12. SPI/IO and internal logic operational. Outputs will recover in instructed state when VPWR voltage level returns to normal as long as the level does not go below VPWRUV.
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Analog Integrated Circuit Device Data Freescale Semiconductor
ELECTRICAL CONNECTIONS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER INPUT (continued) Current Sense Ratio (9.0 V < VPWR < 16 V, CSNS < 4.5 V) CSNS0- 1/ HS0, CSNS0 - 1 / HS1 Current Sense Ratio (CSR[0:1] ) Accuracy HS[0:1] Output Current 1.0 A 2.0 A 5.0 A 6.5 A 10 A Current Sense Ratio (VPWR = 9.0 V - 16 V, CSNS < 4.5 V) CSNS2 - 3 / HS2, CSNS2 - 3 / HS3 Current Sense Ratio (CSR[2:3] ) Accuracy HS[2:3] Output Current 0.5 A 1.0 A 3.0 A 3.7 A 5.0 A Current Sense Clamp Voltage ICNS = 15 mA Generated by the Device HS0 AND HS1 POWER OUTPUTS Drain-to-Source ON Resistance (IOUT = 5.5 A) TJ = 25C VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V TJ = 150C VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V Reverse Battery Source-to-Drain ON Resistance (IOUT = -5.5 A, TJ = 25C) VPWR = -12 V Output Self-Limiting Peak Current Outputs ON, VOUT = VPWR - 2.0 V Output Self-Limiting Sustain Current Outputs ON, VOUT = VPWR - 2.0 V Open Load Detection Current (13) IOLDC ILIM(SUS) 13 30 25 - 34 100 A ILIM(PK) 33 49 66 A RDS(ON)REV - - 0.02 A - - - - - - 0.034 0.017 0.017 - - - - - - 0.02 0.01 0.01 RDS(ON) VSENSE 4.5 6.0 7.0 - 30 -19 -13.5 -12 - 9.0 - - - - - 30 19 13.5 12 9.0 V CSR[2:3]_ACC CSR - 1/880 - % -35 -19 -14 -12 -12 - - - - - 35 19 14 12 12 - CSR[0:1] _ACC CSR[0:1] - 1/1400 - % - Symbol Min Typ Max Unit
Notes 13. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF.
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ELECTRICAL CONNECTIONS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic HS0 AND HS1 POWER OUTPUTS (continued) Output Fault Detection Threshold (14) Output Programmed OFF Output Negative Clamp Voltage 0.5 A < IOUT < 2.0 A, Output OFF Overtemperature Shutdown (Outputs OFF) Overtemperature Shutdown Hysteresis HS2 AND HS3 POWER OUTPUTS Drain-to-Source ON Resistance (IOUT = 4.5 A) TJ = 25C VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V TJ = 150C VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V Reverse Battery Source-to-Drain ON Resistance (IOUT = 4.5 A, TJ = 25C) VPWR = -12 V Output Self-Limiting Peak Current Outputs ON, VOUT = VPWR -2.0 V Output Self-Limiting Sustain Current Outputs ON, VOUT = VPWR -2.0 V Open Load Detection Current
(16) (17) (15) (15)
Symbol
Min
Typ
Max
Unit
VOFD(THRES) 2.0 VCL - 20 TSD TSD(HYS) 160 10 - 175 - - 190 30 3.0 4.0
V
V
C C
RDS(ON) - - - - - - RDS(ON)REV - ILIM(PK) 15 ILIM(SUS) 6.0 IOLDC VOFD(THRES) 2.0 VCL - 20 - 170 - - 190 30 3.0 4.0 25 10 - 15 100 23 35 - 0.08 - - - - - - 0.08 0.04 0.04 0.136 0.068 0.068
A
A
A V
Output Fault Detection Threshold Outputs Programmed OFF Output Negative Clamp Voltage
V
0.5 A < IOUT < 2.0 A, Outputs OFF Overtemperature Shutdown (Outputs OFF) Overtemperature Shutdown Hysteresis
(18) (18)
TSD TSD(HYS)
160 10
C C
Notes 14. Output fault detection threshold with outputs programmed OFF. For the Low-Side Outputs, fault detection thresholds are the same for output open and battery shorts. 15. Guaranteed by design. Not production tested. 16. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 17. Output fault detection threshold with outputs programmed OFF. 18. Guaranteed by design. Not production tested.
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ELECTRICAL CONNECTIONS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic LOW-SIDE POWER OUTPUTS Drain-to-Source ON Resistance (IOUT = 0.3 A) TJ = 25C VPWR = 4.5 V; VDD = 3.5 V, 33888A Only VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V TJ = 150C VPWR = 4.5 V; VDD = 3.5 V, 33888A Only VPWR = 6.0 V VPWR = 9.0 V VPWR = 13 V Output Self-Limiting Current (Outputs Programmed ON, VOUT = 3.0 V) Low-Side 4, 6, 8, 10 Low-Side 5, 7, 9, 11 Output OFF Open Load Detection Current (19) Output Programmed OFF, VOUT = 3.0 V Output Fault Detection Threshold (20) Output Programmed OFF Output Clamp Voltage 2.0 mA < IOUT < 200 mA, Outputs OFF Low-Side Body Diode Voltage (I = -300 mA, TJ = 125C) Overtemperature Shutdown (Outputs OFF) Overtemperature Shutdown Hysteresis
(21) (21)
Symbol
Min
Typ
Max
Unit
RDS(ON) - - - - - - - - ILIM 0.5 0.8 IOLDC 25 VOFD(THRES) 2.0 VCL 41 VBD TLIM TLIM(HYS) 0.5 160 10 53 0.7 170 20 60 0.9 190 30 3.0 4.0 50 100 0.9 1.3 1.5 2.0 - - - - - - - - 8.0 1.0 0.7 0.6 8.0 1.8 1.1 0.9
A
A
V
V
V C C
Notes 19. Output OFF Open Load Detection Current is the current required to flow through the load for the purpose of detecting the existence of an open load condition when the specific output is commanded OFF. 20. Output fault detection threshold with outputs programmed OFF. For the low-side outputs, fault detection thresholds are the same for output open and battery shorts. 21. Guaranteed by design. Not production tested.
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ELECTRICAL CONNECTIONS STATIC ELECTRICAL CHARACTERISTICS
Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic CONTROL INTERFACE Input Logic High Voltage (22) Input Logic Low Voltage
(22) (23)
Symbol
Min
Typ
Max
Unit
VIH VIL VIN(HYS) IDWN RDWN
(24)
0.7 VDD - 100 5.0 100 5.0 5.0 7.0 - 2.0 0.8 VDD - - 5.0 - -
- - 350 - 200 - - - - - 0.2 0 4.0 -
- 1.0 750 20 400 20 20 14 - 0.3 - 0.4 5.0 12 20
V V mV A k A A V V V V A pF pF
Input Logic Voltage Hysteresis (SI, CS, SCLK, IHS[0:3], ILS)
Input Logic Pulldown Current (SI, SCLK, IHS[0:3], ILS, WDIN) Input Logic Pulldown Resistor (WAKE, RST) Input Logic Pullup Current (CS, VIN = 0.7 VDD) Input Logic Pullup Current (FSI, VIN = 3.5 V) Wake Input Clamp Voltage (IWICI < 2.5 mA)
(25)
IUPC IUPF VWIC VWIF VSOH VSOL ISOLK CIN
Wake Input Forward Voltage (IWICI = - 2.5 mA) SO High-State Output Voltage (IOH = 1.0 mA) FS, SO Low-State Output Voltage (IOL = -1.6 mA) SO Tri-State Leakage Current (CS 3.5 V) Input Capacitance
(26) (23)
SO, FS Tri-State Capacitance
CSO
Notes 22. Upper and lower logic threshold voltage range applies to SI, CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN input signals. The WAKE, FSI, and RST signals are derived from an internal supply. 23. Parameter is guaranteed by design but is not production tested. 24. CS is pulled up to VDD. 25. 26. The current must be limited by a series resistor when using voltages higher than the WICV. Input capacitance of SI, CS, SCLK, RST, IHS[0:3], ILS, WAKE, and WDIN. This parameter is guaranteed by process monitoring but is not production tested.
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ELECTRICAL CONNECTIONS DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUT TIMING High-Side Output Rising Fast Slew Rate (27) 6.0 V < VPWR < 9.0 V 9.0 V < VPWR < 16 V 16 V < VPWR < 27 V High-Side Output Rising Slow Slew Rate 6.0 V < VPWR < 9.0 V 9.0 V < VPWR < 16 V 16 V < VPWR < 27 V High-Side Output Falling Fast Slew Rate (27) 6.0 V < VPWR < 9.0 V 9.0 V < VPWR < 16 V 16 V < VPWR < 27 V High-Side Output Falling Slow Slew Rate (28) 6.0 V < VPWR < 9.0 V 9.0 V < VPWR < 16 V 16 V < VPWR < 27 V High-Side Output Turn ON Delay Time (29) High-Side Output Turn OFF Delay Time (30) Low-Side Output Falling Slew Rate (31) Low-Side Output Rising Slew Rate (31) Low-Side Output Turn ON Delay Time (32) Low-Side Output Turn OFF Delay Time (33) Low-Side Output Fault Delay Timer (34) SRF_SLOW 0.05 0.08 0.08 - 0.15 - 30 80 3.0 6.0 2.0 4.0 150 0.3 0.4 0.5 150 150 10 20 10 10 250 s s V/s V/s s s s SRF_FAST 0.2 0.3 0.5 - 0.8 - 1.0 1.5 2.2 V/s
(28)
Symbol
Min
Typ
Max
Unit
SRR_FAST 0.03 0.05 0.1 SRR_SLOW 0.01 0.01 0.01 - 0.08 - 0.14 0.18 0.2 - 0.5 - 0.6 0.8 1.1
V/s
V/s
V/s
t DLY(ON) t DLY(OFF)
SRF SRR
5.0 5.0 0.5 1.0 0.5 0.5 70
t DLY(ON) t DLY(OFF) t DLY(FS)
Notes 27. High-side output rise and fall fast slew rates measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR - 3.0 V (see Figure 5, page 17). These parameters are guaranteed by process monitoring. 28. High-side output rise and fall slow slew rates measured across a 5.0 resistive load at high-side output = 0.5 V to VPWR - 3.0 V (see Figure 5, page 17). These parameters are guaranteed by process monitoring. 29. High-side output turn-ON delay time measured from 50% of the rising IHS to 0.5 V of output OFF with RL = 27 resistive load (see Figure 5, page 17). 30. High-side output turn-OFF delay time measured from 50% of the falling IHS to VPWR - 2.0 V of the output OFF with RL = 27 resistive load (see Figure 5, page 17). 31. Low-side output rise and fall slew rates measured across a 5.0 resistive load at low-side output = 10% to 90% (see Figure 6, page 17). 32. Low-side output turn-ON delay time measured from 50% of the rising ILS to 90% of VOUT with RL = 27 resistive load (see Figure 6, page 17). 33. Low-side output turn-OFF delay time measured from 50% of the falling ILS to 10% of VOUT with RL = 27 resistive load (see Figure 6, page 17). These parameters are guaranteed by process monitoring. 34. Propagation time of Short Fault Disable Report Delay measured from rising edge of CS to output disabled, low-side = 5.0 V, and device configured for low-side output overcurrent latch-off using CLOCCR.
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ELECTRICAL CONNECTIONS DYNAMIC ELECTRICAL CHARACTERISTICS
Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 6.0 V VPWR 27 V, 4.5 V VDD 5.5 V, -40C TJ 150C unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25C under nominal conditions unless otherwise noted.
Characteristic POWER OUTPUT TIMING (continued) Watchdog Timeout (35) Peak Current Limit Timer
(36) (37)
Symbol
Min
Typ
Max
Unit
t WDTO t PCT f PWM
340 40 -
584 70 125
770 100 -
ms ms Hz
Direct Input Switching Frequency SPI INTERFACE TIMING
(38)
Recommended Frequency of SPI Operation Normal Mode Extended Mode: VDD = 3.4 V; VPWR = 4.5 V, APNB Suffix Only Required Low State Duration for RST
(39) (40) (40) (40)
f SPI - - t WRST t CS t ENBL t LEAD t WSCLKh t WSCLKl
(40)
MHz - - 50 - - 50 - - 50 25 25 3.0 2.1 167 300 5.0 167 167 167 167 83 83 ns ns s ns ns ns ns ns ns ns - 25 50 ns - 25 - - - 65 50 50 50 145 145 ns ns ns ns ns - 65 105
- - - - - - - - -
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time) Required High State Duration of SCLK (Required Setup Time) Required Low State Duration of SCLK (Required Setup Time)
(40) (40)
Falling Edge of SCLK to Rising Edge of CS (Required Setup Time) SI to Falling Edge of SCLK (Required Setup Time) Falling Edge of SCLK to SI (Required Hold Time) SO Rise Time CL = 200 pF SO Fall Time CL = 200 pF SI, CS, SCLK, Incoming Signal Rise Time (41) SI, CS, SCLK, Incoming Signal Fall Time
(41) (42) (43) (40)
t LAG t SI (SU) t SI (HOLD) t RSO
(40)
t FSO
t RSI t FSI t SO(EN) t SO(DIS) t VALID
- - - -
Time from Falling Edge of CS to SO Low Impedance Time from Rising Edge of CS to SO High Impedance Time from Rising Edge of SCLK to SO Data Valid 0.2 VDD SO 0.8 VDD, CL = 200 pF
(44)
Notes 35. Watchdog timeout delay is measured from the rising edge of WAKE or RST from the sleep state to the HS[0:1] turn-ON with the outputs driven OFF and the FSI floating. The accuracy of t WDTO is maintained for all configured watchdog time-outs. 36. 37. 38. 39. 40. 41. 42. 43. 44. t PCT measured from the rising edge of CS to 90% of ILIMPKHS[x,x] when the peak current limit is enabled. This frequency is a typical value. Maximum switching frequencies are dictated by the turn-ON delay, turn-OFF delay, output rise and fall times, and the maximum allowable junction temperature. Symmetrical 50% duty cycle SCLK clock period of 333 ns. RST low duration measured with outputs enabled and going to OFF or disabled condition. Maximum setup time required for the 33888 is the minimum guaranteed time needed from the MCU. Rise and fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing. Time required for output status data to be available for use at SO. 1.0 k pullup on CS. Time required for output status data to be terminated at SO. 1.0 k pullup on CS. Time required to obtain valid data out from SO following the rise of SCLK.
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ELECTRICAL CONNECTIONS TIMING DIAGRAMS
TIMING DIAGRAMS
Direct input or spi bit Direct Input or SPI Bit
VPWR VPWR
VPWR - 0.5V VPWR -0.5 V VPWR - V VPWR -3.0 3V
SRR_SLOW SRr_slow
SRF_SLOW SRf_slow
SRF_FAST SRf_fast SRR_FAST SRr_fast
0.5 V 0.5V t DLY(ON) Tdly(on)
Tdly(off) t DLY(OFF)
Figure 5. Output Slew Rates and Time Delays, High Side
Direct input or SPI bit
VPWR 90%
SRf
SRr
10% Tdly(on) Tdly(off)
Figure 6. Output Slew Rates and Time Delays, Low Side
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FUNCTIONAL DESCRIPTION INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
This 33888 is a single-package combination of a power die with four discrete high-side MOSFETs and an integrated IC control die consisting of eight low-side drivers with appropriate control, protection, and diagnostic features. The high-side drivers are useful for both internal and external vehicle lighting applications as well as capable of driving inductive solenoid loads. The low-side drivers are capable of controlling low-current on/off type inductive loads, such as relays and solenoids as well as LED indicators and small lamps (see Figure 2, page 3). The device is useful in body control, instrumentation, and other high-power switching applications and systems. The 33888 is available in two packages: a powerenhanced 12 x 12 non-leaded Power QFN package with exposed tabs and a 64-lead Power QFP plastic package. Both packages are intended to be soldered directly onto the printed circuit board. The 33888 differs from the 33888A as explained in Table 1, page 2.
FUNCTIONAL PIN DESCRIPTION FAULT STATUS (FS)
This output pin is an open drain indication that goes active low when a fault mode is detected by the device. Specific device fault indication is given via the SO pin. the rising edges of SCLK. The serial output data provides fault information for each output and is returned MSB first when the device is addressed. OD11 through OD0 are output fault bits for outputs 11 through 0, respectively.
POSITIVE POWER SUPPLY (VPWR)
These pin connects to the positive power supply and are the source input of operational power for the device.
CHIP SELECT (CS)
This is an input pin connected to a chip select output of a microcontroller (MCU). This IC controls which device is addressed (selected) by pulling the CS pin of the desired device logic Low, enabling the SPI communication with the device, while other devices on the serial link keep their serial outputs tri-stated. This input has an internal active pullup and requires CMOS logic levels.
LOW-SIDE OUTPUT (LS4, LS6, LS8, LS10)
Each low-side pin is one 0.6 low-side output MOSFET drain, which pulls current through the connected loads. Each of the outputs is actively clamped at 53 V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 500 mA.
SERIAL CLOCK (SCLK)
This input pin is connected to the SCLK pin of the master MCU, which is a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an operating frequency, fSPI, and is idle between command transfers. It is 50% duty cycle and has CMOS logic levels. This signal is used to shift data to and from the 33888.
GROUND (GND)
These pins serve as the ground for the source of the lowside output transistors as well as the logic portion of the device.
LOW-SIDE OUTPUT (LS5, LS7, LS9, LS11)
Each low-side pin is one 0.6 low-side output MOSFET drain, which pulls current through the connected loads. Each of the outputs is actively clamped at 53 V. These outputs are current and thermal overload protected. Maximum steady state current through each of these outputs is 800 mA.
SERIAL INPUT (SI)
This input pin is connected to the SPI Serial Data Output pin of the MCU from which it receives output command data. This input has an internal active pull-down and requires CMOS logic levels. The serial data transmitted on this line is a 16-bit control command sent MSB first, which controls the twelve output channels. Bits D3 : D0 control the high-side outputs HS3 : HS0, respectively. Bits D11: D4 control the lowside outputs LS11: LS4, respectively. The MUC will ensure that data is available on the falling edge of SCLK.
DIGITAL DRAIN VOLTAGE (VDD)
This is an external input pin used to supply power to the SPI circuit.
SERIAL OUTPUT (SO)
This is an output pin connected to the SPI Serial Data Input pin of the MCU or to the SI pin of the next device in a daisy chain. This output will remain tri-stated unless the device is selected by a low CS pin. The output signal generated will have CMOS logic levels and the output data will transition on
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LOW-SIDE INPUT (ILS)
This input pin is used to directly control a number of the low-side devices as configured by SPI. This pin may or may not be activated depending on the configured state of the internal logic.
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Analog Integrated Circuit Device Data Freescale Semiconductor
FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION
HIGH-SIDE INPUT (IHS3, IHS2, IHS0, IHS1)
Each high-side input pin is used to directly control only one designated high-side output. These inputs may or may not be activated depending on the configured state of the internal logic.
initialized and then immediately followed by normal operation.
WAKE (WAKE)
This pin is used to input a logic [1] signal in order to enable the watchdog timer function. An internal clamp protects the pin from high voltages when current is limited with an external resistor. This input has a passive internal pulldown.
CURRENT SENSE (2-3, 0-1)
These pins deliver a metered amount of the high-side output current that can be used to generate signal ground referenced output voltages for use by the MCU. Each respective CSNS pin can be configured via SPI to deliver current from either of the two assigned outputs, or the currents could be the sum of the two. Current from HS0 and/ or HS1 are sensed via CSNS0 - 1. Current from HS2 and/or HS3 are sensed via CSNS2 - 3.
RESET (RST)
This input pin is used to initialize the device configuration and fault registers, as well as place the device in a low current standby mode. This pin also starts the watchdog timeout when transitioned from logic [0] to logic [1]. This pin should not be allowed to be at logic [1] until VDD is in regulation. This input has an internal passive pulldown.
HIGH SIDE OUTPUT (HS3, HS2)
Each pin is the source of a 40 m MOSFET high-side driver, which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS pins depending on the internal configuration. These outputs are current limited and thermally protected. During fail-safe mode, output HS2 will be turned on until the device is reinitialized and then immediately followed by normal operation.
FAIL-SAFE INPUT (FSI)
The Fail-Safe input pin level determines the state of the outputs after a watchdog timeout occurs. This pin has an internal pullup. If the FSI pin is left to float to a logic [1], then HS0 and HS2 will turn on when in the Fail-Safe state. If the FSI pin is tied to GND, the watchdog circuit and fail-safe operation will be disabled, thus allowing operation without a watchdog signal.
HIGH SIDE OUTPUT (HS1, HS0)
Each pin is the source of a 10 m MOSFET high-side driver, which delivers current through the connected loads. These outputs can be controlled via SPI or using the IHS pins depending on the internal configuration. These outputs are current limited and thermally protected. During fail-safe mode, output HS0 will be turned on until the device is re
WATCHDOG INPUT (WDIN)
This input pin is a CMOS logic level input that is used to monitor system operation. If the incoming watchdog signal does not transition within the normal watchdog timeout range, the device will operate in the Fail-Safe mode. This input has an active internal pulldown.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES WATCHDOG AND FAIL-SAFE OPERATION
The watchdog is enabled and a timeout is started when the WAKE or RST transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to VPWR with a series limiting resistance that limits the internal clamp current. The timeout is a multiple of an internal oscillator. As long as the WDIN pin or the WD bit (D15) of an incoming SPI message is toggled within the minimum watchdog timeout, WDTO (or a divided value configured during a WDCSCR message), then the device will operate normally. If the watchdog timeout occurs before the WD bit or the WDIN pin is toggled, then the device will revert to a Fail-Safe mode until the device is re initialized (if the FSI pin is left disconnected). During Fail-Safe mode, all outputs will be OFF except for HS0 and HS2, which will be driven ON regardless of the state of the various direct inputs and modes (Table 7). The device can be brought out of the Fail-Safe mode by transitioning the WAKE and RST pins from logic [1] to logic [0]. In the event the WAKE pin was not transitioned to a logic [1] during normal operation and the watchdog times out, then the device can be brought out of fail-safe by bringing the RST to a logic [0]. If the FSI pin is tied to GND, then the watchdog, and therefore fail-safe operation, will be disabled. Table 7. Fail-Safe Operation and Transitions to Other 33888 Modes
WAKE 0 1 RS LS[4:11], WDTO HS0 HS2 HS[1,3] T 0 0 x NO OF OF F F OF OF F F OFF OFF Comments Device in Sleep mode. All outputs are OFF. When RST transitions to logic [1], device is in default. Fail-Safe mode. Device reset into Default mode by transitioning WAKE to logic [0]. Device in Normal operating mode. Fail-Safe mode. Device reset into Default mode by transitioning RST to logic [0]. Device in Normal operating mode. Fail-Safe mode. Device reset into Default mode by transitioning RST and WAKE to logic [0].
1
0
YES
ON ON
OFF
0 0
1 1
NO YES
S
S
S OFF
ON ON
1 1
1 1
NO YES
S
S
S OFF
DEFAULT MODE
The default mode describes the state of the device after first applying VPWR voltage or a reset transition from logic [0] to logic [1] prior to SPI communication. In the default mode, all outputs will be off (assuming that the direct inputs ILS and IHS[0:3] and the WAKE pin are at logic [0] ). All of the specific pin functions will operate as though all of the addressable configuration register bits were set to logic [0]. This means, for example, that all of the low-side outputs will be controllable by the ILS pin, and that all high-side outputs will be controllable via their respective IHS pins. During the default mode, all high-side drivers will default with open load detection enabled. All low-side drivers will default with open load detection disabled. This mode allows limited control of the 33888 with the direct inputs in the absence of an SPI. Returning the device to the default state after a period of normal operation, followed by the removal of the VPWR voltage, requires that the RST input be held at a logic [0] state until VPWR falls to a level below 2.0 V. If the RST and VDD input levels are normal, then failure to allow VPWR to fall below 2.0 V will result in an internal bias circuit clamping the VPWR pin to approximately 3.5 V. Once VPWR falls below 2.0 V, the RST can be returned to 5.0 V without re-enabling the bias circuit.
ON ON
Assumptions: Normal operating voltage and junction temperatures, FSI pin floating. x = Don't care. S = State determined by SPI and/or direct input configurations.
FAULT LOGIC REQUIREMENTS
The 33888 indicates all of the following faults as they occur: * Overtemperature Fault * Overvoltage Fault * Open Load Fault * Overcurrent Fault With the exception of the overvoltage, these faults are output specific. The overvoltage fault is a global fault. The overcurrent fault is only reported for the low-side outputs. The 33888 low-side outputs incorporate an internal fault filter, t DLY(FS). The fault timer filters noise and switching transients for overcurrent faults when the output is ON and open load faults when the output is OFF. All faults are latched and indicated by a logic [1] for each output in the 33888 status word (Table 10, page 25). If the fault is removed, the status bit for the faulted output will be cleared by a rising edge on CS.
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FUNCTIONAL DEVICE OPERATION OPERATIONAL MODES
The FS pin is driven to a logic [0] when a fault exists on any of the outputs. FS provides real time monitoring of the overvoltage fault. For the high-side outputs, FS provides real time monitoring of the open load and overtemperature. For the low-side outputs, the FS is latched to a logic [0] for open load, overtemperature, and overcurrent faults. The latch is cleared by toggling the state of the faulted output or by bringing RST low.
OVERVOLTAGE FAULT
The 33888 shuts down all outputs during an overvoltage condition on the VPWR pin. The outputs remain in the OFF state until the overvoltage condition is removed. Fault status for all outputs is latched into the status register. Following an overvoltage condition, the next write cycle sent by the SO pin of the 33888 is logic [1] on OD11: OD0, indicating all outputs have shut down. If the overvoltage condition is removed, the status register can be cleared by a rising edge on CS.
OVERTEMPERATURE FAULT
The 33888 incorporates overtemperature detection and shutdown circuitry into each individual output structure. Overtemperature detection occurs when an output is in the ON state. When an output is shut down due to an overtemperature condition, no other output is affected. The output experiencing the fault is shut down to protect itself from damage. A fault bit is loaded into the status register if the overtemperature condition is removed, and the fault bit is cleared upon the rising edge of CS. For the low-side outputs, the faulted output is latched OFF during an overtemperature condition. If the temperature falls below the recovery level, TLIM(HYS), then the output can be turned back ON only after the output has first been commanded OFF either through the SPI or the ILS, depending on the logic configuration. For the high-side output(s), an overtemperature condition will result in the output(s) turning OFF until the temperature falls below the TLIM(HYS). This cycle will continue indefinitely until action is taken by the MCU to shut the output(s) OFF. 33888
LOW = Logic 0 MOSFET
OPEN LOAD FAULT
The 33888 incorporates open load detection circuitry on every output. A high-side or low-side output open load fault is detected and reported as a fault condition when the corresponding output is disabled (OFF) if it was configured for open load detection by setting the appropriate bit to logic [0] (HS3 : HS0) or logic [1] (LS11: LS4) in the OLFCR register (see Figure 7). The high-side open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn off the output. If the open load fault is removed or if the faulted output is commanded ON, the status register can be cleared by a rising edge on CS. Note that the device default state will enable the high-side open load detection and disable the low-side open load detection circuits, respectively. It is recommended to disable the open load detection circuitry (OL bit sets to logic [1]) in case of a permanent open load fault condition.
VPWR RL OUT 50 mA
+
-
VTHRES
VOFD(THRES)LS 2.0 V-4.0 V
Figure 7. Low-Side Output OFF Open Load Detection
OVERCURRENT FAULT REQUIREMENTS: LOWSIDE OUTPUT
An overcurrent condition is defined as any current value greater than ILIM (500 mA minimum value for LS5, LS7, LS9, LS11, and 800 mA minimum value for LS4, LS6, LS8, LS10). The status of the corresponding bit in the CLOCCR register determines whether a specific output shuts down or continues to operate in an analog current limited mode until either the overcurrent condition is removed or the thermal shutdown limit is reached (Figure 10, page 27). If the overcurrent shutdown mode is disabled, the fault reporting is disabled as well.
For the low-side output of interest, if a D11: D4 bit was set to a logic [1] in the OLCR register, the overcurrent protection shutdown circuitry will be enabled for that output. When a low-side output is commanded ON either from the SPI or the ILS pin, the drain of the low-side driver will be monitored for a voltage greater than the fault detection threshold (3.0 V typical). If the drain voltage exceeds this threshold, a timer will start and the output will be turned off and a fault latched in the status register after the timeout expires. The faulted output can be retried only by commanding the output OFF and back ON either through the SPI or the ILS pin, depending on the logic configuration. If the fault is gone, the retried output will return to normal operation and the status register can be cleared on a rising edge of CS. If the fault remains, the
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
retried output will latch off after the fault timer expires and the fault bit will remain set in the status register. For the low-side output of interest, if a D11 : D4 bit was set to a logic [0] in the OLCR register, the output experiencing an overcurrent condition is not disabled until an overtemperature fault threshold has been reached. The specific output goes into an analog current limit mode of operation, ILIM. The 33888 uses overtemperature shutdown to protect all outputs in this mode of operation. If the overcurrent condition is removed before the output has reached its overtemperature limit, the output will function as if no fault has occurred. Note that each pair of low-side drivers, LS4 : LS5, LS6 : LS7, LS8 : LS9, and LS10 : LS11, consists of a 500 mA and a 800 mA output. Each pair of outputs shares ground bond wires. The bond wires are not rated to handle both outputs in current limit mode simultaneously.
OVERCURRENT FAULT REQUIREMENTS: HIGHSIDE OUTPUT
For the high-side output of interest, the output current is limited to one of four levels depending on the type of highside output, the amount of time that has elapsed since the output was switched on, and the state of the CLOCCR register. Assuming that bits D3 : D0 of the CLOCCR register are at logic [0], the current limit levels of the outputs will be initially at their peak levels as specified by the ILIM(PK)HS[0:3]. After the high-side output is switched on, the peak current timer starts. After a period of time t PCT, the current limit level changes to the sustain levels ILIMSUSHS[x,x]. For the high-side output of interest, if a D3 : D0 bit of the CLOCCR is at logic [1], then the assigned output will only current limit at the sustain level specified by ILIMSUSHS[x,x]. Current is limited until the overtemperature circuitry shuts OFF the device. The device turns ON automatically when the temperature fails below the TLIM(HYS). This cycle continues indefinitely until action is taken by the master to shut the output(s) OFF.
LOGIC COMMANDS AND REGISTERS SPI INTERFACE AND PROTOCOL DESCRIPTION
The SPI interface has full duplex, three-wire synchronous data transfer and has four I/O lines associated with it: Serial Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip Select (CS). The SI/SO pins of the 33888 follow a first-in first-out (D15 / D0) protocol with both input and output words transferring the most significant bit first. All inputs are compatible with 5.0 V CMOS logic levels. During SPI output control, a logic [0] in a message word will result in the designated output being turned off. Similarly, a logic [1] will turn on a corresponding output. The SPI lines perform the following functions: Serial Clock (SCLK) The SCLK pin clocks the internal shift registers of the 33888. The serial input (SI) pin accepts data into the input shift register on the falling edge of the SCLK signal while the serial output pin (SO) shifts data information out of the SO line driver on the rising edge of the SCLK signal. It is important that the SCLK pin be in a logic [0] state whenever the chip select (CS) makes any transition. For this reason, it is recommended that the SCLK pin be kept in a logic [0] state as long as the device is not accessed (CS in logic [1] state). SCLK has an active internal pulldown, IDWN. When CS is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high impedance). (See Figures 8 and 9 on page 23.) Serial Interface (SI) This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial data is required on the SI pin, starting with D15 to D0. The 12 outputs of the 33888 are configured and controlled using the 3-bit addressing scheme and the 12 assigned data bits designed into the 33888. SI has an active internal pulldown, IDWN. Serial Output (SO) The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high-impedance state until the CS pin is put into a logic [0] state. The SO data report the status of the outputs as well as provide the capability to reflect the state of the direct inputs. The SO pin changes states on the rising edge of SCLK and reads out on the falling edge of SCLK. When an output is ON or OFF and not faulted, the corresponding SO bit, OD11: OD0, is a logic [0]. If the output is faulted, the corresponding SO state is a logic [1]. SO OD14 : OD12 reflect the state of six various inputs (three at a time) depending upon the reported state of the previously written watchdog bit OD15. Chip Select (CS) The CS pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the 33888 is capable of transferring information to and receiving information from the MCU. The 33888 latches in data from the input shift registers to the addressed registers on the rising edge of CS. The 33888 transfers status information from the power outputs to the shift registers on the falling edge of CS. The output driver on the SO pin is enabled when CS is logic [0]. CS is only transitioned from a logic [1] state to a logic [0] state when SCLK is a logic [0]. CS has an active internal pullup, IUP. The 33888 is capable of communicating directly with the MCU via the 16-bit SPI protocol as described in the next section.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
CSB CS
SCLK
SI
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SO
OD15
OD14 OD13
OD12 OD11 OD10
OD9
OD8
OD7
OD6
OD5
OD4
OD3
OD2
OD1
OD0
Notes 1. RST is in a logic [1] state during the above operation. 2. D15:D0 relate to the most recent ordered entry of program data into the 33888. 3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the 33888.
Figure 8. Single 16-Bit Word SPI Communication
CSB CS
SCLK
SI
D15
D14
D13
D2
D1
D0
D15*
D14*
D13*
D2*
D1*
D0*
SO
OD15
OD14 OD13
OD2
OD1
OD0
D15
D14
D13
D2
D1
D0
Notes 1. RST is a logic [1] state during the above operation. 2. D15:D0 relate to the most recent ordered entry of program data into the 33888. 3. D15*:D0* relate to the first 16 bits of ordered entry data out of the 33888. 4. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the 33888.
Figure 9. Multiple 16-Bit Word SPI Communication
SERIAL INPUT COMMUNICATION
SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB, D15, and ending with the LSB, D0 (refer to Table 8, page 23). Each incoming command message on the SI pin can be interpreted using the following bit assignments: the first twelve LSBs, D11: D0, control each of the twelve outputs; the next three bits, D14 : D12, determine the command mode; and the MSB, D15, is the watchdog bit. Multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable or to confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is not 16 bits will be ignored.
The 33888 has six registers that are used to configure the device and control the state of the four high-side and eight low-side outputs (Table 9, page 24). The registers are addressed via D14 : D12 of the incoming SPI word (Table 8, page 23). Table 8. SI Message Bit Assignment
Bit Sig SI Msg Bit MSB D15 D14 : 12 D11 D10 Message Bit Description Watchdog in: toggled to satisfy watchdog requirements. Register address bits. Used to configure Low-Side Output LS11. Used to configure Low-Side Output LS10.
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Table 8. SI Message Bit Assignment (continued)
D9 D8 D7 D6 Used to configure Low-Side Output LS9. Used to configure Low-Side Output LS8. Used to configure Low-Side Output LS7. Used to configure Low-Side Output LS6.
Table 8. SI Message Bit Assignment (continued)
Bit Sig SI Msg Bit D5 Message Bit Description Used to configure Low-Side Output LS5 (Watchdog timeout MSB during WDCSCR configuration). Used to configure Low-Side Output LS4 (Watchdog timeout LSB during WDCSCR configuration). Used to configure High-Side Output HS3. Used to configure High-Side Output HS2. Used to configure High-Side Output HS1. Used to configure High-Side Output HS0.
D4
D3 D2 D1 LSB D0
Table 9. Serial Input Address and Configuration Bit Map
SI Register SOCR DICR LFCR WDCSCR OLCR CLOCCR NOT USED TEST WD D15 x x x x x x x x D14 0 1 0 1 0 1 0 1 Address D13 0 0 1 1 0 0 1 1 D12 0 0 0 0 1 1 1 1 D11 LS11 D10 LS10 D9 LS9 Low-Side D8 LS8 D7 LS7 D6 LS6 D5 LS5 D4 LS4 D3 HS3 High-Side D2 HS2 D1 HS1 D0 HS0
PWB11 PWB10 PWB9 PWB8 PWB7 PWB6 PWB5 PWB4 PWB3 PWB2 PWB1 PWB0 A/ OB11 NA OL11 OC11 - - A/ OB10 NA OL10 OC10 - - A/OB9 A/OB8 A/OB7 A/OB6 A/OB5 A/OB4 A/OB3 A/OB2 A/OB1 A/OB0 NA OL9 OC9 - - NA OL8 OC8 - - NA OL7 OC7 - - NA OL6 OC6 - - WDH OL5 OC5 - - WDL OL4 OC4 - - ILIMPK CS3 OLB3 ILIM3 - CS2 OLB2 ILIM2 - WD CS1 OLB1 ILIM1 - ILIM CS0 OLB0 ILIM0 - OT
x = Don't care. NA = Not applicable.
LOGIC COMMANDS AND REGISTERS DEVICE REGISTER ADDRESSING
The following section describes the possible register addresses and their impact on device operation. Address 000 -- SPI Output Control Register (SOCR) The SOCR register allows the MCU to control the outputs via the SPI. Incoming message bits D3 : D0 reflect the desired states of high-side outputs HS3 : HS0. Message bits D11: D4 reflect the desired state of low-side outputs LS11: LS4, respectively. Address 100-- Direct Input Control Register (DICR) The DICR register is used by the MCU to enable direct input control of the outputs. For the outputs, a logic [0] on bits D11: D0 will enable the corresponding output for direct control. A logic [1] on a D11: D0 bit will disable the output from direct control. Address 010 -- Logic Function Control Register (LFCR) The LFCR register is used by the MCU to configure the relationship between SOCR bits D11: D0 and the direct inputs IHS[0:3] and ILS. While addressing this register (if the direct inputs were enabled for direct control with the DICR), a logic [1] on any or all of the D3 : D0 bits will result in a Boolean AND of the IHS[0:3] pin(s) with its (their) corresponding D3 : D0 message bit(s) when addressing the SOCR. A logic [1] on any or all of the D11: D4 bits will result in a Boolean AND of the ILS and the corresponding D11: D4 message bits when addressing the SOCR. Similarly, a logic [0] on the D3 : D0 bits will result in a Boolean OR of the IHS[0:3] pin(s) with their corresponding message bits when addressing the SOCR register, and the ILS will be Boolean OR'd with message bits D11: D4 when addressing the SOCR register (if ILS is enabled).
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FUNCTIONAL DEVICE OPERATION LOGIC COMMANDS AND REGISTERS
Address 110 -- Watchdog and Current Sense Configuration Register (WDCSCR) The WDCSCR register is used by the MCU to configure the watchdog timeout and the CSNS0-1 and CSNS2-3 pins. The watchdog timeout is configured using bits D4 and D5. The state of D4 and D5 determine the divided value of the WDTO. For example, if D5 and D4 are logic [0] and logic [0], respectively, then the WDTO will be in the default state as specified in Table 9, page 24. A D5 and a D4 of logic [0] and logic [1] will result in a watchdog timeout of WDTO / 2. Similarly, a D5 and a D4 of logic [1] and logic [0] result in a watchdog timeout of WDTO / 4, and a D5 and a D4 of logic [1] and logic [1] result in a watchdog timeout of WDTO / 8. Note that when D5 and D4 bits are programmed for the desired watchdog timeout period, the WD bit (D15) should be toggled as well to ensure that the new timeout period is programmed at the beginning of a new count sequence. CSNS0 - 1 is the current sense output for the HS0 and HS1 outputs. Similarly, the CSNS2 - 3 pin is the current sense output for the HS2 and HS3 outputs. In this mode, a logic [1] on any or all of the message bits that control the high-side outputs will result in the sensed current from the corresponding output being directed out of the appropriate CSNS output. For example, if D1 and D0 are both logic [1], then the sensed current from HS0 and HS1 will be summed into the CSNS0 - 1. If D2 is logic [1] and D3 is logic [0], then only the sensed current from HS2 will be directed out of CSNS2 - 3. Address 001 -- Open Load Configuration Register (OLCR) The OLCR register allows the MCU to configure each of the outputs for open load fault detection. While in this mode, a logic [1] on any of the D3 : D0 message bits will disable the corresponding outputs' circuitry that allows the device to detect open load faults while the output is OFF. For the lowside drivers, a logic [1] on any of the D11: D4 bits will enable the open load detection circuitry. This feature allows the MCU to minimize load current in some applications and may be useful to diagnose output shorts to battery (for HS). Address 101 -- Current Limit Overcurrent Configuration Register (CLOCCR) The CLOCCR register allows the MCU to individually override the peak current limit levels for each of the high-side outputs. A logic [1] on any or all of the D3 : D0 bit(s) results in the corresponding HS3 : HS0 output pins to current limit at the sustain current limit level. This register also allows the MCU to enable or disable the overcurrent shutdown of the low-side output pins. A logic [1] on any or all of the D11: D4 message bit(s) will result in the corresponding LS11: LS4 pins latching off if the current exceeds ILIM after a timeout of t DLY(FS). Address 011 -- Not Used Not currently used.
Address 111 -- TEST The TEST register is reserved for test and is not accessible via SPI during normal operation.
SERIAL OUTPUT COMMUNICATION (DEVICE STATUS RETURN DATA)
When the CS pin is pulled low, the output status register for each output is loaded into the output register and the fault data is clocked out MSB (OD15) first as the new message data is clocked into the SI pin. OD15 reflects the state of the watchdog bit (D15) that was addressed during the prior SOCR communication (refer to Table 10, page 25). If bit OD15 is logic [0], then the three MSBs OD14 : OD12 will reflect the logic states of the IHS0, IHS1, and FSI pins, respectively. If bit OD15 is logic [1], then the same three MSB bits will reflect the logic states of the IHS2, IHS3, and WAKE pins. The next twelve bits clocked out of SO following a low transition of the CS pin (OD11 : OD0) will reflect the state of each output, with a logic [1] in any of the bits indicating that the respective output experienced a fault condition prior to the CS transition. Any bits clocked out of the SO pin after the first 16 will be representative of the initial message bits that were clocked into the SI pin since the CS pin first transitioned to a logic [0]. This feature is useful for daisy chaining devices as well as message verification. Following a CS transition logic [0] to logic [1], the device determines if the message was of a valid length (a valid message length is one that is a multiple of 16 bits) and if so, latches the data into the appropriate registers. At this time, the SO pin is tri-stated and the fault status register is now able to accept new fault status information. Table 10. Serial Output Bit Assignment
Bit SO Sig Msg Bit MS B OD15 OD14 Message Bit Description Reflects the state of the Watchdog bit from the previously clocked-in message. If OD15 is logic [0], then this bit will reflect the state of the direct input IHS0. If OD15 is logic [1], then this bit will reflect the state of IHS2. If OD15 is logic [0], then this bit will reflect the state of the direct input IHS1. If OD15 is logic [1], then this bit will reflect the state of IHS3. If OD15 is logic [0], then this bit will reflect the state of the input FSI. If OD15 is logic [1], then this bit will reflect the state of the input WAKE. Reports the absence or presence of a fault on LS11. Reports the absence or presence of a fault on LS10. Reports the absence or presence of a fault on LS9. Reports the absence or presence of a fault on LS8. Reports the absence or presence of a fault on LS7. Reports the absence or presence of a fault on LS6.
OD13
OD12
OD11 OD10 OD9 OD8 OD7 OD6
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES
Table 10. Serial Output Bit Assignment (continued)
OD5 OD4 OD3 OD2 OD1 LSB LSB OD0 OD0 Reports the absence or presence of a fault on LS5. Reports the absence or presence of a fault on LS4. Reports the absence or presence of a fault on HS3. Reports the absence or presence of a fault on HS2. Reports the absence or presence of a fault on HS1. Reports the absence or presence of a fault on HS0. Reports the absence or presence of a fault on HS0.
OPEN LOAD
An open load condition is only detected when the output is off and the open load detection for the output of concern is enabled. The first SPI read after the output is commanded on will clear the fault bit for this output.
OVER TEMPERATURE
An over temperature condition is indicated and latched into the fault register if the output is on and the indicating output experienced an over temperature event since the last SPI write. Each output has a dedicated temperature sensor. The high side drivers will turn off after the over temperature shutdown level is reached until the temperature falls below the specified hysteresis level and then will turn back on automatically, unless the output has been commanded off. In either case, a fault indication for the faulted output will be present for the next SPI read.
The MC33888 device reports the occurrence of the following faults via the output dedicated bits clocked out of the SO pin: * Over voltage * Open Load * Over temperature In the event of an occurrence of faults, the bits clocked out of the device will indicate the presence of a fault with a logic [1] on the output dedicated bit, prior to and since the last SPI communication, or at the time of the CSB pin going to logic [0]. Each type of fault can be differentiated from the others as follows:
CURRENT LIMIT
An output which current limits will not indicate a fault unless the limitation results in enough power dissipation to increase the temperature of the limiting transistor to its over temperature shutdown level. Each of these faults are indicated real time by the FLTB pin, which could be used as an initial indication of the presence of a fault within the device. Determining the actual faulted output would requires an analysis of the fault bits provided by the device via the SO pin. Note that the very first SPI read after the battery falls below 6V may not be correct, if the VDD remained in specification and a reset was not generated by the MCU.
OVER VOLTAGE
An over voltage occurrence can be inferred if all twelve bits representing each of the outputs are logic [1] at the same time.
PROTECTION AND DIAGNOSTIC FEATURES REVERSE BATTERY REQUIREMENTS
The low-side and high-side outputs survive the application of reverse battery as low as -16 V.
GROUND DISCONNECT PROTECTION
In the event that the 33888 ground is disconnected from load ground, the device protects itself and safely turns OFF the outputs, regardless of the state of the output at the time of disconnection.
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FUNCTIONAL DEVICE OPERATION PROTECTION AND DIAGNOSTIC FEATURES
33888
HIGH = Fault MOSFET ON
VPWR RL OUT
+
- Digital
+
Analog - VREF VOFD(THRES)LS 2.0 V-4.0 V
VTHRES
Figure 10. Low-Side Short Circuit Detection and Analog Current Limit
UNDERVOLTAGE SHUTDOWN REQUIREMENTS
All outputs turn off at some battery voltage below 6.0 V; For the A version, the low side shutdown at a lower value, VPWRUV. however, as long as the level stays above 5.0 V, the internal logic states within the device are designed to be sustained. This ensures that when the battery level then rises above 6.0 V, the device will return to the state that it was in prior to the excursion between 5.0 V and 6.0 V (assuming that there was no SPI communication or direct input changes during the event). If the battery voltage falls to a level below 5.0 V, then the internal logic is re initialized and the device is then in the default state upon the return of levels in excess of 6.0 V.
If the VPWR supply is disconnected, no issue exists for resistive or capacitive loads, but additional protection circuitry is required for the device to support a battery disconnect for an inductive load connected to HS pins.
Drain-Source Clamp Voltage (VCL = 53 V) Drain Current (ID = 0.5 A) Drain-Source ON Voltage (VDS(ON)) Current Area (IA) GND
Drain Voltage Clamp Energy (EJ = IA x VCL x t)
OUTPUT VOLTAGE CLAMPING
Each output has an internal clamp to provide protection and dissipate the energy stored in inductive loads. Each clamp independently limits the drain-to-source voltage to the range specified in the Power Outputs section of Table 5, Static Electrical Characteristics beginning on page 10. Also see Figure 11.
VPWR
Time
Figure 11. Low-Side Output Voltage Clamping
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TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
Figure 12 shows a typical lighting application for the 33888. 55W bulb driven with 10 milliohm outputs, and 21W plus 5W lamps with 40 milliohm outputs.
VPWR +5.0 V +5.0 V
100nF
8 X Relay or LED
10 k FS IHS0.IHS3 ILS RST SPI WDIN CSNS2-3 CSNS0-1 FSI VDD
33888
VPWR LS4:11
4 MCU 4
Loads
A/D A/D
GND
HS2 HS3 HS0 HS1
21 W 5.0 W 21 W 5.0 W 55 W 55 W
Figure 12. 33888 Typical Application Diagram An excel tool has been created to calculate the dissipated PWM frequency, ambient temperature and thermal impedance. The calculations are done with a RDS(ON) at an power and the junction temperature knowing the application conditions in steady state, as shown in Figure 13. estimated junction temperature. The current is also considered constant in the loads. The parameters to enter concern the loads (bulbs only considered) and the board. They are VPWR, loads (in Watts),
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TYPICAL APPLICATIONS
Figure 13. Figure 13 - MC33888 power dissipation calculator Automotive lamps do not tolerate high voltages very well. the duration and number of activation cycles must be limited Tests of a few lamps indicated that failures can occur when with a dedicated MCU fault management using the fault 18V is applied for a few seconds. Consequently, PWM reporting through SPI. switching allows to reduce the effective RMS voltage in order to drive bulbs safety. The "Vbatt PWM" threshold determines SHAFFNER TESTS the transition between the fully-on and PWMing modes. The MC33888 device is protected in case of positive and For example, to maintain the power dissipation associated negative transients on VPWR and the output lines (HS[0:3] with a 13V battery at 100% duty cycle, the duty cycle would and LS[4:11]) per ISO 7637-2 standard. be adjusted to (13/18), or 52%, when the battery is at 18V. The following characterization has been done without The loads must be chosen in order to guarantee the device decoupling capacitors and for HS1 resistive load=2.5 and normal operating condition as junction temperature from -40 HS3 resistive load=3. to 150 C. In case of permanent current limitation conditions, Table 11. Results of Fast Transient Pulses on VPWR
Pulses on VPWR Pulse 1 Ri = 10 5000 occurrences Pulse 2a Ri = 2 5000 occurrences Pulse 3a Ri = 50 Duration 1 hour Pulse 3b Ri = 50 Duration: 1 hour Pulse 5a Ri = 2 (Load dump) 50 pulses Pulse 5b Ri = 2 (Load dump) 50 pulses HS1 & 3 ON state loaded PASS: -100V HS1 & 3 ON state open load PASS : -40V, FAIL : -50V PASS: +50V PASS: +42V , FAIL: +50V PASS: -150V PASS: +100V PASS: +42V PASS: +42V PASS: -150V PASS: +100V PASS: +42V PASS: +42V PASS: -150V PASS: +100V PASS: +42V PASS: +42V PASS: -150V PASS: +100V PASS: +42V PASS: +42V PASS: +50V HS1 & 3 OFF state loaded PASS: -100V HS1 & 3 OFF state open load PASS : -40V, FAIL: -50V PASS: +50V
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TYPICAL APPLICATIONS
Table 12. Rating of Fast Transient Pulses on VPWR
Test Pulse 1 1 2A 2A 3A 3B 5A 5B Test Level -100V -40V +50V +42V -150V +100V +42V +42v Clamped Rate D A D A A A A A Nb of pulses or test time 5000 for each config 5000 for each config 5000 for each config 5000 for each config 1h for each config 1h for each config 50 for each config 50 for each config Comment Failure in case of openload condition / Failure in case of openload condition for high-side `on' / / / When outputs are on, the load dump reset it When outputs are on, the load dump reset it
Rate signification: A: Device fully operational after test without any degradation. B: One or more function is (are) unavailable during the test and good after C: One or more function is (are) unavailable during the test and after it. D: Device's damaged. Pulse on one output while others are open: Table 13. Results of Fast Transient Pulses on HS1 and HS3
Pulse on high-side output Pulse 1 Ri = 10, 5000 occurrences HS1 PASS: -100 V HS3 PASS: -100 V
Table 14. Results of Fast Transient Pulses on LS4 and LS5
Pulse on low-side output Pulse 2a Ri = 2, 5000 occurrences LS4 PASS: +50 V LS5 PASS: +50 V
Table 15. Rating of Fast Transient Pulses on HS1, HS3, LS4, and LS5
Test pulse 1 2A Test Level -100V +50V Rate A A Nb of pulses or test time 5000 for each config 5000 for each config Comment / /
Rate signification: A: Device fully operational after test without any degradation. B: One or more function is (are) unavailable during the test and good after C: One or more function is (are) unavailable during the test and after it. D: Device's damaged.
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PACKAGING PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the "98A" listed below.
PNB SUFFIX APNB SUFFIX 36-PIN NON-LEADED PACKAGE 98ARL10544D ISSUE E 33888
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PACKAGING PACKAGE DIMENSIONS
PNB SUFFIX APNB SUFFIX 36-PIN NON-LEADED PACKAGE 98ARL10544D ISSUE E
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PACKAGING PACKAGE DIMENSIONS
FB SUFFIX 64-PIN PLASTIC PACKAGE 98ARH99043A ISSUE D
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PACKAGING PACKAGE DIMENSIONS
FB SUFFIX 64-PIN PLASTIC PACKAGE 98ARH99043A ISSUE D
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
ADDITIONAL DOCUMENTATION
THERMAL ADDENDUM (REV 2.0)
Introduction This thermal addendum is provided as a supplement to the MC33888 technical datasheet. The addendum provides thermal performance information that may be critical in the design and development of system applications. All electrical, application, and packaging information is provided in the datasheet. Packaging and Thermal Considerations This package is a dual die package. There are two heat sources in the package independently heating with P1 and P2. This results in two junction temperatures, TJ1 and TJ2, and a thermal resistance matrix with RJAmn. For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference temperature while only heat source 1 is heating with P1. For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the reference temperature while heat source 2 is heating with P2. This applies to RJ21 and RJ22, respectively.
33888PNB
36-PIN PQFN
PNB SUFFIX 98ARL10544D 36-PIN PQFN 14 mm x 14 mm Note For package dimensions, refer to the 33888 device data sheet.
TJ1 TJ2
=
RJA11 RJA12 RJA21 RJA22
.
P1 P2
The stated values are solely for a thermal performance comparison of one package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a package in an application-specific environment. Stated values were obtained by measurement and simulation according to the standards listed below. Standards Table 16. Thermal Performance Comparison
1 = Power Chip, 2 = Logic Chip [C/W] Thermal Resistance JAmn (1), (2) JAmn
(1), (2)
m = 1, n=1 19 6.0 37 <1
m = 1, n = 2 m = 2, n = 1 18 5.0 36 0
m = 2, n=2 20 6.0 37 1 0.2 * All measurements are in millimeters 0.2 1.0 1.0
JAmn (1), (2) JAmn (1), (2)
Notes 1. Per JEDEC JESD51-2 at natural convection, still air condition. 2. 2s2p thermal test board per JEDEC JESD51-7and JESD51-5. 3. Per JEDEC JESD51-8, with the board temperature on the center trace near the power outputs. 4. Single layer thermal test board per JEDEC JESD51-3 and JESD51-5. 5. Thermal resistance between the die junction and the exposed pad, "infinite" heat sink attached to exposed pad.
Note: Recommended via diameter is 0.5 mm. PTH (plated through hole) via must be plugged / filled with epoxy or solder mask in order to minimize void formation and to avoid any solder wicking into the via.
Figure 14. Surface Mount for Power PQFN with Exposed Pads
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ADDITIONAL DOCUMENTATION THERMAL ADDENDUM (REV 2.0)
33888 Pin Connections 36-Pin PQFN 0.8 mm Pitch 12.0 mm x 12.0 mm Body
Figure 15. Thermal Test Board Device on Thermal Test Board Material: Single layer printed circuit board FR4, 1.6 mm thickness Cu traces, 0.07 mm thickness 80 mm x 100 mm board area, including edge connector for thermal testing Cu heat-spreading areas on board surface Natural convection, still air Table 17. Thermal Resistance Performance
1 = Power Chip, 2 = Logic Chip (C/W) Thermal Resistance JAmn Area A (mm2) 0 300 600 m = 1, n=1 37 29 28 m = 1, n = 2 m = 2, n = 1 36 29 27 m = 2, n=2 37 30 29
Outline:
Area A: Ambient Conditions:
JA is the thermal resistance between die junction and ambient air. This device is a dual die package. Index m indicates the die that is heated. Index n refers to the number of the die where the junction temperature is sensed.
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40
Thermal Resistance [C/W]
30
20
x
JA11 JA22 JA12 = JA21
10
0 0 300 Heat Spreading Area A [mm] 600
Figure 16. Device on Thermal Test Board RJA
100
Thermal Resistance [C/W]
x
10
JA11 JA22 JA12 = JA21
1
0.1 1.00E-03
1.00E-02
1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04
Time[s]
Figure 17. Transient Thermal Resistance JA, 1W Step Response, Device on Thermal Test Board Area A = 600 (mm2)
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REVISION HISTORY
REVISION HISTORY
REVISION 5.0
DATE 7/2006
DESCRIPTION OF CHANGES
* * * * * * * * *
6.0
2/2007
*
Implemented Revision History page Converted to Freescale format and updated to the prevailing form and style Added Thermal Addendum Added last sentence to Open Load Fault on page 21 Added Fault Reporting Description, following Table 10. Serial Output Bit Assignment on page 25 Made numerous changes and description additions to Typical Applications on page 28 Removed Part Number MC33888PNB/R2 from Ordering Information Block on page 1. Added Shaffner information and tables to the Typical Applications section of the data sheet, beginning on page 28. Added titles to Table 11 - Results of Fast Transient Pulses on VPWR on page 29, Table 12 - Rating of Fast Transient Pulses on VPWR on page 30, Table 13 - Results of Fast Transient Pulses on HS1 and HS3 on page 30, Table 14 - Results of Fast Transient Pulses on LS4 and LS5 on page 30, and Table 15 - Rating of Fast Transient Pulses on HS1, HS3, LS4, and LS5 on page 30 Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from Maximum Ratings table on page 9. Added note with instructions from www.freescale.com.
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REVISION HISTORY
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