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FEDL70Q5111LA-01
Semiconductor 1 ML70Q5111LA
Bluetooth Baseband Controller IC
This version: December 2001
GENERAL DESCRIPTION
The ML70Q5111LA is a CMOS digital IC for use in 2.4 GHz band BluetoothTM systems. This IC incorporates the ARM7TDMI as the CPU core, features a highly expandable architecture, and supports the interfaces for a variety of applications. Used in conjunction with the ML7050LA (Bluetooth RF Transceiver IC) and the OKI Bluetooth Protocol Stack Software, data/voice communications are possible while maintaining interconnectivity with other Bluetooth systems. Also this IC is equiped with 4 Mbit Flash ROM to reduce the external parts.
FEATURES
* * * * * * * * * * * * Compliant to Bluetooth Specification (Ver. 1.1) The ARM7TDMI is installed as the CPU (operation at a maximum of 32 MHz in this LSI) 1-Ch, 16-bit auto-reload timer 3-Ch, 18-bit auto-reload timer Interrupt controller (17 causes) Built-in 8 kbyte, 4-Way Unified Cache Built-in 32 kbyte Up to a total of 2 Mbyte of SRAM, ROM, and Flash ROM can be connected to the external memory bus. Built-in 4Mbit Flash ROM - Endurance 104 cycles Selectable master clock (12/13/16 MHz). PCM-CVSD transcoder is installed. Installed interfaces: - UART(*) interface (Up to 921.6 Kbps) - USB(*) interface (conforms to USB1.1) - UART/synchronous serial port interface - General-purpose I/O interface (programmable interrupts) - PCM interface (PCMLinear/A-law/-law can be selected) - JTAG interface (*) This mark indicates interfaces that support the HCI command. Built-in Regulator and Power-on-Reset Single power supply voltage: 3.0 to 3.6 V Package: 144-pin BGA (P-LFBGA144-1111-0.80-MC) (Dimensions: 11 mm x 11 mm x 1.5 mm; pin pitch: 0.8 mm)
* * *
ARM and ARM7TDMI are registered trademarks of ARM Ltd., UK. Thumb is trademark of ARM Ltd., UK. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc. and licensed to Oki Electric Industry. The information contained herein can change without notice owing to the product being under development.
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FEDL70Q5111LA-01
1 Semiconductor
ML70Q5111LA
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage Allowable power dissipation Storage temperature Symbol VDD VI Pd Tstg Conditions -- -- -- -- Rating -0.3 to +4.5 -0.3 to +4.5 1.35 -55 to 150 Unit V V W C
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage "H" level input voltage "L" level input voltage Operating temperature Symbol VDD Vih Vil Ta Conditions -- -- -- -- Min. 3.0 2.2 0 -40 Typ. 3.3 -- -- -- Max. 3.6 3.6 0.8 85 Unit V V V C
INTERNAL FLASH ROM PROGRAMMING CONDITIONS
Parameter Supply voltage Operating temperature Symbol VDD Ta Conditions -- During Read During Programming Min. 3.0 -40 0 Typ. 3.3 -- -- Max. 3.6 85 85 Unit V C C
ELECTRICAL CHARACTERISTICS
DC Characteristics(1) (Except USB port)
(VDD = 3.3 V 0.3 V, Ta = -40 to 85C) Parameter "H" level output voltage "L" level output voltage Input leak current Output leak current Power supply current (during operation) Power supply current (during stand-by) Symbol Voh Vol Ii Io Iddo Idds Conditions Ioh = -2 mA Iol = 2mA Vi = GND to 3.6 V Vo = GND to VDD During 32 MHz operation CLK Stopped Min. 2.4 -- -10 -10 0 -- Typ. -- -- -- -- 70 200 Max. -- 0.4 10 10 90 800 Unit V V A A mA A
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FEDL70Q5111LA-01
1 Semiconductor DC Characteristics(2) USB port (D+, D-)
ML70Q5111LA
Parameter Differential input sensitivity Differential common mode range
Single ended receiver threshold
Symbol VDI VCM VSE VOH VOL ILO
Conditions {(D+) - (D-)} Includes VDI -- 15 K to GND 1.5 K to 3.6 V 0 V < VIN < VDD
(VDD = 3.3 V 0.3 V, Ta = -40 to 85C) Min. Typ. Max. Unit 0.2 0.8 0.8 2.8 -- -10 -- -- -- -- -- -- -- 2.5 2.0 3.6 0.3 +10 V V V V V A
"H" output voltage "L" output voltage Output leakage current
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FEDL70Q5111LA-01
1 Semiconductor
ML70Q5111LA
PIN PLACEMENT
1 NC A PLL_LE B RX_ POW C PLL_ OFF D PLL_ CLK E RXD F VDD G CIO15 H CIO12 J CIO9 K CIO6 L CIO4 M NC N
2 PLL_PS
3 PLL LOCK
4 GND MWE
5 MRE
6 GND
7 D-
8 TEST_L
9
10
11
12
13 NC
SCLK FSEL0 TXCSEL AGND1 TEST_L SCLK SEL GND TMS
RXC
TEST_L PLL_ POW TX_ POW RSSI_ CLK
TEST TEST_L TEST_L RESET BBWSEL PU _OUT MCS1 VDD GND TEST_L VTM
TCK
TXD
MCS0
TEST_L AVDD1
GND
TRST
PLL_ DATA GND
TEST_H RESET
D+
TEST_L TEST_L
SCLK REMAP0 XCLK FSEL1
VDD
SCLK
LVDD
REGVBG AGND0 REGVDD AVDD0
TXC_IN
GND
RSSI
GND
REMAP1REGOUT
REG GND MOE0
PCM OUT
PCMCLK PCMIN
MBS0
MOE1
GND
TDO
PCM SYNC
TDI
MBS1
VDD
MD0
GND
GND
CIO11
CIO14
MD1
MD4
VDD
MD2
CIO13
CIO10
CIO7
MA15
MA11
VDD
MA6
MA3
MD13
MD7
MD3
MD5
CIO8
CIO2
CIO0
MA17
GND
MA9
MA7
MA0
VDD
MD9
MD6
MD8
CIO5
MA19
MA16
MA14
MA12
MA10
GND
MA5
MA2
MD14
MD11
MD10
CIO3
CIO1
MA18
GND
MA13
MA8
MA4
MA1
MD15
MD12
GND
NC
TOP VIEW
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1 Semiconductor
ML70Q5111LA
PIN DESCRIPTIONS
RF I/F
Pin Name TXD RXD PLL_DATA PLL_CLK PLL_LE PLL_OFF PLL_POW TX_POW RX_POW RSSI RSSI_CLK PLL_PS PLLLOCK RXC Direction [*0] O I O O O O O O O I O O I O Internal Pull Up/Down -- -- -- -- -- -- -- -- -- Pull down -- -- Pull down -- Initial Value L -- L L L L H H H -- H L -- L Pin Placement C2 F1 D2 E1 B1 D1 C3 D3 C1 F4 E3 A2 A3 B2 Description Transmit data output (To ML7050LA Pin# A8) Receive data input (To ML7050LA Pin# H5) PLL setting data output (To ML7050LA Pin# H3) PLL setting clock output (To ML7050LA Pin# G3) PLL setting load enable output (To ML7050LA Pin# H4) PLL Open-loop/Closed-loop control signal output (To ML7050LA Pin# G8) Local transmit circuit power control signal output (To ML7050LA Pin# A7) Transmit power control signal output (To ML7050LA Pin# B6) Receive power control signal output (To ML7050LA Pin# B3) Receive field strength data input RSSI transfer clock PLL power control signal output PLL lock signal input Bluetooth receive clock output (1 MHz) Bluetooth transmit clock input (1 MHz) TXC_IN I Pull down -- F2 When the transmit clock is used by a clock (RXC) that is generated from the receive data, set TXCSEL(Pin# A10) to H and connect to RXC(Pin# B2). Bluetooth transmit clock setting pin TXCSEL I Pull down -- A10 L: Select 1 MHz divided by internal PLL. H: Select TXC_IN input signal.
[*0]
"I" = Input, "O" = Output, "I/O" = Input/Output, "Oc" = Open Collector
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FEDL70Q5111LA-01
1 Semiconductor CLK and Configuration
Pin Name SCLK XCLK SCLKSEL Direction I I I Internal Pull Up/Down -- -- Pull down Initial Value -- -- -- Pin Placement D13 D11 B10 Description
ML70Q5111LA
Master clock (12, 13 or 16 MHz) input pin (Power level: CMOS level) User clock input pin System clock select pin L: Select CLK divided by internal PLL H: Select XCLK input signal Master clock select pin SCLKFSEL[1:0] = "00" : 12 MHz "01" : 13 MHz "10" : 16 MHz "11" : Forbidden Hardware reset pin (Reset = L) Hardware reset pin (Reset = L), Output BANK0 region bit width select pin L: 8-bit H: 16-bit REMAP select pin during boot up REMAP[1:0] = "00" Forbidden "01" Stacked Flash ROM "10" External MCS1 device "11" External MCS0 device
SCLKFSEL0 SCLKFSEL1 RESET RESET_OUT BBWSEL
I I I O I
Pull down Pull down -- -- Pull down
-- -- -- -- --
A9 D9 D5 B9 B8
REMAP0 REMAP1
I I
-- --
-- --
D10 F11
Memory I/F
Pin Name MA[19:0] MD[15:0] MWE MRE MCS0 MCS1 MBS0 MBS1 MOE0 MOE1 Direction O I/O O O O O O O O O Internal Pull Up/Down -- Pull up -- -- -- -- -- -- -- -- Initial Value L -- H H H H H H H H Pin Placement [*1] [*2] B4 A5 C4 C5 G10 H10 G13 G11 Description External address bus External data bus External write enable signal output External read enable signal output External space 0 chip select External space 1 chip select External lower byte select External upper byte select External MCS0 device output enable (MCS0 and MRE OR output) External MCS1 device output enable (MCS1 and MRE OR output)
[*1]
MA19: M3; MA18: N4; MA17: L5; MA13: N6; MA12: M6; MA11: K6; MA6: K8; MA5: M9; MA4: N8;
MA16: M4; MA15: K5; MA14: M5 MA10: M7; MA9: L7; MA8: N7; MA3: K9; MA2: M10; MA1: N9;
MA7: L8 MA0: L9
[*2]
MD15: N10; MD14: M11; MD13: K10; MD12: N11; MD11: M12; MD10: M13 MD9: L11; MD8: L13; MD7: K11; MD6: L12; MD5: K13; MD4: J11; MD3: K12; MD2: J13; MD1: J10; MD0: H12
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1 Semiconductor
ML70Q5111LA
USB I/F
Pin Name D+ D- VBUS (GPIO0) Direction I/O I/O I Internal Pull Up/Down -- -- -- Initial Value Z Z -- Pin Placement D6 A7 L4 USB data USB data USB detection pin Description
UART I/F
Pin Name SOUT SIN DCD RTS CTS DSR DTR RI Direction O I I O I I O I Internal Pull Up/Down -- -- -- -- -- -- -- -- Initial Value H -- -- H -- -- H -- Pin Placement H1 J4 K2 J1 J3 K3 K1 L2 Description ACE transmit serial data (Pin shared with GPIO15) ACE receive serial data (Pin shared with GPIO14) Data carrier detection (Pin shared with GPIO13) ACE transmit data ready (Pin shared with GPIO12) ACE transmit ready (Pin shared with GPIO11) Receive data ready (Pin shared with GPIO10) Receive ready (Pin shared with GPIO9) Ring indicator (Pin shared with GPIO8)
SIO I/F
Pin Name STXD SRXD STDCLK SRDCLK Direction O I I/O I/O Internal Pull Up/Down -- -- -- -- Initial Value H -- -- -- Pin Placement K4 L1 M2 M1 Description Serial data output (Pin shared with GPIO7) Serial data input (Pin shared with GPIO6) Clock for serial data output (Pin shared with GPIO5) During initialization: input Clock for serial data input (Pin shared with GPIO4) During initialization: input
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FEDL70Q5111LA-01
1 Semiconductor PLAT_SIO I/F
Pin Name UTXD URXD Direction O I Internal Pull Up/Down -- -- Initial Value H -- Pin Placement N2 L3
ML70Q5111LA
Description Serial data output (Pin shared with GPIO3) Serial data input (Pin shared with GPIO2)
GPIO I/F
Pin Name GPIO[15:0] Direction I/O Internal Pull Up/Down -- Initial Value -- Pin Placement [*3] Description Parallel I/O data During initialization: input
JTAG I/F
Pin Name TDI TDO TRST TMS TCK Direction I O I I I Internal Pull Up/Down Pull down -- Pull down Pull down Pull down Initial Value -- L -- -- -- Pin Placement H4 H2 C13 B12 B13 Description Serial data input Serial data output Reset pin Mode setting pin Serial data clock
PCM I/F
Pin Name PCMOUT PCMIN PCMSYNC Direction O I I/O Internal Pull Up/Down -- Pull down Pull down Initial Value L -- -- Pin Placement G2 G4 H3 Description PCM data output PCM data input PCM sync signal (8 kHz) During initialization: input (can be switched by an internal register) PCM clock (64 kHz/128 kHz) During initialization: input (can be switched by an internal register)
PCMCLK
I/O
Pull down
--
G3
[*3]
CIO15: CIO14: CIO13: CIO12: CIO11: CIO10: CIO9: CIO8: CIO7: CIO6: CIO5: CIO4: CIO3: CIO2: CIO1: CIO0:
H1 J4 K2 J1 J3 K3 K1 L2 K4 L1 M2 M1 N2 L3 N3 L4
GPIO15/SOUT (UART I/F) GPIO14/SIN (UART I/F) GPIO13/DCD (UART I/F) GPIO12/RTS (UART I/F) GPIO11/CTS (UART I/F) GPIO10/DSR (UART I/F) GPIO9/DTR (UART I/F) GPIO8/RI (UART I/F) GPIO7/STXD (SIO I/F) GPIO6/SRXD (SIO I/F) GPIO5/STXDCLK (SIIO I/F) GPIO4/SRXDCLK (SIO I/F) GPIO3/UTXD (PLAT_SIO I/F) GPIO2/URXD (PLAT_SIO I/F) GPIO1 GPIO0/VBUS (USB I/F) 8/26
FEDL70Q5111LA-01
1 Semiconductor TEST I/F
Pin Name TEST_L TEST_H TEST_PU VTM NC Direction I I Oc I -- Internal Pull Up/Down -- -- -- -- -- Initial Value -- -- L -- -- Pin Placement [*4] D4 B5 C9 A1, A13, N1, N13 Test pin (input) Test pin (input) Test monitor pin Test pin No Connection
ML70Q5111LA
Description
Power, GND
Pin Name VDD LVDD GND AVDD0 AVDD1 AGND0 AGND1 REGVDD REGGND REGOUT REGVBG Direction -- -- -- -- -- -- -- -- -- -- -- Internal Pull Up/Down -- -- -- -- -- -- -- -- -- -- -- Initial Value -- -- -- -- -- -- -- -- -- -- -- Pin Placement [*5] E4 [*6] E13 C11 E11 A11 E12 F13 F12 E10 Description I/O power pin 3.3 V 0.3 V I/O power pin 3.3 V 0.3 V (Same voltage to the VDD for ML7050LA) Digital block ground pin Analog block power pin 2.5 V 0.25 V (Connect to REGOUT pin: F12) Analog block ground pin (Connect to REGGND pin: F13) Regulator power pin (3.0 to 3.6 V) Regulator ground pin Regulator output Regulator reference voltage tuning
[*4]
[*5] [*6]
TEST_L (TEST5): A8 TEST_L (TEST4): D8 TEST_L (TEST3): C8 TEST_L (TEST2): B7 TEST_L (TEST1): D7 TEST_L (TEST0): B6 TEST_L (PLLSEL): C10 TSET_L (PLLEN): A12 TSET_L (SVCO1): B3 C6, G1, K7, J12, H11, D12, L10 B11, C7, A6, A4, E2, F3, J2, N5, L6, M8, N12, H13, G12, F10, C12
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FEDL70Q5111LA-01
1 Semiconductor
ML70Q5111LA
REFERENCE FOR VOLTAGE SUPPLY CIRCUIT
ML70Q5111LA
REGVDD REG_VBG REGOUT 10 REGGND AVDD0 0.1 AGND0 AVDD1 0.1 AGND1 0.018 1
VDD GND 10 10 0.1 0.1
VDD GND
Capacitors shold locate close to LSI pins. Unit: F
Feed lines should be separated from LSI pins.
Example for ML70Q5111LA voltage supply circuit
The circuit is subject to change according to the specific LSI board design. Please contact Oki Electric Industry Co., Ltd. for detailed information.
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1 Semiconductor
BLOCK DIAGRAM
SIO I/F
CLK GEN AMBA APB
Default Slave 16 I/F AMBA AHB I/F APB Ctl I/F I/F AMBA APB I/F USB GPIO I/F SIO I/F I/F I/F I/F UART I/F I/F CTL/ WDT 3ch TIMER IRC Arbiter TIC ARM7 TDMI Cache/ Bus I/F 4 Mbit Flash ROM
Clock 32 kB RAM Timer SIO APB Ctl System Control XMC(BIU)
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I/F I/F PCM/ CVSD BT-BB Core SIO I/F USB I/F GPIO I/F UART I/F PCM Codec
8 Mbit SRAM
8 Mbit Flash ROM
ML70Q5111LA
RFLSI
FEDL70Q5111LA-01
ML70Q5111LA
FEDL70Q5111LA-01
1 Semiconductor
ML70Q5111LA
DESCRIPTION OF INTERNAL BLOCKS
CLKGEN Block * Generates from the SCLK (12/13/16 MHz) clock that is supplied to each block * STOP/HALT function * External clock selection function CTL/WDT Block * * * * * * * * Control of the frequency division function of the internal main clock Control of clock supplied to each peripheral Control of reset of each peripheral STOP/HALT control External clock selection control CIO switching function Watchdog timer function (interrupt/reset) 3 types of count stop functions
Timer Block * * * * 3 channels 18 bit timer counter for each channel Iterrupt at counter overflow Independent mode for each channel (one shot/interval/free run)
Baseband Core Block
RF LSI Tx SCO Buffer Audio Codec I/F Tx ACL Buffer Packet Composer TXD
Security APB ARM I/F Rx SCO Buffer Rx ACL Buffer
Timing
FHCNT
RF CNT
CNT
Packet Decomposer
RXD
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FEDL70Q5111LA-01
1 Semiconductor
ML70Q5111LA
* RF Controller - RF power supply control (PLL, TX, RX) - Local PLL frequency division ratio setting - Receive clock regeneration function - Synchronization detection (synchronizing within the permissable error limit of SyncWord) - Receive clock re-timing function * FH Controller hopping - Sequence control - Frequency hopping selection function - CRC computation's initial value selection function * Timing Generator - Bluetooth clock generation - Operation interrupts depend on mode (slot, scan, sniff, hold, park) - Sync detection timing generation (sync window 10 s) - PLL setting timing generation - Transmit/Receive timing generation - Multi-master timing management function * Packet Composer - Access code generation (SyncWord generation, appending PR*TRAILER) - Packet header generation (HEC generation, scrambling, FEC encoding) - Payload generation (CRC generation, encryption, scrambling, FEC encoding) - Packet synthesis * Packet Decomposer - Packet decomposition (separating the packet header and the payload) - Packet header processing (FEC decoding, descrambling, HEC error detection, header information separation) - Payload processing (FEC decoding, descrambling, encryption decoding, CRC judgement, payload separation) * Security - Various key generation functions (initialization, link key, encryption key) - Certification function - Encryption function
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FEDL70Q5111LA-01
1 Semiconductor
ML70Q5111LA
USB Block * Conforms to USB standard Ver. 1.1. * Supports 12 Mbps transfer * Supports 4 data transfer types (control transfer, bulk transfer, interrupt transfer, and isochronous transfer) * Built-in USB transceiver circuit * 5 or 6 built-in end points, and built-in FIFO for data storage * 8-, 16-, 32-bit read/write is possible for the FIFOs of EP0 to EP5 (with byte control) UART Block * * * * * * * * * * Full-duplex buffering method All status reporting function Built-in 64-byte transmit/receive FIFO Modem control based on CTS, DCD, and DSR Programmable serial interface 5-, 6-, 7-, 8-bit characters Generation and verification of odd parity, even parity, or no parity 1, 1.5, or 2 stop bits Programmable Baud Rate Generator (1200 bps to 921.6 kbps) Error servicing for parity, overrun, and framing errors
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FEDL70Q5111LA-01
1 Semiconductor SIO Block * UART/Synchronous type serial port interface * UART Mode: - Data length: can be selected as 7 or 8 bits - Supports odd parity, even parity, or no parity - Error servicing for parity, overrun, and framing errors - Supports 1 or 2 stop bits - Full-duplex communication is possible * Clock synchronization mode: - Data length: can be selected as 7 or 8 bits - Error servicing for overrun errors - Full-duplex communication is possible PLAT-SIO Block * * * * * * * Start-stop synchronization type serial port interface Built-in dedicated baud rate generator Data length of 7 or 8 bits can be selected 1 or 2 stop bits can be selected. Supports odd or even parity Error servicing for parity, overrun, and framing errors Full-duplex communication is possible
ML70Q5111LA
PCM-CVSD Transcoder Block * Application side I/O: - PCM Codec - APB-Bus (USB) * Application-side format: - PCM linear (8, 16 bits/sample, 64 kHz sampling frequency)/A-law/-law * Bluetooth-side format: - CVSD/A-law/-law * All combinations of the above conversions are supported * PCMSYMC/PCMCLK I/O can be switched (in the input state after initialization) GPIO Block * * * * * All 16 bits Input/Output selection possible for each bit Interrupts can be used for all bits Interrupt masks and interrupt modes can be set for all bits In the input state immediately after a reset
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FEDL70Q5111LA-01
1 Semiconductor
ML70Q5111LA
APPLICATION NOTES
Operation During Boot Up * Remapping during boot up is performed according to external pins REMAP[1:0]. REMAP1 L L H H REMAP0 L H L H : : : : Forbidden Stack Flash ROM Devices connected to external MCS1 Devices connected to external MCS0
* Bit width that corresponds to BANK0 during boot up is set according to external pin BBWSEL. BBWSEL = L : BBWSEL = H : Clock Selection * The CPU clock supply source is selected according to external pin SCLKSEL. SCLKSEL = L : Use 32/16/8/4 MHz clock that was divided down from the internal PLL output of 192 MHz that was generated from external pin SCLK. (Initial value is 32 MHz.) Use external pin XCLK. 8-bit 16-bit
SCLKSEL = H :
Note: The clock supply source can also be set by the CLKCNT register in the CTL/WDT block. * Bluetooth transmission clock is selected according to external pin TXCSEL. TXCSEL = L : MHz). TXCSEL = H : Use 1 MHz clock that was divided down from the internal PLL output (192 Use external pin TXC_IN.
Note: This clock can also be set by the CLKCNT register in the CTL/WDT block. * SCLK selection (12/13/16 MHz). SCLKFSEL[1:0] = "00" : 12 MHz "01" : 13 MHz "10" : 16 MHz "11" : Forbidden HCI Transport Selection * HCI is selected (USB/UART) according to the logical value of GPIO0 at initial powerup of ML70Q5111LA. GPIO0 = L GPIO0 = H : : UART is used as HCI. USB is used as HCI.
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FEDL70Q5111LA-01
1 Semiconductor USB Peripheral Circuit * Please contact Oki Electric Industry Co., Ltd. when using USB.
ML70Q5111LA
Setting the UART Baud Rate * Use the HCI_VS_Set_LC_Parameters command of the Vendor Specific Commands to set the UART baud rate. Available baud rate settings: 1200/2400/4800/7200/9600/19.2K/38.4K/56K/57.6K/115.2K/230.4K/345.6K/460.8K/921.6K (Initial value is 115.2 kbps.) Setting the PCM-CVSD Transcoder * Please use the HCI_VS_Set_LC_Parameters command of the Vendor Specific Commands in HCI to set the PCM-CVSD transcoder parameters. * It is possible to set the following parameters using the VCCTL command: - PCMSYNC/PCMCLK mode (in the input state after initialization) - Mute reception (initial setting: OFF) - Mute transmission (initial setting: OFF) - Air coding CVSD (initial setting)/-law/A-law - Interface coding Linear (initial setting)/-law/A-law - PCM format (data width of one PCM Linear sample) 8-bit (initial setting)/14-bit/16-bit - Serial interface format Short frame (initial setting)/long frame - Application interface mode PCM Codec I/F (initial setting)/APB I/F
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FEDL70Q5111LA-01
1 Semiconductor External Memory * ML70Q5111LA specifications for the devices that are connected to MCS0 and MCS1 are explained below. * When the device is connected to MCS0: - 1 memory bank - Bus width: 8 or 16 bits - Byte access control: MBS*/MWE - Supported devices: Normal SRAM, Flash Memory, Page mode Flash memory Bus timing to the device connected to MCS0
MRE MWE XA MCS0 MBS* XD_I (read) XD_O (write) 1 or 2 clocks [*1] [*2] 1 or 2 clocks 1 clock fixed [*1]
ML70Q5111LA
[*1]
[*2]
Access time: 3, 4, 5, 6, 7, 8 clock cycles (including 1 clock cycle for set-up) 6, 8, 10, 12, 14, 16 clock cycles (including 2 clock cycles for set-up) Data OFF time: 1, 2, 3, 4 clock cycles
Note: Oki software settings: - Insert the maximum wait immediately after reset. - Page mode: OFF - During operation (32 MHz operation), Access time: 3 clock cycles Data OFF time: 1 clock cycle Note: A device with an access time of 120 nsec or less is recommended.
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FEDL70Q5111LA-01
1 Semiconductor * When the device is connected to MCS1: - 1 memory bank - Bus width: 8-bit or 16-bit - Byte access control: MBS*/MWE Bus timing to the device connected to MCS1 (IOWRTYPE = 0)
MRE MWE XA MCS1 MBS* XD_I (read) XD_O (write) [*3] [*1] [*2] [*3] [*1]
ML70Q5111LA
1 clock fixed
Bus timing to the device connected to MCS1 (IOWRTYPE = 1)
MRE MWE XA MCSn1 MBS* XD_I (read) XD_O (write) [*1] [*3] [*2] 1 clock fixed 1 clock fixed [*3] [*4] [*1]
[*1] [*2] [*3] [*4]
Access time: 2, 4, 8, 16, 32 clock cycles (including 1 clock cycle for set-up) Data OFF time: 1, 2, 3, 4 clock cycles Address set-up time: 1, 2, 3, 4 clock cycles Write data set-up time: 0 clock cycles (IOWRTYPE = 0) 0, 1, 2, 3 clock cycles (IOWRTYPE = 1)
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FEDL70Q5111LA-01
1 Semiconductor Relationship between address set-up time and write data set-up time (when IOWRTYPE = 1) - Address set-up time: 1 clock cycle (write data set-up: 0 clock cycles) 2 clock cycles (write data set-up: 1 clock cycle) 3 clock cycles (write data set-up: 2 clock cycles) 4 clock cycles (write data set-up: 3 clock cycles) Note: Oki software settings: - Insert the maximum wait immediately after reset. - IOWRTYPE = 0 - During operation (32 MHz operation), Access time: 2 clock cycles Data OFF time: 1 clock cycle Address set-up time: 1 clock cycle Note: A device with an access time of 120 nsec or less is recommended. * Miscellaneous - MA0 is not used with devices that have a 16-bit data bus. Connect MA1 to device A0. (MA0 is Open.) - Connect MA0 to device A0 for devices that have an 8-bit data bus. - MOE0 is the AND signal for MCS0 and MRE. Perform an open process when this is not in use. - MOE1 is the AND signal for MCS1 and MRE. Perform an open process when this is not in use.
ML70Q5111LA
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FEDL70Q5111LA-01
1 Semiconductor Process when interface pins are unused
ML70Q5111LA
* The following tables show the processes that are performed when interface pins are not used. RF I/F
Pin Name PLL_DATA PLL_CLK PLL_LE PLL_OFF PLL_POW TX_POW RX_POW RSSI RSSI_CLK PLL_PS PLLLOCK RXC TXC_IN TXCSEL Process When Pin Not Used Open Open Open Open Open Open Open Pull down or GND Open Open Pull down or GND Open Pull down or GND Pull down or GND Comments
GPIO
Pin Name GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 Process When Pin Not Used Pull up or VDD Pull down or GND Pull down or GND Pull up or VDD Pull down or GND Pull down or GND Pull up or VDD Pull up or VDD Pull up or VDD Pull up or VDD Pull down or GND Pull up or VDD Pull up or VDD Pull down or GND Pull up or VDD Pull up or VDD This process is not applicable when used as SOUT (UART I/F). This process is not applicable when used as RTS (UART I/F). This process is not applicable when used as DTR (UART I/F). This process is not applicable when used as STXD (SIO I/F). This process is not applicable when used as UTXD (PLAT SIO I/F). Comments This process is not applicable when used as VBUS (USB I/F).
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FEDL70Q5111LA-01
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ML70Q5111LA
Memory I/F
Pin Name Process When Pin Not Used Comments When connected For 16-bit devices: * Open MA0. * Connect from MA1 in order from A0 of the connected device. For 8-bit devices: * Connect to each corresponding address.
MA[19:0]
Open
MD[15:0] MWE MRE MCS0 MCS1 MBS0 MBS1 MOE0 MOE1
Open Open Open Open Open Open Open Open Open Only use when connecting to a device that has only one, but not both of MCS* or MRE.
USB I/F
Pin Name D+ D- VBUS (GPIO0) Process When Pin Not Used Open Open When using UART: Pull down or GND When using USB: Pull up or Vdd This process is not applicable when used as GPIO. Comments
UART I/F
Pin Name SOUT (GPIO15) SIN (GPIO14) DCD (GPIO13) RTS (GPIO12) CTS (GPIO11) DSR (GPIO10) DTR (GPIO9) RI (GPIO8) Process When Pin Not Used Open Pull up or VDD Pull down or GND Open Pull down or GND Pull down or GND Open Pull up or VDD This process is not applicable when used as GPIO. This process is not applicable when used as GPIO. Comments This process is not applicable when used as GPIO.
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FEDL70Q5111LA-01
1 Semiconductor SIO I/F
Pin Name STXD (GPIO7) SRXD (GPIO6) STDCLK (GPIO5) SRDCLK (GPIO4) Process When Pin Not Used Open Pull up or VDD Pull down or GND Pull down or GND
ML70Q5111LA
Comments This process is not applicable when used as GPIO.
PLAT_SIO I/F
Pin Name UTXD (GPIO3) URXD (GPIO2) Process When Pin Not Used Open Pull down or GND Comments This process is not applicable when used as GPIO.
JTAG I/F
Pin Name TDI TDO TRST TMS TCK Process When Pin Not Used Open Open Open Open Open Comments
PCM I/F
Pin Name PCMOUT PCMIN PCMSYNC PCMCLK Process When Pin Not Used Open Open Open Open Comments
Processes of Other Pins TEST I/F, etc.
Pin Name TEST_L TEST_H TEST_PU VTM RESET RESET_OUT NC Process When Pin Not Used GND VDD Open Open Pull up or VDD Open Open Comments
* The unused pin configurations are subject to change according to the specific application. Please contact Oki Electric Industry Co., Ltd. for detailed board layout information.
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FEDL70Q5111LA-01
1 Semiconductor
ML70Q5111LA
ABOUT BLUETOOTH SOFTWARE
* At Oki Electric Industry Co., Ltd., we have made available as Pack 1 the software protocol stack of the lower layer up to HCI that conforms to the Bluetooth Specification Ver. 1.1 for external Flash memory and internal Flash memory.Pack 1 contents: Baseband Controller, LMP, HCI. * Please contact Oki Electric Industry about upper software protocol stack above HCI. * Please contact Oki Electric Industry Co., Ltd. for more information regarding software contents, pricing, etc.
VENDOR SPECIFICCOMMANDS
* Parameters can be set with the Pack 1 software by using the following Vendor Specific Commands. * Please contact Oki Electric Industry Co., Ltd. for more information. (Command example) HCI_VS_Set_LC_Parameters: Sets the link control information.
The following table shows the link control information that can be set.
Link Control Information PCM for SCO Link 0: 2: UART baud rate 4: 6: 8: Poling rate Master clock setting for ML7050LA Comments 0: -law, 1: A-law, 2: Linear 9600 bps 38.4 kbps 115.2 kbps 345.6 kbps 460.8 kbps 1: 3: 5: 7: 9: 19.2 kbps 56 kbps 230.4 kbps 57.6 kbps 921.6 kbps
Unit: 625 sec 12: 12 MHz 13: 13 MHz 16: 16 MHz
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FEDL70Q5111LA-01
1 Semiconductor
ML70Q5111LA
PACKAGE DIMENSIONS
(Unit: mm)
P-LFBGA144-1111-0.80
5
Package material Ball material Package weight (g) Rev. No./Last Revised
Epoxy resin Sn/Pb 0.3 TYP. 1/Aug.25,1999
Caution regarding the installation of surface mounted type packages:
Surface mounted type packages are very susceptible to heat during reflow mounting and package moisture content when in storage. Therefore, please contact your Oki Electric Industry Co., Ltd. sales representative when considering reflow experiments and let us know the product name, package name, pin count, package code, the desired mounting conditions (reflow method, temperature, count), storage conditions, etc.
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1 Semiconductor
ML70Q5111LA
1.
NOTICE The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission.
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Copyright 2001 Oki Electric Industry Co., Ltd.
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