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OKI Semiconductor ML87V2105
PEDL87V2105DIGEST-02
Issue Date: Dec. 20, 2003
Preliminary
Video Signal Noise Reduction IC with a Built-in 5.6 Mbit Frame Memory
This document contains minimum specifications. For full specifications, please contact your nearest Oki office or representative.
GENERAL DESCRIPTION
The ML87V2105 comprises a 5.6 Mbit frame memory, a noise reduction filter, and a memory controller to reduce frame-recursive 3D noise in video signals. The motion adaptive noise reduction is performed between frames, between fields, or between lines, to reduce the afterimage particular to 3D noise reduction as far as possible, while achieving effective noise reduction. The ML87V2105 also features an automatic noise reduction mode that automatically detects the noise level in the input video data to set the optimum noise reduction. Because it is possible to select the same format for output as for input, the ML87V2105 can be introduced into an existing system, making it easy to achieve noise reduction.
FEATURES
* Built-in memory: Frame memory (4:1:1 data equivalent) x 1 unit * Maximum input and output operating frequencies (16 bits/8 bits, ITU-R BT.656): 14.75/29.5 MHz * Power supply voltage: 3.3 V 0.3 V * Input pin: LVTTL (3.3 V) * Output pin: LVCMOS (3.3 V) * Input data format: YCbCr (8 bits (Y) + 8 bits (CbCr) (4:2:2) + Sync.): 16-bit mode YCbCr (8 bits (YCbCr) (4:2:2) + Sync.): 8-bit mode ITU-R BT.656 (8 bits (YCbCr)): ITU-R BT.656 mode * Output data format: YCbCr (8 bits (Y) + 8 bits (CbCr) (4:2:2) + Sync.): 16-bit mode YCbCr (8 bits (YCbCr) (4:2:2) + Sync.): 8-bit mode (Selectable in 8-bit input mode) ITU-R BT.656 (8 bits (YCbCr)): ITU-R BT.656 mode (Selectable in input ITU-R BT.656) * Serial bus: I2C-bus interface: (Standard mode: 100 kbps/Fast mode: 400 kbps) * Internal memory controller: Compatible with 625/50 Hz 2:1, 525/60 Hz 2:1 Compatible horizontal effective pixels: 640 (525 line mode only), 720, 768 * Frame-recursive noise reduction: Frame-recursive noise detection and subtraction Auto mode noise reduction * Package: 100 pin TQFP (TQFP100-P-1414-0.50-K)(ML87V2105TB)
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ML87V2105
BLOCK DIAGRAM
YI0-7 CI0-7
x16
Input/Output Process Block + 3D NR
Frame Memory 5.6Mbits x16
YO0-7 CO0-7
OVS ICLK IVS IHS SCL SDA SLA1 SLA2 MODE0-2 TEST1-7 RESET Memory Controller OHS HREF CLKO I2C-bus I/F Register Control Signal
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ML87V2105
PIN CONFIGURATION (TOP VIEW)
RESET
TEST6
TEST7
CO7
CO6
CO5
CO4
CO3
CO2
CO1
52
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VDD 76 N.C. 77 VSS 78 N.C. 79 N.C. 80 N.C. 81 N.C. 82 N.C. 83 N.C. 84 N.C. 85 N.C. 86 TEST5 87 VDD 88 TEST4 89 TEST3 90 TEST2 91 TEST1 92 N.C. 93 N.C. 94 N.C. 95 TESTM 96 SELF 97 VSS 98 N.C. 99 VDD 100 YI4 10 YI3 11 YI2 12 YI1 13 YI0 14 VDD 15 ICLK 16 VSS 17 CI7 18 CI6 19 CI5 20 CI4 21 CI3 22 CI2 23 CI1 24 N.C. 1 VSS 2 SDA 3 SCL 4 SLA1 5 SLA2 6 CI0 25 YI7 7 YI6 8 YI5 9
51
CO0
YO7
YO6
YO5
YO4
YO3
YO2
YO1
YO0
N.C.
VDD
VDD
VSS
VSS
VSS
50 49 48 47 46 45 44 43 42 41 40
VDD N.C. VSS HREF OVS OHS N.C. N.C. N.C. N.C. VDD N.C. N.C. VSS VDD CLKO MODE2 N.C. MODE1 MODE0 IHS IVS VSS N.C. VDD
ML87V2105TB
(TQFP100-P-1414-0.50-K)
39 38 37 36 35 34 33 32 31 30 29 28 27 26
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PIN DESCRIPTIONS
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 Symbol N.C. VSS SDA SCL SLA1 SLA2 YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 VDD ICLK VSS CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 VDD N.C. VSS IVS IHS MODE0 MODE1 N.C. MODE2 CLKO VDD VSS N.C. N.C. I/O -- -- I/O I I I I I I I I I I I -- I -- I I I I I I I I -- -- -- I I I Pad Remarks Unused pin Ground Schmitt(IN)/ OpenDrain(OUT) Schmitt Internal pull-down 50k Internal pull-down 50k I2C-bus data pin I2C-bus clock pin Slave address setting pin Slave address setting pin Luminance signal input pin bit 7 (MSB) Luminance signal input pin bit 6 Luminance signal input pin bit 5 Luminance signal input pin bit 4 Luminance signal input pin bit 3 Luminance signal input pin bit 2 Luminance signal input pin bit 1 Luminance signal input pin bit 0 (LSB) Power supply 3.3 V Input system clock pin Ground Color difference signal input pin bit 7 (MSB) Color difference signal input pin bit 6 Color difference signal input pin bit 5 Color difference signal input pin bit 4 Color difference signal input pin bit 3 Color difference signal input pin bit 2 Color difference signal input pin bit 1 Color difference signal input pin bit 0 (LSB) Power supply 3.3 V Unused pin Ground Pin Description
Internal pull-down 50k Internal pull-down 50k Internal pull-down 50k Internal pull-down 50k Internal pull-down 50k Internal pull-down 50k Internal pull-down 50k Internal pull-down 50k
Schmitt Input system vertical sync signal input pin Internal pull-down 50k Schmitt Input system horizontal sync signal input pin Internal pull-down 50k Internal pull-down 50k Mode setting pin - bit 0 Mode setting pin - bit 1 Unused pin Mode setting pin - bit 2 Clock output (I2C-bus control possible) Power supply 3.3 V Ground Unused pin Unused pin
I Internal pull-down 50k -- I Internal pull-down 50k O/(I) -- -- -- --
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No. 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Symbol VDD N.C. N.C. N.C. N.C. OHS OVS HREF VSS N.C. VDD CO0 CO1 CO2 CO3 VSS CO4 CO5 CO6 CO7 VDD N.C. VSS YO0 YO1 YO2 YO3 VDD YO4 YO5 YO6 YO7 VSS TEST7 TEST6 RESET
I/O -- -- -- -- -- O O O -- -- -- O/(I) O/(I) O/(I) O/(I) -- O/(I) O/(I) O/(I) O/(I) -- -- -- O O O O -- O O O O -- I I I
Pad Remarks
Schmitt
Pin Description Power supply 3.3 V Unused pin Unused pin Unused pin Unused pin Horizontal sync signal output pin Vertical sync signal output pin Data output horizontal reference signal output pin Ground Unused pin Power supply 3.3 V Color difference signal output pin - bit 0 (LSB) Color difference signal output pin - bit 1 Color difference signal output pin - bit 2 Color difference signal output pin - bit 3 Ground Color difference signal output pin - bit 4 Color difference signal output pin - bit 5 Color difference signal output pin - bit 6 Color difference signal output pin - bit 7(MSB) Power supply 3.3 V Unused pin Ground Luminance signal output pin - bit 0 (LSB) Luminance signal output pin - bit 1 Luminance signal output pin - bit 2 Luminance signal output pin - bit 3 Power supply 3.3 V Luminance signal output pin - bit 4 Luminance signal output pin - bit 5 Luminance signal output pin - bit 6 Luminance signal output pin - bit 7 (MSB) Ground Test input pin - bit 7 (1: test mode) Test input pin - bit 6 (1: test mode) System reset/input pin 0: System reset 1: Operation
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ML87V2105
No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
Symbol VDD N.C. VSS N.C. N.C. N.C. N.C. N.C. N.C. N.C. N.C. TEST5 VDD TEST4 TEST3 TEST2 TEST1 N.C. N.C. N.C. TESTM SELF VSS
I/O -- -- -- -- -- -- -- -- -- -- -- I -- I I I I -- -- -- I I --
Pin Description Power supply 3.3 V Unused pin Ground Unused pin Unused pin Unused pin Unused pin Unused pin Unused pin Unused pin Unused pin Internal pull-down 50k Test input pin - bit 5 (1: test mode) Power supply 3.3 V Internal pull-down 50k Test input pin - bit 4 (1: test mode) Internal pull-down 50k Test input pin - bit 3 (1: test mode) Internal pull-down 50k Test input pin - bit 2 (1: test mode) Internal pull-down 50k Test input pin - bit 1 (1: test mode) Unused pin Unused pin Unused pin Internal pull-down 50k Memory test input pin (1: test mode) Internal pull-down 50k Self refresh setting pin (0: Self refresh stopped, 1: Self refresh operated) Ground
Pad Remarks
Notes: Keep the test mode pins fixed to 0 or leave them open. CL0 to CL7 and CLK0 are configured as inputs only in the test mode.
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ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Power supply voltage Input pin voltage Output pin short-circuit current Power dissipation Operating temperature Storage temperature Symbol VDD VI IOS PD Topr Tstg Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C -- -- Rating -0.3 to + 4.6 -0.3 to + 7.0 50 1 0 to 70 -50 to + 150 Unit V V mA W C C
Recommended Operating Conditions
Parameter Power supply voltage Power supply voltage Operating temperature Symbol VDD VSS Ta Min. 3.0 0 0 Typ. 3.3 0 -- Max. 3.6 0 70 Unit V V C
Pin Capacitance
(VCC = 3.3 V 0.3 V, f = 1 MHz, Ta = 25C) Parameter Input capacitance Input/output capacitance (CO0 to CO7, CLK0) Input/output capacitance (SDA) Output capacitance (YO0 to YO7, OVS, OHS, HREF) Symbol Ci Cio1 Cio2 Co Min. -- -- -- -- Max. 5 10 10 10 Unit pF pF pF pF
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ML87V2105
DC Characteristics
(Ta = 0 to 70C) Parameter H level input voltage L level input voltage Schmitt trigger threshold voltage (SDA, SCL, IVS, IHS, RESET) Schmitt trigger threshold voltage (SDA, SCL, IVS, IHS, RESET) Hysteresis voltage width H level input current (pull-down) Input leakage current H level output voltage (other than SDA) L level output voltage (other than SDA) L level output voltage (N-Ch.OD) (SDA) Output leakage current Supply current (during operation) Supply current (during standby) Symbol VIH VIL Vt+ Vt- Vh IIH IIL VOH VOL VOOL IOL IDD1 IDD2 Condition -- -- -- -- -- 50 k Pull Down TTL IOH = -4 mA IOL = 4 mA IOL = 4 mA 0 Vout VDD Output disabled ICLK: 29.5 MHz Output disabled Input pin = VIL Min. 2.0 -0.3 -- 0.8 0.1 20 -10 2.4 0 0 -10 -- -- Max. VDD+0.3 0.8 2.0 -- -- 200 10 VDD 0.4 0.4 10 80 5 Unit V V V V V A A V V V A mA mA
AC Characteristics
(Ta = 0 to 70C) Parameter ICLK clock cycle time ICLK clock cycle time ICLK clock duty ratio ICLK input set-up time ICLK input hold time ICLK output delay time CLKO delay time Data through time Symbol tICLK tICLK dtICLK tIISU tIIH tIOD tCKD tDIDO Condition 16-bit input mode 8-bit input mode ITU-R BT.656 mode -- -- -- CL = 30 pF CL = 30 pF (IICLK output) CL = 30 pF (ICLK output) CL = 30 pF Min. 66 33 40 5 3 5 2 2 5 Max. -- -- 60 -- -- 25 25 25 20 Unit ns ns % ns ns ns ns ns ns
*1: ( ) indicates the input internal system clock cycle. Note 1: Measurement conditions Output comparison level: VOH = 1.5 V, VOL = 1.5 V Input voltage level: VIH = 3.0 V, VIL = 0.0 V Note 2: .When writing input data to the memory, compensation is applied from the second input system vertical synchronization signal when VDD reaches 3.0 V after the power is turned on, and when RESET = 1. (Due to memory initialization, the first data for the first field is not compensated.) Note 3: .When reading output data from the memory, compensation is applied from the second output system vertical synchronization signal when VDD reaches 3.0 V after the power is turned on, and when RESET = 1. (Due to memory initialization, the first data for the first field is not compensated.)
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ML87V2105
INPUT/OUTPUT TIMING
1. ICLK input/output timing
tICLK ICLK DATA & CONTROL INPUT(ICLK) DATA & CONTROL OUTPUT(ICLK) CLKO (CKINV=0) tCKD CLKO (CKINV=1) 50% tIISU tIIH 50% tIOD 50% tCKD 50% 50%
2. Data through mode input/output timing
DATA & CONTROL INPUT tDIDO DATA & CONTROL OUTPUT
50%
50%
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CIRCUIT APPLICATION EXAMPLES
Application Example 1 Mode setting: Open Slave address: 1011100 Input format: 16-bit YCbCr (Register setting: DISEL = 0, R656 = 0)
3.3V
I2C-bus MATER CONTROLLER
SELF 97 VDD 15,26,36,40,50, 60,67,76,88,100 SDA SCL YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 CI7 CI6 CI5 CI4 CI3 CI2 CI1 CI0 IVS IHS 3 4
VIDEO IN
DIGITAL VIDEO DECODER (ML86V766X)
7 8 9 10 11 12 13 14 18 19 20 21 22 23 24 25 29 30
NR-FIFO ML87V2105
2,17,28,37,48, 55,62,72,78,98
71 70 69 68 66 65 64 63 59 58 57 56 54 53 52 51 47 46 45 35
YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 CO7 CO6 CO5 CO4 CO3 CO2 CO1 CO0 HREF OVS OHS CLKO
SCAN CONVERTER (ML87V230X) or MPEG ENCODER
DATA OUT
CLK RESET
ICLK
System Reset
RESET
GND
75
16
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ML87V2105
Application Example 2 Mode setting: Open Slave address: 1011100 Input format: ITU-R BT656 (Register setting: DISEL = 0, R656 = 1)
3.3V
I2C-bus MATER CONTROLLER
SELF 97 VDD 15,26,36,40,50, 60,67,76,88,100 SDA SCL YI7 YI6 YI5 YI4 YI3 YI2 YI1 YI0 3 4
VIDEO IN
DIGITAL VIDEO DECODER (ML86V7666)
CI7(OPEN) CI6(OPEN) CI5(OPEN) CI4(OPEN) CI3(OPEN) CI2(OPEN) CI1(OPEN) CI0(OPEN)
7 8 9 10 11 12 13 14 18 19 20 21 22 23 24 25
NR-FIFO ML87V2105
2,17,28,37,48, 55,62,72,78,98
IVS(OPEN) 29 IHS(OPEN) 30
71 70 69 68 66 65 64 63 59 58 57 56 54 53 52 51 47 46 45 35
YO7 YO6 YO5 YO4 YO3 YO2 YO1 YO0 CO7(OPEN) CO6(OPEN) CO5(OPEN) CO4(OPEN) CO3(OPEN) CO2(OPEN) CO1(OPEN) CO0(OPEN) HREF(OPEN) OVS(OPEN) OHS(OPEN) CLKO(OPEN)
SCAN CONVERTER (ML87V230X) or MPEG ENCODER
DATA OUT
ICLK(27MHz)
System Reset
RESET
GND
75
16
RESET
CLK
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ML87V2105
PACKAGE DIMENSIONS
(Unit: mm)
TQFP100-P-1414-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.55 TYP. 4/Oct. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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REVISION HISTORY
Document No.
PEDL87V2105DIGEST-01 PEDL87V2105DIGEST-02
Page Date
Oct.20,2003 Dec.20,2003
Previous Edition - 14
Current Edition 14 14
Description
Preliminary edition 1 Internal pull down, application schematic
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NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2003 Oki Electric Industry Co., Ltd.
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