PEDR27V6466F-01-08
1 Semiconductor MR27V6466F
GENERAL DESCRIPTION
This version: Jul. 2001 Previous version: Jun. 2001
Preliminary
4,194,304-Word x 16-Bit or 2,097,152-Word x 32-Bit Synchronous One Time PROM
The MR27V6466F is a 64 Mbit One Time Programmable Synchronous Read Only Memory whose configuration can be electrically switched between 4,194,304 x 16 bit (word mode) and 2,097,152 x 32 bit (double word mode) by the state of the WORD pin. The MR27V6466F supports high speed synchronous read operation using a single 3.3 V power supply.
FEATURES ON READ
* * * * * 3.3 V power supply LVTTL compatible with multiplexed address Dual electrically switchable configuration 4M x 16 (word mode) / 2M x 32 (double word mode) All inputs are sampled at the rising edge of the system clock. High speed read operation 100 MHz : CAS Latency = 5, 6 tRCD min: 2 clock cycles 66 MHz : CAS Latency = 5, 6 tRCD min: 2 clock cycles 50 MHz : CAS Latency = 4, 5, 6 tRCD min: 1 clock cycles Burst length (4, 8) Data scramble (sequential, interleave) DQM for data out masking No Precharge operation is required. No Refresh operation is required. No power on sequence is required. Mode register is automatically initialized to the default state after power on. "Row Active" or "Mode Register Set" command is applicable as the first command just after power on. Single Bank operation Package: TSOP(2)86-P-400-0.50-K (Product Name : MR27V6466FTA)
* * * * *
FEATURES ON PROGRAMMING
* * 8.0 V programming power supply Programming algorithm is compatible with conventional asynchronous OTP. MR27V6466F can be programmed with conventional EPROM programmers. Synchronous Burst read or Static Programming Operation is selected by the state of STO pin. High STO level enables full static programming. (Program, Program Verify, Asynchronous Read) Low STO level enables synchronous burst read. Exclusive 86-pin socket adapters are available from OKI to support programming requirements. The socket adapter is used on a 48-DIP socket on the programmer. The socket adapter for 64M synchronous OTP is distinguished from the socket adapter for 32M SOTP. The socket adapter is designed with the STO pin connected to VCC in order to program MR27V6466F as conventional OTP. EPROM programmer must have the algorithm for MR27V6466F on the exclusive socket adapter. *Device damage can occur if improper algorithm is used. Programming with address multiplexed input is also available. High speed programming 25 s programming pulse per word allows high speed programming.
* *
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MR27V6466F
BLOCK DIAGRAM
Row Address Latch
Row Select
Row Decoder
Column Address Latch
A0 | A12
Address Buffer
Memory Cell Array 2 M x 32 or 4 M x 16
Column Select Column Decoder Sense Amplifier & Program Bias
CS RAS CAS MR WORD Mode Register Command Controller Burst sequence Controller
Data Output Latch
Data Input Buffer
Data Output Selector
CLK Buffer
Program Mode Controller
Data Output / Input Buffer & Data Output / Address Buffer
CKE
CLK
OE CE
DQ0 to DQ15 STO DQ23 to DQ31 CAP0 to CAP8 AMPX DQ16 to DQ22
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PIN CONFIGURATION
TOP VIEW
Programming in Static Operation (STO is high) Synchronous Read (STO is VSS or open) VCC DQ0 VCCQ DC DQ1 VSSQ DC DQ2 VCCQ DC DQ3 VSSQ DC DC VCC DC NC CAS RAS DC WORD A12 A11 A10 A0 A1 A2 NC VCC NC DQ4 VSSQ DC DQ5 VCCQ DC DQ6 VSSQ DC DQ7 VCCQ CAP8 VCC VCC DQ0 VCCQ DQ16 DQ1 VSSQ DQ17 DQ2 VCCQ DQ18 DQ3 VSSQ DQ19 MR VCC DQM NC CAS RAS CS WORD A12 A11 A10 A0 A1 A2 NC VCC NC DQ4 VSSQ DQ20 DQ5 VCCQ DQ21 DQ6 VSSQ DQ22 DQ7 VCCQ DQ23 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 VSS DQ31 VSSQ DQ15 DQ30 VCCQ DQ14 DQ29 VSSQ DQ13 DQ28 VCCQ DQ12 NC VSS DC DC DC CLK CKE A9 A8 A7 A6 A5 A4 A3 DC VSS DC DQ27 VCCQ DQ11 DQ26 VSSQ DQ10 DQ25 VCCQ DQ9 DQ24 VSSQ DQ8 VSS VSS CAP0 VSSQ DQ15 CAP1 VCCQ DQ14 CAP2 VSSQ DQ13 CAP3 VCCQ DQ12 NC VSS VPP CE OE DC DC A9 A8 A7 A6 A5 A4 A3 AMPX VSS STO CAP4 VCCQ DQ11 CAP5 VSSQ DQ10 CAP6 VCCQ DQ9 CAP7 VSSQ DQ8 VSS
66
65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
DC (Don't Care) : Logical input level is ignored. However the pin is connected to the input buffer of OTP.
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MR27V6466F
PIN FUNCTION FOR SYNCHRONOUS READ OPERATION
(STO pin is low level or open)
Pin Name STO CLK CS Function Static Operation System Clock Chip Select Description Must be low for synchronous operation. Internal resistance (around 10k ohms) pulls the input level down to VSS when this pin is open. High level STO enables programming operation compatible with standard OTPs. All inputs are sampled at the rising edge. Enables command sampling by the CLK signal with a low level on the CS input. Masks internal system clock to freeze the CLK operation of subsequent CLK cycle. CKE must be enabled for command sampling cycles. CLK is disabled for two types of operations. 1) Clock Suspend 2) Power Down Row and column addresses are multiplexed on the same pins. Row address: RA0 to RA12 Column address: CA0 to CA7 (x32) /CA0 to CA8 (x16) LSB:CA0(Both x32 and x16) RAS CAS MR DQ0 to DQ31 DQM Row Address Strobe Column Address Strobe Mode Register Set Data Output Data Output Masking Functionality depends on the combination. See the function table. Data outputs are valid at the rising edge of CLK for read cycles. Except for read cycles DQn is high-Z state. Data outputs are masked after two cycles from when high level DQM is applied. The WORD pin defines the organization of each read command to be x16 (word mode) or x32 (double word mode). High = x32 Low = x16 When WORD is low (x16,word mode) ,DQ16 to DQ31 are held on High-Z state. VCC VSS VCCQ VSSQ NC DC Power Supply Ground Data Output Power Supply Data Output Ground No Connection Don't Care Logical input level is ignored. 3.3 V Power supply to DQ0-DQ31 3.3 V Power supply
CKE
Clock Enable
A0 to A12
Address
WORD
x32/x16 Organization Selection
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MR27V6466F
PIN FUNCTION FOR PROGRAMMING OPERATION
(STO pin is high level)
Pin Name STO Function Static Operation Description Must be set high for programming operation. Internal resistance (around 10 k ohms) pulls the input level down to VSS for open state condition to be low level for synchronous read operation. When AMPX is low, the addresses are not multiplexed and all address bits must be supplied to A0 to A12 (Row Address) and CAP0 to CAP8 (Column Address) simultaneously. When AMPX is high, multiplexed address inputs are enabled on A0 to A12. A0 to A12 RAS Address Row Address Strobe Row address input. When AMPX is high, row address is latched at the rising egde of RAS. When AMPX is low, input is not used. CAS Column Address Atrobe When AMPX is high, column address is latched at the rising egde of CAS. When AMPX is low, input is not used. DQ0 to DQ15 Data Input/Output Input of data for programming and output for program verify and read data. The WORD pin defines the organization to be x16 (word mode) or x32 (double word mode). High = x32 Low = x16 This pin must be set low for programming operation. When WORD is low, High-Z state on CAP0 to CAP8 is held to be input pins. When AMPX is low, column address input. When AMPX is high, input is not used. OE CE VCC/VSS VCCQ/VSSQ Output Enable Chip Enable Power Supply/Ground Data Output Power/Ground Control signal input for programming. OE of conventional OTPs. Control signal input for programming. Function for programming is associated with conventional OTPs. Power and ground for the input buffers and the core logic. Power and ground for output. High voltage program power is supplied through VPP pin. When VPP is higher than a predetermined voltage level between VCC + 0.5 V and VCC + 2 V, pin function alters to high VPP mode. To keep stable static read operation VPP pin must be kept lower than VCC + 0.5 V.
AMPX
Address Multiplex
WORD
x32/x16 Organization Selection
CAP0 to CAP8
Address Input
Vpp
Program Power Supply
The persons who design socket adapter or make programming algorithm on the condition of omitting socket adapter provided with OKI study this table. Other persons can ignore this table. The functionality of programming must be checked with the specification of socket adapter that will be supplied by OKI. MR27V6466F on the socket adapter is the same programming functionality as conventional OTPs.
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MR27V6466F
FUNCTION COMMAND TABLE FOR SYNCHRONOUS READ
CKEN-1 WORD CKEN DQM Command Name Mode Register Set Row Active Read Word (x16) Read Double Word (x32) Burst Stop Precharge Clock Suspend (on Read) Power Down (on Active Standby) Read Output Mask Output Exit Output Enable High-Z Output Write on SDRAM No Operation Illegal on SDRAM Function Mode Register Set Row Address Latch Column Address Latch Trigger Burst Read Column Address Latch Trigger Burst Read Burst Stop Burst Stop Entry Exit Entry Note 1 2 3 3 4 4 5 5 6 6 Add. STO L L L L L L L L L L L L L L L L CAS L H L L H H X X X X X X L L X H RAS MR L H H H L L X X X X X X L H X H CS L L L L L L H X H X X X L L H L
H H H H H H H L H L H H H H H H
X X X X X X L H L H X X X H X X
L L H H H L X X X X X X H L X H
X X X X X X X X X X L H X X X X
Code
X X L H X X X X X X X X X X X X
RA CA CA X X X X X X X X X X X X
( H = Logical high, L = Logical low, X = Don't Care, L of STO includes pin open due to internal pull down resistor) (CKEN expresses the logical level at the simultaneous cycle with a command. )
Notes: 1. Refer to "Mode Register Field Table" for Address Codes, and Mode Transition Chart for operational state. After power on, any command can be sampled at any cycle in Active Standby state. After "Mode Register Set" command is sampled, no new command can be accepted for 3 CLK cycles. The CS input must be kept high for the 3 CLK cycles to prevent unexpected sampling of a command. 2. The "Row Active" command is effective till new "Row Active" command is implemented. 3. The WORD input is sampled simultaneously with "Read" command to select data width. A Double Word Burst (x32) or a Word Burst (x16) is selected by the WORD input for each "Read" command. On condition of constant voltage level on WORD pin, the organization is fixed to either x16 or x32. "Read" command ends it's implementation by itself at the finishing cycle of the burst read. 4. Since OTP technology uses static sense amplifiers, the "Precharge" command is not required. However, due to customer request for the similarity of logical input code with SDRAM command, the name of "Precharge" is adopted. The function of "Precharge" command and "Burst Stop" command is only to stop the burst read cycles delayed by CAS Latency. 5. Sampled low level CKE disables CLK buffer to suspend internal clock signals at the next rising edge of CLK. Sampled high level CKE enables internal clock at the next rising edge of CLK. Low level CKE sampled in the period from the simultaneous cycle with a "Read" command till the end of the burst read cycle is distinguished with internal command controller from the low level CKE sampled in Active Standby state, then power is consumed because of data sensing and burst read operation. 6. Low level CKE sampled in Active Standby state cuts power dissipation to be in Power Down state. High level CKE sampled in Power Down state enables internal CKE to be in Active Standby state with preserved row address.
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MR27V6466F
FUNCTION STATE TABLE FOR SYNCHRONOUS READ
CKE CAS RAS Note 1 2 3 4 5 2 2 5 5 Add. Current State MR Action at next clock cycle or cycles Mode Register Set Row Address Latch Column Address Latch Trigger Burst Read Entry Power Down NOP NOP NOP NOP NOP NOP Illegal Row Address Latch Column Address Latch Trigger Burst Read Clock Suspend Entry Stop the Burst Read Cycle delayed by CAS Latency Stop the Burst Read Cycle delayed by CAS Latency NOP NOP NOP NOP Exit Power Down Power Down Exit Clock Suspend Clock Suspend Active Standby Active Standby after Burst Read Clock Suspend Active Standby Active Standby Read Read Read Read Active Standby Power Down Read Clock Suspend State after the completion of the command Active Standby Active Standby Active Standby after Burst Read Power Down Active Standby Active Standby Active Standby Active Standby Active Standby Active Standby
CS
Command Mode Register Set Row Active Read Power Down Burst Stop Precharge NOP NOP NOP NOP Mode Register Set Row Active Read Clock Suspend Burst Stop Precharge NOP NOP NOP NOP Exit Power Down Power Down Exit Clock Suspend Clock Suspend
H H H L H H H H H H H H H L Read H H H H H H Power Down Clock Suspend H L H L
L L L H L L L L L H L L L X L L L L L H X X X X
L L H X H L L H H X L L H X H L L H H X X X X X
L H L X H H L L H X L H L X H H L L H X X X X X
L H H X L L H L H X L H H X L L H L H X X X X X
Code RA CA X X X X X X X Code RA CA X X X X X X X X X X X
Active Standby
( H = Logical high, L = Logical low, X = Don't Care)
Notes: 1. The latched row address is preserved during any state except another "Row Active" command. 2. Low level CKE sampled in Active Standby state disables internal clock and cuts power dissipation to be in Power Down state. High level CKE sampled in Power Down state enables internal clock to be in Active Standby state. 3. To preserve previous "Read" command, the latest "Row Active" command must be implemented at CL1 clock cycle or later after the previous "Read" command. 4. To preserve previous "Read" command, the latest "Read" command must be implemented at CL-1 clock cycle or later after the previous "Read" command. 5. Sampled low level CKE in the period of Burst Read disables CLK buffer to suspend internal clock signals at the next rising edge of CLK. Sampled high level CKE in the Clock Suspend enables internal clock at the next rising edge of CLK.
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MR27V6466F
MODE REGISTER FIELD TABLE
Address Function A5 0 0 0 0 1 1 1 1 A4 0 0 1 1 0 0 1 1 A3 0 1 0 1 0 1 0 1 A5 A4 CAS Latency CAS Latency Reserved Reserved Reserved 4 5 6 Reserved Reserved A3 A2 Burst Type A2 0 1 Type
Sequential Interleave
A1 Burst Length A1 0 0 1 1 A0 0 1 0 1
A0
Burst Length Reserved 4 8 Reserved
Note: A7 and A8 must be low during Mode Register Set cycle. During power on, mode register is initialized to the default state when VCC reaches a specific voltage (less than 3.0 V). The default state of Mode Register is as shown below. CAS Latency = 5 Burst Type = Sequential Burst Length = 4
BURST SEQUENCE (BURST LENGTH = 4)
Initial address A1 0 0 1 1 A0 0 1 0 1 0 1 2 3 Sequential 1 2 3 0 2 3 0 1 3 0 1 2 0 1 2 3 Interleave 1 0 3 2 2 3 0 1 3 2 1 0
BURST SEQUENCE (BURST LENGTH = 8)
Initial address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 Sequential 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 Interleave 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0
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MR27V6466F
ADDRESSING MAP
(1) WORD = "H": x32 Organization
Pin Name Row Address Column Address A0 RA0 CA0 A1 RA1 CA1 A2 RA2 CA2 A3 RA3 CA3 A4 RA4 CA4 A5 RA5 CA5 A6 RA6 CA6 A7 RA7 CA7 A8 RA8 X A9 RA9 X A10 RA10 X A11 RA11 X A12 RA12 X
( X = Don't Care)
(2) WORD = "L": x16 Organization
Pin Name Row Address Column Address A0 RA0 CA0 A1 RA1 CA1 A2 RA2 CA2 A3 RA3 CA3 A4 RA4 CA4 A5 RA5 CA5 A6 RA6 CA6 A7 RA7 CA7 A8 RA8 CA8 A9 RA9 X A10 RA10 X A11 RA11 X A12 RA12 X
( X = Don't Care)
(3) Programming
Address displayed on programmer: x16 Device Address: x16 STO = "H", AMPX = "L" Address (STO = "L") WORD = "L": x16 Address (STO = "L") WORD = "H": x32 Address displayed on programmer: x16 Device Address: x16 STO = "H", AMPX = "L" Address (STO = "L") WORD = "L": x16 Address (STO = "L") WORD = "H": x32 Ad0 CAP0 CA0 Note1 Ad1 CAP1 Note2 CA1 CA0 Ad2 CAP2 Note3 CA2 Note4 CA1 Ad15 A6 RA6 RA6 Ad3 CAP3 CA3 Note5 CA2 Ad16 A7 RA7 RA7 Ad4 CAP4 CA4 CA3 Ad5 CAP5 CA5 CA4 Ad6 CAP6 CA6 CA5 Ad7 CAP7 CA7 CA6 Ad8 CAP8 CA8 CA7 Ad9 A0 RA0 RA0 Ad10 A1 RA1 RA1 Ad11 A2 RA2 RA2 Ad12 A3 RA3 RA3
Ad13 A4 RA4 RA4
Ad14 A5 RA5 RA5
Ad17 A8 RA8 RA8
Ad18 A9 RA9 RA9
Ad19 A10 RA10 RA10
Ad20 A11 RA11 RA11
Ad21 A12 RA12 RA12
Users of MR27V6466F are recommended to study the relationship between "Address displayed on programmer" and "Address (STO = "L")" ignoring "Device Address: x16, STO = "H"". The order of data on Synchronous Read operation (STO="L") is checked on this table. "Device Address : x16, STO = "H"" will be utilized to design socket adapter on programmer or to check boards designed to mount blank OTP and program OTP on board. OKI will supply a socket adapter to program MR27V6466F as conventional x16 standard OTP. The users and the venders of programmer who use the socket adapter can ignore "Device Address: x16, STO = "H"". The persons who use 32Mbit SOTP and 64Mbit SOTP must be careful to distinguish the socket adapters for 64Mbit from one for 32Mbit. The difference is caused from the additional assignment of column address and 1 bit shift of row address on 64Mbit SOTP Note 1. A0 in programmer distinguishes upper word (x16) or lower word (x16) of Double word (x32). On word (x16) organization the address of device corresponds to the address of programmer. On double word (x32) organization the address numeral code of device is half of that in programmer, and output on DQ0 to DQ15 is lower word (A0 = "0") and output on DQ16 to DQ31 is upper word (A0 = "1"). 2. CA1 is MSB of burst read on condition of WORD = "L" and BL = 4. 3. CA2 is MSB of burst read on condition of WORD = "L" and BL = 8. 4. CA1 is MSB of burst read on condition of WORD = "H" and BL = 4. 5. CA2 is MSB of burst read on condition of WORD = "H" and BL = 8.
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MR27V6466F
READ OPERATIONS
Clock (CLK) The clock input enables MR27V6466F to sample all the inputs, to control internal circuitry, and to turn on output drivers. All timings are referred to the rising edge of the clock. All inputs with high level CKE and low level CS should be valid at the rising edge of CLK for proper functionality. Clock Enable (CKE) The clock enable (CKE) turns on or switches off the admission of the clock input into the internal clock signal lines. All internal circuits are controlled by the internal clock signal to implement each command. High level CKE sampled at CKEN-1 clock cycle enables the admission of the rising edge of clock input into internal clock line at CKEN cycle. Low level CKE sampled at CKE N-1 cycle suspends the rising edge of CLK at CKEN cycle. The suspension of internal clock signal in all state ignores new input except CKE, and holds internal state and output state. Low level CKE in Active Standby state, defined as Power Down state, cuts power dissipation. In Power Down state, the contents of mode resister and Row Address are preserved. After recovering high level CKE to exit from Power Down state, MR27V6466F is in Active Standby state. Low level CKE just after the sampling of "Read" command till the completion of burst read, defined as Clock Suspend, makes read operation go on with power dissipation. Any command operation does not interrupted by arbitrary low level CKE. Sampling command with low level CKE preceded with high level CKE is illegal. Power On Apply power and start clock considering following issues. 1. During power on, Mode Register is initialized into the default state. (default state: CAS latency = 5, Burst Type = Sequential, Burst length = 4) 2. After power on, MR27V6466F is in Active Standby state and ready for "Mode Register set" command or "Row Active" command. MR27V6466F requires neither command nor waiting time as power on sequence after starting CLK input in order to start "Row Active" command to read data. 3. It is recommended in order to utilize default state of Mode Register that MR and CKE inputs are maintained to be pulled up during power on till the implementation of the first "Row Active" command. After above power on, "Row Active" command and "Read" command can be started immediately on default Mode Register state. 4. It is recommended that DQM input is maintained to be pulled up to prevent unexpected operation of output buffers. Organization Control The organization of data output (DQ0~DQ31) depends on the logical level on WORD at the input timing of each "Read" command. High level sampling of WORD derives double word mode (x32) output and low level sampling of WORD derives word mode (x16) output. Constant WORD level input brings consistent organization. MODE Register Mode register stores the operating mode of MR27V6466F. Operating modes are consisted with CAS latency, Burst Type and Burst Length. Registration of RAS latency is not required, because RAS to CAS delay (tRCD) is requested independently of system clock. When the contents of Mode register are required to be changed for the next operation, "Mode Register Set" command can be sampled at any cycle in Active Standby state. After "Mode Register Set" command is sampled, CS must be fixed to logical high level to prevent sampling of new command input during succeeding three clock cycles. Refer to Mode Resister Field Table for the relation between Operation modes and input pin assignment
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MR27V6466F
READ OPERATIONS
CAS Latency After sampling "Read" command, MR27V6466F starts actual data read operation with sense amplifiers, and transmits the data from sense amplifiers to data out buffers to start burst read. This flow of sequential functionality takes time as clock cycles defined as CAS latency (CL). CAS latency can be set in Mode Register between from four cycles to six cycles. In this sequence (from sampling "Read" command to start of driving data bus), sense amplifiers consume maximum current flow. The detailed sequence is as shown below. 1. 2. 3. 4. 5. 6. Fix the column address of memory matrix driver. Row address is already fixed with "Row Active" command. (at 1st cycle) Read the data of selected memory cells with sense amplifiers. Deliver the data detected with sense amplifiers to the register for data output latch. Couple selectively the section of the register storing each (double) word to output buffers. Enable the output buffers to drive data bus (at CL-1 cycle). Data the output on data bus can be sampled at the rising edge of system clock at CL cycle.
New "Row Active" command or new "Read" command can be sampled to perform gapless burst read at CL-1 clock cycle of the last "Read" command. New command preceeding CL-1 cycle interrupts sense amplifiers to read the data at the selected memory cells of the last "Read" command. Interrupted "Read" command perishes or outputs invalid data before the starting of the data burst of new "Read" command. Refer to the timing chart of "Burst Read/Interrupt I" and "Burst Read/Interrupt II". Burst Read Data outputs are consecutive during the cycle number defined as Burst Length (BL). The latest burst read is completed unless any interruption such as "Precharge" command stops the sequential data output. Burst Length is set in Mode Register as either four or eight. After sampling of "Read" command, the first output can be read at the cycle delayed by CAS latency. Burst Type is also stored in Mode register as either sequential or interleave. The output buffers go into a high impedance state after burst read sequence is finished, unless a new "Read" command has been sampled to perform gapless read or preemptive read. Burst read can be interrupted by "Burst Stop" command or "Precharge" command at the cycle delayed by CAS latency from the command. On condition that reading data with sense amplifiers of preceding "Read" command is not interrupted by new "Read" command or "Row active" command, burst read of preceding "Read" command is continued regularly until the burst data sequence of the new "Read" command starts. The new (latest) burst data sequence always starts regularly. DQM Input level on DQM is sampled at the rising edge of system clock to mask data at two cycles later. The output of masked data is in a high-Z state.
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MR27V6466F
Read Operation Mode transfer chart
CKE = H
CKE = L
Row Active
Mode Register Set
Entry Active Standby Exit Power Down
Entry Read DQM Exit Clock Suspend
Burst Stop Precharge* * All operation of "Precharge" command is to stop burst read. Note:
: passing command : state can be kept for any duration
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MR27V6466F
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on VCC Relative to VSS Voltage on Any Pin Relative to VSS Voltage on VPP Relative to VSS Operating Temperature Storage Temperature Short Circuit Current Power Dissipation Symbol VCC, VCCQ VIN, VOUT, DC VPP TA TSTG IOS PD Min. -0.5 -0.5 -0.5 0 -55 -- -- Max. 5 VCC + 0.5 10 70 125 50 1.0 Unit V V V C C mA W
RECOMMENDED OPERATION CONDITION FOR SYNCRONOUS READ
Parameter Power Supply Voltage Voltage Level on DC Pin Input High Voltage Input Low Voltage Operating Temperature Power Dissipation1 (Airflow over 1 m/s) Power Dissipation2 (No airflow) Power Dissipation3 (Airflow over 1 m/s) Power Dissipation4 (No airflow) Symbol VCC, VCCQ -- VIH VIL TA PD1 PD2 PD3 PD4 Min. 3.0 -0.5 2.0 -0.3 0 -- -- -- -- Typ. 3.3 -- -- -- -- -- -- -- -- Max. 3.6 VCC + 0.3 VCC + 0.3 0.8 70 0.6 0.4 0.9 0.6 Unit V V V V C W W W W 3 3 1 2 Note
Notes: 1. VIH max can be VCC + 1.5V for the pulse width shorter than 3 ns. Pulse width is measured at 50% of pulse peak level. 2. VIL min can be -1.5 V for the pulse width shorter than 3 ns. Pulse width is measured at 50% of pulse peak level. 3. The clock frequency is under 83MHz.
CAPACITANCE
Parameter Input Capacitance Output Capacitance Symbol CIN COUT Min. -- -- Max. 5 7 Unit pF pF
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MR27V6466F
DC CHARACTERISTICS FOR SYNCHRONOUS READ
Parameter Power Down Current Active Standby Current Gapless Burst Read Current Input Leak Current Output Leak Current Input High Voltage Input Low Voltage Voltage Level on DC Pin Output High Voltage Level Output Low Voltage Level ( Voltage levels are referred to VSS ) VOH VOL Symbol ICCS1 ICCS2 ICC1 ICC2 IIL IOL VIH VIL Min. -- -- -- Max. 1 150 120 250 10 10 VCC+0.3V 0.8 VCC+0.3V -- 0.4 Unit mA A mA Test Condition CKE = 0.8V CKE = 0 V CKE = 2.4V CS = 2.4V tCC = 10 ns tCC = 10 ns, DQM = H, CL = 5, BL = 4 tCC = 10 ns
-- -10 -10 2.0 -0.3 -0.5 2.4 --
mA A A V V V V V
CKE = 2.4V
0V > VIN > VCC + 0.3 V 0V > VIN > VCC Note 1 Note 2 IOH = -4 mA IOL = 4 mA
Notes: 1. VIH max can be VCC + 1.5V for the pulse width shorter than 3 ns. Pulse width is measured at 50% of pulse peak level. 2. VIL min can be -1.5 V for the pulse width shorter than 3 ns. Pulse width is measured at 50% of pulse peak level.
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MR27V6466F
AC CHARACTERISTICS FOR SYNCHRONOUS READ (1/2)
Parameter CLK Cycle Time Data to Valid Output Delay Data Output Hold Time CLK High Pulse Width CLK Low Pulse Width Input Setup Time Input Hold Time CLK to Output in Low-Z CLK to Output in High-Z Input Level Transition Time "Row Active" to "Read" Delay Time "Read" to "Row Active" Delay ( Words of preceding "Read" command can be read ) < Random Access > BL = 4 CL = 4 CL = 5 CL = 6 CL = 4 CL = 5 CL = 6 CL = 4 CL = 5 CL = 6 CL = 4 CL = 5 CL = 6 CL = 4 CL = 5 CL = 6 CL = 4 CL = 5 CL = 6 CL = 4 CL = 5 CL = 4 CL = 5 CL = 6 Symbol tCC tAC tOH tCH tCL tSI tHI tOLZ tOHZ tT tRCD tCRD tCRD tCRD tCRD tCRD tCRD tCCD tCCD tCCD tCCD tCCD tCCD tRC tRC tRC tRC tRC tRC tCCD tCCD tCCD tCCD tCCD Min. 10 -- 2.3 3 3 2 1 0 -- 0.1 1CLK 2CLK 3CLK 4CLK 5CLK 3CLK 4CLK 5CLK 3CLK 4CLK 5CLK 3CLK 4CLK 5CLK 3CLK + tRCD 4CLK + tRCD 5CLK + tRCD 3CLK + tRCD 4CLK + tRCD 5CLK + tRCD 4CLK 4CLK 8CLK 8CLK 8CLK 1CLK 1CLK tSI + 1CLK tSI + 3CLK Max. -- 6 -- -- -- -- -- -- 7 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Cycle Notes
2 1,2 1 1 1,2 1 1 1,2 1 1 1,2 1 1 1,2 1 1 1,2 1 1 1,2 1 1,2 1 1
BL = 8
"Read" to "Read" Delay ( Words of preceding "Read" command can be read ) < Sequential Access >
BL = 4
BL = 8
"Row Active" Cycle Time ( Words of preceding "Read" command can be read ) < Random Access >
BL = 4
BL = 8 BL = 4 BL = 8
"Read" to "Read" Delay ( Consecutive Column Read ) < Sequential Access >
"Read" to "Burst Stop" Delay "Read" to "Precharge" Delay Power down Exit Setup Time Power down Exit to "Read" Delay
tPDE tPDR
Notes: 1. The shortage of clock cycles interrupts the data sensing of preceding "Read" command. The shortage of cycle time for preceding command is detected by internal command controller to cease the preceding command operation. The latest "Row Active" or "Read" command is completed. When a legal tCCD is shorter than BL, burst read is terminated with another burst read. 2. Up to 50 MHz
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
AC CHARACTERISTICS FOR SYNCHRONOUS READ (2/2)
Parameter Clock Disable Time from CKE Clock Enable Time from CKE Output High Impedance from DQM Recovery from DQM Output High Impedance from "Burst Stop" Output High Impedance from "Precharge" "Row Active" Input from "Mode Register Set" Symbol tCKE tCKE tDQM tDQM tBOH tPOH tMRD Value 1CLK 1CLK 2CLK 2CLK CL CL 3 Unit Cycle Cycle Cycle Cycle Cycle Cycle Cycle Notes
AC TEST CONDITIONS
Parameter Input Signal Levels Timing Reference Level of Input/Output Signals Transition Time of Input Signals Output Load Values VIH/VIL = 2.4 V/0.4 V 1.4 V tr/tf = 1 ns/1 ns LVTTL 1 2 Notes
Notes: 1. The transition time of input signals is measured between 0.8 V and 2.0 V. If tr or tf is longer than 1ns, the "Timing Reference Level of Input/Output Signals" is changed to VIL or VIH/0.8 V or 2.0 V respectively. 2. Output Load
1.4 V
ZO = 50 Output
50
50 pF
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Read Cycle I: Random Access @ CAS Latency = 5, Burst length = 4
0 CLK tCC tCH CKE tRC CS tSI tHI RAS tRCD tCL
High
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CAS
ADDR
Ra
Ca
Rb
Cb
tOH DQ a0 a1 a2 a3 b0 b1 b2 b3
tAC MR
tOHZ
Don't Care Row Active Read Row Active Read
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Read Cycle II: Random Access with Gapless Burst @ CAS Latency = 4, Burst length = 4
0 CLK tCC tCH CKE tRC CS tSI tHI RAS tRCD tCL High 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CAS
ADDR
Ra Ca
Rb Cb tOH
Rc Cc
DQ
tAC
a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3
MR
Don't Care Row Active Row Active Row Active Read Read Read
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Read Cycle III: Consecutive Column Read @ CAS Latency = 5, Burst length = 4
0 CLK
1
2 tCC
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
tCH CKE
tCL High
CS tSI tHI RAS tRCD
CAS tCCD
ADDR
Ra
Ca
Cb tOH
DQ tAC
a0 a1 a2 a3 b0 b1 b2 b3 tOHZ
MR
Don't Care Read Row Active Read
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
"Burst Stop" command & "Precharge" command @ CAS Latency = 5
0 CLK tCC tCH CKE tCL High 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CS tSI tHI RAS tRCD
CAS tBOH tPOH
ADDR
Ra
Ca
Rb tOH
Cb
DQ tAC
a0 a1 tOHZ
b0 b1
MR
Don't Care Row Active Read Row Active Burst Stop Read Precharge
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Clock Suspend @ CAS Latency = 5, Burst length = 4
0 CLK tCC tCH CKE tCKE CS tSI tHI RAS tRCD tCKE tCKE tCKE tCL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CAS tCCD
ADDR
Ra
Ca
Cb Read "a" operation (Note2) Read "b" operation
DQ
a0
a1
a2
a3 b0 b1 b2 b3
( Note1 )
MR
Don't Care Row Active Read Read Exit Clock Suspend Entry Clock Suspend Entry Exit
Note 1. 2.
At cycle numbers 9, 12 and 13, the rising edge of internal clock is omitted because of low level CKE at cycles 8, 11 and 12. Clock suspend is defined with the low level CKE sampled in the period of read operation.
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Power Down @ CAS Latency = 4, Burst length = 4
0 CLK
1
2 tCC
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
tCH CKE
tCL
tSI tPDE tPDR Power Down (Note1)
CS Read Operation RAS
CAS
ADDR
Ca
Cb
DQ
a0 a1 a2 a3
MR
Read
Power Down Entry
Read Power Down Exit Row Active
Note 1.
Minimum current consumption is expected in Power Down state. Low level CKE sampled only in Active Standby state is defined as Power Down "Entry" command and it cuts current consumption into a minimum level. After Power Down "Exit" the contents of Mode Register and row address are preserved. During Power Down state no command can be sampled.
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Mode Register Set @ CAS Latency = 4, Burst length = 4
0 CLK
1
2 tCC
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
tCH CKE
tCL
Power Down
tMRD
CS
RAS
CAS
ADDR
key
Rb
Cb
DQ
High - Z
b0 b1 b2 b3
MR
Don't Care Power Down Entry Mode Register Set Power Down Exit Row Active Read
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
DQM Operation @ CAS Latency = 4, Burst length = 8
0 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CMD
RD
CKE tCKE DQM tDQM DQ High - Z Q0 Q1 Q3 tDQM Q4 Q6 Q7 tCKE
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Burst Read/Interrupt I @ CAS Latency = 4, Burst length = 8
0 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CMD
RD RD tCCD
RD
RD
RD
ADDR
a
b
c
d
e Invalid State
DQ
High-Z
Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2
Qe0 Qe1 Qe2 Qe3
RD is interrupted by RD RD command perishes.
RD sets up Qc2 as the final Qcn.
The output state of interrupted command preceded by data read cycle is invalid. Invalid state: "H", "L" or High-Z
RD is interrupted by RD.
Burst Read/Interrupt II @ CAS Latency = 4, Burst length = 4
0 CLK tRC CMD RD
ACT
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
RD tCRD a
ACT
RD
tRCD ADDR c A
B
b
DQ
High-Z Invalid State
Qa0 Qa1 Qa2 Qa3
Qb0 Qb1 Qb2 Qb3
RD is interrupted by ACT
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Preemptive Burst Read I @ CAS Latency = 4, Burst length = 8
0 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CMD
RD
RD
RD
RD
ADDR
a
b
c
d
DQ
High-Z
Qa0 Qa1 Qa2 Qb0 Qb1 Qb2 Qb3 Qc0 Qc1 Qc2 Qc3 Qc4 Qd0 Qd1 Qd2
Preemptive Burst Read II @ CAS Latency = 4, Burst length = 8
0 CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
CMD
ACT
RD
ACT
RD
ADDR
A
a
A
b
DQ
High-Z
Qa0 Qa1 Qa2 Qa3 Qa4 Qb0 Qb1 Qb2 Qb3 Qb4 Qb5 Qb6 Qb7
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MR27V6466F
RECOMMENDED OPERATING CONDITIONS AND DC CHARACTERISTICS FOR PROGRAMMING (STO is High level)
Parameter VPP Supply Voltage Symbol VPP1 VPP2 VCC1 VCC Supply Voltage VCC2 VCC3 VPP Current VCC Current Input Leak Current Output Leak Current Output High Voltage Level Output Low Voltage Level Input High Voltage Input Low Voltage Voltage Level on DC pin OE Input Distinctive High Voltage For Contact Check VH IPP1 IPP2 ICCP1 ICCP2 IIL IOL VOH VOL VIH VIL Min. 7.75 -0.3 3.9 4.5 2.75 -- -- -- -- -10 -10 2.4 -- 3.2 -0.3 -0.3 6.6 20 Typ. 8.0 VCC 4.0 4.6 2.8 -- -- -- -- -- -- -- -- -- -- -- 6.7 25 Max. 8.25 VCC+0.5 4.1 4.7 2.85 50 100 150 200 10 10 -- 0.45 VCC+0.7 0.45 VCC+0.5 6.8 30 Unit V V V V V mA A mA mA A A V V V V V V C VCC = 3.0 V IOH =-400 A IOL = 2.1 mA VCC = 2.8/4.6 V VCC = 2.8/4.6 V Condition Program Mode Read Mode Program Mode Read Mode Read Mode VPP = 8.25 V, VCC = 4.1 V VPP = VCC = 4.7 V VPP = 8.25 V, VCC = 4.1 V VPP = VCC = 4.6 V Notes 1 2 1 2 2
Operating Temperature Ta (Voltage levels are referred to VSS)
Notes: 1. Program represents the modes below. Program, Program Verify, Program Inhibit 2. Read represents the modes below. Read, Output Disable, Standby
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MR27V6466F
FUNCTION TABLE FOR PROGRAMMING
CAP0~ CAP8 WORD AMPX DQ0~ DQ15 Notes 1 1 1 Add. STO H H H H H H H H H H H H H H H STO RAS CAS X X X X X X X X X
VCC
OE
CE
Function
VPP
Program Program Inhibit Program Verify Read Full Static Output Disable Standby Contact Check Contact Check Contact Check
4.0 V 4.0 V 4.0 V
8.0 V 8.0 V 8.0 V
L H H L L H L L L
H H L L H X 6.7 V 6.7 V 6.7 V
L L L L L L L L L
DIN HZ DOUT DOUT HZ HZ AAAA 5555 5555
A0 to A8 A0 to A8 A0 to A8 A0 to A8 A0 to A8 A0 to A8 0AA 155 155
A9 to A21 A9 to A21 A9 to A21 A9 to A21 A9 to A21 A9 to A21 16AA 0955 0955
L/ Open L/ Open L/ Open L/ Open L/ Open L/ Open L/ Open L/ Open L/ Open
2.8/ 4.6 V 2.8/ 4.6 V 2.8/
2.8/ 4.6V 2.8/ 4.6V 2.8/
4.6 V 4.6V
3.0 V 3.0 V 3.0 V 3.0 V 3.0 V 3.0 V
ADDRESS MULTIPLEX
CAP0~ CAP8 WORD AMPX DQ0~ DQ15 Notes
Add. RA/CA RA/CA X X -
Program Program Inhibit Program Verify Address multiplex Read Output Disable Standby Contact Check Contact Check
4.0 V 4.0 V 4.0 V
8.0 V 8.0 V 8.0 V
L H H L L H -
H H L L H X -
OE
CE
Function
L L L L L L -
DIN HZ DOUT DOUT HZ HZ -
-
RAS CAS H H X X -
VCC
VPP
H H H H H H -
2.8/ 4.6V 2.8/ 4.6V 2.8/ 4.6V
-
2.8/ 4.6V 2.8/ 4.6V 2.8/ 4.6V
-
( H = Logical high, L = Logical low, X = Don't Care in the range of logical level)
Notes: 1. Dual procedures to check complementary output codes on the indicated complementary address inputs assure every address, DQ, and OE pin connection. When address input code is incorrect, output code is "FFFF".
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MR27V6466F
PROGRAMMING OPERATION
STO Synchronous read is far different from anyone of conventional nonvolatile memories. STO input level switches operation mode either synchronous read or conventional EPROM/OTP type programming. The word "Programming" contains actual programming (inject electrons into floating gates of memory cells), program verify (verify data on actual programming bias), and read on programmer. High level STO assures full compatible programming operation with conventional EPROM/OTP. Low level STO assures high speed synchronous read. "Full static programming" is recommended for loose devices. Program MR27V6466F is programmed with 25 microsecond pulse width on 4.0 V VCC and 8.0 V VPP. OKI recommends consecutive programming, because of the similarity of device sorting process. Almost all words can be programmed sufficiently with one pulse. Programmers are recommended to be equipped with large current capacity of VPP and VCC supplying source and responsive capacitance (around 0.1 F) on each socket to stabilize VPP and VCC voltage level, since switching speed of transistors produced with advanced wafer process technology is very fast and high voltage immunity of those is decreasing. Excessive overshooting of VPP voltage may destroy device permanently. Excessive overshooting of VCC voltage may cause misprogramming or disturbance. Excessive undershooting of VPP or VCC level may cause insufficient electron injection into floating gate. Additional programming increases programming time. Program Inhibit When VPP is 8.0 V, address must be changed only in "Program Inhibit" mode. Program Verify This operation mode is utilized to check that each word is programmed sufficiently. It is recommended to take time more than some seconds between actual programming and "Program Verify" ("Read") for each word, because just after the actual programming (injection of electron into floating gate) of each word, pretended excessive electrons are attached around floating gate to show false sufficiency of programming. Programming flow is selected to separate "Program" and "Program Verify" to take enough time. Contact Check When programmed OTP lot contains failed devices at a rate of more than 0.1%, some of or almost all failed devices are caused by misconnection with the sockets on the programmer. The possibility of misconnection is increased with surface mount devices such as SOP or TSOP. OKI will supply socket adapters exclusively applicable to MR27V6466F, but connections of all pins can not be assured with these socket adapters. Following contact check sequence before actual programming is recommended. Supply VCC with 3.0 V power source. Bias logical low level on CE. Supply 6.7 V on OE to enable contact check mode. Apply two address codes and check each output respectively. If irregular address code is applied, then output is FFFF. 5. CE must be checked with a method suitable for the programmer. 6. VPP can be checked with current flow (more than 100 A) in Program Inhibit mode. 7. AMPX and WORD pins is open in the socket adapter, since these pins are pulled down to VSS when STO is high. 1. 2. 3. 4.
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
AC CHARACTERISTICS FOR PROGRAMMING (STO is High Level)
Parameter VPP Setup Time Address Setup Time Data Setup Time Address Hold Time Data Hold Time Program Pulse Width OE Setup Time Data Valid from OE OE High to Output Float Delay Address Setup Time(RAS/CAS) RAS/CAS Pulse Width Address Hold Time(RAS/CAS) RAS Precharge Time RAS to CAS Delay Address to CE Delay Symbol tVS tAS tDS tAH tDH tPW tOES tOE tOHZ tASR tASC tRAS tCAS tAHR tAHC tRP tRCD tACD Min. 2 100 100 1 100 24 1 -- 0 15 15 15 1 30 100 Typ. -- -- -- -- -- 25 -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- 26 -- 100 100 -- -- -- -- -- -- Unit s ns ns s ns s s ns ns ns ns ns s ns ns Condition VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V VPP = 8.0 V, VCC = 4.0 V Notes
AC CHARACTERISTICS FOR VERIFY AND READ (STO is High Level)
Parameter Address Access Time RAS Access Time CAS Access Time CE Access Time OE Access Time CE High to Output Float Delay OE High to Output Float Delay Address Hold from OE high Address Setup Time(RAS/CAS) RAS/CAS Pulse Width Address Hold Time(RAS/CAS) RAS to CAS Delay Address to CE Delay Symbol tACC tACC tACC tCE tOE tCHZ tOHZ tAHO tASR tASC tRAS tCAS tAHR tAHC tRCD tACD Min. -- -- -- -- -- -- -- 0 15 15 15 30 100 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 100 100 100 100 30 25 20 -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Condition VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V VPP = VCC = 2.8/4.6 V Notes
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Consecutive Programming Waveforms (VPP = 8.0 V, AMPX = L)
CAP0 to CAP8 A0 to A12 tAS CE High OE tDS DQ0 to DQ15 tVS VPP DIN tDH DIN tPW tAH
Consecutive Program Verify Cycle (VPP = 8.0 V, AMPX = L)
CAP0 to CAP8 A0 to A12 High CE tACC Note1 OE tOE DQ0 to DQ15 DOUT tOHZ DOUT tAHO
Notes: 1. Falling edge of OE must be preceded with data stabilizing time of more than tACC max, because output of invalid state can cause unstable system operation. Output buffer of MR27V6466F is designed to drive 100 pF load in 5ns.
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Program and Program Verify Cycle Waveforms (AMPX = L)
CAP0 to CAP8 A0 to A12 tAS CE tOES OE tOHZ DQ0 to DQ15 tDS DIN 8.0V VPP tDH tOE DOUT tOHZ tPW
Read Cycle (AMPX = L)
CAP0 to CAP8 A0 to A12
CE tACC OE tOE DQ0 to DQ15 DOUT DOUT tOHZ tCE tCHZ
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Consecutive Programming Waveforms (VPP = 8.0 V, AMPX = H, WORD = L)
A0 to A12
Row address tRAS tAHR
Column address
RA
RAS tASR CAS
tRCD tCAS tAHC
tRP
tASC CE tACD
tPW
High OE tDS DQ0 to DQ15 tVS VPP DIN tDH
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PEDR27V6466F-01-08
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MR27V6466F
Consecutive Program Verify Cycle (VPP = 8.0 V, AMPX = H, WORD = L)
A0 to A12
Row address tRAS tAHR
Column address
RAS tASR CAS
tRCD tCAS tAHC
tASC CE tACC OE tOE DQ0 to DQ15
High Note1
tOHZ DOUT
Notes: 1. Falling edge of OE must be preceded with data stabilizing time of more than tACC max, because output of invalid state can cause unstable system operation. Output buffer of MR27V6466F is designed to drive 100 pF load in 5ns.
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Program and Program Verify Cycle Waveforms (AMPX = H, WORD = L)
A0 to A12
Row address tRAS tAHR
Column address
RA
RAS tASR CAS
tRCD tCAS tAHC
tRP
tASC CE
tPW tOES
OE
tACD tDS tDH DIN 8.0V tOE tOHZ DOUT
DQ0 to DQ15
VPP
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
Read Cycle (AMPX = H, WORD = L)
A0 to A12
Row address tRAS tAHR
Column address
RAS tRCD tASR CAS tASC CE tCAS tAHC
OE tACC DQ0 to DQ15 DOUT tOHZ
A0 to A12
Row address tRAS tAHR
Column address
RAS tRCD tASR CAS tASC CE tCE OE tOE DQ0 to DQ15 DOUT tOHZ tCHZ tCAS tAHC
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
PROGRAMMING FLOW CHART
START
VPP = VCC = 3.3 V
CONTACT CHECK
ADDRESS = FIRST LOCATION
VCC = 4.0 V VPP = 8.0 V
PROGRAM ONE 25 s PULSE
INCREMENT ADDRESS
NO
LAST ADDRESS YES X=0
VERFY ONE WORD PASS INCREMENT ADDRESS NO LAST ADDRESS YES VPP = VCC = 2.8 V
NG
X=X+1
YES
X=2 NO PROGRAM ONE 25 s PULSE
READ WORD PASS VPP = VCC = 4.6 V
NG
READ WORD PASS DEVICE PASSED
NG
DEVICE FAILED
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PEDR27V6466F-01-08
1 Semiconductor
MR27V6466F
PACKAGE DIMENSIONS
(Unit: mm)
TSOP(2)86-P-400-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.53 TYP. 1/Jul. 14, 1998
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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MR27V6466F
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2001 Oki Electric Industry Co., Ltd.
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