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| MX23J12840 128M-BIT NAND INTERFACE XtraROMTM FEATURES * Word organization - (16,777,216 + 1,048,576Note) by 8 bits * Page size - (512 + 16Note) by 8 bits * Block size - (16,384 + 512Note) by 8 bits Note : Underlined parts are redundancy and fixed to all FFH. * Operation mode - READ mode (1), READ mode (2), READ mode (3), RESET * Operating supply voltage : VCC = 2.7~3.6V * Access Time - Memory cell array to starting address : 7 us (MAX.) - Read cycle time : 50 ns (MAX.) - RE access time : 35 ns (MAX.) * Operating supply current - During read : 30 mA (MAX.) (50 ns cycle operation) - During standby (CMOS) : 40 uA (MAX.) * Package Type - 48-pin TSOP(I) (12mmx20mm) * XtraROMTM : factory pre-programmed ROM with Macronix NBitTM technology, supporting short TAT * Process - 0.15um PIN CONFIGURATIONS 48 TSOP NC NC NC NC NC GND RB RE CE NC NC VCC VSS NC NC CLE ALE WE NC NC NC NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 NC NC NC NC I/O7 I/O6 I/O5 I/O4 NC NC NC VCC GND NC NC NC I/O3 I/O2 I/O1 I/O0 NC NC NC NC PIN DESCRIPTION SYMBOL I/O0~I/O7 CLE ALE WE RE CE RB VCC NC GND PIN NAME Address Input/Command Inputs/ Data Outputs Command Latch Enable Address Latch Enable Write Enable Read Enable Chip Enable READY, /BUSY pin Supply Voltage No Connection Ground MX23J12840 (Normal Type) ORDER INFORMATION Part No. MX23J12840TC-50G MX23J12840TC-50 MX23J12840TI-50G Package 48 pin TSOP (Pb-free, RoHS) 48 pin TSOP 48 pin TSOP (Pb-free, RoHS) Grade Commercial Commercial Industrial P/N:PM1097 REV. 1.2, OCT. 28, 2005 1 MX23J12840 BLOCK DIAGRAM Data Register Circuit I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Input/Output Buffer Sense Amplifier Address Register Y-Selector Command Register CE Control Logic X-Decoder Memory Cell Matrix CLE ALE WE RE READ Contorol Circuit READY/BUSY Control Circuit VCC RB (Open-drain) P/N:PM1097 REV. 1.2, OCT. 28, 2005 2 MX23J12840 MEMORY MAP 1 Page=528 Bytes 0 0 1 2 1 Block =32 Pages . . 30 31 . . . . . . . . . 32,765 32,766 32,767 512 Bytes (Main memory) . . . 255 256 . . . 511 . 527 (A) (B) (C) 1,024 Blocks =32,768 Pages 16 Bytes (Redundancy) * The start address (SA) during read operation is specified divided into three areas using three types of read commands. - In read mode (1), start address (SA) is set in area (A). - In read mode (2), start address (SA) is set in area (B). - In read mode (3), start address (SA) is set in area (C). One page consists of a total of 528 bytes broken down into 512 bytes (main memory) and 16 bytes (redundancy). One block consists of 32 pages. Caution The data of area (C) is redundancy, which is not programmable and is fixed to all FFH. P/N:PM1097 REV. 1.2, OCT. 28, 2005 3 MX23J12840 Operation Modes Command input, address input, and serial read are all performed from I/O pins, and the respective statuses are controlled by the CLE, ALE, WE, RE, and CE signals. Command input cycle Address input cycle Serial read cycle CLE CE WE ALE RE I/O0~ I/O7 RB Busy Operation mode Mode Command input cycle Address input cycle Serial read cycle CLE H L L ALE L H L CE L L L WE RE H H H Operation mode during serial read Mode Data output Output Hi-Z Standby Remark : VIH or VIL P/N:PM1097 REV. 1.2, OCT. 28, 2005 CLE L L L ALE L L L CE L L H WE H H H RE L H x I/O0 - I/O7 Data output Hi-Z Hi-Z 4 MX23J12840 Operation Commands The following six operation settings are possible by inputting commands from I/O pins. Command Read mode(1) Read mode(2) Read mode(3) Reset Note2 Note1 Hex 00 01 50 FF I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Command receivable during Busy L L L H L L H H L L L H L L H H L L L H L L L H L L L H L H L H Notes: 1. The data output in read mode (3) is all FFH. 2. The only command that can be executed when the device is Busy is the reset command. Do not set any of the other commands while the device is Busy. I/O Pin Correspondence Table during Address Input Cycle (Address Setting) (1) When 00H or 01H command is set [Read mode (1), Read mode (2)] Command 1st address cycle 2nd address cycle 3rd address cycle I/O7 A7 A16 X I/O6 A6 A15 A23 I/O5 A5 A14 A22 I/O4 A4 A13 A21 I/O3 A3 A12 A20 I/O2 A2 A11 A19 I/O1 A1 A10 A18 I/O0 A0 A9 A17 (2) When 50H command is set [Read mode (3)] Command 1st address cycle 2nd address cycle 3rd address cycle I/O7 X A16 X I/O6 X A15 A23 I/O5 X A14 A22 I/O4 X A13 A21 I/O3 A3 A12 A20 I/O2 A2 A11 A19 I/O1 A1 A10 A18 I/O0 A0 A9 A17 Remarks 1. A0 to A23 are internal addresses. 2. Internal address A8 is set internally with command 00H or 01H. 3. When 50H command is set [read mode (3)], the I/O4, I/O5, I/O6, and I/O7 inputs of the 1st address cycle are VIH or VIL. P/N:PM1097 REV. 1.2, OCT. 28, 2005 5 MX23J12840 Electrical Specifications Absolute Maximum Ratings Parameter Supply voltage Input voltage Input / Output voltage Operating ambient temperature Storage temperature Symbol VCC VI VI/O TA Tstg Condition Rating -0.5 to +4.6 -0.3 to VCC+0.3 -0.3 to VCC+0.3 (< 4.6) -40 to 85 -65 to +150 Unit V V V C C Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (TA = 25 C) Parameter Input capacitance Output capacitance Symbol CI CO Test condition f = 1 MHz MIN. TYP. MAX. 10 10 Unit pF pF DC Characteristics (TA = -40 to 85 C, VCC = 2.7~3.6V) Parameter High level input voltage Low level input voltage High level output voltage Low level output voltage Input leakage current Output leakage current Power supply current in read Standby current (CMOS) RB pin output current Symbol VIH VIL VOH VOL ILI ILO ICCO1 ICCS2 IOL(RB) IOH =-400uA IOL = 2.1 mA VI = 0 V to VCC VO = 0 V to VCC CE = VIL, IOUT =0 mA, tCYCLE = 50 ns CE = VCC-0.2 V VOL = 0.4 V 8 40 uA mA Test conditions MIN. 2.0 -0.3 2.4 0.4 10 10 30 TYP. MAX. VCC+0.3 +0.8 Unit V V V V uA uA mA P/N:PM1097 REV. 1.2, OCT. 28, 2005 6 MX23J12840 AC Characteristics (TA = -40 to 85 C, VCC = 2.7~3.6V) Parameter CLE setup time CLE hold time CE setup time CE hold time Write pulse width ALE setup time ALE hold time Data setup time Data hold time Write cycle time WE high hold time Ready to RE falling edge Read pulse width Read cycle time RE access time (serial data access) CE high hold time for last address in serial read cycle RE high to output Hi-Z CE high to output Hi-Z RE high hold time Output Hi-Z to RE falling edge WE high to RE low Memory cell array to starting address WE high to Busy ALE low to RE low (read cycle) RE last clock rising edge to Busy (in sequential read) CE high to Ready (when interrupted by CE in read mode) Device reset time Symbol tCLS tCLH tCS tCH tWP tALS tALH tDS tDH tWC tWH tRR tRP tRC tREA tCEH tRHZ tCHZ tREH tIR tWHR tR tWB tAR2 tRB tCRY tRST Note MIN. 0 10 0 10 25 0 10 20 10 50 15 20 35 50 TYP. MAX. Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 35 100 10 15 0 30 7 200 50 200 1 6 30 20 ns ns ns ns ns ns ns us ns ns ns us us Note :tCRY (time from CE to Ready) depends on the pull-up resister of the RB pin. P/N:PM1097 REV. 1.2, OCT. 28, 2005 7 MX23J12840 AC Test Conditions Input Waveform (Rise/Fall Time < 5ns) 1.5V Test points 1.5V Output Waveform 1.5V Test points 1.5V Input Pulse Levels : 0.4 ~ 2.4V Output Load : 1 TTL + 100pF P/N:PM1097 REV. 1.2, OCT. 28, 2005 8 MX23J12840 READ CYCLE TIMING CHART (1) (In case of read mode (1)) CLE tCLS tCLH CE tCS tWC tR tCEH WE tCRY tALH tALS tWP tWH tALH tAR2 tCHZ ALE tRR tRC tRC RE tRP tREH tRHZ tRHZ DOUT DOUT tWB tDS tDH tDS A0-A7 tDS A9-A16 tDS A17-A24 tDS A25 I/O0~ I/O7 00H DOUT N tDH tDH tDH tDH tREA N+1 527 tRB RB Access page M Output Page M Data Remarks: 1. Start address (SA) specification when read is performed with command 00H. N: 0 to 255 2. The time (tCRY) from CE high level until Busy is cancelled depends on the pull-up register of the RB output pin. P/N:PM1097 REV. 1.2, OCT. 28, 2005 9 MX23J12840 READ CYCLE TIMING CHART (2) (In case of read mode (2)) CLE tCLS tCLH CE tCS tWC tR tCEH WE tCRY tALH tALS tWP tWH tALH tAR2 tCHZ ALE tRR tRC tRC RE tRP tREH tRHZ tRHZ DOUT DOUT tWB tDS tDH tDS A0-A7 tDS A9-A16 tDS A17-A24 tDS A25 I/O0~ I/O7 01H DOUT 256+N tDH tDH tDH tDH tREA 256+N+1 527 tRB RB Access page M Output Page M Data Remarks 1. Start address (SA) specification when read is performed with command 01H. N: 0 to 255 2. The time (tCRY) from CE high level until Busy is cancelled depends on the pull-up register of the RB output pin. P/N:PM1097 REV. 1.2, OCT. 28, 2005 10 MX23J12840 READ CYCLE TIMING CHART (3) (In case of read mode (3)) CLE tCLS tCLH CE tCS tWC tR tCEH WE tCRY tALH tALS tWP tWH tALH tAR2 tCHZ ALE tRR tRC tRC RE tRP tREH tRHZ tRHZ DOUT DOUT tWB tDS tDH tDS A0-A3 tDS A9-A16 tDS A17-A24 tDS A25 I/O0~ I/O7 50H DOUT 512+N tDH tDH tDH tDH tREA 512+N+1 527 tRB RB Access page M Output Page M Data Remarks 1. Start address (SA) specification when read is performed with command 50H. N: 0 to 15 2. The start address of area C (redundancy data) is specified with A0 tp A3 during the 1st address cycle. At this time, A4 to A7 are Don't Care. 3. The time (tCRY) from CE high level until Busy is cancelled depends on the pull-up register of the RB output pin. P/N:PM1097 REV. 1.2, OCT. 28, 2005 11 MX23J12840 Sequential Read In read modes (1), (2), and (3), when a command (00H, 01H, 50H) is input and an address specified, if it is in the block that includes the address that was specified first, the address is automatically incremented and the read operation is continuously performed until the last address in the same block, by inputting the RE# clock. At this time, a Busy period (tR) occurs after the last address is accessed in a page. Note Command Address input input 00H 01H 50H Page M data output Page M+1 data output Output of in last page in block Command input 00H 01H 50H Note Address input Data output tR RB tR tR tR tCRY tR Busy Busy Busy Busy Busy Busy In same block (Maximum of 32 pages) Note :To perform read again after reading the 527th byte of data of the last page of block, stop the read operation once, and then restart the read operation by inputting again the read command and an address. Relationship Between Command and Start Address (SA) during Sequential Read (A) 0 256 (B) 512 (C) 527 (A) 256 (B) 512 (C) 527 (A) 256 (B) 512 SA SA SA (C) 527 1block =32 pages Sequential read mode (1) (When "00H" command is input) Sequential read mode (2) (When "01H" command is input) Note Sequential read mode (3) (When "50H" command is input) Note : When the "50H" command is set, only the (C) area (redundancy data part) is continuously read. * When the "00H" command is set, the start address (SA) is set to area (A). * When the "01H" command is set, the start address (SA) is set to area (B). * When the "50H" command is set, the start address (SA) is set to area (C). P/N:PM1097 REV. 1.2, OCT. 28, 2005 12 MX23J12840 SEQUENTIAL READ CYCLE TIMING CHART(1) (In case of read mode (1)) CLE tCLS tCLH CE tCS tWC tR WE tALH tALS tWP tWH tALH tAR2 ALE tRR tRC tRC RE tRP tREH tRHZ DOUT DOUT tWB tDS tDH tDS A0-A7 tDS A9-A16 tDS A17-A24 tDS A25 tR tRR I/O0~ I/O7 00H DOUT DOUT DOUT N tDH tDH tDH tDH tREA N+1 527 tRB 0 1 RB Access page M Output Page M Data Access page M+1 Output page M+1 data Remarks 1.Start address (SA) specification when read is performed with command 00H. N:0 to 255. P/N:PM1097 REV. 1.2, OCT. 28, 2005 13 MX23J12840 SEQUENTIAL READ CYCLE TIMING CHART(2) (In case of read mode (2)) CLE tCLS tCLH CE tCS tWC tR WE tALH tALS tWP tWH tALH tAR2 ALE tRR tRC tRC RE tRP tREH tRHZ DOUT DOUT tWB tDS tDH tDS A0-A7 tDS A9-A16 tDS A17-A24 tDS A25 tR tRR I/O0~ I/O7 01H DOUT DOUT DOUT 256+N tDH tDH tDH tDH tREA 256+N+1 527 tRB 0 1 RB Access page M Output Page M Data Access page M+1 Output page M+1 data Remarks 1.Start address (SA) specification when read is performed with command 01H. N:0 to 255. P/N:PM1097 REV. 1.2, OCT. 28, 2005 14 MX23J12840 SEQUENTIAL READ CYCLE TIMING CHART(3) (In case of read mode (3)) CLE tCLS tCLH CE tCS tWC tR WE tALH tALS tWP tWH tALH tAR2 ALE tRR tRC tRC RE tRP tREH tRHZ DOUT DOUT tWB tDS tDH tDS A0-A3 tDS A9-A16 tDS A17-A24 tDS A25 tR tRR I/O0~ I/O7 50H DOUT DOUT DOUT 512+N tDH tDH tDH tDH tREA 512+N+1 527 tRB 512 513 RB Access page M Output Page M Data Access page M+1 Output page M+1 data Remarks 1.Start address (SA) specification when read is performed with command 50H. N:0 to 15. P/N:PM1097 REV. 1.2, OCT. 28, 2005 15 MX23J12840 Reset Cycle Timing Chart CLE tCLS tCLH CE tCS tCH WE tRST tALS tWP tALH ALE tDS tDH I/O0~ I/O7 FFH tWB RB P/N:PM1097 REV. 1.2, OCT. 28, 2005 16 MX23J12840 [Usage Cautions] (1) Rated operation Operation using timing other than shown in the timing charts is not guaranteed. (2) Commands that can be input The only commands that can be input are 00H, 01H, 50H, and FFH. Do not input any other commands. If other commands are input, the subsequent operation is not guaranteed. (3) Command limitations during Busy period Do not input commands other than the reset command (FFH) during the Busy period. If a command is input during the Busy period, the subsequent operation is not guaranteed. (4) Cautions regarding RE clock * Following the last RE clock, do not input the RE clock until the RB pin changes from Busy to Ready. * Do not input the RE clock other than during data output. (5) Cautions upon power application Since the state of the device is undetermined upon power on, input high level to the CE pin and execute the reset command following power on. (6) Cautions during read mode * Perform address input immediately following command input. If address input is done without performing command input first, the correct data cannot be output because the operation mode is undetermined. * To execute the read mode after the read mode has been stopped with the reset command (FFH) and CE, input again a command and address. (7) Busy output following access of last address in page in read mode After the access to the last address in a page, if the delay (tRHCH) from RE to CE is 30 ns or less, the Ready status is maintained and Busy is not output by keeping CE high level for a set period (tCEH). tCEH CE tRHCH RE 526 527 RB P/N:PM1097 REV. 1.2, OCT. 28, 2005 17 MX23J12840 PACKAGE INFORMATION P/N:PM1097 REV. 1.2, OCT. 28, 2005 18 MX23J12840 REVISION HISTORY Revision # Description Page 1.0 1. Changed standby current from 100uA to 40uA P1,6 2. Removed "Advanced Information" P1 1.1 1. Added "Order Information" P1 1.2 1. Removed tWHC P7 2. Modified "Read cycle timing chart" and "Sequential read cycle timing P9~11 chart" P13~15 Date AUG/16/2005 SEP/06/2005 OCT/28/2005 P/N:PM1097 REV. 1.2, OCT. 28, 2005 19 MX23J12840 MACRONIX INTERNATIONAL CO., LTD. Headquarters: TEL:+886-3-578-6688 FAX:+886-3-563-2888 Europe Office : TEL:+32-2-456-8020 FAX:+32-2-456-8021 Hong Kong Office : TEL:+86-755-834-335-79 FAX:+86-755-834-380-78 Japan Office : Kawasaki Office : TEL:+81-44-246-9100 FAX:+81-44-246-9105 Osaka Office : TEL:+81-6-4807-5460 FAX:+81-6-4807-5461 Singapore Office : TEL:+65-6346-5505 FAX:+65-6348-8096 Taipei Office : TEL:+886-2-2509-3300 FAX:+886-2-2509-2200 MACRONIX AMERICA, INC. TEL:+1-408-262-8887 FAX:+1-408-262-8810 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. |
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