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DISCRETE SEMICONDUCTORS
DATA SHEET
PHN405 4 N-channel 60 m FET array enhancement mode MOS transistors
Product specification Supersedes data of 1997 Jun 19 File under Discrete Semiconductors, SC13 1998 Mar 17
Philips Semiconductors
Product specification
4 N-channel 60 m FET array enhancement mode MOS transistors
FEATURES * High-speed switching * No secondary breakdown * Very low on-state resistance * Current monitoring. APPLICATIONS * Motor and actuator driver * Power management * Synchronized rectification. DESCRIPTION Four enhancement mode MOS transistors in a 16-pin plastic SOT338-1 (SSOP16) package. Two transistors feature current monitoring (sense FETs). CAUTION The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. PINNING - SOT338-1 (SSOP16) PIN 1 and 4 2 3 5 and 8 6 7 9 10 11 and 15 12 13 14 16 SYMBOL d1 s1 g1 d2 s2 g2 g3 s3 d3 m3 g4 s4 m4
PHN405
DESCRIPTION drain 1 source 1 gate 1 drain 2 source 2 gate 2 gate 3 source 3 drain 3 current monitor 3 gate 4 source 4 current monitor 4
handbook, full pagewidth
d3
16
9
g4 m4 s4 d1
g3 m3 s3 d2
g1 1 8
g2
MAM276
s1
s2
Fig.1 Simplified outline and symbol.
1998 Mar 17
2
Philips Semiconductors
Product specification
4 N-channel 60 m FET array enhancement mode MOS transistors
QUICK REFERENCE DATA SYMBOL VDS VGS VGSth ID RDSon Ptot PARAMETER drain-source voltage (DC) gate-source voltage (DC) gate-source threshold voltage drain current (DC) drain-source on-state resistance total power dissipation ID = 1 mA; VDS = VGS Ts = 80 C ID = 2 A; VGS = 10 V Ts = 80 C CONDITIONS - - 1 - - - MIN.
PHN405
MAX. 30 20 2.8 3.7 60 1.4 V V V A
UNIT
m W
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL Per FET VDS VGS ID IDM Ptot drain-source voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation Ts = 80 C; note 1 note 2 Ts = 80 C; note 3 Ts = 80 C; note 4 Ts = 80 C; note 5 Tstg Tj IM IMM IS ISM Notes 1. Ts is the temperature at the soldering point of the drain lead. 2. Pulse width and duty cycle limited by maximum junction temperature. 3. When only one FET dissipates. 4. When either FETs 1 and 3 or 2 and 4 dissipate an equal amount of power. 5. When all four FETs dissipate an equal amount of power. storage temperature operating junction temperature Ts = 80 C note 2 Ts = 80 C note 2 - - - - - - - -55 -55 - - - - 30 20 3.7 14.8 1.4 1.25 1.09 +150 +150 V V A A W W W C C PARAMETER CONDITIONS MIN. MAX. UNIT
Current monitor monitor current (DC) peak monitor current 50 220 mA mA
Source-drain diode source current (DC) peak source current 1.4 5.6 A A
1998 Mar 17
3
Philips Semiconductors
Product specification
4 N-channel 60 m FET array enhancement mode MOS transistors
PHN405
handbook, halfpage
2
MDA804
Ptot (W)
10 2 handbook, halfpage ID (A) 10 (1)
MDA805
1.6
tp = 1 ms 10 ms
1.2 1 0.8
1
P 10
= T
tp DC
100 ms 1s
0.4 tp T 0 0 50 100 150 Ts (C) 200 10
2 1
t
10
1
10
VDS (V)
10 2
= 0.01; Ts = 80 C. (1) RDSon limitation.
Fig.2 Power derating curve.
Fig.3 SOAR.
THERMAL CHARACTERISTICS SYMBOL Per FET Rth j-s thermal resistance from junction to soldering point note 1 note 2 note 3 Notes 1. When only one FET dissipates. 2. When either FETs 1 and 3 or 2 and 4 dissipate an equal amount of power. 3. When all four FETs dissipate an equal amount of power. 50 56 64 K/W K/W K/W PARAMETER CONDITIONS VALUE UNIT
1998 Mar 17
4
Philips Semiconductors
Product specification
4 N-channel 60 m FET array enhancement mode MOS transistors
CHARACTERISTICS Tj = 25 C unless otherwise specified. SYMBOL Per FET V(BR)DSS VGSth IDSS IGSS RDSon Ciss Coss Crss QG QGS QGD td(on) tf ton td(off) tr toff drain-source breakdown voltage gate-source threshold voltage drain-source leakage current gate leakage current drain-source on-state resistance input capacitance output capacitance reverse transfer capacitance total gate charge gate-source charge gate-drain charge VGS = 0; ID = 10 A VGS = VDS ; ID = 1 mA VGS = 0; VDS = 24 V VGS = 20 V; VDS = 0 VGS = 4.5 V; ID = 1 A VGS = 10 V; ID = 2 A VGS = 0; VDS = 24 V; f = 1 MHz VGS = 0; VDS = 24 V; f = 1 MHz VGS = 0; VDS = 24 V; f = 1 MHz VDD = 15 V; ID = 1 A; VDD = 15 V; ID = 1 A; VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = 0 to 10 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGS = 10 to 0 V; VDD = 20 V; ID = 1 A; Rgen = 6 VGM = 10 V; ID = 25 mA; IS = 0 VGM = 4.5 V; ID = 12 mA; IS = 0 IS /IM CMoss source to monitor current ratio output capacitance of monitor cells VGS = 10 V; ID = 2 A; VMS = 0 VGM = VMS = 0; VDS = 24 V; f = 1 MHz 30 1 - - - - - - - - - - - - - - - - - - - - - 230 90 50 7.1 0.5 2.4 PARAMETER CONDITIONS MIN. TYP.
PHN405
MAX. - 2.8 100 100 120 60 - - - 10 - - - - 10 - - 30
UNIT
V V nA nA m m pF pF pF nC nC nC
VGS = 10 V; VDD = 15 V; ID = 1 A -
Switching times turn-on delay time fall time turn-on switching time turn-off delay time rise time turn-off switching time 3.5 3.5 7 12 8 20 ns ns ns ns ns ns
Current monitor RDMon on-state drain-monitor resistance - - - - - - 66.7 1.35 4 8 - - pF
Source-drain diode VSD trr source-drain diode forward voltage reverse recovery time VGD = 0; IS = 1.25 A IS = 1.25 A; di/dt = -100 A/s - - - 25 1 - V ns
1998 Mar 17
5
Philips Semiconductors
Product specification
4 N-channel 60 m FET array enhancement mode MOS transistors
PHN405
handbook, full pagewidth
VDD Vin RL Vout 0
90 %
10 %
90 % Vin Vout 10 % 0 td(on) tf
MAM274
td(off) tr toff
ton
Fig.4 Switching times test circuit with input and output waveforms.
102 handbook, full pagewidth Rth j-s (K/W) 10 =1 0.75 0.5 0.33 0.2 0.1 0.05 1 0.02 0.01
MDA797
10-1 0
P
= T
tp
tp T 10-2 10-6 10-5 10-4 10-3 10-2 10-1 1 tp (s)
t
10
Fig.5 Transient thermal resistance from junction to soldering point as a function of pulse time; typical values.
1998 Mar 17
6
Philips Semiconductors
Product specification
4 N-channel 60 m FET array enhancement mode MOS transistors
PHN405
handbook, halfpage
10
MDA799
VGS
handbook, halfpage
20 ID
MDA807
(V) 8
(A) 16
(1) (2)
(3)
6
12
(4)
4
8
(5)
2
4
(6) (7) (8)
0 0 2 4 6 QG (nC) 8
0 0 2 4 6 8 10 VDS (V)
Tamb = 25 C; tp = 80 s; = 0. (1) (2) (3) (4) VGS = 10 V. VGS = 7.5 V. VGS = 6 V. VGS = 5 V. (5) (6) (7) (8) VGS = 4.5 V. VGS = 4 V. VGS = 3.5 V. VGS = 3 V.
VDD = 15 V; ID = 1 A; Tamb = 25 C.
Fig.6
Gate-source voltage as a function of total gate charge; typical values.
Fig.7
Output characteristics; typical values.
handbook, halfpage
16
MDA798
handbook, halfpage
ID (A) 12
500 C (pF)
MDA806
400
300 8 200 4 100
Ciss
Coss Crss
0 0 2 4 VGS (V) 6
0 0 5 10 15 20 25 VDS (V)
VDS = 10 V; Tamb = 25 C; tp = 80 s; = 0.
VGS = 0 ; f = 1 MHz; Tj = 25 C.
Fig.9 Fig.8 Transfer characteristic; typical values.
Capacitance as a function of drain-source voltage; typical values.
1998 Mar 17
7
Philips Semiconductors
Product specification
4 N-channel 60 m FET array enhancement mode MOS transistors
PHN405
handbook, halfpage
8
MDA800
handbook, halfpage
10
MDA801
IS (A) 6
(1) (2) (3)
RDSon () 1
(1)(2)(3)(4)(5)(6)(7)(8)(9)
4 10-1 2
0 0 0.4 0.8 VSD (V) 1.2
10-2
0
2
4
6
8
10 VGS (V)
Tamb = 25 C; tp = 300 s; = 0. tp = 300 s; = 0. (1) Tamb = 150 C. (2) Tamb = 25 C. (3) Tamb = -65 C. (1) ID = 0.25 A. (2) ID = 0.5 A. (3) ID = 1 A. (4) ID = 2 A.
(5) (6) (7) (8) (9)
ID = 4 A. ID = 8 A. ID = 10 A. ID = 13 A. ID = 16 A.
Fig.10 Source current as a function of source-drain diode forward voltage; typical values.
Fig.11 Drain-source on-state resistance as a function of gate-source voltage; typical values.
1998 Mar 17
8
Philips Semiconductors
Product specification
4 N-channel 60 m FET array enhancement mode MOS transistors
PHN405
handbook, halfpage
1.2
MDA802
handbook, halfpage
1.8 k
MDA803
k
1
1.4
(1) (2)
0.8
1
0.6 -75
-25
25
75
125
175 Tj (C)
0.6 -75
-25
25
75
125
175 Tj (C)
R DSon at T j k = ---------------------------------------R DSon at 25 C V GSth at T j k = ------------------------------------V GSth at 25C VGSth at VDS = VGS; ID = 1 mA. RDSon at: (1) VGS = 10 V; ID = 2 A. (2) VGS = 4.5 V; ID = 1 A.
Fig.12 Temperature coefficient of gate-source threshold voltage as a function of junction temperature; typical values.
Fig.13 Temperature coefficient of drain-source on-resistance as a function of junction temperature; typical values.
1998 Mar 17
9
Philips Semiconductors
Product specification
4 N-channel 60 m FET array enhancement mode MOS transistors
PACKAGE OUTLINE SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
PHN405
SOT338-1
D
E
A X
c y HE vM A
Z 16 9
Q A2 pin 1 index Lp L 1 bp 8 wM detail X A1 (A 3) A
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.0 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 6.4 6.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 1.00 0.55 8 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC MO-150AC EIAJ EUROPEAN PROJECTION
ISSUE DATE 94-01-14 95-02-04
1998 Mar 17
10
Philips Semiconductors
Product specification
4 N-channel 60 m FET array enhancement mode MOS transistors
DEFINITIONS Data Sheet Status Objective specification Preliminary specification Product specification Limiting values
PHN405
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1998 Mar 17
11
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
Internet: http://www.semiconductors.philips.com
SCA57
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
135108/00/03/pp12
Date of release: 1998 Mar 17
Document order number:
9397 750 03251

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