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Peripheral Imaging Corporation PI3039 600DPI CIS Image Sensor Chip Engineering Data Sheet
TM
Description:
Peripheral Imaging Corporation PI3039 CIS (Contact Image Sensor) sensor chip is a linear array image sensor chip with a 600 elements per inch resolution. The sensor chip is fabricated with PIC's proprietary CMOS Image Sensing Technology. Since this image sensor chip is intended for CIS module applications, multiple numbers of these sensors will be serially cascaded to form a linear scanning image array of arbitrary length. These sensors are butted end-to-end on a printed circuit board (PCB). The sensors are mounted using the chip-onboard technology to form scanning arrays with various lengths
8080 m
1 2 3 4 189 190 191 192
ROW OF 192 SENSORS AND VIDEO SIGNAL LINE MULTIPLEXER
READ OUT SHIFT REGISTER
360 m
BUFFER
BUFFER
CHIP SELECT
BUFFER
SP
CP
VDD
VSS
IOUT
EOS
Figure 1. PI3039 Sensor Block Diagram
Figure 1 is a block diagram of the sensor chip. Each sensor chip consists of 192 detector elements, their associated multiplexing switches, buffer amplifiers, and a chip selector. The detector's elementto-element spacing is approximately 42m. The size of each chip without the scribe lines is 8080 m by 360 m. Each sensor chip has 6 bonding pads. The pad symbols and functions are described in Table 1.
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SYMBOL SP CP VDD VSS IOUT EOS
FUNCTION Start Pulse: Input to start the line scan. Clock Pulse: Input to clock the Shift Register. Positive Supply: +5 volt supply connected to substrate. VSS is tied to ground: Connection topside common Video Signal Current Output from a source follower. End of Scan Pulse: Output from the shift register at end of scan.
Table 1. Pad Symbols and Functions
8080 m
Read Line PI3039 IMAGE SENSOR, 192 PIXELS, 42 m PITCH
333 m
360 m EOS
SP
X X
CP
VDD
VSS
IOUT
Y
NOTE: ALL PAD OPENINGS ARE 140 X 80 m
FUNCTION START INPUT CLOCK INPUT +5 SUPPLY TIED TO GROUND VIDEO SIGNAL OUT SCAN OUTPUT Y 30 30 30 30 30 30 X 575 2195 3295 4373 5495 7272 NOTES: 1. THE DRAWING IS NOT TO SCALE. 2. THE DIE LENGTH AND WIDTH ARE GIVEN AS SHOWN. 3. THE PAD LOCATION ARE GIVEN IN THE TABLE. 4. THERE ARE 2 EXAMPLES OF THE X & Y LOCATIONS SHOWN ON THE FIRST 2 PADS. 5. ALL DIMENSIONS ARE IN m.
PAD SP CP VDD VSS IOUT EOS
Figure 2. Bonding Pad Layout Diagram:
Figure 2 shows the bonding pad locations for PI3039 Sensor Chip. The locations are referenced to the lower left corner of the die.
Electro-Optical Characteristics (25o C)
Table 2, below, lists the electro-optical characteristics of PI3039 sensor chip at 25o C.
Parameters Number of Photo-elements Pixel-to-pixel spacing Chip scanning rate Clock frequency IOUT (Saturation charge output for a given sample time) At 5.0 MHz clock frequency. Symbols Typical 192 42 38.4 5.0 170 to 200 Units elements m sec MHz pC Notes
Tint (1) fclk
(2)
@ typical 5 MHz pixel rate. See note 2. See note 2 With 570nm light source. At saturation exposure of 5.7 Joules/cm2
Qsat (3)
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Video Voltage Output from an A4 size CIS module, PI620MC-A4. (Four Tapped Outputs, for high speed application) Output voltage non-uniformity Chip-to-chip non-uniformity Dark output voltage Dark output non-uniformity
Vpavg (4)
1.0 0.300
Volts Volts
Up (5) Ucc Vd (6) Ud (6)
7.5 7.5 <50 <20
% % mV mV
Using a Red LED Source. Using a Yellow-Green LED Source. At minimum integration time @ 277 sec @ 5MHz clock rate. Test circuit used only the amplifier of note 4. Test circuit used only the amplifier in note 4. Test circuit see note 4 Test circuit see note 4
Table 2. Electro-Optical Characteristic
Notes:
1) Tint stands for the line scanning rate or the integration time. It is determined by the time interval between two start pulses. @the maximum clock rate of 6.5 MHz, Tint = 29.5 sec, 2) fclk stands for the input clock frequency: Maximum operating frequency is 6.5 MHz. 3) There are three types of signal outputs that are called out in the table. See under the section entitled, Output Circuits for Converting the Video Signal. The referenced section discusses each video output circuits. Two are defined for pulsed current, or charge processing, see Figure 4A, Virtual Ground Amplifier or see Figure 4C, Signal Current to Voltage Converter. The third is voltage output circuit, specified for most CIS (contact imaging sensors) application because its lower cost and simpler implementation advantages. See Figure 4B, Voltage Buffer Amplifier. 4) Specified for CIS application is a circuit with a buffer amplifier that interfaces the video output. See Figure 4B, Voltage Buffer Amplifier. This typical video output line is terminated with a commonly used standard op-amp circuit. It is located under the section entitled, Output Circuits for Converting the Video Signal. The PI227MC-A4 CIS module, employing this type of output circuit, was used in the measurements. Note a LED light source is an integral part of the module. 5) Up is the uniformity specification. It is measure with the image sensor exposed under a uniform light source. Up = [(Vpmax-Vpavg)/Vpavg]x100% Or [(Vpavg-Vpmin)/Vpavg]x100%, which ever is greater. Where Vpavg = a Vpn/Npixels Vpn is the nth pixels of sensor chip. Npixels is the total number of pixels in sensor chip. Vpmax is the maximum pixel output voltage in the light. Vpmin is the minimum pixel output voltage in the light. Note: In the light means the sensor is exposed to the light.
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6) Video output in dark:Vd = a Vdn/Npixels Note: In the dark means that sensor are placed on dark target and measured with the light off. 7) Uniformity in the dark: Ud = (Vdmax-Vdmin) Vdmax is the maximum pixel output voltage in the dark. Vdmin is the minimum pixel output voltage in the dark.
Absolute Maximum Ratings:
Parameters Power Supply Voltage Power Supply Current Input clock pulse (high level) Input clock pulse (low level) Symbol VDD IDD Vih Vil Maximum Rating 7.0 <3.0 Vdd + 0.5 -0.25 Units Volts ma Volts Volts
Table 3. Absolute Maximum Ratings
Environmental Ratings:
Operating Temperature Operating Humidity Storage Temperature Storage Humidity Top Hop Tstg Hstg 0 to 50 10 to 85 -25 to 75 10 to 90
o
C RH % o C RH %
Table 4. Absolute Maximum Ratings
Operating Range at Room Temperature
Parameters Power Supply Input clock pulses high level Input clock pulse low level Video Signal Current (Charge for given sample time) Clock Frequency Clock pulse duty cycle Clock pulse high durations Integration time Operating Temperature Symbols VDD Vih (1) Vil (1) Iout (2) fclk (3)(4) Dty (5) Tw Tint (6) Top Min 4.5 4.0 0 Typical 5.0 5.0 0 See note. 5.0 50 100 25 Max 5.5 VDD 0.8 Units Volts Volts Volts
0.1
6.5
29.54 50
MHz % nsec sec o C
Table 5. Recommended Operating Condition at Room Temperature Note 1) Applies to both CP and SP. 2) See note 3 under Table 2. 3) Although the clock frequency will operate the device at less than 100KHz, it is recommended that the device be operated above 500KHz. This recommendation is for long module length, such as the A4 size with 27 sequentially cascaded sensors. The long module at low clock rates has a long scan time. This results in a long photo integration time that generates leakage currents. The leakage currents randomly store arbitrary amounts of charges in the photo-site, contributing to the FPN in the dark.
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4) For fclk < 5.0 MHz, the clock duty cycle is typically 25 %. But at fclk = 5.0 MHz or higher a typical of 50% is recommended. This is to keep the die-to-die FPN, fixed pattern noise, to a minimum between die transitions in CIS operation. 5) Dty is the ratio of clock pulse width over the clock period. 6) Tint at the minimum integration time is specified with a maximum clock frequency of 6.5 MHz. This specification is for a single sensor. When multiple sensors are cascaded in series, this minimum integration time increases with each additional number of sensors.
Switching Characteristics @ 25o C.
Since these image sensors are applied in multiple-length line array with a wide range in scanning speeds, two types of output video amplifiers are used. Three video output circuits are discussed under the section entitled, Output Circuits for Converting the Video Signal. But there are only two basic types. One is current sensing amplifier and the other is charge storing buffer amplifier. Simplified block diagrams show their interface connections with the image sensors. They were also used to measure the specifications given in this data sheet. The timing relationships among these two different video signals and the image sensor's two input clocks, its start pulse, SP, its shift register clock, CP, and its shift register output, EOS, are shown in two diagrams, Figure 3A and its supplement, Figure 3B. The two timing diagrams are accompanied with two tables of timing symbol's specification. These symbols graphically define the timing relationships among the waveforms in the timing diagrams, see Figure 3A, Timing Diagram of the PI3039 Sensor. The switching specifications are given in Table 6A, Timing Symbol's Definition. Except for the analog video output, the rest are digital clock waveforms. Their levels are +5 Volts CMOS compatible. The video signal, Iout, timing is specified in Table 6A. Its amplitude was specified in Table 2, Electro-Optical Characteristics.
to
CP (CLOCK)
tprh
tw
tonoff
SP (START)
tdh
terdl tefdl tdtt
tds
IOUT (VIDEO CURRENT PULSE)
FIRST PIXEL LAST PIXEL
tdtp
EOS (END OF SCAN)
Figure 3A. Timing Diagram of the PI3039 Sensor (Uses Video Output Circuit in Figure 4B)
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Item Clock cycle time Clock pulse width Clock duty cycle Data setup time Data hold time Prohibit crossing time SP turn on and off EOS rise delay EOS fall delay Signal delay time to peak Signal fall time delay
Symbol to (1) tw (2) Dty (3) tds tdh Tprh (4) Tonoff(5) terdl tefdl tdtp(6) tftd(6)
Minimum 154 77 25 20 20
Mean
Maximum 10000 75
50
20 80 75 20 80
Units ns ns % ns ns ns Note 5 ns ns ns ns
Table 6A. Timing Symbol's Definition
Notes: 1. Minimum to is specified at the maximum clock frequency of 6.5MHz. 2. Since the clock pulse width varies with frequency, tw will vary according to duty cycle. This minimum is specified @ 6.5MHz and 50% duty cycle. 3. The clock duty cycle typically is 25 %. At 5.0 MHz or higher 50% is recommended. This recommendation is to keep the die-to-die FPN, fixed pattern noise, to a minimum between die transitions in CIS operation. 4. Tprh is the time where the start pulse high is prohibited. No consecutive falling clock edges are allowed during one cycle of SP. Otherwise, two start pulses or more will load into the shift register for each negative going clock edge. Multiple start pulses loaded into the shift register will access proportional numbers of multiple pixels simultaneously at each clock cycle. 5. The recommended time to start and stop the SP is between two consecutive rising clock edges, indicated by the tonoff arrows. 6. These values, tdtp and tftd, are measurements from the circuit in Figure 4B, which is essentially the pulse voltage across the 50 ohm resistor. This is one of circuit employed to convert the Video Signal current to voltage. See discussion on the two amplifier configurations under the section entitled, Output Circuits for Converting the Video Signal.
to
CP
tsmp
VIDEO OUTPUT
Dark Level Vd
Vp
tvf
Reset Level
Figure 3B. Supplement Timing Diagram
This supplementary timing diagram, Figure 3B, Supplement Timing Diagram, graphically defines the symbols used to describe timing relationship between the waveforms at the output
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of the Voltage Buffer Amplifier. The accompanying Table 6B, Timing Symbol's Definition, is on the next page. Cp is the same clock that is shown in Figure 3A. As in the Figure 3A, it is the reference for defining the video signal pulse times. Vp is the peak amplitude of the pixel when the image sensor is under light exposure. Vd is the dark level of the pixel when the image sensor has no light exposure. The Reset Level is during the time when image sensor is reset to ground with an external shunting switch, SW. Refer to any of the simplified block diagrams in the section under Output Circuits for Converting the Video Signal. The video line reset is active while Cp is high. The video signal charges video line with the falling edge of Cp. The shape of the video is a typical characteristic that is exhibited when the sensor current charges the video line capacitance. It continues to rise until it becomes asymptotic to a horizontal line. However for clock frequency >2.0MHz, the slope does not reach the asymptotic condition. Because of this ever-charging slope, the output voltage changes with the clock frequency and its duty cycle. Hence, there is no optimum point for the video pixel sampling position. Using an edge triggered sampling A/D with a very narrow aperture, the users of these CIS devices samples the signal as close to top of the waveform as possible. Although the optimum way is adjust the sampling position in the application, the following sampling time given in terms of clock-time ratio will provide a rule-of-thumb in setting the sampling time. By using the relationship below, the user can place the sampling clock within an acceptable range.
Tsmp [to x (1.0 - Dty) + Damp] where Dty is the clock duty cycle defined in above Table 6A. Item Clock Pulse Period Video Sample Time Amplifier Group Delay Video fall time Symbol to(1) tsmp (2) Damp (3) tvf Minimum 166 107 15 20 Mean 200 120 20 30 Maximum 10000 Units ns ns % ns
Table 6B. Supplement Timing Symbol's Definition Notes: 1) to is the clock cycle period with minimum set with 6.0 MHz. 2) tsmp has been previously defined above, with Dty=0.5 3) Damp is group delay time associated with the amplifier design in Figure 4C, Video Buffer Amplifier, EL2044 by Elantec.
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Output Circuits for Converting the Video Signals
This section discusses the test methods employed to measure the PI3039 image sensors video performance characteristics and serves as a reference for Table 2, notes 3 & 4. It also serves as an application note for implementing the PI3039 image sensors. The output of each sensor element in PI3039 image sensor is an emitter of a source follows. Accordingly, when its video output line is terminated into low impedance line, such as current amplifier in Figure 4A, the pulsed video signal currents proportional to photon integration time are produced. At high sampling frequency rate, these video current pulse widths are limited to the pixel sampling time. Hence, the output signal voltage is limited to the signal current pulse time and amplitude. Accordingly, the usual practice is to integrate this small signal charge instead of using a sensing resistor, RFB, in Figure 4A. In this case, RFB can be changed to a capacitor with a reset switch, thus converting the circuit to a Miller Integrator. The integrator will convert the charges to proportional signal voltages. However the disadvantage is in low-cost application, the cost is higher than just using single amplifier, as well as, the complexity for its implementation. Not to mention, that it will require a signal-inverting amplifier if a positive going signal is desired. But, kept in this simple resistor feedback form and, if the application can accept an inverted output voltage, this current-to-voltage amplifier can also implement a relatively low cost and simple circuit. Accordingly it is introduced and discussed as one of the three amplifier structures that can be used for the video output of the PI3039 device. The other amplifiers that will be discussed are configured as simple buffer amplifiers.
From all sensor video IOUT
RIN
0
RFB
Video Output
RESET SWITCH
SW OP-AMP
Figure 4A. Virtual Ground Amplifier
The first circuit is shown in Figure 4A. Virtual Ground Amplifier. The signal currents from the photo site is converted into voltage signal through its feedback resistor, while the photo-site output see a very close approximation to a ground because the input resistor value can be small enough to render the video line capacitance negligible, hence, providing a fast responding video samples. The first method is to use the video line capacitance as a charge storing capacitance. When the selected sensor's photo-site outputs its video signal current the video line reset switch, SW, is open. Then after the video is sampled by host system, SW closes and resets the video line and the photo-site that is presently under interrogation. Then
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it opens just prior to the next following pixel readout. This reset is active during CP's high state. The disadvantage of this circuit is that it has negative going output and will have pulse shape of the current impulse that decays over a long period. Hence, it may not be desirable at low clock sample frequencies. To get around this decaying type of sampling pixels, this second circuit may be more desirable. See Figure 4B, Voltage Buffer Amplifier. This method uses the video line as storage medium. It uses a buffer amplifier and buffers the video line with its high input impedance. Hence, the video line effectively approaches the condition of an open circuit and becomes a capacitance that is proportional to video line length and geometry. When the photo site produces the signal current, it charges the video line capacitance and converts the output into a voltage signal. The switch, SW, is a video line reset switch. It resets the video line and the photo-site presently under interrogation, just prior to the next following pixel readout. This reset is active during CP's high state. Figure 4B, Voltage Buffer Amplifier, shows the buffer amplifier configuration. The general video wave shape and timing characteristics of this circuit are discussed under section entitled Switching Characteristics @ 25o C. Figure 3B, Supplement Timing Diagram, shows the general signal wave shape and its timing relationship to the clock. Its accompanying Table 6B, Supplement Timing Symbol's Definition, defines the symbols used in the Figure 3B. This circuit is generally employed in CIS applications where the clock speeds are under 5.0MHz.
From all sensor video
OP-AMP
Video Output
IOUT
SW
RIN
RFB
Figure 4B. Voltage Buffer Amplifier
This video line charging implementation is extensively used because its simplicity and low cost. However, speed is limited because of the video line capacitance. For any given video line capacitance, the rate of signal charge remains the same, hence, the charging slope. As the sampling frequency is increased, the pixel's signal window decreases, reducing the amplitude and at very high frequency the video sample become triangular in shape. This effect is especially prevalent when longer line arrays are implemented. However, the CIS modules are cascaded structure of N Image sensors in series to form various lengths of line arrays. It is easy to see that as N increases the length of the video line on the PCB increases, thus, increasing the video line capacitance and making it difficult to extract the signal, especially, at high speeds.
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This third circuit is desirable for high-speed application, specifically, above 5.0 MHz. Again, a buffer amplifier is employed. It uses the same buffer stage as in the above second circuit. It has a positive-going output buffer amplifier, but instead of applying the video directly to the input of amplifier, it uses a small shunt-sensing resistor to ground. See Figure 4C, Signal Current To Voltage Converter. In this case, a small 50 ohms resistor load, low enough in impedance to allow the image sensor to effectively see a virtual ground, is employed. This low impedance minimizes the effect of video line capacitance. The signal is pulsed out as an impulse current. Accordingly, this signal current produces a fast rising signal voltage across the resistor, then the signal decays at a slightly slower rate. Accordingly, at high clock rates, the time duration is short enough for the impulse current to develop an approximated square wave voltage across the resistor. See Figure 3A, Timing of the PI3039 Sensor. Iout, the signal current across the 50 ohms is exemplified as a very fast rising and falling signal voltage pulse. The advantage of this circuit is its a positive going output signal, which it eliminates the need for the second inverter stage. In addition, although it is not recommend for low frequency operation, its low impedance video line lends to high-speed operation, above 5.0 MHz. Accordingly, this circuit offers the high-speed performance, in addition to, the cost and implementation advantage. Disadvantage is that since it senses the output on a 50W resistor, the signal-to-noise slightly less than the circuit that stores the signal charges on the video line.
From all sensor video
IOUT
OP-AMP
Video Output
50 ohms
SW
RIN
RFB
Figure 4C. Signal Current to Voltage Converter
(c)2002 Peripheral Imaging Corporation. Printed in USA. All rights reserved. Specifications are subject to change without notice. Contents may not be reproduced in whole or in part without the express prior written permission of Peripheral Imaging Corporation. Information furnished herein is believed to be accurate and reliable. However, no responsibility is assumed by Peripheral Imaging Corporation for its use nor for any infringement of patents or other rights granted by implication or otherwise under any patent or patent rights of Peripheral Imaging Corporation.
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