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| PLL102-10 Low Skew Output Buffer FEATURES * * * * * * * * Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs. Zero input - output delay. Less than 700 ps device - device skew. Less than 250 ps skew between outputs. Less than 100 ps cycle - cycle jitter. 2.5V or 3.3V power supply operation. Available in 8-Pin SOIC or MSOP package. PIN CONFIGURATION REFIN GND CLK1 CLK2 1 8 CLKOUT DNC DNC VDD PLL102-10 2 3 4 7 6 5 DESCRIPTION The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than 350 ps, the device acts as a zero delay buffer. BLOCK DIAGRAM REFIN PLL CLKOUT CLK1 CLK2 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/22/05 Page 1 PLL102-10 Low Skew Output Buffer PIN DESCRIPTIONS Name REFIN GND CLK1 CLK2 VDD DNC CLKOUT2 Number 1 2 3 4 5 6&7 8 Type I P O O P O Description Input reference frequency. Spread spectrum modulation on this signal will be passed to the output (up to 100kHz SST modulation). Ground Connection. Buffered clock output. Buffered clock output. 2.5V or 3.3V Power Supply connection. Do Not Connect Buffered clock output. Internal feed back on this pin. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) SYMBOL VDD VI VO TS TA TJ MIN. -0.5 -0.5 -65 -40 MAX. 4.6 VDD+0.5 VDD+0.5 150 85 125 260 UNITS V V V C C C C Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Electrical Characteristics PARAMETERS Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Supply Current SYMBOL VDD VIL VIH VOL VOH IDD CONDITIONS MIN. 2.25 2.0 TYP. MAX. 3.63 0.8 0.4 UNITS V V V V V mA IOL = 24mA IOH = 24mA Unloaded outputs at 100MHz, VDD=3.3V. 2.4 22 30 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/17/05 Page 2 PLL102-10 Low Skew Output Buffer 3. Switching Characteristics PARAMETERS Output Frequency Duty Cycle Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Device to Device Skew Cycle to Cycle Jitter PLL Lock Time Jitter; Absolute Jitter Jitter; 1-sigma SYMBOL t1 DC Tr Tf Tskew Tdelay Tdsk-dsk Tcyc-cyc Tlock Tjabs Tj1-s DESCRIPTION Measured at VDD/2, CL=15pF, Fout = 100MHz Measured between 10% and 90%VDD, CL=15pF Measured between 90% and 10%, CL=15pF All outputs equally loaded, CL=15pF Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of devices Measured at 100MHz Stable power supply, valid clock presented on REF pin At 10,000 cycles, low jitter input signal At 10,000 cycles, low jitter input signal MIN. 50 45 TYP. 50 1.2 1.2 MAX. 120 55 1.5 1.5 250 UNITS MHz % ns ns ps ps ps ps peak ms ps ps 0 0 350 700 60 1.0 20 9 50 15 SWITCHING WAVEFORMS Duty Cycle Timing t1 t2 VDD/2 VDD/2 VDD/2 VDD/2 Output - Output Skew Output VDD/2 Output TSKEW 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/17/05 Page 3 PLL102-10 Low Skew Output Buffer SWITCHING WAVE FORMS All Outputs Rise/Fall Time 2.0V 2.0V 0.8V tr tf 3.3V 0V Output 0.8V Input to Output Propagation Delay VDD/2 Input VDD/2 Output Tdelay Device to Device Skew VDD/2 Device1 CLKOUT VDD/2 Device2 CLKOUT Tdsk - dsk 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/17/05 Page 4 PLL102-10 Low Skew Output Buffer Output-Output Skew The skew between CLKOUT and the CLK(1-2) outputs is not dynamically adjusted by the PLL. Since CLKOUT is one of the inputs to the PLL, zero phase difference is maintained from REF to CLKOUT. If all outputs are equally loaded, zero phase difference will be maintained from REF to all outputs. If applications requiring zero output-output skew, all the outputs must be equally loaded. If the CLK(1-2) outputs are less loaded than CLKOUT, CLK(1-2) outputs will lead it; if the CLK(1-2) is more loaded than CLKOUT, CLK(1-2) will lag the CLKOUT. Since the CLKOUT and the CLK(1-2) outputs are identical, they all start at the same time, but difference loads cause them to have different rise times and different times crossing the measurement thresholds. REF CLKOUT CLK(1-2) Zero Delay REF input and all outputs are equally loaded REF CLKOUT CLK(1-2) REF input and CLK(1-2) outputs are equally loaded, with CLK(1-2) less loaded than CLKOUT. Advanced REF CLKOUT CLK(1-2) Delayed REF input and CLK(1-2) outputs loaded equally, withCLK(1-2) more loaded then CLKOUT. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/17/05 Page 5 PLL102-10 Low Skew Output Buffer PACKAGE INFORMATION SOIC 8L Symbol A A1 A2 B C D E H L e Dimension in MM Min. Max. 1.35 1.75 0.10 0.25 1.25 1.50 0.33 0.53 0.19 0.27 4.80 5.00 3.80 4.00 5.80 6.20 0.40 0.89 1.27 BSC E H D A2 A A1 e b C L ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL102-10 S C PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRIAL PACKAGE TYPE S=SOICI Order Number PLL102-10SC-R PLL102-10SC Marking P102-10SC P102-10SC Package Option SOIC - Tape and Reel SOIC - Tube PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/17/05 Page 6 |
Price & Availability of PLL102-10SC-R
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