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1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
S5K711CA, S5K711LA (1/7" CIF CMOS Image Sensor)
Preliminary Specification Revision 0.2 Apr. 2002
1
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
DOCUMENT TITLE
1/7" Optical Size 352x352(CIF) 3.3V/2.8V CMOS Image Sensor
REVISION HISTORY
Revision No. 0.0 0.1 0.2 History Initial Draft Pin description error corrected (LHOLD polarity). Timing chart added. STRB signal polarity error corrected SFCM timing diagram corrected Operation description added. Draft Date Remark
Feb. 16, 2002 Preliminary Feb. 21, 2002 Preliminary Apr. 10, 2002 Preliminary
2
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
INTRODUCTION
The S5K711CA and S5K711LA are highly integrated single chip CMOS image sensors fabricated by SAMSUNG 0.35m CMOS image sensor process technology. It is developed for imaging application to realize high-efficiency and low-power photo sensor. The sensor has 352 x 352 effective pixels with 1/7 inch optical format. The sensor has on-chip 8-bit ADC blocks to digitize the pixel output and also on-chip CDS to reduce Fixed Pattern Noise (FPN) drastically. With its few interface signals and 8-bit raw data directly connected to the external devices, a camera system can be configured easily. S5K711CA is suitable for a camera system with standard 3.3V logic operation and S5K711LA is suitable for low power camera module with 2.8V power supply.
FEATURES
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Process Technology: 0.35m DPTM CMOS Optical Size: 1/7 inch Unit Pixel: 5.6 m X 5.6 m Effective Resolution: 352X352, CIF Line Progressive Read Out. 8-bit Raw Image Data Output Programmable Exposure Time Programmable Gain Control Auto Dark Level Compensation Windowing and Panning Sub-Sampling (2X, 3X, 4X) Cotinuous and Single Frame Capture Mode Standby-Mode for Power Saving Maximum 70 Frame per Second Bad Pixel Replacement Single Power Supply Voltage: 3.3V or 2.8V Package Type: 32-CLCC/PLCC
PRODUCTS
Product Code S5K711CA01 S5K711LA01 S5K711CA02 S5K711LA02 S5K711CA03 S5K711LA03 Power Supply 3.3 V 2.8 V 3.3 V 2.8 V 3.3 V 2.8 V Backend Process None On-chip micro lens On-chip color filter and micro lens Description Monochrome image sensor High sensitivity monochrome Image sensor RGB color image sensor
3
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
BLOCK DIAGRAM
VDDD VSSD
MCLK
Main Clock Divider
8-bit Column ADC Odd Column CDS DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0
VSYNC HSYNC DCLK
Active Pixel Sensor Array
Control Registers SCL SDA
Even Column CDS 8-bit Column ADC
I C Interface
2
4
Processing
RSTN STBYN STRB LHOLD
Row Driver
Timing Generator
VDDA VSSA
Post
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
BLOCK DIAGRAM (TOP VIEW ON CHIP. DISPLAYED IMAGE WILL BE FLIPPED.)
Active Pixels 8 6
Optical Black Pixels
Effective Active Pixel 352X352
10
4
G R G R G R G R
B G B G B G B G
G R G R G R G R
B G B G B G B G
G R G R G R G R
B G B G B G B G
G R G R G R G R
B G B G B G B G
G R G R G R G R
B G B G B G B G
G R G R G R G R
B G B G B G B G
4
30
(14,14) read out start point 6 (0,0) 8
5
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
PIN CONFIGURATION
VDDA
MCLK
VSSD
4
3
2
1
32
31
30
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7
5 6 7 8 9 10 11 12 13 14 First Readout Pixel
29 28 27 26 25 24 23 22 21 20
RSTN
VSSA
(NC)
SDA
SCL
STBYN VSSA VDDA STRB LHOLD VDDA VSSA TEST2
15
16
17
18 HSYNC
VSYNC
VDDD
VDDA
(NC)
VSSA
DCLK
19
6
TEST1
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
MAXIMUM ABSOLUTE LIMIT
Characteristic Operating voltage (VDDD, VDDA supply relative to VSSD, VSSA) Input voltage Operating temperature Storage temperature VDD VIN TOPR TSTG -0.3 to 3.8 -0.3 to VDD+0.3 (Max. 3.8) -20 to +60 -40 to +125(1) -40 to +85(2)
NOTES: 1. The maximum allowed storage temperature for S5K711C(L)X01. 2. The maximum allowed storage temperature for S5K711C(L)X02 and S5K711C(L)X03.
Symbol
Value
Unit V
C
7
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
ELECTRICAL CHARACTERISTICS DC Characteristics (TA = -20 to +60C, CL = 15pF) Characteristics Operating voltage
(1)
Symbol VDD VIH VIL IIL IILD VOH VOL IOZ ISTB IDD
Condition VDDD, VDDA VIN = VDD to VSS VIN = VDD IOH = -1A IOH = -4mA IOL = 1A IOL = 4mA VOUT = VDD STBYN=Low(Active) All input clocks = Low fMCLK = 12 MHz 0 lux illumination VDD = 3.3V (7) VDD = 2.8V (8)
Min 3.0 2.55 0.8VDD 0 -10 10 VDD-0.05 2.4 -
Typ 3.3 2.8 30 27 18
Max 3.6 3.05 0.2VDD 10 60 0.05 0.4 10 5 -
Unit V
Input voltage
Input leakage current(2) Input leakage current with pull-down(3) High Level Output voltage (4) Low Level Output voltage (5) High-Z output leakage current (6) Supply current
A
V
A A mA
NOTES: 1. Applied to MCLK, RSTN, STBYN, STRB, SCL, SDA, TEST1, TEST2 pin. 2. MCLK, RSTN, STBYN, STRB, SCL, SDA pin 3. TEST1, TEST2 pin 4. DCLK, HSYNC, VSYNC, DATA0 to DATA7 pin 5. DCLK, HSYNC, VSYNC, DATA0 to DATA7, SCL, SDA pin 6. SDA pin when in High-Z output state 7. S5K711CA 8. S5K711LA
8
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
Imaging Characteristics (Light source with 3200K of color temperature and IR cut filter (CM-500S, 1mm thickness) is used. Electrical operating conditions follow the recommended typical values. The control registers are set to the default values. TA = 25C if not specified.) Characteristic Saturation level(1) Sensitivity(2) Symbol VSAT S Condition S5K711CA S5K711LA S5K711(C,L)X01 S5K711(C,L)X02 S5K711(C,L)X03 Dark level(3) VDARK TA = 40C TA = 60C Dynamic range(4) Signal to noise ratio(5) Dark signal non-uniformity(6) Photo response nonuniformity(7) Vertical fixed pattern noise(8) Horizontal fixed pattern noise(9) DR S/N DSNU PRNU VFPN HFPN TA = 60C Min 950 850 Typ 1000 900 1500 4000 1500 9 50 48 40 4 4 4 Max 18 100 100 8 8 8 mV/sec % % % dB mV/sec mV/lux sec Unit mV
NOTES: 1. Measured minimum output level at 100 lux illumination for exposure time 1/30 sec. 7X7 rank filter is applied for the whole pixel area to elemiate the values from defective pixels. 2. Measured average output at 25% of saturation level illumination for exposure time 1/30 sec. Green channel output values are used for color version. 3. Measured average output at zero illumination without any offset compensation for exposure time 1/30 sec. 4. 20 log (saturation level/ dark level rms noise excluding fixed pattern noise). 48dB is limited by 8-bit ADC. 5. 20 log (average output level/rms noise excluding fixed pattern noise) at 25% of saturation level illumination for exposure time 1/30 sec. 6. Difference between maximum and minimum pixel output levels at zero illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to elemiate the values from defective pixels. 7, Difference between maximum and minimum pixel output levels divided by average output level at 25% of saturation level illumination for exposure time 1/30 sec. 7X7 median filter is applied for the whole pixel area to elemiate the values from defective pixels. 8. For the column-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec. 9. For the row-averaged pixel output values, maximum relative deviation of values from 7-depth median filtered values for neighboring 7 columns at 25% of saturation level illumination for exposure time 1/30 sec.
9
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
AC Characteristics (VDD = 3.0V to 3.6V for S5K711CA, VDD = 2.55V to 3.05V for S5K711LA, Ta = -20 to + 60 C, CL = 50pF) Characteristic Main input clock frequency Data output clock frequency Propagation delay time from main input clock Symbol fMCLK fDCLK tPDMV tPDMH tPDMD tPDMO Propagation delay time from data output clock tPDDV tPDDH tPDDO Reset input pulse width Standby input pulse width tWRST tWSTB Condition Duty = 50% VSYNC output HSYNC output DCLK output DATA output VSYNC output HSYNC output DATA output RSTN=low(active) STBYN=low(active) Min 6 2 5 4 Typ 12 6 Max 30 15 20 20 15 20 10 5 5 TMCLK(1) ns Unit MHz
NOTES: 1. The period time of main input clock, MCLK.
I2C Serial Interface Characteristics Characteristic Clock frequency Clock high pulse width Clock low pulse width Clock rise/fall time Data set-up time Data hold time START condition hold time STOP condition setup time STOP to new START gap Capacitance for each pin Capacitive bus load Pull-up resistor Symbol fSCK tWH tWL tR/tF tDS tDH tSTH tSTS tGSS CPIN CBUS RPU Condition SCK SCK SCK, SDA SDA to SCK SDA to SCK SCL, SDA SCL, SDA SCL, SDA to VDD Min 800 1000 300 1200 4 4 8 1.5 4 200 10 k pF Typ Max 400 300 TMCLK Unit kHz ns
10
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
PIN DESCRIPTION Table 1. Pin Description Pin No VDDD (16) VSSD (1) VDDA (3, 14, 23, 26) VSSA (2, 15, 22, 27) MCLK (32) RSTN (29) STBYN (28) LHOLD (24) I/O Power Power Power Power I I I I Master clock Reset Standby Line hold Analog power supply Name Digital power supply Function For I/O circuit and logical circuit ( VDD 10% ) 0V (GND) For analog circuit ( VDD 10% ) 0V (GND) Master clock pulse input for all timing generators. Initializing all the device registers. (Active low) Activating power saving mode. ( high=normal operation, low=power saving mode ) Asserting the device to hold line progress for zoomed image output. ( low= line holding, high= normal operation) Triggering the integration start and stop when single frame capture mode. 8-bit image data outputs. When ADC resolution is reduced, the unused lower bits are set to 0. Image data output synchronizing pulse output. Horizontal synchronizing pulse or data valid signal output. Vertical synchronizing pulse or line valid signal output. I2C serial interface clock input I2C serial interface data bus (external pull-up resistor required) Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins. Test input signal. Though it can be opened in normal operation (internally pulled down), it is recommended to ground the test pins.
STRB (25) DATA0~DATA7 (5~12) DCLK (17) HSYNC (18) VSYNC (19) SCL (31) SDA (30) TEST1 (20)
I O O O O I I/O I
Strobing Image data output Data clock Horizontal sync clock Vertical sync clock Serial interface clock Serial interface data Test input 1
TEST2 (21)
I
Test input 2
11
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
Control Registers Address (Hex) 00h Reset Value 00h Bits [5] [4] [3] [2] [1] [0] 01h 10h [7] [6] [5:4] Mnemonic sckinv idinv bprm dlcm ccsm shutc mircv mirch mcdiv Description (Factory use only) Column color inversion (Factory use only) Line color inversion Bad pixel replacement mode 0b: disabled (default), 1b: enabled Dark level compensation mode 0b: manual (default), 1b: auto Color channel separation mode 0b: not separated (default), 1b: separated Electronic shutter mode 0b: disabled (default), 1b: enabled Vertical mirror control 0b: normal (default), 1b: mirrored Horizontal mirror control 0b: normal (default), 1b: mirrored Main clock divider 00b: DCLK=MCLK, 01b: DCLK=MCLK/2 (default) 10b: DCLK=MCLK/4, 11b: DCLK=MCLK/8 [3:2] subsr Row subsampling mode 00b: disabled (default), 01b: 2X, 10b: 3X, 11b: 4X [1:0] subsc Column subsampling mode 00b: disabled (default), 01b: 2X, 10b: 3X, 11b: 4X 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 00h 0Eh 00h 0Eh 01h 20h 01h 60h 80h [0] [7:0] [0] [7:0] [0] [7:0] [1:0] [7:0] [7:0] wrp_high wrp_low wcp_high wcp_low wrd_high wrd_low wcw_high wcw_low offsdef Row start point for window of interest wrp[8:0] = 14d(default) Column start point for window of interest wcp[8:0] = 14d(default) Row depth for window of interest wrd[8:0] = 288d(default) Column width for window of interest wcw[9:0] = 352d(default) (Factory use only) Analog offset reference offsdef[7:0] = 128d (default)
12
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
Address (Hex) 0Bh
Reset Value 01h
Bits [3] [2:0]
Mnemonic sfcen sint_high sint_low cintr_high cintr_low cintc_high cintc_low vswd vspolar vsdisp vsstrt_high vsstrt_low vblank_high vblank_low hswd hspolar hsdisp hsstart_high hsstart_low hblank_high hblank_low
Description Single frame capture enable 0b: disabled (default), 1b: enabled Integration time in single frame capture mode sint[10:0] = 399d (default) Row-step integration time in continuous frame capture mode cintr[11:0] = 199d (default) Column-step integration time in continuous frame capture mode cintc[12:0] = 0d (default) VSYNC width vswd[7:0] = 1d (default) VSYNC polarity 0: active high (default), 1: active low VSYNC display mode 0: sync mode (default), 1: data valid mode VSYNC start position vsstrt[9:0] = 0d (default) Vertical blank depth vblank[11:0] = 111d (default) HSYNC width hswd[7:0] = 32d (default) HSYNC polarity 0: active high (default), 1: active low HSYNC display mode 0: sync mode (default), 1: data valid mode HSYNC start position hsstrt[9:0] = 0d (default) Horizontal blank depth hblank[13:0] = 148d (default)
0Ch 0Dh 0Eh 0Fh 10h 11h 12h
8Fh 00h C7h 00h 00h 01h 00h
[7:0] [3:0] [7:0] [4:0] [7:0] [7:0] [5] [4] [1:0]
13h 14h 15h 16h 17h
00h 00h 6Fh 20h 00h
[7:0] [3:0] [7:0] [7:0] [5] [4] [1:0]
18h 19h 1Ah
00h 00h 94h
[7:0] [5:0] [7:0]
13
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
Address (Hex) 1Bh
Reset Value 77h
Bits [3:0] [7:4]
Mnemonic sgg1 sgg2 sgg3 sgg4 pgcr pgcg1
st
Description 1 sectional global gain sgg1[3:0] = 7d (default) 2 sectional global gain sgg2[3:0] = 7d (default) 3 sectional global gain sgg3[3:0] = 7d (default) 4 sectional global gain sgg4[3:0] = 7d (default) Red channel gain pgcr[6:0] = 0d (default) Green(Red row) channel gain or all channel gain (ccsm=0) pgcg1[6:0] = 0d (default) Green(Blue row) channel gain pgcg2[6:0] = 0d (default) Blue channel gain pgcb[6:0] = 0d (default) Red channel analog offset offsr[7:0] = 128 (default) Green(Red row) channel analog offset or all channel offset (ccsm=0) offsg1[7:0] = 128 (default) Green(Blue row) channel analog offset offsg2[7:0] = 128 (default) Blue channel analog offset offsb[7:0] = 128 (default) Bad pixel threshold pthresh[6:0] = 20d (default) ADC offset adcoffs[7:0] = 0d (default) (Factory use only) Reset clipping enable (Factory use only) P12 start control
th rd nd
1Ch
77h
[3:0] [7:4]
1Dh 1Eh
00h 00h
[6:0] [6:0]
1Fh 20h 21h 22h
00h 00h 80h 80h
[6:0] [6:0] [7:0] [7:0]
pgcg2 pgcb offsr offsg1
23h 24h 25h 26h
80h 80h 14h 00h
[7:0] [7:0] [6:0] [7:0]
offsg2 offsb pthresh adcoffs
27h
01h
[4] [3:0]
clipen p12stp
14
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
Address (Hex) 28h 29h 2Ah 2Bh
Reset Value 40h 00h 00h 02h
Bits [7:5] [4:0] [7:0] [7:0] [3] [2] [1] [0]
Mnemonic stbystrt stbystp rxstrt blank vtest htest i2ctest nandtree
Description (Factory use only) Stand-by start (Factory use only) Stand-by stop (Factory use only) Reset start control Blank register for general purpose (Factory use only) Vertical function test mode (Factory use only) Horizontal function test mode (Factory use only) IIC test mode (Factory use only) NAND tree test mode
15
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
OPERATION DESCRIPTION
1. Output Data Format 1-1. Main Clock Divider All the data output and sync signals are synchronized to data clock output (DCLK). It is generated by dividing the input main clock (MCLK). The dividing ratio is 1, 2, 4, and 8 according to main clock dividing control register (mcdiv). If ratio of 1 is used, the duty must be within 40% to 60%. 1-2. Synchronous Signal Output The horizontal sync(HSYNC) and vertical sync(VSYNC) signals are also available. The sync pulse width, polarity and position are programmable by control registers (ref. timing chart). When display mode is enabled, the sync signal outputs indicate that the output data is valid (hsdisp=1) or the output rows are valid (vsdisp=1). 1-3. Window of Interest Control Window of Interest (WOI) is defined as the pixel address range to be read out. The WOI can be assigned anywhere on the pixel array. It is composed of four values: row start pointer(wrp), column start pointer(wcp), row depth(wrd) and column width(wcw). Each value can be programmed by control registers. For convenience of color signal processing, wcp is truncated to even numbers so that the starting data of each line is the red and green column of Bayer pattern. Figure 4 refers to a pictorial representation of the WOI on the displayed pixel 0 0 (wcp,wrp) wcw 400
Window Of Interest wrd
380 image. Figure 4. WOI definition. 1-4. Vertical Mirror and Horizontal Mirror Mode Control The pixel data are read out from left to right in horizontal direction and from top to bottom in vertical direction normally. By changing the mirror mode, the read-out sequence can be reversed and the resulting image can be flipped like a mirror image. Pixel data are read out from right to left in horizontal mirror mode and from bottom to top in vertical mirror mode. The horizontal and the vertical mirror mode can programmed by Horizontal Mirror Control Register (mirch) and Vertical Mirror Control Register (mircv). 1-5. Sub-sampling Control The user can read out the pixel data in sub-sampling rate in both horizontal and vertical direction. Sub-sampling can be done in four rates : full, 1/2, 1/3 and 1/4. The user controls the sub-sampling using the Sub-sampling Control Registers, subsr and subsc. The sub-sampling is performed only in the Bayer space.
16
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG subsr=01b, subsc=01b
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG GRGRGRGRGR BG BG BG BG BG subsr=00b, subsc=11b
G B G B G B G B G B G B G B G B
R G R G R G R G R G R G R G R G
G B G B G B G B G B G B G B G B
Figure 5. Bayer Space Sub-Sampling Examples 1-6. Line Rate and Frame Rate Control (Virtual Frame) The line rate and the frame rate can be changeable by varying the size of virtual frame. The virtual frame' width s and depth are controlled by effective WOI and blank depthes. The effective WOI is scaled by the subsampling factors from WOI set by register values. For CDS and ADC function, the virtual column width must be larger than 256/(2^mcdiv)+180. The resulting frame time and line time which are inverse of frame rate and line rate are represented by following equations: 1 frame time = { wrd / (subsr+1) + vblank } * (1 line time) 1 line time = { wcw / (subsc+1) + hblank } * (DCLK period) 1-7. Continuous Frame Capture Mode(CFCM) Integration Time Control (Electronic Shutter Control) In CFCM operation, the integration time is controlled by shutter operation. The shutter operation is done when shutter control register (shutc) is set to "1". In shutter operation, the integration time is determined by the Row Step Integration Time Control Register(cintr) and Column Step Integration Time Control Register(cintc). The resulting integration time is expressed as; Integration Time = (cintr - 1) * (1 line time) + (cintc +110) * (DCLK period) where cintr = 1 to { wrd / (subsr+1) + vblank }, cintc = 0 to { wcw / (subsc+1) + hblank -180 }. 1-8. Single Frame Capture Mode(SFCM) Integration Time Control To capture a still image, SFCM can be set by Single Frame Capture Enable Register(sfcen). Rolling shutter mode is implemented. The integration time is controlled by SFCM Integration Time Register (sint). The light integration period for each rows progresses with reading rows. The integration time is expressed as : Integration Time = sint * (1 line time)
17
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
2. Analog to Digital Converter ( ADC) The image sensor has on-chip ADC. Two-channel column parallel ADC scheme is used for separated color channel gain and offset control. 2-1. ADC resolution The ADC resolution is fixed to 8bit. 2-2. Correlated Double Sampling ( CDS ) The analog output signal of each pixel includes some temporal random noise caused by the pixel reset action and some fixed pattern noise by the in-pixel amplifier offset deviation. To eliminate those noise components, a correlated double sampling(CDS) circuit is used before converting to digital. The output signal sampled twice, once for the reset level and once for the actual signal level sampling. 2-3. Programmable Gain and Offset Control The user can controls the gain of individual color channel by the Programmable Gain Control Registers (pgcr, pgcg1, pgcg2, pgcb) and offset by Offset Control Registers (offsr, offsg1, offsg2, offsb). If the Color Channel Separation Mode is disabled (ccsm=0), pgcg1 and offsg1 change the gains and offsets for all channels. As increasing the gain control register, the ADC conversion input range decreases and the gain increased as following equation: Channel Gain = 128 / (128 - Programmable Gain Control Register Value[6:0]) R G1 R G1 G2 B G2 B R G1 R G1 G2 B G2 B
10 9 8
45 40 35
Relative Channel Gain
6 5 4 3 2 1 0 16 32 48 64 80 96 112 128
Channel Gain (dB)
7
30 25 20 15 10 5 0 0 16 32 48 64 80 96 112 128
Programmable Gain Control
Programmable Gain Control
Figure 6. Relative Channel Gain
18
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
2-4. Quadrisectional Global Gain Control The user can controls the global gain to change the gain for all color channels by the Global Gain Control Registers (sgg1, sgg2, sgg3, sgg4). The global gain control register is composed of four register groups and each register value decides the gain for each quarter section of output code level. Global Gain = (sgg[3:0]+1) / 8
2.0 1.8 1.6
10
5
Relative Global Gain
1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0 2 4 6 8 10 12 14 16
Glabal Gain (dB)
0
-5
-10
-15
-20 0 2 4 6 8 10 12 14 16
P r o g r a m m able G a i n C o n t r o l
P r o g r a m m a b le G a i n C o n t r o l
Figure 7. Relative Global Gain The ADC gain is dependent on MCLK frequency (not on DCLK frequency). The default global gain is set for typical MCLK frequency (12MHz). When the frequency is changed, the global gain should be changed to maintain the resulting gain over unity for assuring appropriate ADC conversion range.
15 14 13 12 11
Minimum Glabal Gain
10 9 8 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 MCLK frequency (MHz)
19
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
Figure 8. Recommended Minimum Global Gain Control Value By appropriately programming these four register values, the different output resolution according to the signal can be achieved and the intra-scene dynamic range can be increased by 16 times. In another application, the sectional global gain control can be used as a rough gamma correction with four sectional linear approximation curve as shown in Figure 9.
sgg1
sgg2
sgg3
sgg4
sgg1=1111b sgg2=0111b sgg3=0011b sgg4=0000b
ADC input signal
sgg1=0111b sgg2=0111b sgg3=0111b sgg4=0111b
0
63
127
191
255
ADC output code at 8-bit resolution
Figure 9. Quadrisectional Glabal Gain Control
3. Post Processing 3-1. Dark Level Compensation The dark level of Image sensor is defined as average output level without illumination. It includes pixel ouput caused by leakage current of the photodiodes and ADC offset. To compensate the dark level, the output level of optical black(OB) pixels can be a good reference value. When Auto Dark Level Compensation Register (dlcm) is set, the image sensor detects the OB pixel level at the start of every frame and anglog-to-digital conversion range is shifted to compensate the dark level for that frame. So, the resulting output data of that frame will be almost zero under dark state. If user wants the dark level which is not zero, the ADC Offset Register (adcoffs) can be used. The lower 7-bit value represent the offset value in outout code for compensation and the MSB is the sign to define whether the offset is positive (adcoffs[7]=0) or negative (adcoffs[7]=1). When not in auto dark level compensation mode, the adcoffs[7:0] act as a output code value to subtract the output image data. Please notify that the all the 8-bit data are used for an offset value without sign bit. 3-2. Bad Pixel Replacement When the Bad Pixel Replacement Register (bprm) is enabled, the image sensor check that the image data is less or greater than horizontally neighboring pixels in same color channel by the preset threshold value (pthresh). If satisfied, the output of the pixel is replaced by the averaged value of the neghiboring two pixels. The detectable defected pixels are rare and the bad pixel replacement action can remove defected image effectively. But it reduces the line resolution in horizontal direction.
20
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
4. I C Serial Interface The I C is an industry standard serial interface. The I C contains a serial two-wire half duplex interface that features bi-directional operation, master or slave mode. The general SDA and SCL are the bi-directional data and clock pins, respectively. These pins are open-drain type ports and will require a pull-up resistor to VDD. The image 2 sensor operates in salve mode only and the SCL is input only. The I C bus interface is composed of following parts : START signal, 7-bit slave device address (0010001b) transmission followed by a read/write bit, an acknowledgement signal from the slave, 8-bit data transfer followed by an acknowledgement signal and STOP signal. The SDA bus line may only be changed while SCL is low. The data on the SDA bus line is valid on the highto-low transition of SCL. SCL SDA "0"
Start
2 2
2
D7 "0"
2
D6
D5
D4
D5
D2
D1
D0
Ack
"1"
"0"
"0"
"0"
"1"
Write Ack I2C Register Address
I C Bus Address
SCL SDA D7 D6 D5 D4 D3 D2 D1 D0
Data to Write
2
Ack Stop
Figure 10. I C Bus Write Cycle
SCL SDA "0"
Start
D7 "0"
2
D6
D5
D4
D5
D2
D1
D0
X
"1"
"0"
"0"
"0"
"1"
Write Ack I2C Register Address Ack
I C Bus Address
SCL SDA "0"
Re-Start
D7 "0"
2
D6
D5
D4
D5
D2
D1
D0
"1"
"0"
"0"
"0"
"1"
Read Ack Data to be Read Ack Stop
I C Bus Address
Figure 11. I C Bus Read Cycle
2
21
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
TIMING CHART
VERTICAL TIMING DIAGRAM Continuous Frame Capture Mode ( Default Case )
VSYNC vswd (1row) rows HSYNC 1 frame = wrd + vblank (399 rows )
DATA wrp (14th row) wrd (288 rows) vblank (111 rows)
( Delayed Vertical Sync Case)
1 frame = wrd + vblank VSYNC vsstrt vswd
HSYNC
DATA 2 rows 2 rows
( Vertical Data Valid Mode Case) vsdisp=1
VSYNC
HSYNC (hsdisp=0) HSYNC (hsdisp=1)
DATA wrd vblank
22
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
VERTICAL TIMING DIAGRAM (continued) Single Frame Capture Mode
Normal frame output STRB 3 rows 1 row 1 row 1 row Integration time for 1st readout row Integration time for 2nd readout row Integration time for 3rd readout row Integration time for 4th readout row
sint X (1 row time) VSYNC
HSYNC 2 rows DATA
23
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
HORIZONTAL TIMING DIAGRAM ( Default Case )
VSYNC 1 row = wcw + hblank ( 500 columns )
HSYNC hswd ( 32 DCLK) 10 DCLK DCLK
DATA wcp ( 14th column) wcw ( 352 columns ) hblank ( 148 columns )
( Delayed Horizontal Sync Case )
VSYNC HSYNC hsstrt DCLK
1 row = wcw + hblank
hswd
DATA 42 DCLK wcw 42 DCLK
( Horizontal Data Valid Mode Case ) hsdisp=1
VSYNC HSYNC
DCLK
DATA 42 DCLK wcw hblank
24
1/7 INCH CIF CMOS IMAGE SENSOR
S5K711CA, S5K711LA
LINE HOLD MODE TIMING DIAGRAM
line held
LHOLD
HSYNC (i)-th row (i+1)-th row (i+2)-th row 42 DCLK hblank
DATA
hblank - 42 DCLK
25
S5K711CA, S5K711LA
1/7" CIF CMOS IMAGE SENSOR
PACKAGE DIMENSION 32pin CLCC
10.668SQ +0.25/-0.13 4 5 1 32 29 28
TOP VIEW
Center of Image Area (X=+0.48 0.15, Y=0.00 0.15 from package center) Max. Chip Rotation = 1.5 degree Max. Chip Tilt = 0.05mm
12 13 20
21
Glass
0.55 0.05 1.65 0.18
SIDE VIEW
7.112 0.13 1.016 0.08 32 1
BOTTOM VIEW
R 0.15 4 Corners 0.51 0.08
0.889 0.18
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