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| PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808 INTRODUCTION S5T8808 is a superior low-power-programmable PLL frequency synthesizer which can be used in a high performance Wide Area Pager system. KS8808 consists of 2 kinds of divider block including a 17-bit Shift register, 16-bit Latch, 14/16-bits Counter, Prescaler, and a phase detector block including a Phase detector, Lock detector and a Charge pump. 16-SSOP-0044 FEATURES * Maximum operating frequency: 150MHz @ 500mVP-P, VDD1 = 0.95V 180MHz @ 500mVP-P, VDD1 = 1.0V (Magnification = 1 : 4) * * On-chip reference oscillator supports external crystal which oscillates up to 18MHz Superior supply current: (VDD1 = VDD2 = 1.0V, VDD3 = 3.0V) -- FFIN = 90MHz, IDD1 = 0.6mA (Typ.) -- FFIN = 150MHz, IDD1 = 0.9mA (Typ.) -- FFIN = 180MHz, IDD3 = 1.1mA (TyP.) * * * * Operating voltage: VDD1 = 0.95 ~ 2.0V and VDD2 = 0.95V ~ 2.0V and VDD3 = 2.0V ~ 3.3V Reference frequency counter divider range: 1 / 28 ~ 1 / 65532 (Multiple 4) But, the Divider range with FRC_High state: 1 / 7 ~ 1 / 16383 RX frequency counter divider range: 1 / 28 ~ 1 / 65535 Package type: 16-SSOP (0.8mm) ORDERING INFORMATION Device S5T8808X01-V0B0 Package 16-SSOP-0044 Operating Temperature -25C to +75C 1 S5T8808 PLL FREQUENCY SHNTHESIZER FOR PAGE BLOCK DIAGRAM VDD2 OSCI 1 U Amp U 14-Bit Divider ( R - counter ) U Lock Detector FnFr 15 Fr OSCO 2 VDD1 10 LDT FRC 14 U VDD3 VDD3 3 16-Bit Latch NC 16 Schmitt Trigger 16 Phase Detector 4 Charge Pump 16 5 PDP PDA Shift Register * 17- Bit 16-Bit Latch 16 FnFr 9 VDD2 U 16-Bit Divider ( N - counter ) VDD2 EN 13 12 CLK 11 VSS 6 Fin VDD1 7 8 U Amp 14 Fn VDD1 2 PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808 PIN CONFIGURATION OSCI OSCO VDD3 PDA PDP VSS Fin VDD1 1 2 3 4 5 6 7 8 16 15 14 NC Fr Fn EN DATA CLK LDT VDD2 KS8808D S5T8808 13 12 11 10 9 3 S5T8808 PLL FREQUENCY SHNTHESIZER FOR PAGE PIN DESCRIPTION Pin No 1 2 3 4 Symbol OSCI OSCO VDD3 PDA I/O I O - O Description These input / output pins generate the reference frequency. In case of an OSCI pin, external reference frequency can be input through an AC coupling. The highest potential supply terminal that can be supplied up to 2.0V ~ 3.3V, except for VDD1 and VDD2. The Output of RX Phase detector terminal for active loop filter. There are 3-kinds of output signal states according to Rx Loop Error - If Fr < Fn (Fr is leading), the output negative pulse state - If Fr > Fn (Fr is lagging), the output positive pulse state - If Fr = Fn (the same phase), the output is high impedance state The Output of RX Phase detector terminal for active loop filter. There are 3-kinds of output signal states according to Rx Loop Error - If Fr < Fn (Fr is lagging), the output negative pulse state - If Fr > Fn (Fr is leading), the output positive pulse state - If Fr = Fn (the same phase), the output is high impedance state Ground terminal Input terminal for 16-bit Divider from VCO. Mostly, VCO output should be input through an AC coupling and the minimum input level is 500mVP-P (in case of 90MHz) Voltage supply terminal for Oscillator and Fin block. This pin can be supplied up to 0.95 ~ 2.0V from VSS. Voltage supply terminal for each Divider block (N & R counter). This pin can be supplied up to 0.95V ~ 2.0V. Lock detector is also an output of the Phase Detector. The Low state of this output shows the unlock status, which is the error width between the Ref. signal and the VCO output signal. These pins are controlled by -controller and it also has Schmitt Trigger architecture. The features of these pins are as follows; Clock input for 17-bit Shift Register, Serial data input (it include FnFr-on / off and FRC), Latch enable input (User selectable EN1 or EN2) Output terminal for divider value of N-counter. To control the output On/Off, the FnFr bit of the Reference register can be programmed. When FnFr bit set to High, this output shows low level. Output terminal for divider value of N-counter. To control the output On/Off, the FnFr bit of Reference register can be programmed. When FnFr bit set to High, this output shows low level. No Connection. (Internally biased Pull-up) 5 PDP O 6 7 VSS Fin - I 8 9 10 VDD1 VDD2 LDT I I O 11 12 13 14 CLK DATA EN Fn I I I O 15 Fr O 16 NC - 4 PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808 ABSOLUTE MAXIMUM RATINGS Characteristic Supply Voltage Input Voltage Power Dissipation Operating Temperature Storage Temperature Symbol VDD ~ VDD2 VI PD TOPR TSTG Value -0.3 ~ +4.0 VSS - 0.3 ~ VDD + 0.3 350 -25 ~ +75 -40 ~ +125 Unit V V mW C C ELECTRICAL CHARACTERISTICS (Ta = 25C, VDD1 = VDD2 = 1.0V, VDD3 = 3.0V, unless otherwise specified) Characteristic Operating voltage Symbol VDD1 VDD2 Operating current IDD1 IDD2 IDD3 Standby current Input Voltage (DATA, CLK, EN, BS) Input current (Fin, Xin) Input frequency ISB VIL VIH VIH VIL FFIN VIH = VDD1 VIL = 0V FFIN = 0.5VP-P VDD1 = 0.95V VDD1 = 1.0V FOSCI Output current (PDA, PDP) Output current (Fr, Fn, LDT) Setup-time (DATA-CLK, CLK-EN) Hold time IOH1 IOL1 IOH2 IOL2 ts tH VOSCI = 0.5VP-P VOH = 0.4V VOL = VDD1 - 0.4V VOH = 0.4V VOL = VDD1 - 0.4V - - Test Conditions - - FOSCI = 12.8MHz @ 0.5VP-P VDD1 = VDD2 = 1.0V VDD3 = 1.0V - - FFIN = 90MHz FFIN = 150MHz FFIN = 180MHz Min. 0.95 2.0 - - - - - VDD3-0.3 - - - - 7 1.0 1.0 0.1 0.1 2 2 Typ. 1.0 3.0 0.6 0.9 1.1 - - - - - - - - - - - - - - Max. 2.0 3.3 - - - 10 0.3 - 20 20 150 180 18 - - - - - - S S mA mA MHz A A V mA Unit V VDD1 = VDD2 = 0V, VDD2 = 3.0V 5 S5T8808 PLL FREQUENCY SHNTHESIZER FOR PAGE FUNCTIONAL DESCTRIPTION Table 1. Rx Register (17 bits) Bit Name Description Function RxD Rx. Program Data (ND 15 ~ ND 0) 16 Bit Programmable Rx. N-Counter Data Bit 16 (ND 15) ~ Bit 1 (ND 0) PMC Program Mode Control 0: Rx. N-Counter 1: Ref. R-Counter Bit 0 (LSB) Table 2. Reference Register (17 bits) Bit Name Description Function Bit 16 (RD 13) ~ Bit 3 (RD 0) RefD Ref. Program Data (RD 13 ~ RD 0) 14 Bit Programmable Ref. R-Counter FRC Bit 2 FnFr Control Mode 0: No FRC (OSCI/4R) 1: FRC (OSCI/R) Table 3. Control Mode FRC 0 0 1 1 FnFr 0 1 0 1 Fn (Pin 14) Fn out (Fin / N counter) LOW Fn out (Fin / N-counter) LOW Fr (Pin 15) Fr out (OSCI / 4 x R) LOW Fr out (OSCI / R) LOW 0: Fn, Fr function 1: Fn, Fr Low Bit 1 Bit 0 (LSB) PMC Program mode control 0: Rx. N-Counter 1: Ref. R-Counter 6 PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808 PMC = 0 16-bit N_Counter Rx.16Bit N_Counter Data ( ND15 ~ ND0 ) PMC DATA MSB LSB 1 CLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 positive edge triggered EN1 or EN2 Figure 1. Rx. Register Programming Timing PMC = 1 14-bit R_Counter, FRC, FnFr Ref .14Bit R_Counter Data ( RD13 ~ RD0 ) FRC FnFr PMC DATA MSB LSB 1 CLK 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 positive edge triggered EN1 or EN2 Figure 2. Ref. Register Programming Timing * It is possible to use an optional selection of EN1, EN2 (when used EN) 7 S5T8808 PLL FREQUENCY SHNTHESIZER FOR PAGE Serial DATA Input Timing & Phase Detector / Lock Detector Output Waveforms DATA tH 50% CLK tsu EN 1 50% ~ ~ Figure 3. Serial Data Input Timing The architecture of R-Count Divider ~ ~ /4 FRC 14Bit Ref. Prog. Div. Fr PDA PDP LDT Fn tsu OSCI ~ ~ ~ ~ OSCO Phase Detector Fin 16Bit Rx. Prog. Div. Figure 4. Phase Detector / Lock Detector Block Diagram 8 PLL FREQUENCY SHNTHESIZER FOR PAGER S5T8808 Fr Fn PDP PDA LDT Figure 5. Phase Detector / Lock Detector Output Waveforms 9 S5T8808 PLL FREQUENCY SHNTHESIZER FOR PAGE APPLICATION CIRCUIT From Antenna 1st MIXer X To IF IC S5T8808 KS8808D Multiplier 1 OSCI 2 OSCO 3V 3 VDD3 4 PDA NC Fr Fn EN DATA CLK LDT VDD2 16 15 14 13 12 11 10 9 Monitoring 1V MICOM Monitoring Monitoring VCO 5 PDP 6 Vss 7 Fin 8 VDD1 10 |
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