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S i 5 11 0
P R E L I M I N A R Y D A TA S H E E T
S iPH Y TM OC- 48/S TM- 16 S O NE T/S DH TR A N S C E I V E R
Features
Complete low power, high speed, SONET/SDH transceiver with integrated limiting amp, CDR, CMU, and MUX/DEMUX Data Rates Supported: SONET Compliant Loop Timed OC-48/STM-16 and 2.7 Gbps FEC Operation Low Power Operation 1.0 W (typ) Programmable Slicing Level and Sample Phase Adjustment DSPLLTM Based Clock Multiplier Unit w/ Selectable Loop Filter Bandwidths LVDS Parallel Interface Integrated Limiting Amplifier Single Supply 1.8 V Operation Diagnostic and Line Loopbacks 11 x 11 mm BGA Package
Si5110
Bottom View
Applications
Sonet/SDH Transmission Systems Optical Transceiver Modules Sonet/SDH Test Equipment Ordering Information: See page 23.
Description
The Si5110 is a complete low-power transceiver for high-speed serial communication systems operating between 2.5 Gbps and 2.7 Gbps. The receive path consists of a fully integrated limiting amplifier, clock and data recovery unit (CDR), and 1:4 deserializer. The transmit path combines a low jitter clock multiplier unit (CMU) with a 4:1 serializer. The CMU uses Silicon Laboratories' DSPLLTM technology to provide superior jitter performance while reducing design complexity by eliminating external loop filter components. To simplify BER optimization in long haul applications, programmable slicing, and sample phase adjustment are supported. The Si5110 operates from a single 1.8 V supply over the industrial temperature range (-40C to 85C).
Functional Block Diagram
P H AS E AD J S L IC E L V L LO S LOSLVL 1:4 DEMUX R X D IN RE FS EL Loopback Control REFCLK LPTM R E F R AT E TX L O L BW SEL TX C L K D S B L TXCLKOUT TXS Q LCH TX D O U T RES E T 2 4:1 MUX FIFO 2 RE S ET C o n tro l LLBK DLBK 2 T X C L K 4 IN 2
L im itin g AM P
RXLO L RX SQ LCH RXM S BSE L 8
L TR
CDR
R X D O U T[ 3 : 0
2
/
2
RXCLK1 RXCLK2 R X C L K 2 D IV RXCLK2DSB
D S P L L tm TX CM U
/
2 2 8
T X C L K 4O UT T X C L K 4 IN T X D IN [ 3 : 0 ] F IF O R S T
F IF O E R R TX M S B S E L
Preliminary Rev. 0.41 8/01
Copyright (c) 2001 by Silicon Laboratories
Si5110-DS041
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si 5110
2
Preliminary Rev. 0.41
Si5110 TA B L E O F CONT E N TS
Section Page
4 11 11 11 12 12 12 12 13 13 13 14 14 14 14 15 16 18 23 24 26
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limiting Amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Clock and Data Recovery (CDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deserialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auxiliary Clock Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Squelch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DSPLLTM Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Serialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loop Timed Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diagnostic Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Reference Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Si5110 Pinout: 99-Pin BGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Descriptions: Si5110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Preliminary Rev. 0.41
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Si 5110
Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter Ambient Temperature LVTTL Output Supply Voltage Si5110 Supply Voltage Symbol TA VDD33 VDD Test Condition Min* -40 1.71 1.71 Typ 25 -- 1.8 Max* 85 3.47 1.89 Unit C V V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25C unless otherwise stated.
V SIGNAL + Differential VICM, VOCM I/Os SIGNAL - VIS Single Ended Voltage
(SIGNAL +) - (SIGNAL -) Differential Voltage Swing VID,VOD (VID = 2VIS) Differential Peak-to-Peak Voltage t
Figure 1. Differential Voltage Measurement (RXDIN, RXDOUT, RXCLK1, RXCLK2, TXDIN, TXDOUT, TXCLKOUT, TXCLK4OUT, TXCLK4IN)
tsu TXDOUT, TXDIN tCP thd
tCH TXCLKOUT, TXCLK4IN
RXDOUT
RXCLK1 tcq1 tcq2
Figure 2. Data to Clock Delay
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Preliminary Rev. 0.41
Si5110
All Differential IOs tF tR 80% 20%
Figure 3. I/O Rise/Fall Times Table 2. DC Characteristics
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Current Power Dissipation Voltage Reference (VREF) Common Mode Input Voltage (RXDIN) Differential Input Voltage Swing (RXDIN) Common Mode Output Voltage (TXDOUT, TXCLKOUT) Differential Output Voltage Swing (TXDOUT, TXCLKOUT), Differential pk-pk LVPECL Input Voltage HIGH (REFCLK) LVPECL Input Voltage LOW (REFCLK) LVPECL Input Voltage Swing, Differential pk-pk (REFCLK) LVPECL Internally Generated Input Bias (REFCLK) LVDS Input High Voltage (TXDIN, TXCLK4IN) LVDS Input Low Voltage (TXDIN, TXCLK4IN) LVDS Input Voltage, Single Ended pk-pk (TXDIN, TXCLK4IN) LVDS Output High Voltage (RXDOUT, RXCLK1, RXCLK2, TXCLK4OUT) LVDS Output Low Voltage (RXDOUT, RXCLK1, RXCLK2, TXCLK4OUT) LVDS Output Voltage, Differential pk-pk (RXDOUT, RXCLK1, RXCLK2, TXCLK4OUT)
IDD PD VREF VICM VID VOCM VOD VIH VIL VID VIB VIH VIL VISE VOH1 100 Load Line-to-Line 100 Load Line-to-Line 100 Load Line-to-Line, Figure 1 Figure 1 See Figure 1 See Figure 1 VREF driving 10 k load
-- -- 1.21 TBD 10 .8 800 1.975 1.32 250 1.6 -- 0.0 100 TBD
611 1.0 1.25 0.1 -- 0.9 1000 2.3 1.6 -- 1.95 -- -- -- --
TBD TBD 1.29 TBD 1.0 1.0 1200 2.59 1.99 2400 2.3 2.4 -- 600 1.475
mA W V V mV (pk-pk) V mV (pk-pk) V V mV (pk-pk) V V V mV (pk-pk) mV
VOL1
0.925
--
TBD
V
VOSE
500
--
800
mV (pk-pk)
Preliminary Rev. 0.41
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Si 5110
Table 2. DC Characteristics (Continued)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
LVDS Common Mode Voltage (RXDOUT, RXCLK1, RXCLK2, TXCLK4OUT) Input Impedance (TXDIN, TXCLK4IN, REFCLK, RXDIN) Output Short to GND (RXDOUT, RXCLK1, RXCLK2, TXCLK4OUT, TXDOUT, TXCLKOUT) Output Short to VDD (RXDOUT, RXCLK1, RXCLK2, TXCLK4OUT, TXDOUT, TXCLKOUT) LVTTL Input Voltage Low (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET, MODE16 TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, TXMSBSEL, DLBK, LLBK, LPTM) LVTTL Input Voltage High (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET, MODE16 TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, TXMSBSEL, DLBK, LLBK, LPTM) LVTTL Input Low Current (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET, MODE16 TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, TXMSBSEL, DLBK, LLBK, LPTM) LVTTL Input High Current (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET, MODE16 TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, TXMSBSEL, DLBK, LLBK, LPTM) LVTTL Input Impedance (RXMSBSEL, RXCLK2DIV, RXCLK2DSBL, RXSQLCH, REFSEL, LTR, RESET, MODE16 TXCLKDSBL, FIFORST, TXSQLCH, BWSEL, TXMSBSEL, DLBK, LLBK, LPTM) LVTTL Output Voltage Low (LOS, RXLOL, FIFOERR, TXLOL) LVTTL Output Voltage High (LOS, RXLOL, FIFOERR, TXLOL)
VCM
1.125
--
1.275
V
RIN ISC(-)
Each input to common mode
42 --
50 25
58 TBD
mA
ISC(+)
TBD
-100
--
A
VIL2
VDD33 = 3.3 V VDD33 = 1.8 V
-- --
-- --
0.8 0.7
V
VIH2
VDD33 = 3.3 V VDD33 = 1.8 V
2.0 1.7
--
--
V
IIL
--
--
10
A
IIH
--
--
10
A
RIN
10
--
--
k
VOL2 VOH2
VDD33 = 1.8 V VDD33 = 3.3 V VDD33 = 1.8 V VDD33 = 3.3 V
-- -- 1.4 2.4
-- -- -- --
0.4 0.4 -- --
V
V
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Preliminary Rev. 0.41
Si5110
Table 3. AC Characteristics (RXDIN, RXDOUT, RXCLK1, RXCLK2)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Output Clock Frequency (RXCLK1) Duty Cycle (RXCLK1, RXCLK2) Output Rise and Fall Times (RXCLK1, RXCLK2, RXDOUT) Data Invalid Prior to RXCLK1 Data Invalid After RXCLK1 Input Return Loss (RXIN) Slicing Adjust Dynamic Range Slicing Level Offset (referred to RXDIN)
1
fclkout
See Figure 2 tch/tcp, Figure 2
-- 45 -- -- -- 18.7 TBD -20 -500 -5 -22.5 10 -500 -5
622 -- 50 -- -- -- -- -- -- -- -- -- -- --
667 55 -- 200 200 -- -- 20 500 5 22.5 50 500 5
MHz % ps ps ps dB dB mV
V
tR,tF tcq1 tcq2
Figure 3 Figure 2 Figure 2 100 kHz-2.5 GHz 2.5 GHz-4.0 GHz SLICELVL = 200-800 mV SLICELVL = 200-800 mV VSLICE
Slicing Level Accuracy Sampling Phase Adjustment
2
% mV pk-pk
V
PHASEADJ = 200-800 mV LOSLVL = 200-800 mV LOSLVL = 200-800 mV VLOS
LOS Threshold Dynamic Range LOS Threshold Offset3 (referred to RXDIN) LOS Threshold Accuracy
%
Note: 1. Slice level (referred to RXDIN) is calculated as follows: VSLICE = (SLICE_LVL - 0.4 VREF)/15. 2. Sample Phase Offset is calculated as follows: PHASE OFFSET = 22.5(PHASEADJ - 0.4 VREF)/0.3 3. LOS Threshold voltage (referred to RXDIN) is calculated as follows: VLOS = 30 mV + (LOS_LVL - 0.4 VREF)/15.
Preliminary Rev. 0.41
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Si 5110
Table 4. AC Characteristics (TXCLK4OUT, TXCLK4IN, TXCLKOUT, TXDIN, TXDOUT)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
TXCLKOUT Frequency TXCLKOUT Duty Cycle Output Rise Time (TXCLKOUT, TXDOUT) Output Fall Time (TXCLKOUT, TXDOUT) TXCLKOUT Setup to TXDOUT TXCLKOUT Hold From TXDOUT Output Return Loss TXCLK4OUT Frequency TXCLK4OUT Duty Cycle TXCLK4OUT Rise & Fall Times TXDIN Setup to TXCLK4IN TXDIN Hold from TXCLK4IN TXCLK4IN Frequency TXCLK4IN Duty Cycle TXCLK4IN Rise & Fall Times
fclkout
Figure 2 tch/tcp, Figure 2
-- 45 -- -- 25 25 TBD TBD --
2.5 -- 25 25 -- -- -- -- 622 -- -- -- -- 622 -- --
2.7 55 -- -- -- -- -- -- 667 60 300 300 300 667 60 300
GHz % ps ps ps ps dB dB MHz % ps ps ps MHz % ps
tR tF tsu thd
Figure 3 Figure 3 Figure 2 Figure 2 100 kHz-2.5 GHz 2.5 GHz-4.0 GHz
fCLKIN tch/tcp, Figure 2 tR,tF tDSIN tDHIN fCLKIN tch/tcp, Figure 2 tR,tF
40 100 -- -- -- 40 100
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Si5110
Table 5. AC Characteristics (Receiver PLL)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance
JTOL(PP)
f = 600 Hz f = 6000 kHz f = 100 kHz f = 1 MHz
15 1.5 1.5 0.15 --
30 3.0 3.0 0.3 -- 155 78 50 -- 600
-- -- -- -- 20 167 83 60 100 1000
UIpp UIpp UIpp UIpp
s
Acquisition Time
TAQ REFRATE = 1 REFRATE = 0
Input Reference Clock Frequency RCFREQ
-- -- 40 -100 TBD
MHz MHz % ppm ppm
Reference Clock Duty Cycle Reference Clock Frequency Tolerance Frequency Difference at which Receive PLL goes out of Lock (REFCLK compared to the divided down VCO clock) Frequency Difference at which Receive PLL goes into Lock (REFCLK compared to the divided down VCO clock)
RCDUTY RCTOL LOL
LOCK
TBD
300
TBD
ppm
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
Table 6. AC Characteristics (Transmitter Clock Multiplier)
(VDD = 1.8 V 5%, TA = -40C to 85C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Generation Jitter Transfer Bandwidth
JGEN(rms) JBW
PRBS 23 BWSEL = 0 BWSEL = 1 -- -- --
0.005 -- -- 0.05 -- 155 78 -- --
TBD 6 25 0.1 20 167 84 60 100
UIRMS kHz kHz dB
s
Jitter Transfer Peaking Acquisition Time TAQ Valid REFCLK REFRATE = 1 REFRATE = 0 Input Reference Clock Duty Cycle Input Reference Clock Frequency Tolerance RCDUTY RCTOL
-- -- -- 40 -100
Input Reference Clock Frequency RCFREQ
MHz MHz % ppm
Note: Bellcore specifications: GR-1377-CORE, Issue 5, December 1998.
Preliminary Rev. 0.41
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Si 5110
Table 7. Absolute Maximum Ratings
Parameter Symbol Value Unit
DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range Package Temperature (soldering 10 seconds) ESD HBM Tolerance (100 pf, 1.5 k)
VDD VDD33 VDIF
-0.5 to TBD -0.5 to 3.6 -0.3 to (VDD+ 0.3) 50
V V V mA
C C C
TJCT TSTG
-55 to 150 -55 to 150 275 TBD
V
Note: Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Table 8. Thermal Characteristics
Parameter Symbol JA Test Condition Value Unit
Thermal Resistance Junction to Ambient
Still Air
38
C/W
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Preliminary Rev. 0.41
Si5110
Functional Description
The Si5110 transceiver is a low power, fully integrated serializer/deserializer that provides significant margin to all SONET/SDH jitter specifications. The device operates from 2.5-2.7 Gbps making it suitable for OC48/STM-16, and OC-48/STM-16 applications that use 15/14 forward error correction (FEC) coding. The low speed receive/transmit interface uses a low power parallel LVDS interface. the VREF pin. The LOS detection circuitry is disabled by tieing the LOSLVL input to the supply (VDD). This forces the LOS output high. Slicing Level Adjustment To support applications that require BER optimization, the limiting amplifier provides circuitry that supports adjustment of the 0/1 decision threshold (slicing level) over a range of 20 mV when referred to the internally biased RXDIN input. The slicing level is set by applying a voltage between 0.20 V and 0.80 V to the SLICELVL input. The voltage present on SLICELVL sets the slicing level as follows:
( V SLICE - 0.4xVREF ) V LEVEL = ---------------------------------------------------------15
Receiver
The receiver within the Si5110 includes a precision limiting amplifier, jitter tolerant clock and data recovery unit (CDR), and 1:4 demultiplexer. In addition, programmable data slicing and sampling phase adjustment are provided to support bit-error-rate (BER) optimization for long haul applications.
Limiting Amplifier
The Si5110 incorporates a high sensitivity limiting amplifier with sufficient gain to directly accept the output of transimpedance amplifiers. High sensitivity is achieved by using a digital calibration algorithm to cancel out amplifier offsets. This algorithm achieves superior offset cancellation by using statistical averaging to remove noise that may degrade more traditional calibration routines. The limiting amplifier provides sufficient gain to fully saturate with input signals that are less than 10 mV peak-to-peak differential. In addition, input signals that exceed 1 V peak-to-peak differential will not cause any performance degradation.
Loss-of-Signal (LOS) Detection
VLEVEL is the slicing level referred to the RXDIN input, VSLICE is the voltage applied to the SLICE_LVL pin, and VREF is reference voltage output on the VREF pin. The slicing level adjustment may be disabled by tieing the SLCLVL input to the supply (VDD). When slicing is disabled, the slicing offset is set to 0.0 V relative to internally biased input common mode voltage for RXDIN.
Clock and Data Recovery (CDR)
The Si5110 uses an integrated CDR to recover clock and data from a non-return to zero (NRZ) signal input on RXDIN. The recovered data clock is used to regenerate the incoming data by sampling the output of the limiting amplifier at the center of the NRZ bit period. The recovered clock and data is then deserialized by a 1:4 demultiplexer and output via a LVDS compatible low speed interface (RXDOUT[3:0], RXCLK1, and RXCLK2).
Sample Phase Adjustment
The limiting amplifier includes circuitry that generates a loss-of-signal (LOS) alarm when the input signal amplitude on RXDIN falls below an externally controlled threshold. The Si5110 can be configured to drive the LOS output low when the differential input amplitude drops below a threshold set between ~8 mV and 50 mV pk-pk differential. Approximately 3 dB of hysteresis prevents unnecessary switching on LOS. The LOS threshold is set by applying a voltage between 0.20 V and 0.80 V to the LOSLVL input. The voltage present on LOSLVL maps to an input signal threshold as follows:
( V LOSLVL - 0.4xVREF ) V LOS = -------------------------------------------------------------- + 30 mV 15
In applications where it is not desirable to recover data by sampling in the center of the data eye, the Si5110 supports adjustment of the CDR sampling phase across the NRZ data period. When sample phase adjustment is enabled, the sampling instant used for data recovery can be moved over a range of 22.5 relative to the center of the incoming NRZ bit period. Adjustment of the sampling phase is desirable when data eye distortions are introduced by the transmission medium. The sample phase is set by applying a voltage between 0.20 V and 0.80 V to the PHASEADJ input. The voltage present on PHASEADJ maps to sample phase offset as follows:
VLOS is the differential pk-pk LOS threshold referred to the RXDIN input, VLOSLVL is the voltage applied to the LOSLVL pin, and VREF is reference voltage output on
Preliminary Rev. 0.41
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Si 5110
22.5x ( V PHASE - 0.4xVREF ) PhaseOffset = -----------------------------------------------------------------------------0.30
Phase Offset is the sampling offset in degrees from the center of the data eye, VPHASE is the voltage applied to the PHASEADJ pin, and VREF is reference voltage output on the VREF pin. A positive phase offset will adjust the sampling point to lead the default sampling point in the center of the data eye, and a negative phase offset will adjust the sampling point to lag the default sampling point. Data recovery using a sampling phase offset is disabled by tieing the PHASEADJ input to the supply (VDD). This forces a phase offset of 0o to be used for data recovery.
Receiver Lock Detect
bits to the output data word is controlled by the RXMSBSEL input. If RXMSBSEL is tied low, the first bit received is output on RXDOUT0 and the following bits are output in order on RXDOUT1 through RXDOUT3. If RXMSBSEL is tied high, the first bit received is output on RXDOUT3, and the following bits are output in order on RXDOUT2 through RXDOUT0.
Auxiliary Clock Output
To support the widest range of system timing configurations, a second clock output is provided on RXCLK2. This output can be configured to provide a clock equal to either the parallel output word rate or 1/4th the output word rate. The divide factor used to generate RXCLK2 is controlled via the RXCLKDIV2 input as described in the Pin Description table. In applications which do not use RXCLK2, this output can be powered down by forcing the RSCLK2DSBL input high.
The Si5110 provides lock-detect circuitry that indicates whether the PLL has achieved frequency lock with the incoming data. This circuit compares the frequency of a divided down version of the recovered clock with the frequency of the supplied reference clock (REFCLK). If the recovered clock frequency deviates from that of the reference clock by the amount specified in Table 5 on page 9, the PLL is declared out of lock, and the loss-oflock (RXLOL) pin is asserted. In this state, the PLL will attempt to reacquire lock with the incoming data stream. During reacquisition, the recovered clock frequency (RXCLK1 and RXCLK2) will drift over a 1000 ppm range relative to the supplied reference clock. The RXLOL output will remain asserted until the recovered clock frequency is within the REFCLK frequency by the amount specified in Table 5 on page 9.
Lock-to-Reference
Data Squelch
During some system error conditions, such as LOS, it may be desirable to force the receive data output to zero in order to avoid propagation of erroneous data into the downstream processing circuitry. In these applications, the Si5110 provides a data squelching control input, RXSQLCH. When this input is active low, the data on RXDOUT will be forced to 0. Data squelch is disabled if the device is operating in diagnostic loopback mode (DLBK = 0).
Transmitter
The transmitter consists of a low jitter, clock multiplier unit (CMU) with a 4:1 serializer. The CMU uses a phase-locked loop (PLL) architecture based on Silicon Laboratories' proprietary DSPLLTM technology. This technology is used to generate ultra-low jitter clock and data outputs that provide significant margin to the SONET/SDH specifications. The DSPLL architecture also utilizes a digitally implemented loop filter that eliminates the need for external loop filter components. As a result, sensitive noise coupling nodes that typically cause degraded jitter performance in crowded PCB environments are removed. The DSPLL also reduces the complexity and performance requirements of reference clock distribution strategies for OC-48/STM-16 optical port cards. This is possible because the DSPLL provides selectable wideband and narrowband loop filter settings that allow the user to set the jitter attenuation characteristics of the CMU to accommodate reference clock sources that have a high jitter content. Unlike traditional analog PLL implementations, the loop filter
In applications where it is desirable to maintain a stable output clock during an alarm condition like loss-ofsignal, the lock-to-reference input (LTR) can be used to force a stable output clock. When LTR is asserted, the CDR is prevented from acquiring the data signal and the CDR will lock the RXCLKOUT1 and RXCLKOUT2 outputs to the provided REFCLK. In typical applications, the LOS output would be tied to the LTR input to force a stable output clock.
Deserialization
The Si5110 uses a 1:4 demultiplexer to deserialize the high speed input. The deserialized data is output on a 4bit parallel data bus, RXDOUT[3:0], synchronous with the rising edge of RXCLK1. This clock output is derived by dividing down the recovered clock by a factor of 4. Serial Input to Parallel Output Relationship The Si5110 provides the capability to select the order in which the received serial data is mapped to the parallel output bus RXDOUT[3:0]. The mapping of the receive
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Si5110
bandwidth is controlled by a digital filter inside the DSPLL and can be changed without any modification to external components. dividing down the high speed transmit clock, TXCLKOUT, by a factor of 4. The high-speed serial data stream is clocked out of the shift register by TXCLKOUT. The TXCLK4OUT clock output is provided to support data word transfers between the Si5110 and upstream devices using a counter clocking scheme. Input FIFO The Si5110 integrates a FIFO to decouple data transferred into the FIFO via TXCLK4IN from data transferred into the shift register via TXCLK4OUT. The FIFO is eight parallel words deep and accommodates any static phase delay that may be introduced between TXCLK4OUT and TXCLK4IN in counter clocking schemes. Further, the FIFO will accommodate a phase drift or wander between TXCLK4IN and TXCLK4OUT of up to three parallel data words. The FIFO circuitry indicates an overflow or underflow condition by asserting FIFOERR high. This output can be used to recenter the FIFO read/write pointers by tieing it directly to the FIFORST input. The Si5110 will also recenter the read/write pointers after the device's power on reset, external reset via RESET, and each time the DSPLL transitions from an out of lock state to a locked state (TXLOL transitions from low to high).
Parallel Input To Serial Output Relationship
DSPLLTM Clock Multiplier Unit
The Si5110's clock multiplier unit (CMU) uses Silicon Laboratories proprietary DSPLL technology to generate a low jitter, high frequency clock source capable of producing a high speed serial clock and data output with significant margin to the SONET/SDH specifications. This is achieved by using a digital signal processing (DSP) algorithm to replace the loop filter commonly found in analog PLL designs. This algorithm processes the phase detector error term and generates a digital control value to adjust the frequency of the voltage controlled oscillator (VCO). Because external loop filter components are not required, sensitive noise entry points are eliminated, thus making the DSPLL less susceptible to board-level noise sources. Therefore, SONET/SDH jitter compliance is easier to attain in the application.
Programmable Loop Filter Bandwidth
The digitally implemented loop filter allows for two bandwidth settings that provide either wideband or narrowband jitter transfer characteristics. The filter bandwidth is selected via the BWSEL control input. In traditional PLL implementations, changing the loop filter bandwidth would require changing the values of external loop filter components. In narrowband mode, a loop filter cutoff of 6 kHz is provided. This setting makes the Si5110 more tolerant to jitter on the reference clock source. As a result, the complexity of the clock distribution circuitry used to generate the physical layer reference clocks can be simplified without compromising jitter margin to the SONET/SDH specification. In wideband mode, the loop filter provides a cutoff of 25 kHz. This setting is desirable in applications where the reference clock is provided by a low jitter source like the Si5364 Clock Synchronization IC or Si5320 Precision Clock Multiplier/Jitter Attenuator IC. This allows the DSPLL to more closely track the precision reference source resulting in the best possible jitter performance.
The Si5110 provides the capability to select the order in which data on the parallel input bus is transmitted serially. Data on this bus can be transmitted MSB first or LSB first depending on the setting of TXMSBSEL. If TXMSBSEL is tied low, TXDIN0 is transmitted first followed in order by TXDIN1 through TXDIN3. If TXMSBSEL is tied high, TXDIN3 is transmitted first followed in order by TXDIN2 through TXDIN0. This feature simplifies board routing when ICs are mounted on both sides of the PCB.
Transmit Data Squelch
To prevent the transmission of corrupted data into the network, the Si5110 provides a control pin that can be used to force TXDOUT to 0. By driving TXSQLCH low, the high speed serial output, TXDOUT will be forced to 0. Transmit data squelching is disabled when the device is in line loopback mode (LLBK = 0).
Clock Disable
Serialization
The Si5110 includes serialization circuitry that combines a FIFO with a parallel to serial shift register. Low speed data on the parallel 4-bit input bus, TXDIN[3:0], is latched into the FIFO on the rising edge of TXCLK4IN. The data in the FIFO is loaded into the shift register by TXCLK4OUT, an output clock that is produced by
The Si5110 provides a clock disable pin, TXCLKDSBL, that is used to disable the high-speed serial data clock output, TXCLKOUT. When the TXCLKDSBL pin is asserted, the positive and negative terminals of CLKOUT are tied to 1.5 V through 50 on-chip resistors. This feature is used to reduce power consumption in applications that do not use the high speed transmit data clock.
Preliminary Rev. 0.41
13
Si 5110
Loop Timed Operation
The Si5110 can be configured to provide SONET/SDH compliant loop timed operation. When LPTM is asserted high, the transmit clock and data timing is derived from the recovered clock output by the CDR. This is achieved by dividing down the recovered clock and using it as a reference source for the transmit CMU. This will produce a transmit clock and data that are locked to the timing recovered from the received data path. In this mode, a narrow band loop filter setting is recommended. reference clock sources. The first configuration uses an externally provided reference clock that is input via REFCLK. The second configuration uses the parallel data clock, TXCLK4IN, as the reference clock source. When using TXCLK4IN as the reference source, the narrowband loop filter setting in the CMU may be preferable to remove jitter that may be present on the data clock. The selection of reference clock source is controlled via the REFSEL input. The CMU in the Si5110's transmit section multiplies up the provided reference to the serial transmit data rate. When the CMU has achieved lock with the selected reference, the TXLOL output will be driven high.The CDR in the receive section of the Si5110 uses a reference clock to center the PLL frequency so that it is close enough to the data frequency to achieve lock with the incoming data. When the CDR has locked to the data, RXLOL is driven high.
Diagnostic Loopback
The Si5110 supports diagnostic loopback which establishes a loopback path from the serializer output to the deserializer input. This provides a mechanism for looping back data input via the low speed transmit interface TXDIN to the low speed receive data interface RXDOUT. This mode is enabled by forcing DLBK low.
Reset
The Si5110 is reset by holding the RESET pin low for at least 1 s. When RESET is asserted low, the input FIFO pointers reset and the digital control circuitry initializes. When RESET transitions high to start normal operation, the CMU will be calibrated.
Line Loopback
The Si5110 supports line loopback which establishes a loopback path from the high speed receive input to the high speed transmit output. This provides a mechanism for looping back the high-speed clock and data recovered from RXDIN to the transmit data output TXDOUT and clock TXCLKOUT. This mode is enabled by forcing LLBK low.
Voltage Reference Output
The Si5110 provides an output voltage reference that can be used by an external circuit to set the LOS threshold, slicing level, or sampling phase adjustment. One possible implementation would use a resistor divider to set the control voltage for LOSLVL, SLICELVL, or PHASEADJ. A second alternative would use a DAC to set the control voltage. Using this approach, VREF would be used to establish the range of a DAC output. The reference voltage is nominally 1.25 V.
Bias Generation Circuitry
The Si5110 makes use of two external resistors, RXREXT and TXREXT, to set internal bias currents for the receive and transmit sections of the Si5110. The external resistors allows precise generation of bias currents that significantly reduce power consumption. The bias generation circuitry requires 3.09 k (1%) resistors connected between RXREXT/TXREXT and GND.
Reference Clock
The Si5110 is designed to operate with reference clock sources that are either 1/16th or 1/32nd the desired transceiver data rate. The device will support operation with data rates between ~2.5 Gbps and ~2.7 Gbps and the reference clock should be scaled accordingly. For example, to support 2.67 Gbps operation the reference clock source would be approximately 83 MHz or 167 MHz. The REFRATE input pin is used to configure the device for operation with one of the two supported reference clock submultiples of the data rate. The Si5110 supports operation with two selectable
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Preliminary Rev. 0.41
Si5110
Transmit Differential Output Circuitry
The Si5110 utilizes a current-mode logic (CML) architecture to drive the high speed serial output clock and data on TXCLKOUT and TXDOUT. An example of output termination with ac coupling is shown in Figure 4. In applications where direct dc coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 5.
1.5 V
VDD 50 0.1 F Zo = 50
50
50
0.1 F
Zo = 50
50
VDD 24 mA
Figure 4. CML Output Driver Termination (TXCLKOUT, TXDOUT)
Preliminary Rev. 0.41
15
Si 5110
Si5110 Pinout: 99 BGA
10
9
8
7
6
5
4
3
2
1
RXDOUT[0]
RXDOUT[1]
RXCLK[2]
RXCLK[2]
RSVD_GND
RXSQLCH
RXREXT
SLICELVL
PHASEADJ
A
RXDOUT[0]
RXDOUT[1]
RXCLK[1]
RXCLK[1]
RSVD_GND
NC
VREF
LOSLVL
GND
RXDIN
B
RXDOUT[2]
RXDOUT[3]
RXCLK2DIV
RXCLK2DSBL
RSVD_GND
RSVD_GND
LTR
RXLOL
GND
RXDIN
C
RXDOUT[2]
RXDOUT[3]
RXMSBSEL
VDD
VDD
VDD
VDD
RSVD_GND
LOS
GND
D
REFCLK
GND
GND
GND
VDD
VDD
VDD
RESET
GND
TXCLKOUT
E
REFCLK
GND
GND
GND
VDD
VDD
VDD
REFRATE
GND
TXCLKOUT
F
TXDIN[2]
TXDIN[3]
LPTM
VDD
VDD
VDD
VDD
RSVD_GND
VDD33
GND
G
TXDIN[2]
TXDIN[3]
LLBK
DLBK
BWSEL
FIFORST
TXMSBSEL
RSVD_GND
GND
TXDOUT
H
TXDIN[0]
TXDIN[1]
TXCLKDSBL
REFSEL
TXSQLCH
FIFOERR
RSVD_GND
RSVD_GND
GND
TXDOUT
J
TXDIN[0]
TXDIN[1]
TXCLK4IN
TXCLK4IN
TXCLK4OUT
TXCLK4OUT
TXLOL
TXREXT
NC
GND
K
Bottom View
Figure 5. Si5110 Pin Configuration (Bottom View)
16
Preliminary Rev. 0.41
Si5110
1
2
3
4
5
6
7
8
9
10
A
PHASEADJ
SLICELVL
RXREXT
RXSQLCH
RSVD_GND
RXCLK[2]
RXCLK[2]
RXDOUT[1]
RXDOUT[0]
B
RXDIN
GND
LOSLVL
VREF
NC
RSVD_GND
RXCLK[1]
RXCLK[1]
RXDOUT[1]
RXDOUT[0]
C
RXDIN
GND
RXLOL
LTR
RSVD_GND
RSVD_GND
RXCLK2DSBL
RXCLK2DIV
RXDOUT[3]
RXDOUT[2]
D
GND
LOS
RSVD_GND
VDD
VDD
VDD
VDD
RXMSBSEL
RXDOUT[3]
RXDOUT[2]
E
TXCLKOUT
GND
RESET
VDD
VDD
VDD
GND
GND
GND
REFCLK
F
TXCLKOUT
GND
REFRATE
VDD
VDD
VDD
GND
GND
GND
REFCLK
G
GND
VDD33
RSVD_GND
VDD
VDD
VDD
VDD
LPTM
TXDIN[3]
TXDIN[2]
H
TXDOUT
GND
RSVD_GND
TXMSBSEL
FIFORST
BWSEL
DLBK
LLBK
TXDIN[3]
TXDIN[2]
J
TXDOUT
GND
RSVD_GND
RSVD_GND
FIFOERR
TXSQLCH
REFSEL
TXCLKDSBL
TXDIN[1]
TXDIN[0]
K
GND
NC
TXREXT
TXLOL
TXCLKOUT
TXCLKOUT
TXCLKIN
TXCLKIN
TXDIN[1]
TXDIN[0]
Top View
Figure 6. Si5110 Pin Configuration (Transparent Top View)
Preliminary Rev. 0.41
17
Si 5110
Pin Descriptions: Si5110
Pin Number(s)
Name
I/O
Signal Level
Description Bandwidth Select DSPLL. This input selects loop bandwidth of the DSPLL. BWSEL = 0: Loop bandwidth set to 6 kHz. BWSEL = 1: Loop bandwidth set to 25 kHz. Diagnostic Loopback. When this input is active low the transmit clock and data are looped back for output on RXDOUT, RXCLK1 and RXCLK2. This pin should be held high for normal operation. FIFO Error. This output is driven high when a FIFO overflow/underflow has occurred. This output will stick high until reset by asserting FIFORST. FIFO RESET. This input when asserted high resets the read/write FIFO pointers to their initial state. Supply Ground.
H6
BWSEL
I
LVTTL
H7
DLBK
I
LVTTL
J5
FIFOERR
O
LVTTL
H5
FIFORST
I
LVTTL
B2, C2, D1, E2, E7-9, F2, F7-9, G1, H2, J2, K1 H8
GND
GND
LLBK
I
LVTTL
Line Loopback. When this input is active low the recovered clock and data are looped back for output on TXDOUT, and TXCLKOUT. This pin should be held high for normal operation. Loss-of-Signal. This output is driven low when the peak-to-peak signal amplitude is below threshold set via LOSLVL. LOS Threshold Level. Applying an analog voltage to this pin allows adjustment of the Threshold used to declare LOS. Tieing this input high disables LOS detection and forces the LOS output high.
D2
LOS
O
LVTTL
B3
LOSLVL
I
18
Preliminary Rev. 0.41
Si5110
Pin Number(s) Name I/O Signal Level
Description Loop Timed Operation. When this input is forced high, the recovered clock from the receiver is divided down and used as the reference source for the transmit CMU. The narrowband setting for the DSPLL CMU will be sufficient to provide SONET compliant jitter generation and transfer on the transmit data and clock outputs (TXDOUT,TXCLKOUT). This pin should be held low for normal operation. Lock-to-Reference. This input forces a stable output clock by locking RXCLK1 and RXCLK2 to the provided reference. Driving LTR low activates this feature. No Connect. Reserved for device testing. Leave electrically unconnected. No Connect. Reserved for device testing. Leave electrically unconnected.
G8
LPTM
I
LVTTL
C4
LTR
I
LVTTL
B5
NC
K2
NC
A2
PHASEADJ
I
Sampling Phase Adjust. Applying an analog voltage to this pin allows adjustment of the sampling phase across the data eye. Tieing this input high nominally centers the sampling phase.
E10, F10
REFCLK, REFCLK
I
LVPECL
Differential Reference Clock. The reference clock sets the operating frequency of the PLL used to generate the high speed transmit clock. In addition, REFCLK sets the initial operating frequency used by the onboard PLL for clock and data recovery. The Si5110 will operate with reference clock frequencies that are either 1/16 or 1/32 the serial data rate (nominally 155 MHz or 78 MHz). Reference Clock Select. This input configures the Si5110 to operate with one of two reference clock frequencies. If REFRATE is held high, the device requires a reference clock that is 1/16 the serial data rate. If REFRATE is low, a reference clock at 1/32 the serial data rate is required. Reference Clock Selection. This inputs selects the reference clock source used by the CMU. When REFSEL = 0, the low speed data input clock, TXCLK4IN, is used as the CMU reference. When REFSEL = 0, the reference clock provided on REFCLK is used.
F3
REFRATE
I
LVTTL
J7
REFSEL
I
LVTTL
Preliminary Rev. 0.41
19
Si 5110
Pin Number(s) Name I/O Signal Level
Description Device Reset. Forcing this input low for at least 1 s will cause a device reset. For normal operation, this pin should be held high. Reserved Tie To Ground. Must tie directly to GND for proper operation.
E3
RESET
I
LVTTL
A6, B6, C5- 6, D3, G3, H3, J3-4 B7-8
RSVD_GND
RXCLK1, RXCLK1
O
LVDS
Differential Clock Output 1. The clock recovered from the signal present on RXDIN is divided down to the parallel output word rate and output on RXCLK1. In the absence of data, a stable clock on RXCLK1 can be maintained by asserting LTR. Clock Divider Select. This input selects the divide factor used to generate the RXCLK2 output. When this input is driven low, RXCLK2 is equal to the output word rate on RXDOUT. When driven high, RXCLK2 is 1/4th the output word rate. RXCLK2 Disable. Driving this input high will disable the RXCLK2 output. This would be used to save power in applications that do not require an auxiliary clock. Differential Clock Output 2. An auxiliary output clock is provided on this pin that is equivalent to, or a submultiple of, the output word rate. The divide factor used in generating RXCLK2 is set via RXCLK2DIV. Differential Data Input. Clock and data are recovered from the high speed data signal present on these pins. Differential Parallel Data Output. The data recovered from the signal present on RXDIN is demultiplexed and output as a 4-bit parallel word on RXDOUT[3:0]. These outputs are updated on the rising edge of RXCLK1. Loss-of-Lock. This output is driven low when the recovered clock frequency deviates from the reference clock by the amount specified in Table 5.
C8
RXCLK2DIV
I
LVTTL
C7
RXCLK2DSBL
I
LVTTL
A7-8
RXCLK2, RXCLK2
O
LVDS
B1, C1
RXDIN, RXDIN RXDOUT[3:0], RXDOUT[3:0]
I
High Speed Differential LVDS
A9-10, B9, B10, C9, C10, D9, D10 C3
O
RXLOL
O
LVTTL
20
Preliminary Rev. 0.41
Si5110
Pin Number(s) Name I/O Signal Level
Description Data Bus Receive Order. This determines the order of the received data bits on the output bus. For RXMSBSEL = 0, the first data bit received is output on RXDOUT[0] and following data bits are output on RDOUT[1] through RXDOUT[3]. For RXMSBSEL = 1, the first data bit is output on RXDOUT[3] and following data bits are output on RXDOUT[2] through RXDOUT[0]. External Bias Resistor. This resistor is used by the receiver circuitry to establish bias currents within the device. This pin must be connected to GND through a 3.09 k (1%) resistor.
D8
RXMSBSEL
I
LVTTL
A4
RXREXT
A5
RXSQLCH
I
LVTTL
Data Squelch. When this input is low the data on RXDOUT is forced to 0. Set high for normal operation. Slicing Level Adjustment. Applying an analog voltage to this pin allows adjustment of the slicing level applied to the input data eye. Tieing this input high nominally sets the slicing offset to 0.
A3
SLICELVL
I
K7-8
TXCLK4IN, TXCLK4IN TXCLK4OUT, TXCLK4OUT
I
LVDS
Differential Data Clock Input. The rising edge of this input clocks data present on TXDIN into the device. Divided Down Output Clock. This clock output is generated by dividing down the high speed output clock, TXCLKOUT, by a factor of 4. It is intended for use in counter clocking schemes that transfer data between the system ASIC and the Si5110. High Speed Clock Disable. When this input is high, the output driver for TXCLKOUT is disabled. In applications that do not require the output data clock, the output clock driver should be disabled to save power. High Speed Clock Output. The high speed clock output, TXCLKOUT, is generated by the PLL in the clock multiplier unit. Its frequency is nominally 16 times or 32 times the selected reference source.
K5-6
O
LVDS
J8
TXCLKDSBL
I
LVTTL
E1, F1
TXCLKOUT, TXCLKOUT
Preliminary Rev. 0.41
21
Si 5110
Pin Number(s) Name I/O Signal Level
Description Differential Parallel Data Input. The 4-bit data word present on these pins is multiplexed into a high speed serial stream and output on TXDOUT. The data on these inputs is clocked into the device by the rising edge of TXCLK4IN. Differential High Speed Data Output. The 4-bit word input on TXDIN[3:0] is multiplexed into a high speed serial stream that is output on these pins. Input data is multiplexed in sequence from TXDIN0 to TXDIN3 with TXDIN0 transmitted first. This output is updated by the rising edge of TXCLKOUT. CMU Loss-of-Lock. The output is asserted low when the CMU is not phase locked to the selected reference source. Data Bus Transmit Order. For TXMSBSEL = 0, data on TXDIN[0] is transmitted first followed by TXDIN[1] through TXDIN[3]. For TXMSBSEL = 1, TXDIN[3] is transmitted first followed by TXDIN[2] through TXDIN[0]. External Bias Resistor. This resistor is used by the transmitter circuitry to establish bias currents within the device. This pin must be connected to GND through a 3.09 k (1%) resistor.
G9-10, H9- 10, J9-10, K9-10
TXDIN[3:0], TXDIN[3:0]
I
LVDS
H1, J1
TXDOUT, TXDOUT
O
CML
K4
TXLOL
O
LVTTL
H4
TXMSBSEL
I
LVTTL
K3
TXREXT
J6
TXSQLCH
I
LVTTL
Transmit Data Squelch. If TXSQLCH is asserted low, the output data stream on TXDOUT will be forced to 0s. If TXSQLCH = 1, TX squelching is turned off. Supply Voltage. Nominally 1.8 V.
D4-7, E4-6, F4-6, G4-7 G2
VDD VDD33
VDD VDD33
1.8 V
1.8 V or 3.3 V Digital Output Supply. Must be tied to either 1.8 V or 3.3 V. When tied to 3.3 V, LVTTL compatible output voltage swings on RXLOL, LOS, TXLOL, and FIFOERR are supported. Voltage Ref
Voltage Reference. The Si5110 provides an output voltage reference that can be used by an external circuit to set the LOS threshold, slicing level, or sampling phase adjustment. The equivalent resistance between this pin and GND should not be less than 10 k. The reference voltage is nominally 1.25 V.
B4
VREF
O
22
Preliminary Rev. 0.41
Si5110
Ordering Guide
Table 9. Ordering Guide Part Number Package Temperature
SI5110-BC
99 BGA
-40C to 85C
Preliminary Rev. 0.41
23
Si 5110
Package Outline
Figure 7 illustrates the package details for the Si5110. Table 10 lists the values for the dimensions shown in the illustration.
A1 Ball Pad Corner A D A1
10 9 8 7 6 5 4 3 2 1
A1 Ball Pad Corner
e
A B C D
E b 1.00 Ref
E F G H J K
1.00 Ref A2 Seating Plane
e
Top View
Side View
Bottom View
Figure 7. 99-Ball Grid Array (BGA)
Table 10. Package Diagram Dimensions
Symbol Min 1.30 0.31 0.65 -- -- -- -- Millimeters Nom 1.40 0.36 0.70 0.46 11.00 11.00 1.00 Max 1.50 0.41 0.75 -- -- -- --
A A1 A2 b D E e
24
Preliminary Rev. 0.41
Si5110 NOTES:
Preliminary Rev. 0.41
25
Si 5110
Contact Information
Silicon Laboratories Inc.
4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, SiPHY, and DSPLL are trademarks of Silicon Laboratories Inc. Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
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Preliminary Rev. 0.41

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