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| SPICE Device Model SIA811DJ Vishay Siliconix P-Channel 20-V (D-S) MOSFET with Schottky Diode CHARACTERISTICS * P-Channel Vertical DMOS * Macro Model (Subcircuit Model) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74367 S-70135Rev. A, 29-Jan-07 www.vishay.com 1 SPICE Device Model SIA811DJ Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 0.82 35 0.080 0.108 0.143 8 -0.84 Measured Data Unit VGS(th) ID(on) VDS = VGS, ID = -250 A VDS -5 V, VGS = -4.5 V VGS = -4.5 V, ID = -2.8 A V A 0.078 0.109 0.153 7 -0.85 S V Drain-Source On-State Resistancea rDS(on) VGS = -2.5 V, ID = -2.3 A VGS = -1.8 V, ID = -0.54 A Forward Transconductancea Diode Forward Voltage a gfs VSD VDS = -10 V, ID = -2.8 A IS = -4.5 A Dynamic b Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = -10 V, VGS = -8 V, ID = -4.5 A VDS = -10 V, VGS = -4.5 V, ID = -4.5 A VDS = -10 V, VGS = 0 V, f = 1 MHz 456 63 48 5.8 3.5 0.75 1.2 355 75 50 8.5 4.9 0.75 1.2 nC pF Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 74367 S-70135Rev. A, 29-Jan-07 SPICE Device Model SIA811DJ Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) Document Number: 74367 S-70135Rev. A, 29-Jan-07 www.vishay.com 3 |
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