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SIP12201
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Vishay Siliconix
Synchronous Step Down Controller
DESCRIPTION SIP12201 is a synchronous step down controller designed for use in dc-dc converter circuits requiring output currents as high as 10 amperes. SIP12201 is designed to require a minimum number of external components, simplifying design and layout. It accepts input voltages from 4.2 V to 26.0 V, providing an adjustable output with voltage ranging from 0.6 V to 5 V. SIP12201 includes an combination Compensation/ Shutdown pin. Protection features include undervoltage lockout, output current limit, and thermal shutdown. SIP12201 is available in a lead (Pb)-free MLP33-10 package and is specified to operate over the range of - 40 C to 85 C.
FEATURES * 4.2 V to 26.0 V Input Voltage Range * Adjustable Output Voltage - 0.6 to 5.5 V * For Converter loads up to 10 A * High efficiency - 93% * Uses N-channel MOSFETs * 500 kHz operation * Internal Soft Start * Shutdown pin * Output Current Limit * Minimum External Components * MLP33-10 Package APPLICATIONS * Distributed Power * Desktop & Notebook Computers * Battery Operated Equipment * Point of Load Regulation * DSP Cores * Automotive Entertainment
TYPICAL APPLICATION CIRCUIT
V IN
VL VIN
VIN DH LX DL V
OUT
Compensation Shutdown
COMP/SD
FB AGND AGND PGND PGND
GND
Document Number: 73541 S-52083-Rev. A, 10-Oct-05
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SIP12201
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ABSOLUTE MAXIMUM RATINGS
Parameter VIN, LX to GND BST to LX FB, Comp/SD to GND Power Dissipationa, b Maximum Junction Temperature Storage Temperature Notes a. Device mounted with all leads soldered or welded to PC board b. Derate 14 mW/C above + 85 C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating/conditions for extended periods may affect device reliability. Limit 29 6 - 0.3 to 6 560 125 - 55 to + 150 mW C V Unit
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RECOMMENDED OPERATING RANGE
Parameter Input Voltage Range Output Voltage Adjustment Range Operating Temperature Range Limit 4.2 to 26.0 0.6 to 5.5 - 40 to + 85 Unit V C
SPECIFICATIONSa
Parameter Controller Input Voltage Quiescent Current Internal Supply Voltage Oscillator Frequency Oscillator Ramp Amplitude Max Duty Cycle Feedback Voltage FB input Bias Current Transconductance Soft Start Inputs and Outputs SD Input Voltage Shutdown Current MOSFET Drivers Break-before-make time Highside Driver Output Voltage On resistance Rise time Fall time VDH RDSHH RDSHL trH tfH VIN = VBST = VLX = 4.5 V VIN = VBST = VLX = 4.5 V VIN = VL = VBST = 5 V, CL= 2.7 nF VIN = VL = VBST = 5 V, CL= 2.7 nF 4.5 8.7 2.3 51 15 13 3.6 V ns tBBM 10 ns VIL ISD 120 0.15 225 V A VL fOSC VOSC DC VFB IFB GM 2 4 TA = 25C 87 0.591 0.585 VIN Non switching 4.8 400 500 1 93 0.600 0.609 0.615 100 4.2 850 26.0 1250 5.5 600 V A V kHz V % V nA mA/V ms Symbol Test Condition Unless Specified VIN = 5.5 to 26 V Limits -40 to 85C Mina Typb Maxa Unit
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Document Number: 73541 S-52083-Rev. A, 10-Oct-05
SIP12201
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SPECIFICATIONSa
Parameter Lowside Driver Output Voltage On resistance Rise time Fall time Protection Under voltage lockout UVLO-Hysteresis UVLO-High Side UVLO-High Side Hysteresis Thermal Shutdown Temperature Thermal Hysteresis Over Current Limit MOSFET on Voltage Sense Threshold VDL -240 -170 -110 mV Rising Rising VUVLO Rising 3.6 0.180 2.0 0.15 165 20 C C 2.3 3.9 V VDL RDSLH RDSLL trL tfL VIN = VL = 4.5 V VIN = VL = 4.5 V VIN = VL = 5 V, CL= 2.7 nF VIN = VL = 5 V, CL= 2.7 nF 4.5 2.5 0.85 13.4 5.8 3.9 1.4 V ns Symbol Test Condition Unless Specified VIN = 5.5 to 26 V Limits -40 to 85C Mina Typb Maxa Unit
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NOTES: a) The algebriac convention whereby the most negative value is a minimum and the most positive a maximum. b) Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
PIN CONFIGURATION
PIN DESCRIPTION
Pin Number 1 2 3 4 5 6 7 8 9 10 Name COMP/SD FB AGND VIN VL DL PGND BST DH LX Feedback input Analog Ground Input voltage for the power MOSFETs and their gate drive Internal Supply Voltage Lowside gate drive Power Ground Connection for the bootstrap capacitor Highside gate drive Connection for the inductor node Function Combination Compensation and Shut down pin
ORDERING INFORMATION
Part Number SIP12201DM-T1-E3 Eva Kit SIP12201DB Temperature Range -40 to 85 C Temperature Range -40 to 85 C Package MLP33-10 Board Surface Mount
Document Number: 73541 S-52083-Rev. A, 10-Oct-05
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SIP12201
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FUNCTIONAL BLOCK DIAGRAM
SIP12201
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BST Vin Regulator UVLO VL Over Temp Over Voltage DH
Soft Start
Shut Down Over Current Sense
Comp LX
FB GM PWM Comp
Gate Control Logic BBM VL VL
0.6 V OSC 500KHz
Vosc
DL
Pgnd
SD/Comp
Agnd
DETAILED OPERATIONAL DESCRIPTION Enable/ON State: The COMP/SD pin has 10 A pull up current to ensure auto startup as soon as the pin is released by the external pull down MOS. When the internal reference is ready, there will be a clamp current applied at COMP/SD; this is to ensure the COMP/SD pin will not go below 600 mV inadvertently due to the amplifier excursion or noise. The COMP/SD has to go above 600 mV to enable the chip fully. Disable/Shutdown/Off State To disable the chip, the COMP/SD pin has to pulled below 150 mV typically and the external pull down MOSFET has to be able to sink at least 250 A. Once the pin reaches a voltage below the 150 mV level, the chip will go into shutdown mode with only essential curcuitry alive and the current bias of the chip will be cut down to 120 A level typically. Both High Side and Low Side Gates are off. UVLO: The chip enters into Under Voltage Lockout when VL is below 3.4 V (typical). Both High Side Gate and Low Side Gate will be turned off. The chip will go out of UVLO mode when VL is above 3.6 V (typical).
Soft Start: Once the chip is out of shutdown and UVLO mode, the soft start is initiated. The soft start is accomplished done by ramping up the internal reference. During soft start mode the chip can not enter into fault mode. If there is an over current condition (current limit condition), the High Side Gate will be turned off and the Low Side will be turned on. Once the soft start timing elapses, the chip enters into a normal state of operation. Output Over Voltage State: When the Output voltage goes above 1.083 times nominal Output Voltage, the High Side Gate will be turned off and the Low Side Gate will be on. The condition will persist until the Output voltage drops below the trigger voltage minus a hysteresis. Output Over Current State: The SIP12201 will enter a cycle by cycle over current condition when the Low Side MOSFET is turned on, the LX voltage falls below -170 mV with respect to Power Ground. As long as the LX voltage remains below -170 mV the Low Side MOSFET is still turned on, the High Side MOSFET is off. If this condition remains for seven consecutive cycles the IC will go into a fault state. If the over current condition is removed before seven consecutive cycles the IC will revert to normal mode.
Document Number: 73541 S-52083-Rev. A, 10-Oct-05
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SIP12201
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Fault State: The IC can only enter into Fault mode after the soft start mode has ended and seven consecutive over current condition cycles has occurred. Once it enters the Fault state, with the High Side MOSFET turned off and the Low Side MOSFET turned on, any occurring over current condition will be ignored. The Fault State will last for seven soft start cycles. After which the IC will enter Soft Start mode. If the over current condition is removed the IC will operate normally, otherwise the over current sequence is repeated. This fault scheme minimizes thermal stress on the external power MOSFET switches. Over Temperature: When the temperature of the chip goes above 165 C, the chip enters into over temperature shutdown. The High Side gate will be off and the Low Side gate will be on. Only system monitor circuitry will be active. Once the temperature of the chip drops below 145 C, the chip enters into the normal operation mode. Duty-Factor Limitations for Low VOUT / VIN Ratios The SIP12201 output voltage is adjustable down to 0.6 V. However, the minimum duty factor may limit the ability to supply low-voltage outputs from high voltage inputs. With high-input voltages, the required duty factor is approximately:
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Setting the Output Voltage: An output voltage between 0.6 V and 5.5 V (if VIN is between 4.2 V and 6.0 V then the maximum VOUT is 0.9* VIN) and can be configured by connecting FB pin to a resistive divider between the output and GND. Select resistor R2 in the 1 k to 10 k range. R1 is then given by:
R1 = R2
(V V
OUT FB
-1
)
where VFB = 0.6 V.
VOUT
R1 FB R2
0.6 V
(V
OUT
+ R DS(ON) x I LOAD VIN
)
where RDS(ON) x ILOAD is the voltage drop across the synchronous rectifier. The SIP12201 minimum duty factor is 10%, so the maximum input voltage (VIN(MAX)) that can supply a given output voltage is:
VIN ( MAX) 10 (VOUT + R DS(ON) x I LOAD)
If the circuit cannot attain the required duty factor dictated by the input and output voltages, the output voltage still remains in regulation. However, there may be intermittent or continuous half-frequency operations as the controller attempts to lower the average duty factor by deleting pulses. This can increase output voltage ripple and inductor current ripple, which increases noise and reduces efficiency. Furthermore, circuit stability is not guaranteed.
Document Number: 73541 S-52083-Rev. A, 10-Oct-05
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TYPICAL CHARACTERISTICS
100 95 Vin = 5.0 V
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Vin = 10.0 V
2.52 2.515
OUTPUT VOLTAGE ( V)
90
EFFICIENCY (%)
85 Vin = 15.0 V 80 75 70 65 60 55 50 0 2 4 6 8 10 VOUT = 2.5 V Vin = 20.0 V
2.51 2.505 2.5
Vin = 15.0 V
Vin = 20.0 V 2.495 2.49 2.485 2.48 Vin = 5.0 V
0
2
4
6
8
10
LOAD CURRENT (A) EFFICIENCY Vs. LOAD CURRENT
600
0.615
LOAD CURRENT (A) OUTPUT VOLTAGE Vs. LOAD CURRENT
550
FREQUENCY ( kHz)
Vin = 5.5 V to 26 V 500
VOLTAGE (V)
0.605
Vin = 4.2 V to 26 V
0.595
450
Vin = 4.2 V
400 -45
0.585
-10
25
60
95
130
-45
-10
25
60
95
130
TEMPERATURE (C) OSCILLATOR FREQUENCY Vs TEMPERATURE
100
-120
TEMPERATURE (C) FEEDBACK THRESHOLD Vs TEMPERATURE
-140
Vin = 5.5 V to 26 V
Duty Cycle (%)
95
VOLTAGE (mV)
-160 Vin = 5.5 V to 26 V -180 Vin = 4.2 V -200
Vin = 4.2 V
90
85 -45 -10 25 60 95 130
-220 -45 -10 25 60 95 130
TEMPERATURE (C) MAX DUTY CYCLE Vs TEMPERATURE
TEMPERATURE (C) CURRENT SENSE VOLTAGE Vs TEMPERATURE
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Document Number: 73541 S-52083-Rev. A, 10-Oct-05
SIP12201
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TYPICAL CHARACTERISTICS
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1.5
5
CURRENT (mA)
CURRENT (nA)
Vin = 5.5 V to 26 V 1
Vin = 4.2 V 0 Vin = 5.5 V to 26 V -5
0.5
Vin = 4.2 V
0 -45 -10 25 60 95 130
-10 -45 -10 25 60 95 130
TEMPERATURE (C) QUIESCENT CURRENT Vs TEMPERATURE
150
TEMPERATURE (C) FB INPUT BIAS CURRENT Vs TEMPERATURE
120
Vin = 5.5 V to 26 V
CURRENT (A)
90
60 Vin = 4.2 V
30 -45
-10
25
60
95
130
TEMPERATURE (C) SHUTDOWN CURRENT Vs TEMPERATURE
Document Number: 73541 S-52083-Rev. A, 10-Oct-05
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TYPICAL WAVEFORMS
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VLX = 10 V/div DH = 10 V/div
VOUT = 500 mV/div
DL = 10 V/div Inductor Current 2 A/div Inductor Current 2 A/div
1 s/div VIN = 12 V, VOUT = 2.5 V, Load Current = 5 A, L = 1.5 H, COUT = 220 uF X 2 Typical Switching Waveform
10 s/div VIN = 12 V, VOUT = 2.5 V, Load Current = 1 A to 8 A Step, L = 1.5 H, COUT = 220 uF X 2 Load Transient Response
Comp/SD = 1 V/div
VOUT = 1 V/div
VOUT = 20 mV/div
Inductor Current 5 A/div
1 ms/div VIN = 12 V, VOUT = 2.5 V, Load Current = 1 A, Output Filter Cap = 220 uF X 2 Soft Start
1 s/div VIN = 12 V, VOUT = 2.5 V, Load Current = 1 A, L = 1.5 H, COUT = 220 uF X 2 Output Voltage Ripple
Comp/SD = 1 V/div
VOUT = 1 V/div
Inductor Current 5 A/div
1 ms/div VIN = 12 V, VOUT = 2.5 V, Load Current = 1 A, Output Filter Cap = 220 uF X 2 Shut Down
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Document Number: 73541 S-52083-Rev. A, 10-Oct-05
SIP12201
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APPLICATION NOTES Inductor Selection: An inductor is one of the energy storage component in a converter. Choosing an inductor means specifying its size, structure, material, inductance, saturation level, DC-resistance (DCR), and core loss. Fortunately, there are many inductor vendors that offer wide selections with ample specifications and test data, such as Vishay Dale. The following are some key parameters that users should focus on. In PWM mode, inductance has a direct impact on the ripple current. The peak-to-peak inductor ripple current can be calculated as
VOUT (VIN - V OUT) VIN Lf
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To minimize current pulse induced ripple caused by the step-down controller and interference of large voltage spikes from other circuits, a low-ESR input capacitor is required to filter the input voltage. The input capacitor should be rated for the maximum RMS input current:
I RMS = I LOAD(m ax)
V OUT V OUT 1 - V IN V IN
It is common practice to rate for the worst-case RMS ripple that occurs when the duty cycle is at 50%:
I RMS =
IP -
P
I LOAD(max) 2
=
where f = switching frequency. Higher inductance means lower ripple current, lower rms current, lower voltage ripple on both input and output, and higher efficiency, unless the resistive loss of the inductor dominates the overall conduction loss. However, higher inductance also means a bigger inductor size and a slower response to transients. In PSM mode, inductance affects inductor peak current, and consequently impacts the load capability and switching frequency. For fixed line and load conditions, higher inductance results in a lower peak current for each pulse, a lower load capability, and a higher switching frequency. The saturation level is another important parameter in choosing inductors. Note that the saturation levels specified in data sheets are maximum currents. For a dc-to-dc converter operating in PWM mode, it is the maximum peak inductor current that is relevant, and which can be calculated using these equations:
IP - 2
P
Output Capacitor Selection: The selection of the output capacitor is primarily determined by the ESR required to minimize voltage ripple and current ripple. The desired output ripple VOUT can be calculated by:
1 VOUT = (I m ax- I m in) ESR + 8fCOUT
Current ripple can be calculated by:
(I m ax- I m in) = T V OUT ( V IN - V OUT)
Where: VOUT = Desired Output Ripple Voltage f = Switching frequency Imax = Maximum Inductor Current Imin = Minimum Inductor Current T = Switching Period Multiple capacitors placed in parallel may be needed to meet the ESR requirements. However if the ESR is too low it can cause instability problems. MOSFET Selection: The key selection criteria for the MOSFETs include maximum specifications for on-resistance, drainsource voltage, gate source, current, and total gate charge Qg. While the voltage ratings are fairly straightforward, it is important to carefully balance on-resistance and gate charge. In typical MOSFETs, the lower the on-resistance, the higher the gate charge. The power loss of a MOSFET consists of conduction, gate charge, and crossover losses. For lower-current applications, gate charge losses become a significant factor, so low gate charge MOSFETs, such as Vishay Siliconix's LITTLE FOOT family of PWM-optimized devices, are desirable.
L V IN
I PK = I OUT +
This peak current varies with inductance tolerance and other errors, and the rated saturation level varies over temperature. So a sufficient design margin is required when choosing current ratings. A high-frequency core material, such as ferrite, should be chosen, the core loss could lead to serious efficiency penalties. The DCR should be kept as low as possible to reduce conduction losses.
Input Capacitor Selection:
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SIP12201
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Compensation:
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VIN VOUT
R1 FB GM R2 R3 0.6 V C1 ESR OSC 500KHz Vosc PWM Comp C2 COUT Compensation L VOUT
The SIP12201 uses voltage mode control in conjunction with a high frequency Transconductance error amplifier. The voltage feedback loop is compensated at the Comp/ SD pin, which is the output node of the error amplifier. The feedback loop is generally compensated with an RC + C (one pole, one zero) network from comp to GND. Loop stability is affected by the values of the inductor, the output capacitor, the output capacitor ESR, and the error amplifier compensation network. The ideal Bode plot for a compensated system would be gain that rolls off at a slope of -20 dB/decade, crossing 0dB at the desired bandwidth and a phase margin greater than 90 for all frequencies below the 0 dB crossing. The compensation network used with the error amplifier must provide enough phase margin at the 0 dB crossover frequency for the overall open-loop transfer function to be stable. The following guidelines will calculate the compensation pole and zero to stabilize the SiP 12201. The inductor and output capacitor values are usually determined by efficiency, voltage and current ripple requirements. The inductor and the output capacitor create a double pole at the frequency and a -180 phase change:
The fZ(ESR) typically should be higher than the fp(LC) and give a 90 phase boost. R3 and C1 will establish the second zero of the system. The frequency of the zero should be 2X lower than the double pole frequency of the inductor and the output capacitor.
fZ(comp) =
1 2 R3C1
Choose a value for R3 usually between 1 k and 10 k. This second zero will provide the second 90 phase boost and will stabilize the closed loop system. The second pole should be placed at 1/2 the switching frequency.
C2 =
C1 2 R1 C1 FSW-1
f p(LC) =
1 2 L * COUT
The ESR of the output capacitor and the output capacitor value form a zero at the frequency:
Although a mathematical approach to frequency compensation can be used, the added complication of input and/or output filters, unknown capacitor ESR, and gross operating point changes with input voltage, load current variations, all suggest a more practical empirical method. This can be done by injecting at the load a variable frequency small signal voltage between the output and feedback network and using an RC network box to iterate toward the final values; or by obtaining the optimum loop response using a network analyzer to measure the loop Gain and Phase. Layout: As in the design of any switching dc-to-dc converter, driver careful layout will ensure that there is a successful transition from design to production. One of the few drawbacks of switching dc-to-dc converters is the noise induced by their high-frequency switching. Parasitic inductance and capacitance may become significant
Document Number: 73541 S-52083-Rev. A, 10-Oct-05
f Z(ESR) =
1 2 (ESR)(C OUT)
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when a converter is switching at 500 kHz. However, noise levels can be minimized by properly laying out the components. Here are some general guidelines for laying out a step-down converter with the SIP12201. Since power traces in step down converters carry pulsating current, energy stored in trace inductance during the pulse can cause high-frequency ringing with input and output capacitors. Minimizing the length of the power traces will minimize the parasitic inductance in the trace. The same pulsating currents can cause voltage drops due to the trace resistance and cause effects such as ground bounce. Increasing the width of the power trace, which in-creases the cross sectional area, will minimize the trace resistance. In all dcto-dc converters the decoupling capacitors should be placed as close as possible to the pins being decoupled to reduce the noise. The connections to both terminals should be as short as possible with lowinductance (wide) traces. In the SIP12201 converters, the VIN is decoupled to PGND. It may be necessary to decouple VDD to AGND, with the decoupling capacitor being placed adjacent to the pin. AGND and PGND traces should be isolated from each other and only connected at a single node such as a "star ground".
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Document Number: 73541 S-52083-Rev. A, 10-Oct-05
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