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STLC3075
INTEGRATED POTS INTERFACE FOR HOME ACCESS GATEWAY AND WLL
1

FEATURES
MONOCHIP SLIC OPTIMISED FOR WLL & VoIP APPLICATIONS IMPLEMENT ALL KEY FEATURES OF THE BORSHT FUNCTION SINGLE SUPPLY (4.5 TO 12V) BUILT IN DC/DC CONVERTER CONTROLLER. SOFT BATTERY REVERSAL WITH PROGRAMMABLE TRANSITION TIME. ON-HOOK TRANSMISSION. PROGRAMMABLE OFF-HOOK DETECTOR THRESHOLD METERING PULSE GENERATION AND FILTER INTEGRATED RINGING INTEGRATED RING TRIP PARALLEL CONTROL INTERFACE (3.3V LOGIC LEVEL) PROGRAMMABLE CONSTANT CURRENT FEED SURFACE MOUNT PACKAGE INTEGRATED THERMAL PROTECTION DUAL GAIN VALUE OPTION AUTOMATIC RECOGNITION FLYBACK AND
Figure 1. Package
TQFP44
Table 1. Order Codes
Part Number STLC3075 Package TQFP44

BUCKBOOST CONFIGURATION BCDIIIS 90V TECNOLOGY -40 TO +85C OPERATING RANGE
2
DESCRIPTION
The STLC3075 is a SLIC device specifically designed for WLL (Wireless Local Loop), and ISDNTerminal Adaptors and VoIP applications. One of the distinctive characteristic of this device is the ability to operate with a single supply voltage (from +4.5V to +12V) and self generate the negative battery by means of an on chip DC/DC converter controller that drives an external MOS switch.
Figure 2. Block Diagram
PD D0 D1 D2 DET
GAIN SETTING
INPUT LOGIC AND DECODER
OUTPUT LOGIC
BGND
Status and functions
TIP TX RX ZAC1 ZAC RS ZB
LINE OUTPUT
SUPERVISION AC PROC
DRIVER
STAGE
RING
CREV
DC PROC
CSVR
CLK RSENSE GATE VF CZ
DC/DC
CKTTX CTTX1 CTTX2 FTTX
CONV.
TTX PROC
REFERENCE
Vcc Vss
Agnd
CVCC VPOS
VOLT.
REG.
VBAT
Vbat
RTTX
CAC
ILTF RD IREF RLIM RTH
AGND
January 2005
Rev. 3 1/26
STLC3075
2 DESCRIPTION (continued)
The battery level is properly adjusted depending on the operating mode. A useful characteristic for these applications is the integrated ringing generator. The control interface is a parallel type with open drain output and 3.3V logic levels. The metering pulses are generated on chip starting from two logic signals (0, 3.3V) one define the metering pulse frequency and the other the metering pulse duration. An on chip circuit then provides the proper shaping and filtering. Metering pulse amplitude and shaping (rising and decay time) can be programmed by external components. A dedicated cancellation circuit avoid possible CODEC input saturation due to Metering pulse echo. Constant current feed can be set from 20mA to 40mA. Off-hook detection threshold is programmable from 5mA to 9mA. The device, developed in BCDIIIS technology (90V process), operates in the extended temperature range and integrates a thermal protection that sets the device in power down when Tj exceeds 140C. Figure 3. Pin Connection
VBAT1 BGND 35 CREV VBAT CSVR 34 33 32 31 30 29 28 27 26 25 24 23 12 FTTX 13 RX 14 ZAC1 15 ZAC 16 RS 17 ZB 18 CAC 19 TX 20 CZ 21 VF 22 N.C. ILTF RD RTH IREF RLIM AGND CVCC VPOS RSENSE GATE CLK RING 37
N.C.
N.C.
44 D0 D1 D2 PD GAIN SET N.C. DET CKTTX CTTX1 CTTX2 RTTX 1 2 3 4 5 6 7 8 9 10 11
43
42
41
40
39
N.C.
38
N.C.
TIP
36
D00TL488
Table 2. Absolute Maximum Ratings
Symbol Vpos A/BGND Vdig Tj Vbtot
(1)
Parameter Positive Supply Voltage AGND to BGND Pin D0, D1, D2, DET, CKTTX Max. junction Temperature Vbtot=|Vpos|+|Vbat|. (Total voltage applied to the device supply pins). Human Body Model Charged Device Model
Value -0.4 to +13 -1 to +1 -0.4 to 5.5 150 90 1750 500
Unit V V V C V V V
ESD RATING
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)
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Table 3. Operating Range
Symbol Vpos A/BGND Vdig Top Vbat
(1)
Parameter Positive Supply Voltage AGND to BGND Pin D0, D1, D2, DET, CKTTX, PD Ambient Operating Temperature Range Self Generated Battery Voltage
Value 4.5 to +12 -100 to +100 -0.25 to 5.25 -40 to +85 -74 max.
Unit V mV V C V
(1) Vbat is self generated by the on chip DC/DC converter and can be programmed via RF1 and RF2. RF1 and RF2 shall be selected in order to fulfil the a.m limits (see External Components Table page 10)
Table 4. Thermal Data
Symbol Rth j-amb Parameter Thermal Resistance Junction to Ambient Typ. Value 60 Unit C/W
Table 5. Pin Description
N 1 2 3 4 5 6,22,38, 39,40,42 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Pin D0 D1 D2 PD Gain SET NC DET CKTTX CTTX1 CTTX2 RTTX FTTX RX ZAC1 ZAC RS ZB CAC TX CZ VF Control Interface: input bit 0. Control Interface: input bit 1. Control interface: input bit 2. Power Down input. Normally connected to CVCC (or to logic level high). Control gain interface: 0 Level Rxgain = 0dB Txgain = -6dB 1 Level Rxgain = +6dB Txgain = -12dB Not connected. Logic interface output of the supervision detector (active low). Metering pulse clock input (12 KHz or 16KHz square wave). Metering burst shaping external capacitor. Metering burst shaping external capacitor. Metering pulse cancellation buffer output. TTX filter network should be connected to this point. If not used should be left open. Metering pulse buffer input this signal is sent to the line and used to perform TTX filtering. 4 wire input port (RX input); 300K input impedance. This signal is referred to AGND. If connected to single supply CODEC output it must be DC decoupled with proper capacitor. RX buffer output (the AC impedance is connected from this node to ZAC). AC impedance synthesis. Protection resistors image (the image resistor is connected from this node to ZAC). Balance Network for 2 to 4 wire conversion (the balance impedance ZB is connected from this node to AGND. ZA impedance is connected from this node to ZAC1). AC feedback input, AC/DC split capacitor (CAC). 4 wire output port (TX output). The signal is referred to AGND. If connected to single supply CODEC input it must be DC decoupled with proper capacitor. Fly-Back compensation Feedback input for DC/DC converter controller. Function
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Table 5. Pin Description (continued)
N 23 Pin CLK Function Power Switch Controller Clock (typ. 125KHz). This pin can also be connected to CVCC or AGND. When the CLK pin is connected to CVCC an internal auto-oscillation is internally generated and it is used instead of the external clock. When the CLK pin is connected to AGND, the GATE output is disabled. Driver for external Power MOS transistor (P-chanell in Buck-boost configuration, N-channel in Fly-back configuration).
24 25
GATE
RSENSE Voltage input for current sensing. RSENSE resistor should be connected close to this pin and VPOS pin (Buck-boost) or GND (Fly-back). The PCB layout should minimize the extra resistance introduced by the copper tracks. VPOS CVCC AGND RLIM IREF RTH RD ILTF CSVR BGND VBAT RING TIP CREV Positive supply input. Internal positive voltage supply filter. Analog Ground, must be shorted with BGND. Constant current feed programming pin (via RLIM). RLIM should be connected close to this pin and AGND pin to avoid noise injection. Internal bias current setting pin. RREF should be connected close to this pin and AGND pin to avoid noise injection. Off-hook threshold programming pin (via RTH). RTH should be connected close to this pin and AGND pin to avoid noise injection. DC feedback and ring trip input. RD should be connected close to this pin and AGND pin to avoid noise injection. Transversal line current image output. Battery supply filter capacitor. Battery Ground, must be shorted with AGND. Regulated battery voltage self generated by the device via DC/DC converter. Must be shorted to VBAT1. 2 wire port; RING wire (Ib is the current sunk into this pin). 2 wire port; TIP wire (Ia is the current sourced from this pin). Reverse polarity transition time control. A proper capacitor connected between this pin and AGND is setting the reverse polarity transition time. This is the same transition time used to shape the "trapezoidal ringing" during ringing injection. Frame connection. Must be shorted to VBAT.
26 27 28 29 30 31 32 33 34 35 36 37 41 43
44
VBAT1
3
FUNCTIONAL DESCRIPTION
The STLC3075 is a device specifically developed for WLL VoIP and ISDN-TA applications. It is based on a SLIC core, on purpose optimised for these applications, with the addition of a DC/DC converter controller to fulfil the WLL and ISDN-TA design requirements. The SLIC performs the standard feeding, signalling and transmission functions. It can be set in three different operating modes via the D0, D1, D2 pins of the control logic interface (0 to 3.3V logic levels). The loop status is carried out on the DET pin (active low). The DET pin is an open drain output to allow easy interfacing with both 3.3V and 5V logic levels. The four possible SLIC's operating modes are:

Power Down High Impedance Feeding (HI-Z) Active Ringing
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Table 6 shows how to set the different SLIC operating modes. Table 6. SLIC operating modes.
PD 0 1 1 1 1 1 1 D0 0 0 0 0 1 1 1 D1 0 0 1 1 1 1 0 D2 X X 0 1 0 1 0/1 Power Down H.I. Feeding (HI-Z) Active Normal Polarity Active Reverse Polarity Active TTX injection (N.P.) Active TTX injection (R.P.) Ring (D2 bit toggles @ fring) Operating Mode
3.1 DC/DC Converter The DC/DC converter controller is driving an external power MOS transistor N-Ch plus transformer (Flyback configuration) or P-Ch plus inductor (BuckBoost configuration), in order to generate the negative battery voltage needed for device operation. The DC/DC converter controller is synchronised with an external CLK (125KHz typ.) or with an internal clock generated when the pin CLK is connected to CVCC. One Rsense in series to PGND supply (FlyBack) or to VPOS supply (BuckBoost) allows to fix the maximum allowed input peak current. This feature is implemented in order to avoid overload on Vpos supply in case of line transient (ex. ring trip detection). Typ. value is 110m for both configuration and it will guarantee an average current consumption from Vpos < 700mA for BuckBoost configuration and < 1.5A for Fly- Back configuration. The self generated battery voltage is set to a predefined value in on-hook state. This value can be adjusted via one external resistor (RF1) and it is typical -50V. When RING mode is selected this value is increased to -70V typ. Once the line goes in off-hook condition, the DC/DC converter automatically adjusts the generated battery voltage in order to feed the line with a fixed DC current (programmable via RLIM) optimising the power dissipation. 3.2 OPERATING MODES 3.2.1 Power Down When this mode is selected the SLIC is switched off and the TIP and RING pins are in high impedance. Also the line detectors are disabled therefore the off-hook condition cannot be detected. This mode can be selected in emergency condition when it is necessary to cut any current delivered to the line. This mode is also forced by STLC3075 in case of thermal overload (Tj > 140C). In this case the device goes back to the previous status as soon as the junction temperature decrease under the hysteresis threshold. No AC transmission is possible 3.2.2 High Impedance Feeding (HI-Z) This operating mode is normally selected when the telephone is in on-hook in order to monitor the line status keeping the power consumption at the minimum.
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The output voltage in on-hook condition is equal to the self generated battery voltage (-50V typ). When off-hook occurs the DET becomes active (low logic level). The off-hook threshold in HI-Z mode is the same value as programmed in ACTIVE mode. The DC characteristic in HI-Z mode is just equal to the self generated battery with 2x(1600+Rp) in series (see fig. 4), where Rp is the external protection resistance. No AC transmission is possibile. Figure 4. DC Characteristic in HI-Z Mode.
IL Vbat 2x(R1+Rp)
Slope: 2x(R1+Rp) (R1=1600ohm)
VL Vbat (-50V)
3.2.3 Active 3.2.3.1 DC Characteristics & Supervision When this mode is selected the STLC3075 provides both DC feeding and AC transmission. The STLC3075 feeds the line with a constant current fixed by RLIM (20mA to 40mA range). The on-hook voltage is typically 40V allowing on-hook transmission; the self generated Vbat is -50V typ. If the loop resistance is very high and the line current cannot reach the programmed constant current feed value, the STLC3075 behaves like a 40V voltage source with a series impedance equal to the protection resistors 2xRp (typ. 2x50). Fig. 5 shows the typical DC characteristic in ACTIVE mode. The line status (on/off hook) is monitored by the SLIC'S supervision circuit. The off-hook threshold can be programmed via the external resistor RTH in the range from 5mA to 9mA. Independently on the programmed constant current value, the TIP and RING buffers have a current source capability limited to 80mA typ. Figure 5. DC characteristic in ACTIVE mode
IL Ilim (20 to 40mA)
2Rp
10V
VL
Vbat (-50V)
Moreover the power available at Vbat is controlled by the DC/DC converter that limits the peak current drawn from the Vpos supply. The maximum allowed current peak is set by RSENSE resistor.
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3.2.3.2 AC Characteristics The SLIC provides the standard SLIC transmission functions: Once in active mode the SLIC can operate with two different Tx, Rx Gain. Setting properly by the Gain set control bit (see table7). Table 7. Gain Set in Active Mode
Gain set 0 1

4 to 2 wire Gain 0dB +6dB
2 to 4 wire Gain -6dB -12dB
Impedance Synthesis Scale Factor x 50 x 25
Input impedance synthesis: can be real or complex and is set by a scaled (x50 or x25) external ZAC impedance. Transmit and receive: The AC signal present on the 2W port (TIP/RING) is transferred to the TX output with a -6dB or -12dB gain and from the RX input to the 2W port with a 0dB or +6dB gain.
2 to 4 wire conversion: The balance impedance can be real or complex, the proper cancellation is obtained by means of two external impedance ZA and ZB Once in Active mode (D1=1) the SLIC can operate in different states setting properly D0 and D2 control bits (see also Table 8). Table 8. SLIC states in ACTIVE mode
D0 0 0 1 1 D1 1 1 1 1 D2 0 1 0 1 Active Normal Polarity Active Reverse Polarity Active TTX injection (N.P.) Active TTX injection (R.P.) Operating Mode
3.2.3.3 Polarity Reversal The D2 bit controls the line polarity, the transition between the two polarities is performed in a "soft" way. This means that the TIP and RING wire exchange their polarities following a ramp transition (see fig. 6). The transition time is controlled by an external capacitor CREV. This capacitor is also setting the shape of the ringing trapezoidal waveform. When the control pins set battery reversal the line polarity is reversed with a proper transition time set via an external capacitor (CREV). Figure 6. TIP/RING typical transition from Direct to Reverse Polarity
GND TIP
4V typ.
40V typ ON-HOOK
dV/dT set by CREV RING
3.2.3.4 Metering Pulse Injection (TTX) The metering pulses circuit consist of a burst shaping generator that gives a square wave shaped and a low pass filter to reduce the harmonic distortion of the output signal.
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The metering pulse is obtained starting from two logic signals:
CKTTX: is a square wave at the TTX frequency (12 or 16KHz) and should be permanently applied to the CKTTX pin or at least for all the duration of the TTX pulse (including rising and decay phases).
D0: enable the TTX generation circuit and define the TTX pulse duration. These two signals are processed by a dedicated circuitry integrated on chip that generate the metering pulse as an amplitude modulated shaped squarewave (SQTTX) (see fig. 7).
Both the amplitude and the envelope of the squarewave (SQTTX) can be programmed by means of external components. In particular the amplitude is set by the two resistors RLV and the shaping by the capacitor CS. Figure 7. Metering pulse generation circuit.
Low Pass Filter
CTTX1
C1
RLV BURST
SHAPING GENERATOR
CS
SQTTX
R1 CFL
R2 FTTX OP1
+
RTTX
C2
RLV
Sinusoidal wave pulse metering
Required external components vs. filter order.
CTTX2 D0 CKTTX
Order
CFL
R1
C1
R2
C2
THD
1 2 3
Square wave pulse metering
X X X X X X X X X X
13% 6% 3%
The waveform so generated is then filtered and injected on the line. The low pass filter can be obtained using the integrated buffer OP1 connected between pin FTTX (OP1 non inverting input) and RTTX (OP1 output) (see fig. 7) and implementing a "Sallen and Key" configuration. Depending on the external components count it is possible to build an optimised application depending on the distortion level required. In particular harmonic distortion levels equal to 13%, 6% and 3% can be obtained respectively with first, second and third order filters (see fig. 7). The circuit showed in the "Application diagram" is related to the simple first order filter. Once the shaped and filtered signal is obtained at RTTX buffer output it is injected on the TIP/RING pins with a +6dB gain or +12dB gain. It should be noted that this is the nominal condition obtained in presence of ideal TTX echo cancellation (obtained via proper setting of RTTX and CTTX). In addition the effective level obtained on the line will depend on the line impedance and the protection resistors value. In the typical application (TTX line impedance =200 , RP = 50, and ideal TTX echo cancellation) the metering pulse level on the line will be 1.33 or 2.66 times the level applied to the RTTX pin. As already mentioned the metering pulse echo cancellation is obtained by means of two external components (RTTX and CTTX) that should match the line impedance at the TTX frequency. This simple network has a double effect:

Synthesize a low output impedance at the TIP/RING pins at the TTX frequency. Cut the eventual TTX echo that will be transferred from the line to the TX output.
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3.2.4 Ringing When this mode is selected STLC3075 self generate an higher negative battery (-70V typ.) in order to allow a balanced ringing signal of typically 65Vpeak. In this condition both the DC and AC feedback loop are disabled and the SLIC line drivers operate as voltage buffers. The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in fact controls the line polarity (0=direct; 1= reverse). As in the ACTIVE mode the line voltage transition is performed with a ramp transition, obtaining in this way a trapezoidal balanced ring waveform (see fig. 8). The shaping is defined by the CREV external capacitor. Figure 8. TIP/RING typical ringing waveform
GND TIP
2.5V typ.
65V typ.
dV/dT set by CREV RING VBAT
2.5V typ.
Selecting the proper capacitor value it is possible to get different crest factor values. The following table shows the crest factor values obtained with a 20Hz and 25Hz ring frequency and with 1REN. These value are valid either with European or USA specification: Table 9.
CREV CREST FACTOR @20Hz CREST FACTOR @25Hz
22nF 27nF 33nF
(*) Distorsion already less than 10%.
1.2 1.25 1.33
1.26 1.32 Not significant (*)
The ring trip detection is performed sensing the variation of the AC line impedance from on hook (relatively high) to off-hook (low). This particular ring trip method allows to operate without DC offset superimposed on the ring signal and therefore obtaining the maximum possible ring level on the load starting from a given negative battery. It should be noted that such a method is optimised for operation on short loop applications and may not operate properly in presence of long loop applications (> 500). Once ring trip is detected, the DET output is activated (logic level low), at this point the card controller or a simple logic circuit should stop the D2 toggling in order to effectively disconnect the ring signal and then set the STLC3075 in the proper operating mode (normally ACTIVE). 3.2.4.1 Ring Level in Presence of More Telephone in Parallel As already mentioned above the maximum current that can be drawn from the Vpos supply is controlled and limited via the external RSENSE. This will limit also the power available at the self generated negative battery. If for any reason the ringer load is too low the self generated battery will drop in order to keep the power
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STLC3075
consumption to the fixed limit and therefore also the ring voltage level will be reduced. In the typical application with RSENSE = 110m the peak current from Vpos is limited to about 900mA, which correspond to an average current of 700mA max. In this condition the STLC3075 can drive up to 3REN with a ring frequency fr=25Hz (1REN = 1800 + 1.0F, European standard). In order to drive up to 5REN (1REN= 6930 + 8F, US standard) it is necessary to modify the external components as follows: CREV = 15nF RD = 2.2K RSENSE = 100m 3.2.5 Layout Recommendation A properly designed PCB layout is a basic issue to guarantee a correct behaviour and good noise performances. Particular care must be taken on the ground connection and in this case the star configuration allows surely to avoid possible problems (see Application Diagram Figg. 11,12). The ground of the power supply (VPOS) has to be connected to the center of the star, let's call this point SYSTEM-GND. This point should show a resistance as low as possible, that means it should be a ground plane. In particular to avoid noise problems the layout should prevent any coupling between the DC/DC converter components and analog pins that are referred to AGND (ex: RD, IREF, RTH, RLIM, VF). As a first reccomendation the components CV, L, T1, D1, CVPOS, RSENSE should be kept as close as possible to each other and isolated from the other components. Additional improvements can be obtained: decoupling the center of the star from the analog ground of STLC3075 using small chokes. adding a capacitor in the range of 100nF between VPOS and AGND in order to filter the switch frequency on VPOS. 3.2.6 External Components List In order to properly define the external components value the following system parameters have to be defined:

The AC input impedance shown by the SLIC at the line terminals "Zs" to which the return loss measurement is referred. It can be real (typ. 600) or complex. The AC balance impedance, it is the equivalent impedance of the line "Zl" used for evaluation of the trans-hybrid loss performances (2/4 wire conversion). It is usually a complex impedance. The value of the two protection resistors Rp in series with the line termination. The line impedance at the TTX frequency "Zlttx". The metering pulse level amplitude measured at line termination "VLOTTX". In case of low order filtering, VLOTTX represents the amplitude (Vrms) of the fundamental frequency component. (typ 12 or 16KHz). Pulse metering envelope rise and decay time constant "". The slope of the ringing waveform "VTR/T ". The value of the constant current limit current "Ilim". The value of the off-hook current threshold "ITH". The value of the ring trip rectified average threshold current "IRTH". The value of the required self generated negative battery "VBATR" in ring mode (max value is 70V). This value can be obtained from the desired ring peak level + 5V. The value of the maximum current peak drawn from Vpos "IPK".
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Table 10. External Components for BuckBoost configuration
Name Function Formula Typ. Value
RREF CSVR RD CAC RP RLIM RTH CREV RDD CVCC CVpos
Bias setting current Negative Battery Filter Ring Trip threshold setting resistor AC/DC split capacitance Line protection resistor Current limiting programming Off-hook threshold programming (ACTIVE mode) Reverse polarity transition time programming Pull up resistors Internally supply filter capacitor Positive supply filter capacitor with low impedance for switch mode power supply Battery supply filter capacitor with low impedance for switch mode power supply High frequency noise filter High frequency noise filter DC/DC converter switch P ch. MOS transistor
RREF = 1.3/Ibias Ibias = 50A CSVR = 1/(2 fp 1.8M) fp = 50Hz RD = 100/IRTH 2K < RD < 5K
26k 1% 1.5nF 10% 100V 4.12k 1% @ IRTH = 24mA 22F 20% 15V @ RD = 4.12k
Rp > 30 RLIM = 1300/Ilim 32.5k < RLIM < 65k RTH = 290/ITH 27k < RTH < 52k CREV = ((1/3750) * T/VTR)
50 1% 52.3k 1% @ Ilim = 25mA 32.4k 1% @ITH = 9mA 22nF 10% 10V @ 12V/ms 100k 100nF 20% 10V 100F(4)
CV
100F 20% 100V (5)
CVB CRD (6) Q1
470nF 20% 100V 100nF 10% 15V RDS(ON)1.2,VDS = -100V Total gate charge=20nC max. with VGS=4.5V and VDS=1V ID>500mA Vr > 100V, tRR 50ns RSENSE = 100mV/IPK 250KD1
DC/DC converter series diode
RSENSE DC/DC converter peak current limiting RF1 RF2 L Negative battery programming level
Negative battery programming level
DC/DC converter inductor
Table 11. External Components for Fly-back configuration
Name Function Formula Typ. Value
RREF CSVR RD CAC
Bias setting current Negative Battery Filter Ring Trip threshold setting resistor AC/DC split capacitance
RREF = 1.3/Ibias; Ibias = 50A CSVR = 1/(2 fp 1.8M) fp = 50Hz RD = 100/IRTH 2K < RD < 5K
26k 1% 1.5nF 10% 100V 4.12k 1% @ IRTH = 24mA 22F 20% 15V @ RD = 4.12k
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Table 11. External Components for Fly-back configuration (continued)
Name Function Formula Typ. Value
RP RLIM RTH CREV RDD CVCC CVpos
Line protection resistor Current limiting programming Off-hook threshold programming (ACTIVE mode) Reverse polarity transition time programming Pull up resistors Internally supply filter capacitor Positive supply filter capacitor with low impedance for switch mode power supply Battery supply filter capacitor with low impedance for switch mode power supply High frequency noise filter High frequency noise filter Fly-Back compensation capacitor Sense Filter capacitor Sense Filter resistor
Rp > 30 RLIM = 1300/Ilim 32.5k < RLIM < 65k RTH = 290/ITH 27k < RTH < 52k CREV = ((1/3750) * T/VTR)
50 1% 52.3k 1% @ Ilim = 25mA 32.4k 1% @ITH = 9mA 22nF 10% 10V @ 12V/ms 100k 100nF 20% 10V 100F(4)
CV
100F 20% 100V (5)
CVB CRD (6) CZ CSF RSF
470nF 20% 100V 100nF 10% 15V 2.2nF, 20% 120pF, 20% 1k RSENSE = 375mV/IPK RDS(ON)0.05,VDSS = 30V VDG=30V, ID = 6.5A Low threshold drive Vr > 350V, tRR 80ns Fly-Back transformer 4W, Turns Ratio 1:16 fro VPOS range from 4.5V to 8.5V Fly-Back transformer 4W, Turns Ratio 1:8 fro VPOS range from 8.5V to 12V 250KRSENSE DC/DC converter peak current limiting Q1 DC/DC converter switch Nchan MOS transistor DC/DC converter series diode DC/DC Converter transformer
D1 T1
T1
DC/DC Converter transformer
RF1 RF2
Negative battery programming level
Negative battery programming level
Table 12. External Components @Gain Set = 0
Name Function Formula Typ. Value
RS ZAC ZA (1) ZB (1) CCOMP CH
Protection resistance image Two wire AC impedance
Line impedance balancing network
RS = 50 (2Rp) ZAC = 50 (Zs - 2Rp) ZB = 50 Zl fo = 250kHz CCOMP = 1/(2fo100(RP)) CH = CCOMP RTTX = 50Re (Zlttx+2Rp)
5k @ Rp = 50 25k 1% @ Zs = 600 30k 1% @ Zs = 600 30k 1% @ Zl = 600
120pF 10% 10V @ Rp = 50
SLIC impedance balancing network ZA = 50 Zs
AC feedback loop compensation Trans-Hybrid Loss frequency compensation
120pF 10% 10V 15k @Zlttx = 200 real
RTTX (3) Pulse metering cancellation resistor
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Table 12. External Components @Gain Set = 0 (continued)
Name Function Formula Typ. Value
CTTX (3) Pulse metering cancellation capacitor RLV CS CFL Pulse metering level resistor
CTTX = 1/{502fttx[-lm(Zlttx)]} RLV = 63.3*103***VLOTTX = (|Zlttx + 2Rp|/|Zlttx|)
100nF 10% 10V (2) @ Zlttx = 200 real 16.2k @ VLOTTX = 170mVrms 100nF 10% 10V @ = 3.2ms, RLV = 16.2k 1.5nF 10% 10V @fttx = 12kHz RLV = 16.2k
Pulse metering shaping capacitor CS = /(2RLV) Pulse metering filter capacitor CFL = 2/(2fttxRLV)
Table 13. External Components @Gain Set = 1
Name Function Formula Typ. Value
RS ZAC ZA (1) ZB (1) CCOMP CH
Protection resistance image Two wire AC impedance SLIC impedance balancing network Line impedance balancing network AC feedback loop compensation Trans-Hybrid Loss frequency compensation
RS = 25 (2Rp) ZAC = 25 (Zs - 2Rp) ZA = 25 Zs ZB = 25 Zl fo = 250kHz CCOMP = 2/(2fo100(RP)) CH = CCOMP RTTX = 25Re (Zlttx+2Rp) CTTX = 1/252fttx[-lm(Zlttx)] RLV = 31.7*103***VLOTTX = (|Zlttx + 2Rp|/|Zlttx|)
2.55k @ Rp = 50 12.5k 1% @ Zs = 600 15k 1% @ Zs = 600 15k 1% @ ZI = 600
220pF 10% 10VL @ Rp = 50
220pF 10% 10V 7.5k @Zlttx = 200 real 100nF 10% 10V (2) @ Zlttx = 200 real 16.2k @ VLOTTX = 340mVrms 100nF 10% 10V @ = 3.2ms, RLV = 16.2k 1.5nF 10% 10V @fttx = 12kHz RLV = 16.2k
RTTX (3) Pulse metering cancellation resistor CTTX (3) Pulse metering cancellation capacitor RLV CS CFL Pulse metering level resistor
Pulse metering shaping capacitor CS = /(2RLV) Pulse metering filter capacitor CFL = 2/(2fttxRLV)
(1) In case Zs=Zl, ZA and ZB can be replaced by two resistors of same value: RA=RB=|Zs|. (2) In this case CTTX is just operating as a DC decoupling capacitor (fp=100Hz). (3) Defining ZTTX as the impedance of RTTX in series with CTTX, RTTX and CTTX can also be calculated from the following formula: ZTTX=50*(Zlttx+2Rp). (4) CVpos should be defined depending on the power supply current capability and maximum allowable ripple. (5) For low ripple application use 2x47 F in parallel. (6) Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input). (7) RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as follows: 267k -46V -62V 280k -48V -65V 294k -49V -68V 300k -50V -70V
VBAT(ACTIVE) VBATR(RING)
VBATR should be defined considering the ring peak level required (Vringpeak=VBATR-6V typ.). The above relation is valid provided that the Vpos power supply current capability and the RSENSE programming allow to source all the current requested by the particular ringer load configuration. (8) For high efficiency in HI-Z mode coil resistance @125kHz must be < 3
13/26
STLC3075
Figure 9. Application Diagram with N-Channel.
RX TX CVCC VPOS CVPOS
T1 RS RX RS ZAC CCOMP ZAC ZA ZB CH VDD RDD GAIN SET ZB VF CZ CLK RP CONTROL INTERFACE DET D0 D1 D2 PD TTX CLOCK RLV CTTX1 RLV CS CTTX2 FTTX CFL RTTX CAC ILTF RD DET D0 D1 D2 PD CKTTX RTH RLIM IREF RREF RLIM RTH CLK TIP RP RING CSVR CREV CREV CSVR RING VBAT CVB RF1 CV RF2 ZAC1 TX AGND BGND CVCC VPOS GATE RSF RSENSE CSF RSENSE D1 Q1 N-ch
CZ
STLC3075
TIP
RTTX AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CTTX CAC
RD
CRD
D04TL625
PGND
Figure 10. Application Diagram without Metering Pulse Generation with N-Channel.
RX TX CVCC VPOS CVPOS
T1 RS RX RS ZAC CCOMP ZAC ZA ZB CH VDD RDD GAIN SET ZB VF CZ CZ RF2 VBAT CVB RF1 CV ZAC1 TX AGND BGND CVCC VPOS GATE RSF RSENSE CSF RSENSE D1 Q1 N-ch
STLC3075
CONTROL INTERFACE DET D0 D1 D2 PD DET D0 D1 D2 PD CKTTX CTTX1 CTTX2 FTTX RTTX CAC ILTF RD
CLK RP TIP RP RING CSVR CREV
CLK TIP RING
CREV RTH RLIM IREF RREF RLIM
CSVR
RTH
RD AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CAC
CRD
D04TL626
PGND
14/26
STLC3075
Figure 11. Application Diagram with P-Channel.
CVCC RX TX VPOS CVPOS RSENSE
RS
RX RS ZAC
TX
AGND BGND
CVCC
VPOS RSENSE GATE D1 VBAT CVB RF1 CV RF2 L Q1 P-ch
CCOMP ZAC ZA
ZAC1
ZB CH VDD RDD GAIN SET ZB
VF
CLK TIP
CLK RP TIP RP RING
STLC3075
CONTROL INTERFACE DET D0 D1 D2 PD TTX CLOCK RLV CTTX1 RLV CS CTTX2 FTTX CFL RTTX CAC ILTF RD DET D0 D1 D2 PD CKTTX
RING
CSVR CREV CREV RTH RLIM IREF RREF RLIM RTH CSVR
RTTX AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CTTX CAC
RD
CRD
D01TL493A
PGND
Figure 12. Application Diagram without Metering Pulse Generation.
CVCC RX TX VPOS CVPOS RSENSE
RS
RX RS ZAC
TX
AGND BGND
CVCC
VPOS RSENSE GATE D1 VBAT CVB RF1 CV RF2 L Q1 P-ch
CCOMP ZAC ZA
ZAC1
ZB CH VDD RDD ZB
VF
CLK GAIN SET
CLK RP TIP RP RING
STLC3075
CONTROL INTERFACE DET D0 D1 D2 PD DET D0 D1 D2 PD CKTTX CTTX1 CTTX2 FTTX RTTX CAC ILTF RD
TIP RING
CSVR CREV CREV RTH RLIM IREF RREF RLIM RTH CSVR
RD AGND BGND SYSTEM GND SUGGESTED GROUND LAY-OUT CAC
CRD
D01TL494A
PGND
15/26
STLC3075
4
ELECTRICAL CHARACTERISTICS
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85C.
Symbol Parameter Test Condition Min. Typ. Max. Unit
DC CHARACTERISTICS
Vlohi
Line voltage
Il = 0, HI-Z (High impedance feeding) Tamb = 0 to 85C Il = 0, HI-Z (High impedance feeding) Tamb = -40 to 85C Il = 0, ACTIVE Tamb = 0 to 85C Il = 0, ACTIVE Tamb = -40 to 85C ACTIVE mode ACTIVE mode. Rel. to programmed value 20mA to 40mA HI-Z (High Impedance feeding)
44
50
V
Vlohi
Line voltage
42
48
V
Vloa Vloa Ilim Ilima
Line voltage Line voltage Lim. current programming range Lim. current accuracy
33 31 20 -10
40 37 40 10
V V mA %
Rfeed HI
Feeding resistance
2.4
3.6
k
AC CHARACTERISTICS
L/T
Long. to transv. (see Appendix for test circuit) Transv. to long. (see Appendix for test circuit) Transv. to long. (see Appendix for test circuit) 2W return loss Trans-hybrid loss
Rp = 50, 1% tol., ACTIVE N. P., RL = 600 (*) f = 300 to 3400Hz Rp = 50, 1% tol., ACTIVE N. P., RL = 600 (*) f = 300 to 3400Hz Rp = 50, 1% tol., ACTIVE N. P., RL = 600 (*) f = 1kHz 300 to 3400Hz, ACTIVE N. P., RL = 600 (*) 300 to 3400Hz, 20Log|VRX/VTX|, ACTIVE N. P., RL = 600 (*)
at line terminals on ref. imped. ACTIVE N. P., RL = 600 (*)
50
58
dB
T/L
40
45
dB
T/L
48
53
dB
2WRL THL
22 30
26
dB dB
Ovl TXoff G24 G42
2W overload level TX output offset Transmit gain abs. Receive gain abs.
3.2 -250 -6.4 -0.4 250 -5.6 0.4
dBm mV dB dB
ACTIVE N. P., RL = 600 (*) 0dBm @ 1020Hz, ACTIVE N. P., RL = 600 (*) 0dBm @ 1020Hz, ACTIVE N. P., RL = 600 (*)
16/26
STLC3075
4
ELECTRICAL CHARACTERISTICS
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85C.
Symbol Parameter Test Condition Min. Typ. Max. Unit
G24f
TX gain variation vs. freq.
rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., RL = 600 (*) rel. 1020Hz; 0dBm, 300 to 3400Hz, ACTIVE N. P., RL = 600 (*) psophometric filtered ACTIVE N. P., RL = 600 (*) Tamb = 0 to +85C psophometric filtered ACTIVE N. P., RL = 600 (*) Tamb = -40 to +85C psophometric filtered ACTIVE N. P., RL = 600 (*) Tamb = 0 to +85C psophometric filtered ACTIVE N. P., RL = 600 (*) Tamb = -40 to +85C ACTIVE N. P., RL = 600 (*) ACTIVE - TTX Zl = 200 fttx = 12kHz
-0.12
0.12
dB
G24f
RX gain variation vs. freq.
-0.12
0.12
dB
V2Wp
Idle channel noise at line 0dB gainset Idle channel noise at line 0dB gainset Idle channel noise at line 0dB gainset Idle channel noise at line 0dB gainset Total Harmonic Distortion Metering pulse level on line CLK operating range
-73
-68
dBmp
V2Wp
-68
dBmp
V4Wp
-75
-70
dBmp
V4Wp
-75
dBmp
Thd VTTX CLKfreq
-44 130 -10% 170 125 10%
dB mVrms kHz
(*) RL: Line Resistance
RING
Vring
Line voltage
RING D2 toggling @ fr = 25Hz Load = 3REN; Crest Factor = 1.25 1REN = 1800 + 1.0F Tamb = 0 to +85C RING D2 toggling @ fr = 25Hz Load = 3REN; Crest Factor = 1.25 1REN = 1800 + 1.0F Tamb = -40 to +85C
45
49
Vrms
Vring
Line voltage
44
48
Vrms
DETECTORS
IOFFTHA ROFTHA IONTHA
Off/hook current threshold Off/hook loop resistance threshold On/hook current threshold
ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA)
10.5 3.4 6
mA k mA
17/26
STLC3075
4
ELECTRICAL CHARACTERISTICS
Test conditions: Vpos = 6.0V, AGND = BGND, Normal Polarity, Tamb = 25C. External components as listed in the "Typical Values" column of EXTERNAL COMPONENTS Table. Note: Testing of all parameter is performed at 25C. Characterisation as well as design rules used allow correlation of tested performances at other temperatures. All parameters listed here are met in the operating range: -40 to +85C.
Symbol Parameter Test Condition Min. Typ. Max. Unit
RONTHA IOFFTHI ROFFTHI IONTHI RONTHI Irt Irta Trtd Td Rlrt (1) ThAl
On/hook loop resistance threshold Off/hook current threshold Off/hook loop resistance threshold On/hook current threshold On/hook loop resistance threshold Ring Trip detector threshold range Ring Trip detector threshold accuracy Ring trip detection time Dialling distortion Loop resistance Tj for th. alarm activation
ACT. mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) Hi Z mode, RTH = 32.4k 1% (Prog. ITH = 9mA) RING RING RING ACTIVE
8 10.5 800 6 8 20 -15 TBD -1 1 500 160 50 15
k mA
mA k mA % ms ms
C
(1) Rlrt = Maximum loop resistance (incl. telephone) for correct ring trip detection.
DIGITAL INTERFACE INPUTS: D0, D1, D2, PD, CLK OUTPUTS: DET
Vih Vil Iih Iil Vol
In put high voltage Input low voltage Input high current Input low current Output low voltage Iol = 1mA
2 0.8 -10 -10 10 10 0.45
V V
A A
V
PSRR AND POWER CONSUMPTION
PSERRC Ivpos
Power supply rejection Vpos to 2W port Vpos supply current @ ii = 0
Vripple = 100mVrms 50 to 4000Hz HI-Z On-Hook ACTIVE On-Hook, RING (line open) RING Off-Hook RSENSE = 110m
26
36 13 50 55 25 80 90 +20%
dB mA mA mA mApk
Ipk
Peak current limiting accuracy
-20%
950
18/26
STLC3075
5
APPENDIX A
5.1 STLC3075 Test Circuits Referring to the application diagram shown in fig. 11 and using as external components the Typ. Values specified in the "External Components" Tables 10 and 12 (pages 11 and 12) find below the proper configuration for each measurement. All measurements requiring DC current termination should be performed using "Wandel & Goltermann DC Loop Holding Circuit GH-1" or equivalent. Figure 13. 2W Return Loss 2WRL = 20Log(|Zref + Zs|/|Zref-Zs|) = 20Log(E/2Vs)
W&G GH1 Zref TIP 600ohm 100 F Vs 1Kohm E
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3075 application circuit
1Kohm
100 F RING RX
Figure 14. THL Trans Hybrid Loss THL = 20Log|Vrx/Vtx|
W&G GH1 TIP 100 F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx
600ohm
STLC3075 application circuit
100 F RING RX Vrx
19/26
STLC3075
Figure 15. G24 Transmit Gain G24 = 20Log|2Vtx/E|
W&G GH1 TIP 100 F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx
600ohm
STLC3075 application circuit
E 100 F RING RX
Figure 16. G42 Receive Gain G42 = 20Log|VI/Vrx|
W&G GH1 TIP 100 F Vl 600ohm
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3075 application circuit
100 F RING RX Vrx
Figure 17. PSRRC Power supply rejection Vpos to 2W port PSSRC = 20Log|Vn/Vl|
W&G GH1 TIP 100 F Vl 600ohm
100mA DC max Zin = 100K 200 to 6kHz
TX
STLC3075 application circuit
100 F RING VPOS RX
~
Vn
20/26
STLC3075
Figure 18. L/T Longitudinal to Transversal Conversion L/T = 20Log|Vcm/Vl|
W&G GH1 100 F TIP 100 F
100mA DC max Zin = 100K 200 to 6kHz
300ohm
TX
Impedance matching better than 0.1%
Vcm
Vl
STLC3075 application circuit
100 F RING RX
300ohm
100 F
Figure 19. T/L Transversal to Longitudinal Conversion T/L = 20Log|Vrx/Vcm|
300ohm
100 F
W&G GH1 TIP 100 F
100mA DC max
TX
Impedance matching better than 0.1%
Zin = 100K 200 to 6kHz
STLC3075 application circuit
600ohm
Vcm
100 F RING RX Vrx
300ohm
100 F
Figure 20. VTTX Metering Pulse level on line
TIP
TX
Vlttx 200ohm
STLC3075 application circuit
RING
RX CKTTX fttx (12 or 16kHz)
21/26
STLC3075
Figure 21. V2Wp and W4Wp: Idle channel psophometric noise at line and TX. V2Wp = 20Log|Vl/0.774l|; V4Wp = 20Log|Vtx/0.774l|
W&G GH1 TIP 100 F
100mA DC max Zin = 100K 200 to 6kHz
TX Vtx psophometric filtered
600ohm Vl psophometric filtered
STLC3075 application circuit
100 F RING RX
6
APPENDIX B
6.1 STLC3075 Overvoltage Protection Figure 22. Simplified configuration for indoor overvoltage protection
BGND
STPR120A
STLC3075
TIP SM6T39A 2x RING RP1 RP1 RP2 RP2 TIP RING
VBAT STPR120A
RP1 = 30ohm: RP2 =Fuse or PTC > 18ohm
Figure 23. Standard overvoltage protection configuration for K20 compliance
BGND
STLC3075
TIP 2x SM6T39A
RP1
LCP1521
RP2
TIP
RING
RP1
RP2
RING
VBAT
RP1 = 30ohm: RP2 =Fuse or PTC > 18ohm
22/26
STLC3075
7
APPENDIX C
7.1 TYPICAL STATE DIAGRAM FOR STLC3075 OPERATION Figure 24.
Normally used for On Hook Transmission Tj>Tth PD=0, D0=D1=0 Power Down Active On Hook Ring Pause D0=0, D1=1, D2=0
Ring Burst
Ring Burst D0=1, D1=0, D2=0/1 PD=1, D0=D1=0 HI-Z Feeding Active Off Hook Off Hook Detection D0=0, D1=1, D2=0 Ringing
On Hook Detection for T>Tref Ring Trip Detection
On Hook Condition
Off Hook Detection
Note: all state transitions are under the microprocessor control.
23/26
STLC3075
Figure 25. TQFP44 (10 x 10) Mechanical Data & Package Dimensions
mm DIM. MIN. A A1 A2 B C D D1 D3 E E1 E3 e L L1 k 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 12.00 10.00 8.00 0.80 0.60 1.00 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.004 0.464 0.386 0.472 0.394 0.315 0.472 0.394 0.315 0.031 0.024 0.039 0.030 0.480 0.401 0.055 0.015 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch
OUTLINE AND MECHANICAL DATA
TQFP44 (10 x 10 x 1.4mm)
0(min.), 3.5(typ.), 7(max.)
D D1 A A2 A1
33 34 23 22
0.10mm .004 Seating Plane
E1
B
44 1 11
12
E
B C L K
e
TQFP4410
0076922 D
24/26
STLC3075
Table 14. Revision History
Date Revision Description of Changes
October 2004 November 2004
1 2
First Issue Removed all max. values of the `Line Voltage' parameter on the page 16/26. Changed the unit from mA to % of the `Ilima' parameter on the page 16/ 26. Add pin 4 PD in Applications and Block Diagram . Add in Table 2 `ESD Rating'
January 2005
3
25/26
STLC3075
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2005 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com
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