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Micrel, Inc.
3.3V 28Mbps-2.7Gbps AnyRate(R) CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT
DESCRIPTION
SY87721L
SY87721L
FEATURES
s Recovers any data and clock from 28Mbps to 2.7Gbps * OC-1, OC-3, OC-12, OC-48, ATM * Gigabit Ethernet, Fast Ethernet * Fibre Channel, 2x Fibre Channel * P1394, Infiniband * SMPTE-259, SMPTE-292 * Proprietary optical transport s Integrated clock multiplier unit with low jitter generation s Complies with Bellcore, ITU/CCITT and ANSI specifications s Selectable mux for pass through; avoids jitter accumulation when switching through backplanes s Available in 64-Pin EPAD-TQFP package
The SY87721L is a complete Clock Recovery and Data retiming integrated circuit for data rates from 28Mbps up to 2.7Gbps NRZ including SONET FEC data rates. Included in the device, is a fully integrated Clock Multiplier Unit (CMU) that is capable of generating frequencies that cover the same data rate range as the CDR. The device is ideally suited for SONET/SDH/ATM, Fibre Channel, and Gigabit Ethernet applications, as well as other high-speed data transmission applications. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate or code group rate source as reference.
SIMPLIFIED BLOCK DIAGRAM
SY87721L AnyRate Data In 2 CDR AnyRate Data Out 2 2 Recovered Clock Reference Clock 2 CMU 2 Transmit Clock
APPLICATIONS
s SONET/SDH/ATM-based transmission systems, modules, and test equipment s Transponders and section repeaters s Multiplexers: access, add drop (ADM), and terminal (TM) s Terabit routers and broadband cross-connects s Fiber optic test equipment
AnyRate is a registered trademark of Micrel, Inc. M9999-072705 hbwhelp@micrel.com or (408) 955-1690
1
Rev.: B
Amendment: /0
Issue Date: July 2005
Micrel, Inc.
SY87721L
SYSTEM BLOCK DIAGRAM
SY889x3
FIBER PIN DIODE TIA POST AMP
SY87721L
RDATA
SY87724L
4, 5, 8, 10 bits RCLK DEMUX LOCK
AnyRate(R)
CDR
TCLK
MUX
4, 5, 8, 10 bits
SY87729L
REF_CLK
CMU
AnyClockTM
27MHz Fractional Synthesizer SEL
SY889x2
FIBER LASER DIODE LASER DIODE DRIVER
OC-48 EYE DIAGRAM
Time (100ps/div)
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SY87721L
FUNCTIONAL BLOCK DIAGRAM
PLLRW+ PLLRW--
PLLRN+ PLLRN--
ALRSEL
BRDMX
BRD Mux
BRD+ BRD--
RDOUTE+ RDIN+ RDIN-- Phase Detector/ Data Recovery Charge Pump N/W
Mux
RDOUTE-- RDOUTC+ VCO N/W1/W2/W3 RDOUTC-- RCLKE+ RCLKE-- RCLKC+ RCLKC--
Phase/ Frequency Detector
CD
Link Fault Detector
LFIN
REFCLK+ REFCLK-- Phase/ Frequency Detector Charge Pump N/W
Mux
VCO N/W1/W2/W3
Divide by 1, 2, 4, 8, 10, 16, 20, 32
TCLKE+ TCLKE-- TCLKC+ TCLKC--
PLLSN--
PLLSW--
FREQSEL3 FREQSEL2 FREQSEL1
DIVSEL1
VCOSEL2 VCOSEL1
DIVSEL3
DIVSEL2
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PLLSW+
ENPECL
CLKSEL
PLLSN+
Micrel, Inc.
SY87721L
PACKAGE/ORDERING INFORMATION
Ordering Information(1)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 GND ENPECL RDOUTE+ RDOUTE-- RDOUTC+ RDOUTC-- VCCO RCLKE+ RCLKE-- RCLKC+ RCLKC-- VCCO TCLKE+ TCLKE-- TCLKC+ TCLKC--
RDIN+ RDIN-- LFIN BRD+ BRD-- VCCO VCC BRDMX GND VCC GND CD FREQSEL3 FREQSEL2 FREQSEL1 VCOSEL2
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VCOSEL1 PLLRN+ PLLRN-- NC PLLRW+ PLLRW-- NC VCCA GNDA PLLSW-- PLLSW+ NC PLLSN-- PLLSN+ NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Part Number SY87721LHI SY87721LHITR(2) SY87721LHG(3) SY87721LHG(2, 3)
Package Type H64-1 H32-1 H32-1 H32-1
Operating Range Industrial Industrial Industrial Industrial
Package Marking SY87721LHI SY87721LHI SY87721LHG with Pb-Free bar-line indicator SY87721LHG with Pb-Free bar-line indicator
Lead Finish Sn-Pb Sn-Pb Pb-Free NiPdAu Pb-Free NiPdAu
64-Pin EPAD-TQFP
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC DIVSEL1 DIVSEL2 DIVSEL3 ALRSEL CLKSEL GND VCC GND GND GND GND VCC REFCLK-- REFCLK+ GND
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC electricals only. 2. Tape and Reel. 3. Recommended for new designs.
PIN NAMES
INPUTS BRDMX [BRD Mux] - PECL Input This signal indicates what data appears at the BRD output. When logic HIGH, BRD is a direct copy of what appears at RDOUTC. When logic low, BRD is a copy of what appears at RDIN. Unlike RDOUTC, BRD conveys valid data even when ENPECL is logic LOW. Please refer to Table 1.
BRDMX (Input) 0 1 BRD (Output) RDIN RDOUTC Table 1. BRDMX Truth Table
RDIN [Serial Data Input] - Differential PECL Input This differential input accepts the receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of ten frequency ranges, or can be one of five specific frequencies, depending on the state of the FREQSEL and VCOSEL pins. The RDIN- pin has an internal 75K resistor tied to VCC. REFCLK [Reference Clock] - Differential PECL Input This input is used as the reference for the internal frequency synthesizer and the "training" frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN input. The input frequency to REFCLK is limited to 340MHz or less, depending on the setting on the DIVSEL signals. The REFCLK- pin has an internal 75K resistor tied to VCC. CD [Carrier Detect] - PECL Input This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH, the input data stream (RDIN) is recovered
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normally by the Receive PLL. When this input is LOW, the data on the RDOUT output will be internally forced to a constant LOW, the Link Fault Indicator output LFIN forced LOW, and the clock recovery PLL forced to lock onto the synthesized clock frequency generated from REFCLK. VCOSEL1, VCOSEL2 [VCO Select] - TTL Inputs These inputs select the output clock frequency range via either one of three PLLs, or a SONET/SDH specific PLL. Only the selected PLL is enabled. All other PLLs are disabled. Refer to Table 3 for more details. FREQSEL1, ..., FREQSEL3 [Frequency Select] - TTL Inputs These inputs select the post divide ratio of the VCO. Refer to Table 3 for more details. DIVSEL1, ..., DIVSEL3 [Divider Select] - TTL Inputs These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in Table 4. Please note that the divide by 32 selection, "011", is only available for use when FREQSEL are set to "000."
DIVSEL1 0 0 0 0 1 1 1 1 DIVSEL2 0 0 1 1 0 0 1 1 DIVSEL3 0 1 0 1 0 1 0 1 REFCLK Multiplier 1 2 4 32 8 10 16 20
Table 2(1). Reference Clock Multiplier Truth Table
Note: 1. Some combinations of FREQSEL and DIVSEL result in undefined behavior. Refer to Table 3 for more details.
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Micrel, Inc.
SY87721L
CLKSEL [Clock Select] - TTL Input This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. Do not use for skew matching. ENPECL [Enable ECL] - TTL Input This input, when HIGH (ENPECL = 1), enables the differential PECL outputs TCLKE, RDOUTE, and RCLKE. It also disables the CML outputs, by setting TCLKC+, RDOUTC+, and RCLKC+ logic HIGH and setting TCLKC-, RDOUTC-, and RCLKC- logic LOW. When set LOW (ENPECL = 0), this signal enables the differential CML outputs TCLKC, RDOUTC, and RCLKC. It also disables the PECL outputs by setting TCLKE+, RDOUTE+, and RCLKE+ logic HIGH and setting TCLKE-, RDOUTE- and RCLKE- logic LOW. ALRSEL [Auto Lock Range Select] - TTL Input This pin defines the frequency difference, and the frequency difference hysteresis at which `in-lock' and `out of lock' conditions are declared. Please refer to the "AC Characteristics" for more details. OUTPUTS BRD [Buffered Recovered Data] - Differential CML Output The signal is either a buffered RDIN or RDOUTC, depending on the state of the BRDMX input. This allows a user to selectively bypass the CDR or not, as warranted by architecture. This CML output has a voltage swing of 400mV loaded. LFIN [Link Fault Indicate] - O.C. TTL Output This output indicates the status of the input data stream RDIN. Active HIGH indicates that the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (as per ALRSEL). LFIN is an asynchronous output. RDOUTE [Receive Data Out] - Differential PECL Output These ECL 100K outputs (+3.3V referenced) represent the recovered data from the input data stream (RDIN). It is specified on the rising edge of RCLK.
RDOUTC [Receive Data Out] - Differential CML Output This is the CML version of RDOUTE. RCLKE [Receive Clock Out] - Differential PECL Output These ECL 100K outputs (+3.3V referenced) represent the recovered clock used to sample the recovered data (RDOUT). RCLKC [Receive Clock Out] - Differential CML Output This is the CML version of RCLKE. TCLKE [Transmit Clock Out] - Differential PECL Output These ECL 100K outputs (+3.3V referenced) represent either the recovered clock (CLKSEL = HIGH) used to sample the recovered data (RDOUT) or the transmit clock of the frequency synthesizer (CLKSEL = LOW). TCLKC [Transmit Clock Out] - Differential CML Output This is the CML version of TCLKE. PLLSN+, PLLSN- [Clock Synthesis Loop Filter] External loop filter pins for the clock synthesis narrow band PLL. PLLSW+, PLLSW- [Clock Synthesis Loop Filter] External loop filter pins for the clock synthesis wide band PLL. PLLRN+, PLLRN- [Clock Recovery Loop Filter] External loop filter pins for the clock recovery narrow band PLL. PLLRW+, PLLRW- [Clock Recovery Loop Filter] External loop filter pins for the clock recovery wide band PLL. OTHERS VCC VCCO VCCA GND GNDA NC Supply Voltage Output Supply Voltage Analog Supply Voltage Ground Analog Ground These pins are for factory test, and are to be left unconnected during normal use.
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SY87721L
DESCRIPTION
General The SY87721L is a complete clock and data recovery circuit, capable of handling NRZ data rates from 28MHz through to 2.7GHz. A reference PLL is used as a frequency synthesizer, both to multiply a reference clock to the desired transmit rate, and to train the recovery PLL in preparation for actual data recovery. Link Fault Algorithm The SY87721L includes a Link Fault Detection circuit. This circuit provides the following functions: Under Loss-ofLock (LOL) conditions, which can occur when the Carrier Detect (CD) input is active HIGH, the output of the RCLK approximates the output of the TCLK, within a lock range as specified by the state of ALRSEL. Under Loss-of-Signal (LOS) conditions, enabled by driving the Carrier Detect (CD) input to inactive logic LOW, the output of the RCLK becomes an exact copy of the TCLK output. This is the result of forcing the recovery PLL to lock to the synthesized reference. Under LOL and LOS conditions, the LFIN output is an inactive logic LOW. SY87721L follows a prescribed procedure, to acquire and recover the clock of the incoming data stream. This procedure is triggered either by a falling edge on CD, or by the recovered clock PLL indicating a frequency error, compared to the synthesized reference, of greater than 500ppm or 4,500ppm, as selected by ALRSEL. With the CD input set active HIGH, the algorithm begins by phase and frequency training the recovery PLL to the synthesized reference. Once the recovery PLL is within the specified lock range, determined by the state of ALRSEL, the SY87721L will switch from a phase-frequency comparison with the synthesized reference, to a phase-only comparison with the incoming data stream. When the recovery PLL is locked to this incoming data stream (that is, after phase step recovery), then data recovery may proceed and LFIN asserts. Once locked and accepting data, the LFIN signal may de-assert should the data input frequency deviate too far from the synthesized reference frequency. VCO Selection SY87721L sports four complete VCO circuits. Depending on the application and the frequency range, any one of these four perform data recovery. As indicated by the VCO selection table, there are three general purpose VCOs each covering one of three frequency ranges. However, to extend the range of the device, the output of the VCO may be divided down. In the case of the two highest frequency general purpose VCOs (VCOSEL = 1, 0 or 0,1 ), this divisor is always set to 1. For the lowest frequency VCO, the FREQSEL pins select which divisor, and hence, which range of frequencies the VCO will work over. In addition, for SONET/SDH applications, there is a narrow band, extremely low jitter PLL. It also uses the FREQSEL divisor to choose the correct SONET/SDH frequency. The valid modes of operation are shown in Table 3.
VCOSEL1
0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
VCOSEL2
0 0 0 0 0 1 0 1 1 1 1 1 1 1 1
FREQSEL1
0 0 0 1 1 0 0 0 0 0 0 1 1 1 1
FREQSEL2
0 0 1 0 1 0 0 0 0 1 1 0 0 1 1
FREQSEL3
0 1 0 0 0 0 0 0 1 0 1 0 1 0 1
Range (MHz)
2488 (OC48)-2700 1244-1350 622 (OC12)-675 311-337 155 (OC3)-168 1800-2700 1250-1800 650-1300(1) 325-650(2) 163-325 109-216 82-162 55-108 41-81 28-54
Table 3 (3). Frequency Range Selection Truth Table
Notes: 1. REFCLK multiplier of 1 or 2 is not allowed in this range. 2. REFCLK multiplier of 1 is not allowed in this range. 3. Combinations of VCOSEL and FREQSEL other then those in this table result in undefined behavior, and should not be used. M9999-072705 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
SY87721L
LOOP FILTER COMPONENTS
CML OUTPUT DIAGRAM(1)
R
C
VCC
50
50 100
PLLSN+ or PLLSW+
PLLSN- or PLLSW-
Figure 1. Narrow Band and Wide Band Synthesizer Loop Filter
SY87721L
16mA
R
C
Figure 3. 50 Load CML Output
NOTE: 1. VOSW is defined as |VOH-VOL| on any one pin (either the true or the complement pin). As opposed to the single-ended swing, differential swing, VOSW (true pin) + VOSW (complement pin) is double the VOSW value.
PLLRN+ or PLLRW+
PLLRN- or PLLRW-
Figure 2. Narrow Band and Wide Band CDR Loop Filter
PLL PLLSN+, PLLSN- PLLRN+, PLLRN- PLLSW+, PLLSW- PLLRW+, PLLRW-
R 1.2k 390 845 455
C 1F 1F 1F 1F
Table 4. Synthesizer and Clock Recovery Loop Filter Values
OC-48 JITTER TRANSFER AND TOLERANCE
10
100
Jitter Ratio (dB)
Amplitude UI
0
10
-10
1
-20 1000 10000 100000 1.E+6 1.E+7
.1 1000 10000 100000 1.E+6 1.E+7
Modulation Frequency (Hz)
OC-48 Jitter Transfer
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Modulation Frequency (Hz)
OC-48 Jitter Tolerance 7
Micrel, Inc.
SY87721L
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VIN IOUT ICMLOUT Tstore TA JA Power Supply Voltage Input Voltage ECL Output Current CML Output Current Lead Temperature (soldering, 20 sec.) Storage Temperature Range Operating Temperature Range Package Thermal (Junction-to-Ambient) Resistance(2) - 0lfpm - 200lfpm - 500lfpm - Continuous - Surge Parameter Rating -0.5 to +5.0 -0.5 to VCC 50 100 30 +260 -65 to +150 -40 to +85 22.3 17.2 15.1 Unit V V mA mA C C C C/W C/W C/W
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Jedec standard test boards with die attach pad soldered to pcb. Tested at 1W.
DC ELECTRICAL CHARACTERISTICS
VCC =VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C
Symbol VCC ICC Parameter Power Supply Voltage Power Supply Current Min. 3.15 -- Typ. 3.3 360 Max. 3.45 450 Unit V mA Condition
100K PECL DC ELECTRICAL CHARACTERISTICS
VCC =VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C
Symbol VIH VIL IIL VOH VOL Parameter Input HIGH Voltage Input LOW Voltage Input LOW Current Output HIGH Voltage Output LOW Voltage Min. VCC - 1.165 VCC - 1.810 -0.5 VCC - 1.075 VCC - 1.860 Typ. -- -- -- -- -- Max. VCC - 0.880 VCC - 1.475 -- VCC - 0.830 VCC - 1.570 Unit V V A V V VIN = VIL(Min) 50 to VCC -2V 50 to VCC -2V Condition
Note: 1. All PECL inputs have an internal 75k resistor to VEE. In addition, the complement inputs of all differential PECL inputs have a 75k resistor to VCC. Thus, unconnected PECL inputs behave like static logic LOW.
CML DC ELECTRICAL CHARACTERISTICS
VCC =VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C
Symbol VOH VOL VOSW Parameter Output HIGH Voltage Output LOW Voltage Output Voltage Swing Min. VCC - 0.050 -- -- Typ. -- -- 0.4 Max. VCC VCC - 0.65 -- Unit V V V Condition No Load No Load 50 to VCC
Note: 1. VOSW is defined as |VOH-VOL| on any one pin (either the true or the complement pin). As opposed to the single-ended swing, differential swing, VOSW (true pin) + VOSW (complement pin) is double the VOSW value. M9999-072705 hbwhelp@micrel.com or (408) 955-1690
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SY87721L
TTL DC ELECTRICAL CHARACTERISTICS
VCC =VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C
Symbol VIH VIL IIH IIL IOLK VOL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output Leakage Current Output LOW Voltage Min. 2.0 -- -- -- -300 -- -- Typ. -- -- -- -- -- -- -- Max. -- 0.8 +20 +100 -- 500 0.5 Unit V V A A A A V VIN = 2.7V, VCC = 3.45V VIN = VCC, VCC = 3.45V VIN = 0.5V, VCC = Max. VOUT = VCC IOL = 4mA Condition
AC ELECTRICAL CHARACTERISTICS
VCC =VCCO = VCCA = 3.3V 5%; GND = GNDA = 0V; TA = -40C to +85C
Symbol Parameter TCLK Output Jitter Frequency Difference, LFIN shows Out of Lock Frequency Difference, LFIN shows Out of Lock RDIN Maximum Data Rate REFCLK Maximum Frequency tCPWH tCPWL tIRF tODC tRE tFE tRC tFC tDV tDH REFCLK Pulse Width High REFCLK Pulse Width Low REFCLK Input Rise/Fall Time (20% to 80%) Output Duty Cycle (RCLK/TCLK) ECL Output Rise/Fall Time (20% to 80%) CML Output Rise/Fall Time (20% to 80%) Data Valid Data Hold Min. -- 500 4500 2.7 -- 1.2 1.2 -- 45 -- -- 100 100 Typ. -- 1500 6500 -- -- -- -- -- -- -- -- -- -- Max. 0.01 -- -- -- 340 -- -- 1.0 55 600 120 -- -- Unit UI rms ppm ppm Gbps MHz ns ns ns % of UI ps ps ps ps 50 to VCC-2V 50 Load Condition REFCLK Multiplier 16 VCOSEL = 0, 0 ALRSEL High ALRSEL Low
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SY87721L
TIMING WAVEFORMS
tCPWL tCPWH
REFCLK- tDV tDH
RDOUT tODC RCLK tODC
CML VOSW DIAGRAM
VOSW (Single-Ended Swing) VOH CML Pin (True or Complement) VOL
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SY87721L
EVALUATION BOARD SCHEMATIC
VCC 5k R48, 20 VCC R47, 130 S1
1 2 3 4 5 10 9 8 7 6
VCC
L2
L1 VCCO
D1 D2
HEADER 3X2 JP4
1 3 5 2 4 6
C3
C4
C2 D3 LED
C1 R17, 1.7k VCC
RDIN--: FORCE RDIN--: SENSE
RDIN+: FORCE RDIN+: SENSE
BRD--: PIN 53
BRD+: PIN 52
VCC VEE
VCC: PIN 58
VEE: PIN 57
VEE: PIN 56
VEE: PIN 59
SW DIP-5 VEE
VCC L3 VCCA R7 HEADER 6X2 JP1
1 3 5 7 9 11 2 4 6 8 10 12
R1, 5k
R2, 5k
R3, 5k C9
R4, 5k
R5, 5k 1 C10 C5 R8 2 3 4 5 6 C6 7 8 9 R9 10 11 C7 R10 VCOSEL1 PLLRN+ PLLRN-- NC PLLRW+ PLLRW-- NC VCCA GNDA PLLSW-- PLLSW+ NC PLLSN-- PLLSN+ NC
VCC R16, 5k JP2 GND 48 VEE: PIN 48 VEE RDOUTE+ RDOUTE-- RDOUTC+ RDOUTC-- VCCO: PIN 42 RCLKE+ RCLKE-- RCLKC+ RCLKC-- VCCO: PIN 37 TCLKE+ TCLKE-- TCLKC+
64
63
62
61
60
59
58
57
56
55
53 BRD-- 54 VCCO
52
51
50
49
RDIN--
RDIN+
VCC
BRDMX
LFIN
GND
BRD+
VCC
GND
FREQSEL3
CD
FREQSEL2
FREQSEL1
VCOSEL2
ENPECL RDOUTE+ RDOUTE-- RDOUTC+ RDOUTC-- VCCO
47 46 45 44 43 42 41
S3
1 2 3 4 5 6 12 11 10 9 8 7
SY87721L
RCLKE+
RCLKE-- 40 RCLKC+ 39
SW DIP-6 VEE
RCLKC-- 38 VCCO TCLKE+ 37 36
VCC
Notes: 1. C11, C17, C10, C4, C2 = 0.1F 2. C18, C12, C9, C3, C1 = 1F 3. C2, C4, C10, C11, and C17 need to be located right at device pin. If vias to power GND used--use overlapping multiple vias to lower inductance.
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R18, 5k
VEE
R19, 5k
R20, 5k
C18
R21, 5k
R22, 5k L7
R23, 5k C17
12 13 14
TCLKE-- 35 TCLKC+ 34
C8
15 16
REFCLK+
REFCLK--
NC
TCLKC-- 33
DIVSEL3
DIVSEL2
DIVSEL1
18
CLKSEL
ALRSEL
TCLKC--
GND
GND
GND
GND
GND
GND
VCC
VCC
NC
17
19
20
21
22
23 VEE:PIN 23
24 VCC:PIN 24
25 VEE:PIN 25
26 VEE:PIN 26
27
28
29
30
31
32 VEE VEE:PIN 32
REFCLK--: FORCE REFCLK--: SENSE
REFCLK+: FORCE REFCLK+: SENSE
S2
1 2 3 4 5 10 9 8 7 6
L4 VCC C11 C12
R15, 1.2k
R14, 1.2k
R13, 1.2k
R12, 1.2k
R11, 1.2k
SW DIP-8 VCC
VEE
11
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SY87721L
EVALUATION BOARD I/O TERMINATION SCHEMES
TCLK OUTPUTS RCLK OUTPUTS RDOUT OUTPUTS RDIN INPUTS
VCC R36, 68.5 RDIN+:FORCE C31
1
TCLKC-
C19
1
J14
2
RCLKC-
C23 J10
1 2
RDOUTC-
C27
1 2
J6
J1
2
R37, 185.2 VEE
TCLKC+
C20
1 2
J13
RCLKC+
C24
1 2
J9
RDOUTC+
C28
1 2
J5
RDIN+: SENSE
C32
1 2
J2
VCC R38, 68.5
TCLKE- R30, 330 VEE C21
1 2
J12
RCLKE- R32, 330 VEE
C25
1 2
J8
RDOUTE+ R34, 330 VEE
C29
1 2
J4
RDIN-:FORCE
C33
1
J17
2
R39, 185.2 VEE
TCLKE+ R31, 330 VEE
C22
1 2
J11
RCLKE+ R33, 330 VEE
C26
1 2
J7
RDOUTE+ R35, 330 VEE
C30
1 2
J3
RDIN-: SENSE
C34
1 2
J18
Notes: 1. For AC coupling, include capacitors C19 thru C31, C33, C35 and C37. 2. If DC coupling, remove resistors R36 thru R43.
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SY87721L
REFCLK INPUTS
VCC R40, 68.5 REFCLK+:FORCE C35
1
BRD OUTPUTS
BRD+: PIN 52
C39
1 2
J21
VEE: PIN 59
C45 0.01 F C46 0.01 F C47 0.01 F C49 0.01 F C50 0.01 F C51 0.01 F C52 0.01 F C53 0.01 F C54 0.01 F C55 0.01 F C56 0.01 F
J15
2
R41, 185.2 VEE
VCC: PIN 58
VEE: PIN 57
VEE: PIN 48
C36
1 2
REFCLK+: SENSE
J16
BRD--: PIN 53
C40
1 2
J22
VCCO: PIN 42
VCCO: PIN 37
VEE: PIN 32
VCC R42, 68.5 REFCLK-:FORCE C37
1
VEE: PIN 26
J19
2
R43, 185.2 VEE
VEE: PIN 25
VCC: PIN 24
VEE: PIN 23
REFCLK-: SENSE
C38
1 2
J20
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SY87721L
64 LEAD EPAD-TQFP (DIE UP) (H64-1)
+0.05 -0.05 +0.002 -0.002
+0.05 -0.05 +0.012 -0.012
+0.03 -0.03 +0.012 -0.012
+0.15 -0.15 +0.006 -0.006
+0.05 -0.05 +0.002 -0.002
Rev. 02
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 64-Pin EPAD-TQFP Package
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Micrel, Inc.
SY87721L
APPENDIX A
Layout and General Suggestions 1. Establish controlled impedance stripline, microstrip, or co-planar construction techniques. 2. Signal paths should have, approximately, the same width as the device pads. 3. All differential paths are critical timing paths, where skew should be matched to within 10ps. 4. Signal trace impedance should not vary more than 5%. If in doubt, perform TDR analysis of all high-speed signal traces. 5. Maintain compact filter networks as close to filter pins as possible. Provide ground plane relief under filter path to reduce stray capacitance. Be careful of crosstalk coupling into the filter network. 6. Maintain low jitter on the REFCLK input. Isolate the XTAL oscillator from power supply noise by adequately decoupling. Keep XTAL oscillator close to device, and minimize capacitive coupling from adjacent signals. 7. Higher speed operation may require use of fundamental-tone (third-overtone typically have more jitter) crystal based oscillator for optimum performance. Evaluate and compare candidates by measuring TXCLK jitter. 8. Evaluate ASIC AND FPGA REFIN source clocks with suitable jitter analysis equipment, such as TDS11801 tektronix DSO oscilloscope, or Wavecrest DTS2077 Time Interval Analyzer. 9. All unused outputs require termination. NC, however, should be unconnected.
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The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-072705 hbwhelp@micrel.com or (408) 955-1690
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