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T6B70BF
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
T6B70BF
Interface IC for Water Heater
The T6B70BF incorporates two-channel 4-bit DA converter, a pseudo sine wave generator and an external analog signal detection/non-detection circuit. It is designed to be used mainly for communication between water heater and control unit.
Features
* * * * On-chip two-channel 4-bit DA converter (opposite polarities) On-chip pseudo sine wave generator (external clock/16) On-chip external analog signal detection/non-detection circuit On-chip two-channel analog switch Weight: 0.16 g (typ.)
Block Diagram
OSCIN 1 OSCOUT 2 FOUT 3
SCTL
Divide-by16 unit
Pseudo sine wave generator
0C 180C
4-bit DA converter 4-bit DA converter
13 SOUT+ 12 SOUT- 16 VDD
Waveform initialization block
4
Modulation control circuit Zero-cross waveform shaping circuit Amplifier input circuit
SW1IN 14 SW1OUT 15
7 AMPIN 6 AMPOUT
Cycle measurement counter SW2IN 11 SW2OUT 10
RESET
Analog signal detection/non-detection Reset circuit Output buffer
8 VSS 9
DOUT
5
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Pin Assignment
OSCIN OSCOUT FOUT
SCTL RESET
1 2 3 4 T6B70BF 5 6 7 8
16 15 14 13 12 11 10 9
VDD SW1OUT SW1IN SOUT+ SOUT- SW2IN SW2OUT
DOUT
AMPOUT AMPIN VSS
Pin Function
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol OSCIN OSCOUT FOUT
SCTL RESET
Input/Output Input Output Output Input Input Output Input Output Output Input Output Output Input Output
Function Pins connected to oscillation Pins connected to oscillation Output pin for oscillation waveform shaping circuit Modulation control signal input pin Reset signal input pin Amplifier signal output pin Amplifier signal input pin Device GND pin (0 V) Output pin for amplifier input signal detector Output pin on analog SW2 side Input pin on analog SW2 side Pseudo sine wave (opposite polarity of SOUT+ output) output pin Pseudo sine wave output pin Input pin on analog SW1 side Output pin on analog SW1 side Device power supply pin (+5 V)
AMPOUT AMPIN VSS
DOUT
SW2OUT SW2IN SOUT- SOUT+ SW1IN SW1OUT VDD
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Function Description
(1) Pseudo sine wave generator and 4-bit DA converters (sending block) Pseudo sine wave signal with Fosc/16 frequency is driven out from pseudo sine wave output pin (SOUT+ and SOUT-). The outputs of pins SOUT+ and SOUT- have the opposite polarities. The block of pseudo sine wave generator and 4-bit DA converter (the side of SOUT+ pin) are shown below.
SOUT+ pin MSB Pseudo sine wave generator R R R SOUT+
R
R R
R LSB
R R SOUT-
FOSC RST
VSS
The data of pseudo sine wave generator is driven out in the following sequence. 0 1 3 6 9 C E F F E C 9 6 3 1 0 (in hexadecimal)
FF E C E C
2R 9
R
R
9
6 3 01 FSIN 250 kHz @FOSC = 4 MHz
6 3 10
Thus, the pseudo sine waveform of positive-going and negative-going outputs is like a staircase at no load. An analog switch is incorporated so that the driver output buffer is connected to the transmission line only when transmission is performed. However, an emitter follower circuit is externally connected to the driver output buffer. The phase difference between positive-going and negative-going outputs is within 180 5. (pseudo sine wave output phase fluctuation)
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(2) Amplifier input circuit and signal detection/non-detection circuit (receiving block) The modulation signal input block incorporates two level comparators having a high and a low threshold values to detect the external sine wave signal with amplitude higher than the specified threshold. Thus, it avoids signals with amplitude lower than the specified threshold (e.g., noise signals) being detected erroneously. The detection frequency range (frequency window) is determined by the divider ratio 1/18 to 1/14 of Fosc. In detection/non-detection determined condition, when the signals within the specified frequency range are detected (or not detected) sequentially, signals are controlled using the majority rule. The time which detection/non-detection is determined takes 9 to 15 waves to pass when one wave is referenced to Fosc/16 frequency.
VDD R1 APU VDD Reference voltage VH
RESET High comparator VA
R
Q
Cycle measurement counter
APD
R3
7 AMPIN pin
Reference voltage VL
VBIAS Low comparator VB
S Q RESET
Analog signal detection 9 /nondetection DOUT pin circuit
R4
R2
VSS
VSS
VDD
6 AMPOUT pin
AMPIN input sine waveform VH Input sensitivity VPP VL Detect reception Not detect reception Not detect reception Not detect reception
AMPOUT output timing (when RESET is Low) VH VBIAS
AMPOUT Truth Table
VA VBIAS > VH VH > VBIAS > VL L H H VB H H L AMPOUT L Hold H
VL Held at High Held at Low
VBIAS < VL
AMPOUT
VBIAS < VL VBIAS > VH VH > VBIAS > VL VH > VBIAS > VL
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(3) Function description and timing chart of the sending block When modulation control input ( SCTL ) is in High-level, pseudo sine wave output is held at 0 of the phase angle of pseudo sine wave. When modulation control input changes from High-level to Low-level, the pseudo sine wave output (SOUT+) starts from -90 (SOUT- starts from +90). In this case, the time which takes to turn ON is as follows. td (ON) < 500 ns When modulation control input changes from Low-level to High-level, the phase angle is forcibly held at 0, regardless of the phase of the pseudo sine wave output. (the pseudo sine wave output is stopped). In this case, the time which takes to turn OFF is as follows. td (OFF) < 1 s
SCTL
td (ON) SOUT+ pseudo sine wave output (SOUT- output pin has the opposite polarity)
td (OFF)
(4)
Function description and timing chart of the receiving block When it is ready to receive amplifier input signal, the time T (DET) which takes to change from High to Low at DOUT pin is within the time which 9 to 15 waves to pass. In this case, one wave is referenced to 16 Fosc clocks. The time width is determined by the internal clock and amplifier input signal. The timings of the internal clock and internal detection signal in the majority logic circuit are synchronous with each other. When input signals with the cycle, which is within the range specified by the frequency window, are detected (or not detected) sequentially, this rule is valid (the majority rule).
Amplifier input T (DET) T (DET)
DOUT
Note 1: Any communication protocol is used, however, it takes 15 carrier waves to pass when the signal changes its state.
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Timing Chart (SOUT+ = SW1IN, SW1OUT, SOUT- = SW2IN, SW2OUT)
VDD
RESET
OSCIN (4 MHz)
FOUT
AMPIN (250 kHz)
VPP
AMPOUT
High-z
SCTL
When sending td (ON) FSIN td (OFF)
SOUT+
VOPP SOUT-
DOUT
TDET
When receiving TDET
SW1IN SW1OUT
High-z
High-z
SW2IN SW2OUT
High-z
High-z
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Maximum Ratings (Ta = 25C 1.5C)
Characteristics Power supply voltage Input voltage Input peak current Operating temperature Storage temperature Power dissipation Symbol VDD VI IIK Topr Tstg PD (Note 1) Rating -0.3 to 6.0 -0.3 to VDD + 0.3 -20 to 20 -20 to 80 -55 to 125 0.54 Unit V V mA C C W
Note 1: Decreases approximately 4.35 mW per 1C.
Electrical Characteristics
Characteristics VDD pin (pin 16) Operating voltage Current consumption
(unless otherwise specified, VDD = 5.0 V, VSS = 0 V, FOSC = 4 MHz and Ta = -20 to 80C)
Symbol Test Circuit 1 Test Condition Min Typ. Max Unit
VDD IDD FOSC VIHOSC VILOSC IIHROSC IILROSC VOHOSC VOLOSC
No load, Fosc = 4 MHz
4.5
5.0
5.5 10
V mA
OSCIN pin (pin 1) and OSCOUT pin (pin 2) Oscillation frequency High level Input voltage Low level Input current High level Low level High level Output voltage Low level
RESET pin (pin 5)
2 3 3 4 4 3 4
VIN = 5 V, Ta = 25C VIN = 0 V, Ta = 25C IOH = -0.1 mA IOL = +0.1 mA
1 0.7 VDD VSS 3.2 -3.2 VDD - 1.0 VSS
4 6.58 -6.58
10 VDD 0.3 VDD 13.2 -13.2 VDD VSS + 0.6
MHz
V
A
V
Low to High input switching level High to Low input switching level High-level input current Pull-up resistance 1 Pull-up resistance 2
SCTL pin (pin 4)
VIHRST VILRST IIHRST IILRRST1 IILRRST2
5 5 6 7 7 VIN = VDD

0.65 VDD VSS -10 9 6.3
15
VDD 0.35 VDD 10 21 27.3
V V A k k
VIN = VSS, Ta = 25 VIN = VSS, Ta = -20 to 80
Low to High input switching level High to Low input switching level Input current FOUT pin (pin 3) High level Output voltage Low level High level Low level
VIHSCTL VILSCTL IIHSCTL IILSCTL
8 8 9 9 VIN = VDD VIN = VDD

0.65 VDD VSS -1 -1

VDD 0.35 VDD 1 1
V V A
VOHFOUT VOLFOUT
10 11
IOH = -1.0 mA IOL = +1.0 mA
VDD - 1.0 VSS

VDD VSS + 0.6 V
Note 2: One direction in which current flow into the IC should be + (sink) and the other direction in which current flow out from the IC should be - (drain).
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Characteristics
DOUT pin (pin 9)
Symbol
Test Circuit
Test Condition
Min
Typ.
Max
Unit
High level Output voltage Low level
VOHDOUT VOLDOUT
12 13
IOH = -1.0 mA IOL = +1.0 mA Fosc = 4 MHz, AMPIN = 250 kHz Time which takes DOUT to change from High to Low Fosc = 4 MHz, AMPIN = 250 kHz Time which takes DOUT to change from Low to High
VDD - 1.0 VSS

VDD VSS + 0.6 V
Non-reception to reception detection time
TDET1
19
40
60
s
Reception to non-reception detection time AMPIN pin (pin 7) Input dynamic range Pull-up resistance 1 Pull-up resistance 2 Pull-down resistance 1 Pull-down resistance 2 Amplifier input bias voltage
TDET2
19
36
56
s
VAMPIN IILRAPU1 IILRAPU2 IIHRAPD1 IIHRAPD2 VBIAS
14 15 15 16 16 17
VIN = VSS, Ta = 25 VIN = VSS, Ta = -20 to 80 VIN = VDD, Ta = 25 VIN = VDD, Ta = -20 to 80 No load (design goal) No load, receivable amplitude range is 250 kHz, when sine wave signal is applied. (design goal) Fosc = 4 MHz Fosc = 4 MHz Fosc = 4 MHz
VSS 11.6 7 5.9 3 1.54
19.4 9.8 1.63
VDD 27.2 38 13.7 19.2 1.71
V k k k k V
Amplifier input sensitivity
VPP DETON DETOFF1 DETOFF2
18
0.3
0.45
V
Detection frequency range Non-detection frequency (low frequency) Non-detection frequency (high frequency)
19 19 19
236 286

266 222
kHz kHz kHz
SW1IN pin (pin 14) and SW1OUT pin (pin 15) Analog switch input voltage Analog switch output voltage OFF-leak current of analog switch 1 VINASW1 VOUTASW1 IOFFASW1 20
SCTL = H, SW1IN = VDD, SW1OUT = VSS SCTL = L, SW1IN = 5 V, SW1OUT = 0 V
VSS VSS -1

VDD VDD 1
V V A
ON-resistance of analog switch 1
RONASW1
21
35
105
Current measure SW2IN pin (pin 11) and SW2OUT pin (pin 10) Analog switch input voltage Analog switch output voltage OFF-leak current of analog switch 2 VINASW2 VOUTASW2 IOFFASW2 20
SCTL = H, SW2IN = VDD, SW2OUT = VSS SCTL = L, SW2IN = 5 V, SW2OUT = 0 V
VSS VSS -1

VDD VDD 1
V V A
ON-resistance of analog switch 2
RONASW2
21
35
105
Current measure SOUT+ pin (pin 13) and SOUT- pin (pin 12) Output voltage Pseudo sine wave output frequency Pseudo sine wave output start time Pseudo sine wave output stop time Equivalent output impedance VOPP FSIN tdON tdOFF ROUTSIN 22 23 23 23 24 Maximum voltage value at no load FOSC = 4 MHz
SCTL = H L SCTL = L H
0.85 VDD 2.8
250 4
VDD 500 1 5.2
V kHz ns s k
No load
Note:
One direction in which current flow into the IC should be + (sink) and the other direction in which current flow out from the IC should be - (drain).
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Test Circuit
(1) Current consumption
5V ICC
(2)
Oscillation frequency
4 MHz PG
A 1 OSCIN VDD 16 2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT 9
1 to 10 MHz PG Monitor Fosc
5V 1 OSCIN VDD 16
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
9
(3)
High-level input voltage Low-level input voltage High-level output voltage
(4)
High-level input current Low-level input current Low-level output voltage
IIHROSC IILROSC A IOL 1 OSCIN +0.1 mA VDD 16
5V VDD 16 1 OSCIN VIHOSC VOHOSC VILOSC 2 OSCOUT SW1OUT 15 -0.1 mA IOH V 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
5V
VIN
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
VOLOUT V
9
9
(5)
Low to High input switching level High to Low input switching level
5V 1 OSCIN VDD 16
(6)
High-level input current
4 MHz PG
5V 1 OSCIN VDD 16
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL VIHRST VILRST 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
2 OSCOUT SW1OUT 15 3 FOUT Monitor Monitor VIN IIHRST 4 SCTL A 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
9
9
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(7) Pull-up resistance 1 Pull-up resistance 2
5V 1 OSCIN VDD 16
(8)
Low to High input switching level High to Low input switching level
5V 1 OSCIN VDD 16
4 MHz PG
2 OSCOUT SW1OUT 15 IILRRST1 3 FOUT IILRRST2 4 SCTL A 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT 9
2 OSCOUT SW1OUT 15 3 FOUT VIHSCTL VILSCTL 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
Monitor Monitor
9
(9)
High-level input current Low-level input current
5V 1 OSCIN VDD 16
(10) High-level output voltage
5V 1 OSCIN VDD 16
-1.0 mA
OSCOUT SW1OUT 15 IIHSCTL 2 IILSCTL 3 FOUT SW1IN 14 A VIN 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
2 OSCOUT SW1OUT 15 3 FOUT IOH VOHFOUT V 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
9
9
(11) Low-level output voltage
5V +1.0 mA 1 OSCIN IOL VDD 16
(12) High-level output voltage
5V 1 OSCIN VDD 16
4 MHz PG
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10 -1.0 mA
DOUT
VOLFOUT V
9
9
VOHDOUT V
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IOH
T6B70BF
(13) Low-level output voltage
5V 1 OSCIN VDD 16
(14) Input dynamic range
5V 1 OSCIN VDD 16
4 MHz PG
4 MHz PG
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 +1.0 mA SW2IN 11 SW2OUT 10
DOUT 9
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET Monitor IOL VAMPIN 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
9
VOLDOUT V
(15) Pull-up resistance 1 Pull-up resistance 2
5V 1 OSCIN VDD 16
(16) Pull-down resistance 1 Pull-down resistance 2
5V 1 OSCIN VDD 16
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL IILRAPU1 5 RESET IILRAPU2 6 AMPOUT A 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL IIHRAPD1 5 RESET IIHRAPD2 6 AMPOUT A VIN 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
9
9
(17) Amplifier input bias voltage
5V 1 OSCIN VDD 16
(18) Amplifier input sensitivity
5V 1 OSCIN VDD 16
4 MHz PG
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN VBIAS V 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET Monitor 250 kHz Vp-p sine wave 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
9
9
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(19) Detection frequency range Non-detection frequency (low frequency) Non-detection frequency (high frequency) Non-reception to reception detection time Reception to non-reception detection time
5V 1 OSCIN VDD 16 1 OSCIN VDD 16 IOFFASW1 5.0 V V VOPP V VOPP 5.0 V 5.0 V 5.0 V A
(20) OFF-leak current of analog switch 1 OFF-leak current of analog switch 2
4 MHz PG
5V
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL DETON DETOFF1 DETOFF2 200 to 300 kHz PG 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT 9
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN Monitor TDET1 TDET2 8 VSS SW1IN 14 SOUT+ 13
SOUT- 12 IOFFASW2 SW2IN 11 SW2OUT 10
DOUT
A
9
(21) ON-resistance of analog switch 1 ON-resistance of analog switch 2
5V 1 OSCIN VDD 16 RONASW1 5.0 V A
(22) Output voltage
4 MHz PG
5V 1 OSCIN VDD 16
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
SOUT- 12 RONASW2 5.0 V SW2IN 11 SW2OUT 10
DOUT
A
9
9
(23) Pseudo sine wave output frequency Pseudo sine wave output start time Pseudo sine wave output stop time
5V 1 OSCIN VDD 16
(24) Equivalent output impedance
4 MHz PG
4 MHz PG
5V 1 OSCIN VDD 16
2 OSCOUT SW1OUT 15 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
2 OSCOUT SW1OUT 15 FSIN Monitor DEGSOUT Monitor tdON tdOFF 3 FOUT 4 SCTL 5 RESET 6 AMPOUT 7 AMPIN 8 VSS SW1IN 14 SOUT+ 13 SOUT- 12 SW2IN 11 SW2OUT 10
DOUT
A
ROUTSIN A ROUTSIN
9
9
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Markings
LOT CODE T6B70BF
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Package Dimensions
Weight: 0.16 g (typ.)
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RESTRICTIONS ON PRODUCT USE
000707EBA
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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