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TC59LM814/06CFT-50,-55,-60
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
4,194,304-WORDS x 4 BANKS x 16-BITS Network FCRAM TM 8,388,608-WORDS x 4 BANKS x 8-BITS Network FCRAM DESCRIPTION
TM
Network FCRAMTM is Double Data Rate Fast Cycle Random Access Memory. TC59LM814/06CFT are Network FCRAMTM containing 268,435,456 memory cells. TC59LM814CFT is organized as 4,194,304-words x 4 banks sx 16 bits, TC59LM806CFT is organized as 8,388,608 words x 4 banks x 8 bits. TC59LM814/06CFT feature a fully synchronous operation referenced to clock edge whereby all operations are synchronized at a clock input which enables high performance and simple user interface coexistence. TC59LM814/06CFT can operate fast core cycle using the FCRAMTM core architecture compared with regular DDR SDRAM. TC59LM814/06CFT is suitable for Network, Server and other applications where large memory density and low power consumption are required. The Output Driver for Network FCRAMTM is capable of high quality fast data transfer under light loading condition.
FEATURES
PARAMETER CL = 3 CL = 4 tRC Random Read/Write Cycle Time (min) tRAC Random Access Time (max) IDD1S Operating Current (single bank) (max) lDD2P Power Down Current (max) lDD6 Self-Refresh Current (max) tCK Clock Cycle Time (min) -50 5.5 ns 5 ns 25 ns 22 ns 190 mA 2 mA 3 mA TC59LM814/06 -55 6 ns 5.5 ns 27.5 ns 24 ns 180 mA 2 mA 3 mA -60 6.5 ns 6 ns 30 ns 26 ns 170 mA 2 mA 3 mA
*
*
* * * * * * * * *
* * * *
Fully Synchronous Operation * Double Data Rate (DDR) Data input/output are synchronized with both edges of DQS. * Differential Clock (CLK and CLK ) inputs CS , FN and all address input signals are sampled on the positive edge of CLK. Output data (DQs and DQS) is aligned to the crossings of CLK and CLK . Fast clock cycle time of 5 ns minimum Clock: 200 MHz maximum Data: 400 Mbps/pin maximum Quad Independent Banks operation Fast cycle and Short Latency Bidirectional Data Strobe Signal Distributed Auto-Refresh cycle in 7.8 s Self-Refresh Power Down Mode Variable Write Length Control Write Latency = CAS Latency-1 Programable CAS Latency and Burst Length CAS Latency = 3, 4 Burst Length = 2, 4 Organization TC59LM814CFT: 4,194,304 words x 4 banks x 16 bits TC59LM806CFT: 8,388,608 words x 4 banks x 8 bits Power Supply Voltage VDD: 2.5 V 0.15 V VDDQ: 2.5 V 0.15 V 2.5 V CMOS I/O comply with SSTL-2 (half strength driver) Package: 400 x 875 mil, 66 pin TSOPII, 0.65 mm pin pitch (TSOPII66-P-400-0.65)
Notice: FCRAM is a trademark of Fujitsu Limited, Japan.
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PIN NAMES
PIN A0~A14 BA0, BA1 DQ0~DQ7 (x8) Data Input/Output DQ0~DQ15 (x16)
CS
PIN ASSIGNMENT (TOP VIEW)
NAME TC59LM814CFT Address Input Bank Address VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC1 VDDQ LDQS NC1 VDD NC1 NC1 A14 A13 FN CS NC1 BA0 BA1 A10 A0 A1 A2 A3 VDD VDD DQ0 VDDQ NC2 DQ1 VSSQ NC2 DQ2 VDDQ NC2 DQ3 VSSQ NC2 NC1 VDDQ NC2 NC1 VDD NC1 NC1 A14 A13 FN CS NC1 BA0 BA1 A10 A0 A1 A2 A3 VDD TC59LM806CFT 1 2 3 4 5 6 7 8 9 400 mil width 10 875 mil length 11 12 13 14 66 pin TSOPII 15 16 17 18 0.65 mm 19 20 Lead pitch 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 VSS VSS DQ7 DQ15 VSSQ VSSQ NC2 DQ14 DQ6 DQ13 VDDQ VDDQ NC2 DQ12 DQ5 DQ11 VSSQ VSSQ NC2 DQ10 DQ4 DQ9 VDDQ VDDQ NC2 DQ8 NC1 NC1 VSSQ VSSQ DQS UDQS NC1 NC1 VREF VREF VSS1 VSS1 NC NC CLK CLK CLK CLK PD 1 PD 1 NC NC A12 A12 A11 A11 A9 A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 VSS VSS
Chip Select Function Control Power Down Control Clock Input Write/Read Data Strobe
FN PD CLK, CLK DQS (x8) UDQS/LDQS (x16) VDD VSS VDDQ VSSQ VREF NC , NC
1 2
Power (+2.5 V) Ground Power (+2.5 V) (for I/O buffer) Ground (for I/O buffer) Reference Voltage Not Connected
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BLOCK DIAGRAM
CLK
CLK
PD
DLL CLOCK BUFFER
To each block
CS
FN
COMMAND DECODER
CONTROL SIGNAL GENERATOR
BANK #3 BANK #2 BANK #1 DATA CONTROL and LATCH CIRCUIT READ DATA BUFFER WRITE DATA BUFFER DQ BUFFER DQ0~DQn BANK #0 ROW DECODER
MODE REGISTER A0~A14 ADDRESS BUFFER UPPER ADDRESS LATCH LOWER ADDRESS LATCH
MEMORY CELL ARRAY
BA0, BA1
COLUMN DECODER
REFRESH COUNTER BURST COUNTER
WRITE ADDRESS LATCH/ ADDRESS COMPARATOR
DQS
Note: The TC59LM806CFT configuration is 32768 x 256 x 8 of cell array with the DQ pins numbered DQ0~DQ7. The TC59LM814CFT configuration is 32768 x 128 x 16 of cell array with the DQ pins numbered DQ0~DQ15.
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ABSOLUTE MAXIMUM RATINGS
SYMBOL VDD VDDQ VIN VOUT VREF Topr Tstg Tsolder PD IOUT PARAMETER Power Supply Voltage Power Supply Voltage (for I/O buffer) Input Voltage DQ pin Voltage Input Reference Voltage Operating Temperature Storage Temperature Soldering Temperature (10 s) Power Dissipation Short Circuit Output Current RATING -0.3~ 3.3 -0.3~VDD+ 0.3 -0.3~VDD+ 0.3 -0.3~VDDQ + 0.3 -0.3~3.3 0~70 -55~150 260 1 50 UNIT V V V V V C C C W mA NOTES
Caution: Conditions outside the limits listed under "ABSOLUTE MAXIMUM RATINGS" may cause permanent damage to the device. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to "ABSOLUTE MAXIMUM RATINGS" conditions for extended periods may affect device reliability.
RECOMMENDED DC, AC OPERATING CONDITIONS (Notes: 1)(Ta = 0~70C)
SYMBOL VDD VDDQ VREF VIH (DC) VIL (DC) VICK (DC) VID (DC) VIH (AC) VIL (AC) VID (AC) VX (AC) VISO (AC) PARAMETER Power Supply Voltage Power Supply Voltage (for I/O buffer) Input Reference Voltage Input DC High Voltage Input DC Low Voltage Differential Clock DC Input Voltage Input Differential Voltage. CLK and CLK inputs (DC) Input AC High Voltage Input AC Low Voltage Input Differential Voltage. CLK and CLK inputs (AC) Differential AC Input Cross Point Voltage Differential Clock AC Middle Level MIN 2.35 2.35 VDDQ/2 x 96% VREF + 0.2 -0.1 -0.1 0.4 VREF + 0.35 -0.1 0.7 VDDQ/2 - 0.2 VDDQ/2 - 0.2 TYP. 2.5 VDD VDDQ/2 MAX 2.65 VDD VDDQ/2 x 104% VDDQ + 0.2 VREF - 0.2 VDDQ + 0.1 VDDQ + 0.2 VDDQ + 0.2 VREF - 0.35 VDDQ + 0.2 VDDQ/2 + 0.2 VDDQ/2 + 0.2 UNIT V V V V V V V V V V V V 2 5 5 10 7, 10 3, 6 4, 6 7, 10 8, 10 9, 10 NOTES
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Note: (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) All voltages referenced to VSS, VSSQ. VREF is expected to track variations in VDDQ DC level of the transmitting device. Peak to peak AC noise on VREF may not exceed 2% VREF (DC). Overshoot limit: VIH (max) = VDDQ + 0.9 V with a pulse width 5 ns. Undershoot limit: VIL (min) = -0.9 V with a pulse width 5 ns. VIH (DC) and VIL (DC) are levels to maintain the current logic state. VIH (AC) and VIL (AC) are levels to change to the new logic state. VID is magnitude of the difference between CLK input level and CLK input level. The value of VX (AC) is expected to equal VDDQ/2 of the transmitting device. VISO means {VICK (CLK) + VICK ( CLK )} /2 Refer to the figure below.
CLK Vx
CLK
Vx VICK
Vx
Vx VICK
Vx VICK
VID (AC)
VICK VSS |VID (AC)|
0 V Differential VISO VISO (min) VSS VISO (max)
(11)
In the case of external termination, VTT (termination voltage) should be gone in the range of VREF (DC) 0.04 V.
CAPACITANCE (VDD, VDDQ = 2.5 V, f = 1 MHz, Ta = 25C)
SYMBOL CIN CINC CI/O CNC CNC
1 2
PARAMETER Input pin Capacitance Clock pin (CLK, CLK ) Capacitance I/O pin (DQ, DQS) Capacitance NC pin Capacitance NC pin Capacitance
2 1
MIN 2.5 2.5 4.0 4.0
MAX 4.0 4.0 6.0 1.5 6.0
UNIT pF pF pF pF pF
Note: These parameters are periodically sampled and not 100% tested. 2 The NC pins have additional capacitance for adjustment of the adjacent pin capacitance. 2 The NC pins have Power and Ground clamp.
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RECOMMENDED DC OPERATING CONDITIONS (VDD,VDDQ=2.5V 0.15V, Ta = 0~70C)
MAX SYMBOL PARAMETER -50 Operating Current tCK = min; IRC = min, Read/Write command cycling, 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ, 1 bank operation, Burst length = 4, Address change up to 2 times during minimum IRC. Standby Current tCK = min, CS = VIH, PD = VIH, 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ, All banks: inactive state, Other input signals are changed one time during 4 x tCK. Standby (power down) Current tCK = min, CS = VIH, PD = VIL (power down), 0 V VIN VDDQ, All banks: inactive state Auto-Refresh Current tCK = min; IREFC = min, tREFI = min, Auto-Refresh command cycling, 0 V VIN VIL (AC) (max), VIH (AC) (min) VIN VDDQ, Address change up to 2 times during minimum IREFC. Self-Refresh Current Self-Refresh mode PD = 0.2 V, 0 V VIN VDDQ -55 -60 UNIT NOTES
IDD1S
190
180
170
1, 2
IDD2N
40
40
35
1
mA 2 2 2 1
IDD2P
IDD5
65
65
60
1
IDD6
3
3
3
SYMBOL ILI ILO IREF IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC) IOH (DC) IOL (DC)
PARAMETER Input Leakage Current ( 0 V VIN VDDQ, all other pins not under test = 0 V) Output Leakage Current (Output disabled, 0 V VOUT VDDQ) VREF Current Normal Output Driver Output Source DC Current VOH = VDDQ - 0.4 V Output Sink DC Current VOL = 0.4 V
MIN -5 -5 -5 -10 10 -11 11 -8 8 -7 7
MAX 5 5 5
UNIT A A A
NOTES
3 3 3 3 mA 3 3 3 3
Output Source DC Current Strong Output VOH = VDDQ - 0.4 V Driver Output Sink DC Current VOL = 0.4 V Weaker Output Driver Output Source DC Current VOH = VDDQ - 0.4 V Output Sink DC Current VOL = 0.4 V Output Source DC Current VOH = VDDQ - 0.4 V Output Sink DC Current VOL = 0.4 V

Weakest Output Driver
Notes: 1. These parameters depend on the cycle rate and these values are measured at a cycle rate with the minimum values of tCK, tRC and IRC. 2. These parameters depend on the output loading. The specified values are obtained with the output open. 3. Refer to output driver characteristics for the detail. Output Driver Strength is selected by Extended Mode Register.
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AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2)
-50 SYMBOL tRC tCK tRAC tCH tCL tCKQS tQSQ tAC tOH tQSPRE tHP tQSP tQSQV tDQSS tDSPRE tDSPRES tDSPREH tDSP tDSS tDSPST tDSPSTH tDSSK tDS tDH tDIPW tIS tIH tIPW tLZ tHZ PARAMETER MIN Random Cycle Time Clock Cycle Time Random Access Time Clock High Time Clock Low Time DQS Access Time from CLK Data Output Skew from DQS Data Access Time from CLK Data Output Hold Time from CLK DQS (read) Preamble Pulse Width CLK half period (minimum of Actual tCH, tCL) DQS (read) Pulse Width Data Output Valid Time from DQS DQS (write) Low to High Setup Time DQS (write) Preamble Pulse Width DQS First Input Setup Time DQS First Low Input Hold Time CL = 3 CL = 4 25 5.5 5 0.45 x tCK 0.45 x tCK -0.65 -0.65 -0.65 MAX 8.5 8.5 22 0.65 0.4 0.65 0.65 MIN 27.5 6 5.5 0.45 x tCK 0.45 x tCK -0.75 -0.75 -0.75 0.9 x tCK - 0.2 min(tCH, tCL) tHP- 0.6 tHP- 0.6 MAX 12 12 24 0.75 0.45 0.75 0.75 1.1 x tCK + 0.2 MIN 30 6.5 6 0.45 x tCK 0.45 x tCK -0.85 -0.85 -0.85 MAX 12 12 26 0.85 0.5 0.85 0.85 3 3 3 3 3 3 3, 8 4 3, 8 3, 8 3, 8 3 4, 8 4, 8 3 4 ns 3 3 4 3, 4 3, 4 4 3, 4 3, 4 -55 -60 UNIT NOTES
0.9 x tCK 1.1 x tCK - 0.2 + 0.2 min(tCH, tCL) tHP- 0.55 tHP- 0.55
0.9 x tCK 1.1 x tCK - 0.2 + 0.2 min(tCH, tCL) tHP- 0.65 tHP- 0.65
0.75 x tCK 1.25 x tCK 0.75 x tCK 1.25 x tCK 0.75 x tCK 1.25 x tCK 0.4 x tCK 0 0.25 x tCK 0.4 x tCK 0 0.25 x tCK 0.4 x tCK 0 0.25 x tCK
DQS High or Low Input Pulse Width 0.45 x tCK 0.55 x tCK 0.45 x tCK 0.55 x tCK 0.45 x tCK 0.55 x tCK DQS Input Falling Edge to Clock Setup Time CL = 3 CL = 4 1.3 1.3 1.4 1.4 0.45 x tCK 1.4 1.4 1.5 1.5 0.45 x tCK 1.5 1.5
DQS (write) Postamble Pulse Width 0.45 x tCK DQS (write) Postamble Hold Time CL = 3 CL = 4 1.3 1.3
UDQS - LDQS Skew (x16) Data Input Setup Time from DQS Data Input Hold Time from DQS Data Input Pulse Width (for each device) Command/Address Input Setup Time Command/Address Input Hold Time Command/Address Input Pulse Width (for each device) Data-out Low Impedance Time from CLK Data-out High Impedance Time from CLK
-0.5 x tCK 0.5 x tCK -0.5 x tCK 0.5 0.5 1.5 0.9 0.9 2.0 -0.65 0.65 0.5 0.5 1.5 0.9 0.9 2.0 -0.75
0.5 x tCK -0.5 x tCK 0.5 x tCK 0.75 0.6 0.6 1.9 1.0 1.0 2.2 -0.85 0.85 3,6,8 3,7,8 3 3 4 4
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AC CHARACTERISTICS AND OPERATING CONDITIONS (Notes: 1, 2) (continued)
-50 SYMBOL PARAMETER MIN tQSLZ tQSHZ tQPDH tPDEX tT tFPDL tREFI tPAUSE DQS-out Low Impedance Time from CLK DQS-out High Impedance Time from CLK Last output to PD High Hold Time Power Down Exit Time Input Transition Time PD Low Input Window for Self-Refresh Entry Auto-Refresh Average Interval Pause Time after Power-up Random Read/Write Cycle Time (applicable to same bank) CL = 3 CL = 4 -0.65 -0.65 0 2 0.1 -0.5 x tCK 0.4 200 5 5 MAX 0.65 1 5 7.8 MIN -0.75 -0.75 0 2 0.1 -0.5 x tCK 0.4 200 5 5 MAX 0.75 1 5 7.8 MIN -0.85 -0.85 0 2 0.1 -0.5 x tCK 0.4 200 5 5 MAX 0.85 1 5 7.8 3 5 3,6,8 3,7,8 -55 -60 UNIT NOTES
ns 3
s
IRC
IRCD
RDA/WRA to LAL Command Input Delay (applicable to same bank) LAL to RDA/WRA Command Input Delay (applicable to same bank) CL = 3 CL = 4
1
1
1
1
1
1
4 4 2 2 3 1 5 5 15 18 15 18 16 200
1 1
4 4 2 2 3 1 5 5 15 18 15 18 16 200
1 1
4 4 2 2 3 1 5 5 15 18 15 18 16 200
1 1 cycle
IRAS
IRBD
Random Bank Access Delay (applicable to other bank) LAL following RDA to WRA Delay (applicable to other bank) BL = 2 BL = 4
IRWD
IWRD
LAL following WRA to RDA Delay (applicable to other bank) Mode Register Set Cycle Time CL = 3 CL = 4
IRSC
IPD IPDA
PD Low to Inactive State of Input Buffer PD High to Active State of Input Buffer Power down mode valid CL = 3 from REF command CL = 4 Auto-Refresh Cycle Time CL = 3 CL = 4
IPDV
IREFC
ICKD ILOCK
REF Command to Clock Input Disable at Self-Refresh Entry DLL Lock-on Time (applicable to RDA command)
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AC TEST CONDITIONS
SYMBOL VIH (min) VIL (max) VREF VTT VSWING Vr VID (AC) SLEW VOTR PARAMETER Input High Voltage (minimum) Input Low Voltage (maximum) Input Reference Voltage Termination Voltage Input Signal Peak to Peak Swing Differential Clock Input Reference Level Input Differential Voltage Input Signal Minimum Slew Rate Output Timing Measurement Reference Voltage VALUE VREF + 0.35 VREF - 0.35 VDDQ/2 VREF 1.0 VX (AC) 1.5 1.0 VDDQ/2 UNIT V V V V V V V V/ns V NOTES
VDDQ VIH min (AC) VSWING VREF VIL max (AC) VSS T T AC Test Load Measurement point Output Z = 50 CL = 30 pF VREF VTT RT = 50
Output
SLEW = (VIH min (AC) - VIL max (AC))/T
Note: (1) (2) Transition times are measured between VIH min (DC) and VIL max (DC). Transition (rise and fall) of input signals have a fixed slope. If the result of nominal calculation with regard to tCK contains more than one decimal place, the result is rounded up to the nearest decimal place. (i.e., tDQSS = 0.75 x tCK, tCK = 5 ns, 0.75 x 5 ns = 3.75 ns is rounded up to 3.8 ns.) There parameters are measured from the differential clock (CLK and CLK ) AC cross point. These parameters are measured from signal transition point of DQS crossing VREF level. Te tREFI (max) applies to equally distributed refresh method. The tREFI (min) applies to both burst refresh method and distribted refresh method. In such case, the average interval of eight consecutive Auto-Refresh commands has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 s (8 x 400 ns) is to 8 times in the maximum. Low Impedance State is specified at VDDQ/2 0.2 V from steady state. High Impedance State is specified where output buffer is no longer driven. These parameters depend on the clock jitter. These parameters are measured at stable clock.
(3) (4) (5)
(6) (7) (8)
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POWER UP SEQUENCE
(1) (2) (3) (4) (5) (6) (7) (8) (9) As for PD , being maintained by the low state ( 0.2 V) is desirable before a power-supply injection. Apply VDD before or at the same time as VDDQ. Apply VDDQ before or at the same time as VREF. Start clock (CLK, CLK ) and maintain stable condition for 200 s (min). After stable power and clock, apply DESL and take PD =H. Issue EMRS to enable DLL and to define driver strength. (Note: 1) Issue MRS for set CAS latency (CL), Burst Type (BT), and Burst Length (BL). (Note: 1) Issue two or more Auto-Refresh commands (Note: 1). Ready for normal operation after 200 clocks from Extended Mode Register programming.
Note: (1) (2) Sequence 6, 7 and 8 can be issued in random order. L = Logic Low, H = Logic High
2.5V(TYP) VDD 2.5V(TYP) VDDQ 1.25V(TYP) VREF
CLK CLK 200 us(min) PD 200clock cycle(min) tPDEX lPDA lRSC lRSC lREFC lREFC
Command
DESL
RDA MRS DESL op-code
RDA MRS
DESL WRA REF
DESL
WRA REF
DESL
op-code
Address EMRS MRS
DQ Hi-Z DQS EMRS MRS Auto Refresh cycle Normal Operation
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TIMING DIAGRAMS
Input Timing
tCK tCK CLK
CLK
tCH
tCL
tIS
CS
tIH 1st
tIS 2nd
tIH
tIS FN tIPW tIS A0~A14 BA0, BA1 1st
tIH
tIS
tIPW tIH 2nd
tIH
tIS LA
tIH
UA, BA tIPW
DQS tDS tDH DQ (input) tDIPW tDIPW Refer to the Command Truth Table. tDS tDH
Timing of the CLK, CLK
tCH
CLK
tCL VIH VIH (AC) VIL (AC) VIL tCK tT tT
CLK
CLK
VIH VID (AC) VIL
CLK VX VX VX
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Read Timing (Burst Length = 4)
tCH CLK
CLK
tCL
tCK
tIS tIH Input (control & addresses)
LAL (after RDA) (DESL)
tIPW tCKQS tQSP tCKQS tQSP tQSHZ Hi-Z Postamble tLZ tQSQ tQSQV tQSQ Q1
CAS latency = 3
tQSLZ Hi-Z tQSPRE
tCKQS
DQS (output)
Preamble
tQSQV Q2 tAC tCKQS
tQSQ tHZ Q3 tAC tOH tCKQS tQSP Hi-Z
DQ (output)
Hi-Z
Q0 tAC
tCKQS tQSP tQSHZ
CAS latency = 4
tQSLZ Hi-Z tQSPRE
DQS (output)
Preamble tLZ tQSQ DQ (output) Hi-Z Q0 tAC Note: The correspondence of LDQS, UDQS to DQ. (TC59LM814CFT) tQSQV tQSQ Q1
Postamble
tQSQV Q2 tAC
tQSQ tHZ Q3 tAC tOH
LDQS UDQS
DQ0~DQ7 DQ8~DQ15
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Write Timing (Burst Length = 4)
tCH CLK
CLK
tCL
tCK
tIS tIH Input (control & addresses)
LAL (after WRA) (DESL)
tIPW tDSPSTH tDQSS tDSS tDSP tDSP tDSPST
CAS latency = 3
tDSPRES
tDSPREH tDSP
DQS (input) Preamble tDSPRE tDS tDH tDIPW DQ (input) D0 D1 tDQSS tDSPRES
CAS latency = 4
tDSS
Postamble tDS tDH D2 tDH D3 tDSS tDSPSTH tDSP tDSPST
tDS
tDSS tDSP tDSP
tDSPREH
DQS (input) Preamble tDSPRE tDS tDH tDIPW DQ (input) tDQSS D0 D1 tDQSS D2 tDS tDS tDH D3 Postamble
tDH
Note: the correspondence of LDQS, UDQS to DQ. (TC59LM814CFT)
LDQS UDQS
DQ0~DQ7 DQ8~DQ15
tREFI, tPAUSE, IXXXX Timing
CLK
CLK
tREFI, tPAUSE, IXXXX tIS tIH tIS tIH (DESL) Command Note: "IXXXX" means "IRC", "IRCD", "IRAS", etc. Command
Input (control & addresses)
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Write Timing (x16 device) (Burst Length = 4)
CLK
CLK
Input (control & addresses)
CAS latency = 3
WRA
LAL
(DESL)
tDSSK
tDSSK
tDSSK
tDSSK
LDQS Preamble tDS tDH DQ0~DQ7 D0 Postamble tDS tDH D1 tDS tDH D2 tDS tDH D3
UDQS Preamble tDS tDH DQ8~DQ15 D0 Postamble tDS tDH D1 tDS tDH D2 tDS tDH D3
CAS latency = 4
tDSSK
tDSSK
tDSSK
tDSSK
LDQS Preamble tDS tDH DQ0~DQ7 D0 tDS tDH D1 tDS tDH D2 tDS tDH D3
UDQS Preamble tDS tDH DQ8~DQ15 D0
tDS tDH D1
tDS tDH D2
tDS tDH D3
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FUNCTION TRUTH TABLE (Notes: 1, 2, 3)
Command Truth Table (Notes: 4)
* The First Command
SYMBOL DESL RDA WRA FUNCTION Device Deselect Read with Auto-close Write with Auto-close
CS
FN x H L
BA1~BA0 x BA BA
A14~A9 x UA UA
A8 x UA UA
A7 x UA UA
A6~A0 x UA UA
H L L
* The Second Command (The next clock of RDA or WRA command)
SYMBOL LAL LAL REF MRS FUNCTION Lower Address Latch (x16) Lower Address Latch (x8) Auto-Refresh Mode Register Set
CS
FN x x x x
BA1~ BA0 x x x V
A14~ A13 V V x L
A12~ A11 V x x L
A10~A9 x x x L
A8 x x x L
A7 x LA x V
A6~A0 LA LA x V
H H L L
Notes: 1. L = Logic Low, H = Logic High, x = either L or H, V = Valid (specified value), BA = Bank Address, UA = Upper Address, LA = Lower Address 2. All commands are assumed to issue at a valid state. 3. All inputs for command (excluding SELFX and PDEX) are latched on the crossing point of differential clock input where CLK goes to High. 4. Operation mode is decided by the combination of 1st command and 2nd command. Refer to "STATE DIAGRAM" and the command table below.
Read Command Table
COMMAND (SYMBOL) RDA (1st) LAL (2nd)
CS
FN H x
BA1~BA0 BA x
A14~A9 UA x
A8 UA x
A7 UA LA
A6~A0 UA LA
NOTES
L H
5
Notes: 5. For x16 device, A7 is "x" (either L or H).
Write Command Table
* TC59LM814CFT
COMMAND(SYMBOL) WRA (1st) LAL (2nd)
CS
FN L x
BA1~ BA0 BA x
A14 UA LVW0
A13 UA LVW1
A12 UA UVW0
A11 UA UVW1
A10~ A9 UA x
A8 UA x
A7 UA x
A6~A0 UA LA
L H
* TC59LM806CFT
COMMAND(SYMBOL) WRA (1st) LAL (2nd)
CS
FN L x
BA1~ BA0 BA x
A14 UA VW0
A13 UA VW1
A12 UA x
A11 UA x
A10~ A9 UA x
A8 UA x
A7 UA LA
A6~A0 UA LA
L H
Notes: 6. A14~ A11 are used for Variable Write Length (VW) control at Write Operation.
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FUNCTION TRUTH TABLE (continued)
VW Truth Table
SYMBOL Function Write All Words BL=2 Write First One Word Reserved Write All Words BL=4 Write First Two Words Write First One Word L H H H H L H VW0 L VW1 x x L L
Notes: 7. For x16 device, LVW0 and LVW1 control DQ0~DQ7. UVW0 and UVW1 control DQ8~DQ15.
Mode Register Set Command Table
COMMAND (SYMBOL) RDA (1st) MRS (2nd)
CS
FN H x
BA1~BA0 x V
A14~A9 x L
A8 x L
A7 x V
A6~A0 x V
NOTES
L L
8
Notes: 8. Refer to "MODE REGISTER TABLE".
Auto-Refresh Command Table
FUNCTION COMMAND (SYMBOL) WRA (1st) REF (2nd) CURRENT STATE Standby Active PD
CS
FN
BA1~BA0 x x
A14~A9 x x
A8 x x
A7 x x
A6~A0 NOTES x x
n-1 H H
n H H L L L x
Active Auto-Refresh
Self-Refresh Command Table
FUNCTION COMMAND (SYMBOL) WRA (1st) REF (2nd) SELFX CURRENT STATE Standby Active Self-Refresh Self-Refresh PD
CS
FN
BA1~BA0 x x x x
A14~A9 x x x x
A8 x x x x
A7 x x x x
A6~A0 NOTES x x x x 11 9, 10
n-1 H H L L
n H L L H L L x H L x x x
Active Self-Refresh Entry Self-Refresh Continue Self-Refresh Exit
Power Down Table
FUNCTION COMMAND (SYMBOL) PDEN PDEX CURRENT STATE Standby Power Down Power Down PD
CS
FN x x x
BA1~BA0 x x x
A14~A9 x x x
A8 x x x
A7 x x x
A6~A0 NOTES x x x 11
n-1 H L L
n L L H H x H 10
Power Down Entry Power Down Continue Power Down Exit Notes: 9. 10.
PD has to be brought to Low within tFPDL from REF command. PD should be brought to Low after DQ's state turned high impedance.
11. When PD is brought to High from Low, this function is executed asynchronously.
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FUNCTION TRUTH TABLE (continued)
CURRENT STATE PD n-1 n H H H H H L H H H H L H H H H L H H H H H L H H H H H L H H H H H L H H H H H L H L Power Down L L H L L L H H H L L x H H L L x H H L L x H H H L L x H H H L L x H H H L L x H H H L L x x L H H x L H H
CS
FN x H L x x x x x x x x x x x x x x H L x x x x H L x x x x H L x x x x H L x x x x x x x x x x x
ADDRESS x BA, UA BA, UA x x x LA Op-code x x x LA x x x x x BA, UA BA, UA x x x x BA, UA BA, UA x x x x BA, UA BA, UA x x x x BA, UA BA, UA x x x x x x x x x x x
COMMAND DESL RDA WRA PDEN LAL MRS/EMRS PDEN MRS/EMRS LAL REF PDEN REF (self) DESL RDA WRA PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN DESL RDA WRA PDEN PDEX SELFX
ACTION NOP Row activate for Read Row activate for Write Power Down Entry Illegal Refer to Power Down State Begin Read Access to Mode Register Illegal Illegal Invalid Begin Write Auto-Refresh Illegal Self-Refresh Entry Invalid Continue Burst Read to End Illegal Illegal Illegal Illegal Invalid Data Write&Continue Burst Write to End Illegal Illegal Illegal Illegal Invalid NOP Idle after IREFC Illegal Illegal Self-Refresh Entry Illegal Refer to Self-Refreshing State NOP Idle after IRSC Illegal Illegal Illegal Illegal Invalid Invalid Maintain Power Down Mode Exit Power Down Mode Idle after tPDEX Illegal Invalid Maintain Self-Refresh Exit Self-Refresh Idle after IREFC Illegal
NOTES
Idle
H L L H L x H L H L x H L H L x H L L H L x H L L H L x H L L H L x H L L H L x x x H L x x H L
12
Row Active for Read
Row Active for Write
Read
13 13
Write
13 13
Auto-Refreshing
14
Mode Register Accessing
Self-Refreshing
Notes: 12. Illegal if any bank is not idle. 13. Illegal to bank in specified states; Function may be legal in the bank inidicated by Bank Address (BA). 14. Illegal if tFPDL is not satisfied.
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MODE REGISTER TABLE
Regular Mode Register (Notes: 1)
ADDRESS Register BA1 0
*1
BA0 0
*1
A14~A8 0
A7
*3
A6~A4 CL
A3 BT
A2~A0 BL
TE
A7 0 1
TEST MODE (TE) Regular (default) Test Mode Entry
A3 0 1
BURST TYPE (BT) Sequential Interleave
A6 0 0 0 1 1 1
A5 0 1 1 0 0 1
A4 x 0 1 0 1 x
CAS LATENCY (CL)
A2 0 0 0 0
A1 0 0 1 1 x
A0 0 1 0 1
BURST LENGTH (BL) Reserved 2 4 Reserved
*2 *2
Reserved Reserved 3 4 Reserved Reserved
*2 *2
*2 *2
1
x
Extended Mode Register (Notes: 4)
ADDRESS Register BA1 0
*4
BA0 1
*4
A14~A7 0
A6 DIC
A5~A2 0
A1 DIC
A0
*5
DS
A6 0 0 1 1
A1 0 1 0 1
OUTPUT DRIVE IMPEDANCE CONTROL (DIC) Normal Output Driver Strong Output Driver Weaker Output Driver Weakest Output Driver
A0 0 1
DLL SWITCH (DS) DLL Enable DLL Disable
Notes: 1. Regular Mode Register is chosen using the combination of BA0 = 0 and BA1 = 0. 2. "Reserved" places in Regular Mode Register should not be set. 3. A7 in Regular Mode Register must be set to "0" (low state). Because Test Mode is specific mode for supplier. 4. Extended Mode Register is chosen using the combination of BA0 = 1 and BA1 = 0. 5. A0 in Extended Mode Register must be set to "0" to enable DLL for normal operation.
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STATE DIAGRAM
SELFREFRESH SELFX ( PD = H) PD = L PDEX ( PD = H)
POWER DOWN
PDEN ( PD = L) STANDBY (IDLE) MODE REGISTER WRA RDA MRS
PD = H AUTOREFRESH
REF
ACTIVE (RESTORE)
ACTIVE
LAL
LAL
WRITE (BUFFER)
READ
Command input Automatic return The second command at Active state must be issued 1 clock after RDA or WRA command input.
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TIMING DIAGRAMS
SINGLE BANK READ TIMING (CL = 3)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles Command BL = 2 DQS (output) RDA LAL DESL IRAS = 4 cycles RDA LAL
IRC = 5 cycles DESL IRAS = 4 cycles Hi-Z Hi-Z RDA LAL
IRCD=1 cycle Hi-Z
IRCD=1 cycle
CL = 3 DQ (output) BL = 4 DQS (output) Hi-Z CL = 3 DQ (output) Hi-Z Q0 Q1 Q2 Q3 Hi-Z Q0 Q1
CL = 3 Hi-Z Q0 Q1 Hi-Z
Hi-Z CL = 3 Hi-Z Q0 Q1 Q2 Q3
Hi-Z
Hi-Z
SINGLE BANK READ TIMING (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles Command BL = 2 DQS (output) RDA LAL DESL IRAS = 4 cycles RDA LAL
IRC = 5 cycles DESL IRAS = 4 cycles Hi-Z RDA LAL
IRCD = 1 cycle Hi-Z
IRCD = 1 cycle
IRCD = 1 cycle
CL = 4 DQ (output) BL = 4 DQS (output) Hi-Z CL = 4 DQ (output) Hi-Z Q0 Q1 Q2 Q3 Hi-Z Q0 Q1
CL = 4 Hi-Z Q0 Q1
Hi-Z CL = 4 Hi-Z Q0 Q1 Q2
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SINGLE BANK WRITE TIMING (CL = 3)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles Command BL = 2 DQS (input) WL = 2 DQ (input) BL = 4 DQS (input) WL = 2 DQ (input) D0 D1 D2 D3 D0 D1 tDQSS WRA LAL DESL IRAS = 4 cycles WRA LAL
IRC = 5 cycles DESL IRAS = 4 cycles WRA LAL
IRCD = 1 cycle
IRCD = 1 cycle
tDQSS WL = 2 D0 D1 tDQSS
WL = 2 D0 D1 D2 D3
SINGLE BANK WRITE TIMING (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles Command BL = 2 DQS (input) WL = 3 DQ (input) BL = 4 DQS (input) WL = 3 DQ (input) D0 D1 D2 D3 D0 D1 tDQSS WRA LAL DESL IRAS = 4 cycles WRA LAL
IRC = 5 cycles DESL IRAS = 4 cycles WRA LAL
IRCD = 1 cycle
IRCD = 1 cycle
IRCD = 1 cycle
WL = 3 D0 D1 tDQSS
WL = 3 D0 D1 D2 D3
Note:
means H or L
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SINGLE BANK READ-WRITE TIMING (CL = 3)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles Command BL = 2 DQS RDA LAL DESL IRAS = 4 cycles WRA LAL
IRC = 5 cycles DESL IRAS = 4 cycles Hi-Z RDA LAL
IRCD = 1 cycle Hi-Z
IRCD = 1 cycle Hi-Z
CL = 3 DQ BL = 4 DQS Hi-Z CL = 3 DQ Hi-Z Q0 Q1 Q2 Q3 Hi-Z Q0 Q1
WL = 2 Hi-Z D0 D1 tDQSS Hi-Z WL = 2 Hi-Z D0 D1 D2 D3 Hi-Z Hi-Z Hi-Z
SINGLE BANK READ-WRITE TIMING (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles Command BL = 2 DQS Hi-Z CL = 4 DQ BL = 4 DQS Hi-Z Hi-Z Q0 Q1 RDA LAL DESL IRAS = 4 cycles WRA LAL
IRC = 5 cycles DESL IRAS = 4 cycles Hi-Z WL = 3 Hi-Z D0 D1 tDQSS Hi-Z RDA LAL
IRCD = 1 cycle
IRCD = 1 cycle
CL = 4 DQ Hi-Z Q0 Q1 Q2 Q3
WL = 3 Hi-Z D0 D1 D2 D3
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MULTIPLE BANK READ TIMING (CL = 3)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles RDAa LALa RDAb LALb DESL
IRBD = 2 cycles RDAa LALa
IRCD = 1 cycle LALc
IRCD = 1 cycle RDAd LALd RDAb
Command
RDAc
IRCD = 1 cycle Bank Add. (BA0, BA1) BL = 2 DQS (output) Hi-Z Bank "a" x
IRAS = 4 cycles Bank "b" x
IRCD = 1 cycle Bank "a" x
IRBD = 2 cycles Bank "c" x
IRBD = 2 cycles x Bank "b"
Bank "d"
IRBD = 2 cycles Hi-Z CL = 3 CL = 3 Qa0 Qa1 CL = 3 Hi-Z CL = 3 CL = 3 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Hi-Z Qa0 Qa1 Qa2 Qa3 Qc0 Hi-Z Qb0 Qb1 Hi-Z Qa0 Qa1 CL = 3 Hi-Z Qc0
DQ (output) BL = 4 DQS (output)
Hi-Z
DQ (output)
Hi-Z
MULTIPLE BANK READ TIMING (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles RDAa LALa RDAb LALb DESL
IRBD = 2 cycles RDAa LALa
IRCD = 1 cycle LALc
IRCD = 1 cycle RDAd LALd RDAb
Command
RDAc
IRCD = 1 cycle Bank Add. (BA0, BA1) BL = 2 DQS (output) Hi-Z Bank "a" x
IRAS = 4 cycles x
IRCD = 1 cycle Bank "a" x
IRBD = 2 cycles x
IRBD = 2 cycles x Bank "b"
Bank "b"
Bank "c"
Bank "d"
IRBD = 2 cycles Hi-Z CL = 4 CL = 4 Qa0 Qa1 CL = 4 Hi-Z CL = 4 CL = 4 Qa0 Qa1 Qa2 Qa3 Qb0 Qb1 Qb2 Qb3 Hi-Z Qa0 Qa1 Qa2 Hi-Z Qb0 Qb1 Hi-Z CL = 4 Qa0 Qa1
DQ (output) BL = 4 DQS (output)
Hi-Z
DQ (output)
Hi-Z
Note: "x" is don't care. IRC to the same bank must be satisfied.
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MULTIPLE BANK WRITE TIMING (CL = 3)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles WRAa LALa WRAb LALb DESL
IRBD = 2 cycles IRCD = 1 cycle WRAa LALa WRAc LALc
IRCD = 1 cycle LALd WRAb
Command
WRAd
IRCD = 1 cycle Bank Add. (BA0, BA1) BL = 2 DQS (input) Bank "a" x
IRAS = 4 cycles x
IRCD = 1 cycle Bank "a" tDQSS x
IRBD = 2 cycles x
IRBD = 2 cycles x Bank "b"
Bank "b"
Bank "c" tDQSS
Bank "d"
IRBD = 2 cycles
WL = 2 DQ (input) BL = 4 DQS (input) WL = 2 DQ (input) Da0 Da1 tDQSS Db0 Db1 tDQSS
WL = 2 Da0 Da1 tDQSS Dc0 Dc1
WL = 2 Da0 Da1 Da2 Da3 Dc0 Dc1 Dc2
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
MULTIPLE BANK WRITE TIMING (CL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles WRAa LALa WRAb LALb DESL
IRBD = 2 cycles WRAa LALa
IRCD = 1 cycle LALc
IRCD = 1 cycle WRAd LALd WRAb
Command
WRAc
IRCD = 1 cycle Bank Add. (BA0, BA1) BL = 2 DQS (input) Bank "a" x
IRAS = 4 cycles x
IRCD = 1 cycle Bank "a" tDQSS x
IRBD = 2 cycles x
IRBD = 2 cycles x Bank "b"
Bank "b"
Bank "c"
Bank "d" tDQSS
IRBD = 2 cycles
WL = 3 DQ (input) BL = 4 DQS (input) WL = 3 DQ (input) Note: Da0 Da1 tDQSS Db0 Db1 tDQSS
WL = 3 Da0 Da1 tDQSS Dc0 Dc1
WL = 3 Da0 Da1 Da2 Da3 Dc0 Dc1
Da0 Da1 Da2 Da3 Db0 Db1 Db2 Db3
means H or L. "x" is don't care IRC to the same bank must be satisfied.
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MULTIPLE BANK READ-WRITE TIMING (BL = 2)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRBD = 2 cycles Command WRAa LALa
IRCD = 1 cycle IRWD = 2 cycles LALb DESL
IRC = 5 cycles IRBD = 2 cycles IRWD = 2 cycles LALc RDAd LALd DESL WRAc LALc
RDAb
WRAc
IRCD = 1 cycle IWRD = 1 cycle Bank Add. (BA0, BA1) CL = 3 DQS Bank "a" x Bank "b" tDQSS Hi-Z WL = 2 DQ CL = 4 DQS Hi-Z Da0 Da1 tDQSS Hi-Z WL = 3 x
IRCD = 1 cycle IWRD = 1 cycle Bank "c" x Bank "d" tDQSS Hi-Z CL = 3 Hi-Z WL = 2 Qb0 Qb1 Dc0 Dc1 tDQSS Hi-Z WL = 3 Hi-Z x
IRCD = 1 cycle Bank "c" x
CL = 3 Hi-Z Qd0
Hi-Z
CL = 4 Da0 Da1 Hi-Z
CL = 4 Dc0 Dc1 Hi-Z
DQ
Hi-Z
Qb0 Qb1
MULTIPLE BANK READ-WRITE TIMING (BL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRBD = 2 cycles WRAa LALa
IRCD = 1 cycle LALb
IRWD = 3 cycles IRBD = 2 cycles IRCD = 1 cycle DESL WRAc LALc RDAd LALd DESL
Command
RDAb
IRCD = 1 cycle IWRD = 1 cycle Bank Add. (BA0, BA1) CL = 3 DQS Bank "a" x Bank "b" tDQSS Hi-Z WL = 2 DQ Hi-Z CL = 3 Da0 Da1 Da2 Da3 tDQSS Hi-Z WL = 3 x
IRCD = 1 cycle IWRD = 1 cycle Bank "c" x Bank "d" tDQSS x
WL = 2 Qb0 Qb1 Qb2 Qb3 Dc0 Dc1 Dc2 Dc3 tDQSS
CL = 4 DQS
WL = 3 CL = 4
DQ
Hi-Z
Da0 Da1 Da2 Da3
Qb0 Qb1 Qb2 Qb3
Dc0 Dc1 Dc2
Note: "x" is don't care IRC to the same bank must be satisfied.
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SINGLE BANK WRITE with VARIABLE WRITE LENGTH (VW) CONTROL (CL = 3, BL = 4, Sequential mode)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
x8 Command WRA LAL
IRC = 5cycles DESL WRA LAL
IRC = 5cycles DESL WRA LAL
Address
LA=#3 VW=2 (Write First Two Words) UA
UA
LA=#1 VW=1 (Write First One Word)
UA
LA=#3 VW=2
DQS (input) Last two data are masked. DQ (input) x16 Command WRA LAL DESL WRA LAL DESL WRA LAL D0 D1 Address #3 #0 (#1) (#2) D0 #1 (#2) (#3) (#0) Last three data are
Address
UA
LA =#3 UVW=2 LVW=1
UA
LA=#1 UVW=1 LVW=1
UA
LA=#3 UVW=2 LVW=1
Upper byte: Write First Two Words Lower byte: Write First One Word UDQS (input)
Upper byte: Write First One Word Lower byte: Write First One Word
Last two data are masked. DQ8~DQ15 (input) D0 D1 Address #3 #0 (#1) (#2) UDQS (input) Last three data are DQ0~DQ7 (input) D0 Address #3 (#0) (#1) (#2) Note: D0 D0
Last three data are
#1 (#2) (#3) (#0)
Last three data are
#1 (#2) (#3) (#0)
DQS input must be continued till end of burst count even if some of laster data is masked. Refer to "VW Truth Table".
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MODE REGISTER SET TIMING (CL = 3, BL = 2)
0 CLK
CLK
1
2
3
4
5
6
7
8
9
10
11
IRC = 5 cycles Command RDA LAL DESL IRAS = 4 cycles x RDA MRS
IRSC = 5 cycles DESL RDA or WRA
IRCD = 1 cycle A14~A0 BA0, BA1 BA, UA LA
IRCD = 1 cycle Valid (opcode) x BA, UA
DQS (output)
Hi-Z CL = 3
Hi-Z
DQ (output)
Hi-Z
Q0 Q1
Hi-Z
POWER DOWN TIMING (CL = 3, BL = 2)
Read cycle to Power Down Mode
0 CLK
CLK
1
2
3
4
5
6
7
n-1
n
n+1
n+2
IPDA = 1 cycle Command RDA LAL DESL tIH tIS IPD = 1 cycle x DESL RDA or WRA
IRCD = 1 cycle PD
tQPDH
lRC(min), tREFI(max) Hi-Z
tPDEX
DQS (output)
Hi-Z CL = 3
DQ (output)
Hi-Z
Q0 Q1
Hi-Z
Power Down Entry
Power Down Exit
Note: "x" is don't care IPD is defined from the first clock rising edge after PD is brought to "Low". IPDA is defined from the first clock rising edge after PD is brought to "High". PD must be kept "High" level until end of Burst data output. PD should be brought to high within tREFI(max) to maintain the data written into cell.
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POWER DOWN TIMING (CL = 4)
Write cycle to Power Down Mode
0 CLK
CLK
1
2
3
4
5
6
7
8
9
n-1
n
n+1
n+2
IPDA = 1 cycle Command WRA LAL DESL tIH tIS IPD = 1 cycle PD WL=3 BL = 4 DQS (Input) Hi-Z Hi-Z 2 clock cycles lRC(min), tREFI(max) tPDEX x DESL RDA or WRA
DQ (Input) BL = 2 DQS (Input)
Hi-Z
D0 D1 D2 D3
Hi-Z
Hi-Z
Hi-Z
DQ (Input)
Hi-Z
D0 D1
Hi-Z
Power Down Entry Note: "x" is don't care PD must be kept "High" level until WL+2 clock cycles from LAL command. PD should be brought to high within tREFI(max) to maintain the data written into cell.
Power Down Exit
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AUTO-REFRESH TIMING (CL = 3, BL = 4)
0 CLK
CLK
1
2
3
4
5
6
7
n-1
n
n+1
n+2
IRC = 5 cycles Command RDA LAL DESL IRAS = 4 cycles WRA REF
IREFC = 15 cycles DESL RDA or WRA LAL or MRS or REF
IRCD = 1 cycle DQS (output) Hi-Z
IRCD = 1 cycle Hi-Z
CL = 3 DQ (output) Hi-Z Q0 Q1 Q2 Q3 Hi-Z
Note: In case of CL = 3, IREFC must be meet 15 clock cycles. When the Auto-Refresh operation is performed, the synthetic average interval of Auto-Refresh command specified by tREFI must be satisfied. tREFI is average interval time in 8 Refresh cycles that is sampled randomly. t1 CLK t2 t3 t7 t8
WRA REF
WRA REF
WRA REF
WRA REF
WRA REF
8 Refresh cycle
tREFI =
Total time of 8 Refresh cycle 8
=
t1 + t2 + t3 + t4 + t5 + t6 + t7 + t8 8
tREFI is specified to avoid partly concentrated current of Refresh operation that is activated larger area than Read / Write operation.
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SELF-REFRESH ENTRY TIMING (CL = 3)
0 CLK
CLK
1
2
3
4
5
m-1
m
m+1
IRCD = 1 cycle WRA REF tFPDL (max)
IREFC DESL x
*1
Command
tFPDL (min) PD
Auto Refresh Self Refresh Entry IPDV *2 tQPDH DQS (output) DQ (output) Hi-Z ICKD = 16 cycles*3
Qx
Hi-Z
Notes: 1. "x" is don't care. 2. PD must be brought to "Low" within the timing between tFPDL(min) and tFPDL(max) to Self TM Refresh mode.When PD is brought to "Low" after lPDV, FCRAM perform Auto Refresh and enter Power down mode. 3. It is necessary that clock input is continued at least 16 clock cycles from REF command even though PD is brought to "Low" for Self-Refresh Entry.
SELF-REFRESH EXIT TIMING
0 CLK
CLK
*2
1
2
m-1
m
m+1
m+2
n-1
n
n+1
p-1
p
IREFC Command x
*1
IREFC WRA
*5
Command (1st)*6 Command (2nd)*6 RDA IRCD = 1 cycle
*7
DESL
*3
REF
*5
DESL
LAL
*7
IPDA = 1 cycle*4 PD tPDEX
IRCD = 1 cycle
ILOCK DQS (output) DQ (output) Hi-Z
Hi-Z
Self-Refresh Exit Notes: 1. 2. 3. 4. 5. "x" is don't care. Clock should be stable prior to PD = "High" if clock input is suspended in Self-Refresh mode. DESL command must be asserted during IREFC after PD is brought to "High". IPDA is defined from the first clock rising edge after PD is brought to "High". It is desirable that one Auto-Refresh command is issued just after Self-Refresh Exit before any other operation. 6. Any command (except Read command) can be issued after IREFC. 7. Read command (RDA + LAL) can be issued after ILOCK.
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FUNCTIONAL DESCRIPTION Network FCRAM
TM
The FCRAMTM is an acronym of Fast Cycle Random Access Memory. The Network FCRAMTM is competent to perform fast random core access, low latency, low consumption and high-speed data transfer.
PIN FUNCTIONS
CLOCK INPUTS: CLK & CLK
The CLK and CLK inputs are used as the reference for synchronous operation. CLK is master clock input. The CS , FN and all address input signals are sampled on the crossing of the positive edge of CLK and the negative edge of CLK . The DQS and DQ output data are referenced to the crossing point of CLK and CLK . The timing reference point for the differential clock is when the CLK and CLK signals cross during a transition.
POWER DOWN: PD
The PD input controls the entry to the Power Down or Self-Refresh modes. The PD input does not have a Clock Suspend function like a CKE input of a standard SDRAMs, therefore it is illegal to bring PD pin into low state if any Read or Write operation is being performed.
CHIP SELECT & FUNCTION CONTROL: CS & FN
The CS and FN inputs are a control signal for forming the operation commands on FCRAMTM. Each operation mode is decided by the combination of the two consecutive operation commands using the CS and FN inputs.
BANK ADDRESSES: BA0 & BA1
The BA0 and BA1 inputs are latched at the time of assertion of the RDA or WRA command and are selected the bank to be used for the operation.
BA0 Bank #0 Bank #1 Bank #2 Bank #3 0 1 0 1
BA1 0 0 1 1
ADDRESS INPUTS: A0~A14
Address inputs are used to access the arbitrary address of the memory cell array within each bank. The Upper Addresses with Bank addresses are latched at the RDA or WRA command and the Lower Addresses are latched at the LAL command. The A0 to A14 inputs are also used for setting the data in the Regular or Extended Mode Register set cycle.
UPPER ADDRESS TC59LM806CFT TC59LM814CFT A0~A14 A0~A14
LOWER ADDRESS A0~A7 A0~A6
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DATA INPUT/OUTPUT: DQ0~DQ7 or DQ15
The input data of DQ0 to DQ15 are taken in synchronizing with the both edges of DQS input signal. The output data of DQ0 to DQ15 are outputted synchronizing with the both edges of DQS output signal.
DATA STROBE: DQS or LDQS, UDQS
The DQS is bi-directional signal. Both edges of DQS are used as the reference of data input or output. The LDQS is allotted for Lower Byte (DQ0 to DQ7) Data. The UDQS is allotted for Upper Byte (DQ8 to DQ15) Data. In write operation, the DQS used as an input signal is utilized for a latch of write data. In read operation, the DQS that is an output signal provides the read data strobe.
POWER SUPPLY: VDD, VDDQ, VSS, VSSQ
VDD and VSS are power supply pins for memory core and peripheral circuits. VDDQ and VSSQ are power supply pins for the output buffer.
REFERENCE VOLTAGE: VREF
VREF is reference voltage for all input signals.
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COMMAND FUNCTIONS and OPERATIONS
TC59LM814/06CFT are introduced the two consecutive command input method. Therefore, except for Power Down mode, each operation mode decided by the combination of the first command and the second command from stand-by states of the bank to be accessed.
Read Operation (1st command + 2nd command = RDA + LAL)
Issuing the RDA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a read mode. When the LAL command with Lower Addresses is issued at the next clock of the RDA command, the data is read out sequentially synchronizing with the both edges of DQS output signal (Burst Read Operation). The initial valid read data appears after CAS latency from the issuing of the LAL command. The valid data is outputted for a burst length. The CAS latency, the burst length of read data and the burst type must be set in the Mode Register beforehand. The read operated bank goes back automatically to the idle state after lRC.
Write Operation (1st command + 2nd command = WRA + LAL)
Issuing the WRA command with Bank Addresses and Upper Addresses to the idle bank puts the bank designated by Bank Address in a write mode. When the LAL command with Lower Addresses is issued at the next clock of the WRA command, the input data is latched sequentially synchronizing with the both edges of DQS input signal (Burst Write Operation). The data and DQS inputs have to be asserted in keeping with clock input after CAS latency-1 from the issuing of the LAL command. The DQS have to be provided for a burst length. The CAS latency and the burst type must be set in the Mode Register beforehand. The write operated bank goes back automatically to the idle state after lRC.
Auto-Refresh Operation (1st command + 2nd command = WRA + REF)
TC59LM814/06CFT are required to refresh like a standard SDRAM. The Auto-Refresh operation is begun with the REF command following to the WRA command. The Auto-Refresh mode can be effective only when all banks are in the idle state and all outputs are in Hi-Z states. In a point to notice, the write mode started with the WRA command is canceled by the REF command having gone into the next clock of the WRA command instead of the LAL command. The minimum period between the Auto-Refresh command and the next command is specified by lREFC. However, about a synthetic average interval of Auto-Refresh command, it must be careful. In case of equally distributed refresh, Auto-Refresh command has to be issued within once for every 7.8 s by the maximum. In case of burst refresh or random distributed refresh, the average interval of eight consecutive Auto-Refresh command has to be more than 400 ns always. In other words, the number of Auto-Refresh cycles which can be performed within 3.2 s (8 x 400 ns) is to 8 times in the maximum.
Self-Refresh Operation (1st command + 2nd command = WRA + REF with PD = "L")
It is the function of Self-Refresh operation that refresh operation can be performed automatically by using an internal timer. When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM814/06CFT become Self-Refresh mode by issuing the Self-Refresh command. PD has to be brought to "Low" within tFPDL from the REF command following to the WRA command for a Self-Refresh mode entry. In order to satisfy the refresh period, the Self-Refresh entry command should be asserted within 7.8 s after the latest Auto-Refresh command. Once the device enters Self-Refresh mode, the DESL command must be continued for lREFC period. In addition, it is necessary that clock input is kept in lCKD period. The device is in Self-Refresh mode as long as PD held "Low". During Self-Refresh mode, all input and output buffers except for PD are disabled, therefore the power dissipation lowers. Regarding a Self-Refresh mode exit, PD has to be changed over from "Low" to "High" along with the DESL command, and the DESL command has to be continuously issued in the number of clocks specified by lREFC. The Self-Refresh exit function is asynchronous operation. It is required that one Auto-Refresh command is issued to avoid the violation of the refresh period just after lREFC from Self-Refresh exit.
Power Down Mode ( PD = "L")
When all banks are in the idle state and all outputs are in Hi-Z states, the TC59LM814/06CFT become Power Down Mode by asserting PD is "Low". When the device enters the Power Down Mode, all input and output buffers except for PD are disabled after specified time. Therefore, the power dissipation lowers. To exit the Power Down Mode, PD has to be brought to "High" and the DESL command has to be issued at next CLK rising edge after PD goes high. The Power Down exit function is asynchronous operation.
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Mode Register Set (1st command + 2nd command = RDA + MRS)
When all banks are in the idle state, issuing the MRS command following to the RDA command can program the Mode Register. In a point to notice, the read mode started with the RDA command is canceled by the MRS command having gone into the next clock of the RDA command instead of the LAL command. The data to be set in the Mode Register is transferred using A0 to A14, BA0 and BA1 address inputs. The TC59LM814/06CFT have two mode registers. These are Regular and Extended Mode Register. The Regular or Extended Mode Register is chosen by BA0 and BA1 in the MRS command. The Regular Mode Register designates the operation mode for a read or write cycle. The Regular Mode Register has four function fields. The four fields are as follows: (R-1) Burst Length field to set the length of burst data (R-2) Burst Type field to designate the lower address access sequence in a burst cycle (R-3) CAS Latency field to set the access time in clock cycle (R-4) Test Mode field to use for supplier only. The Extended Mode Register has two function fields. The two fields are as follows: (E-1) DLL Switch field to choose either DLL enable or DLL disable (E-2) Output Driver Impedance Control field. Once those fields in the Mode Register are set up, the register contents are maintained until the Mode Register is set up again by another MRS command or power supply is lost. The initial value of the Regular or Extended Mode Register after power-up is undefined, therefore the Mode Register Set command must be issued before proper operation.
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* Regular Mode Register/Extended Mode Register change bits (BA0, BA1) These bits are used to choose either Regular MRS or Extended MRS
BA1 0 0 1 BA0 0 1 x A14~A0 Regular MRS Cycle Extended MRS Cycle Reserved
Regular Mode Register Fields
(R-1) Burst Length field (A2 to A0) This field specifies the data length for column access using the A2 to A0 pins and sets the Burst Length to be 2 or 4 words.
A2 0 0 0 0 1 A1 0 0 1 1 x A0 0 1 0 1 x BURST LENGTH Reserved 2 words 4 words Reserved Reserved
(R-2) Burst Type field (A3) The Burst Type can be chosen Interleave mode or Sequential mode. When the A3 bit is "0", Sequential mode is selected. When the A3 bit is "1", Interleave mode is selected. Both burst types support burst length of 2 and 4 words.
A3 0 1 BURST TYPE Sequential Interleave
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Addressing sequence of Sequential mode (A3) A column access is started from the inputted lower address and is performed by incrementing the lower address input to the device. The address is varied by the Burst Length as the following.
CAS Latency = 3
CLK
CLK
Command DQS
RDA
LAL
DQ
Data Data Data Data 0 1 2 3
Addressing sequence for Sequential mode
DATA Data 0 Data 1 Data 2 Data 3 ACCESS ADDRESS n n+1 n+2 n+3 BURST LENGTH 2 words (address bits is LA0) not carried from LA0~LA1 4 words (address bits is LA1, LA0) not carried from LA1~LA2
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* Addressing sequence of Interleave mode A column access is started from the inputted lower address and is performed by interleaving the address bits in the sequence shown as the following.
Addressing sequence for Interleave mode
DATA Data 0 Data 1 Data 2 Data 3 ACCESS ADDRESS A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 A8 A7 A6 A5 A4 A3 A2 A1 A0 4 words BURST LENGTH 2 words
(R-3)
CAS Latency field (A6 to A4) This field specifies the number of clock cycles from the assertion of the LAL command following the RDA command to the first data read. The minimum values of CAS Latency depends on the frequency of CLK. In a write mode, the place of clock which should input write data is CAS Latency cycles - 1.
A6 0 0 0 0 1 1 1 1 A5 0 0 1 1 0 0 1 1 A4 0 1 0 1 0 1 0 1
CAS LATENCY
Reserved Reserved Reserved 3 4 Reserved Reserved Reserved
(R-4) Test Mode field (A7) This bit is used to enter Test Mode for supplier only and must be set to "0" for normal operation. (R-5) Reserved field in the Regular Mode Register * Reserved bits (A8 to A14) These bits are reserved for future operations. They must be set to "0" for normal operation.
Extended Mode Register fields
(E-1) DLL Switch field (A0) This bit is used to enable DLL. When the A0 bit is set "0", DLL is enabled. (E-2) Output Driver Impedance Control field (A1 / A6) This bit is used to choose Output Driver Strength. Four types of Driver Strength are supported.
A6 0 0 1 1 A1 0 1 0 1 OUTPUT DRIVER IMPEDANCE CONTROL Normal Output Driver Strong Output Driver Weaker Output Driver Weakest Output Driver
(E-3) Reserved field (A2 to A5, A7 to A14) These bits are reserved for future operations and must be set to "0" for normal operation.
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PACKAGE DIMENSIONS
Weight:
0.51 g (typ.)
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RESTRICTIONS ON PRODUCT USE
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000707EBA
TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice.
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