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INTEGRATED CIRCUITS
DATA SHEET
TDA1547 Dual top-performance bitstream DAC
Product specification File under Integrated Circuits, IC01 September 1991
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
FEATURES * Top-grade audio performance - very low harmonic distortion - high signal-to-noise ratio - wide dynamic range of approximately 108 dB (not A-weighted) * High crosstalk immunity * Bitstream concept - high over-sampling rate up to 192 fs - pulse-density modulation - inherently monotonic - no zero-crossing distortion GENERAL DESCRIPTION The TDA1547 is a dedicated one-bit digital-to-analog converter to facilitate a high fidelity sound reproduction of digital audio. The TDA1547 is extremely suitable for use in high quality audio systems such as Compact Disc and DAT players, or in digital amplifiers and digital signal processing systems. The TDA1547 is used in combination with the SAA7350 bitstream circuit, which includes the ORDERING INFORMATION EXTENDED TYPE NUMBER TDA1547(1) Note 1. SOT-232-1; 1996 August 23. PACKAGE PINS 32 PIN POSITION SDIL MATERIAL plastic
TDA1547
third-order noise shaper. The excellent performance of the SAA7350 and TDA1547 bitstream conversion system is obtained by separating the noise shaping circuit and the one-bit conversion circuit over two IC's, thereby reducing the crosstalk between the digital and analog parts. The TDA1547 one-bit converter is processed in BIMOS. In the digital logic and drivers bipolar transistors are used to optimize speed and to reduce digital noise generation. In the analog part the bipolar transistors are used to obtain high performance of the operational amplifiers. Special layout precautions have been taken to achieve a high crosstalk immunity. The layout of the TDA1547 has fully separated left and right channels and supply voltage lines between the digital and analog sections.
CODE SOT232A
September 1991
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Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
handbook, halfpage
DGND VDDD IN R n.c. CLK R VDDD R VSSD R Vref R AGND DAC R
1 2 3 4 5 6 7 8
32 31
VSUB VSSD
30 IN L 29 n.c. 28 CLK L 27 26 25 V DDD L V SSD L V ref L AGND DAC L - DAC L + DAC L AGND L
TDA1547
9 24 23 22 21
- DAC R 10 + DAC R 11 AGND R 12 n.c. 13 + OUT R 14 - OUT R 15 V SSA 16
MCD294
20 n.c. 19 + OUT L 18 17 - OUT L V DDA
Fig.1 Pinning diagram.
September 1991
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Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
PINNING SYMBOL DGND VDDD IN R n.c. CLK R VDDD R VSSD R Vref R AGND DAC R -DAC R +DAC R AGND R n.c. +OUT R -OUT R VSSA VDDA -OUT L +OUT L n.c. AGND L +DAC L -DAC L AGND DAC L Vref L VSSD L VDDD L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 PIN 0 V digital supply 5 V digital supply for both channels serial one-bit data input for the right channel pin not connected; should preferably be connected to digital ground clock input for the right channel DESCRIPTION
TDA1547
5 V digital supply for the right channel; this voltage determines the internal logic HIGH level in the right channel -3.5 V digital supply for the right channel; this voltage determines the internal logic LOW level in the right channel -4 V reference voltage for the right channel switched capacitor DAC 0 V reference voltage for the right channel switched capacitor DAC; this pin should be connected to analog ground output from the right negative switched capacitor DAC; feedback connection for the right negative operational amplifier output from the right positive switched capacitor DAC; feedback connection for the right positive operational amplifier 0 V reference voltage for both right channel operational amplifiers pin not connected; should preferably be connected to analog ground + output of the switched capacitor operational amplifier - output of the switched capacitor operational amplifier -5 V analog supply 5 V analog supply - output of the switched capacitor operational amplifier + output of the switched capacitor operational amplifier pin not connected; should preferably be connected to analog ground 0 V reference voltage for both left channel operational amplifiers output from the left positive switched capacitor DAC; feedback connection for the left positive operational amplifier output from the left negative switched capacitor DAC; feedback connection for left negative operational amplifier 0 V reference voltage for the left channel switched capacitor DAC; this pin should be connected to analog ground -4 V reference voltage for the left channel switched capacitor DAC -3.5 V digital supply for the left channel; this voltage determines the internal logic LOW level in the left channel 5 V digital supply for the left channel; this voltage determines the internal logic HIGH level in the left channel
September 1991
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Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
SYMBOL CLK L n.c. IN L VSSD VSUB
PIN 28 29 30 31 32 clock input for the left channel
DESCRIPTION pin not connected; should preferably be connected to digital ground serial one-bit data input for the left channel -5 V digital supply for both channels -5 V substrate voltage
QUICK REFERENCE DATA SYMBOL Supply voltages VDDD L. R VDDD VSSD L. R VSSD VDDA VSSA Supply current IDDD L. R IDDD ISSD L. R ISSD IDDA ISSA Ptot VOUT(RMS) positive digital supply current for one channel; pins 27 and 6 digital supply current for both channels; pin 2 negative digital supply current for one channel; pins 26 and 7 negative supply current for both channels; pin 31 positive analog supply current; pin 17 negative analog supply current; pin 16 total power dissipation output voltage (RMS value) fCLK = 8.46 MHz; notes 1 and 2 - - - - - - - 0.85 0.1 29.0 -0.1 -28.0 51.0 -51.0 800 1.0 - - - - - - - 1.15 mA mA mA mA mA mA mW V positive digital supply voltage for one channel; pins 27 and 6 digital supply voltage for both channels; pin 2 negative digital supply voltage for one channel; pins 26 and 7 negative digital supply voltage for both channels; pin 31 positive analog supply voltage; pin 17 negative analog supply voltage; pin 16 4.5 4.5 -4.0 -5.5 4.5 -6.0 5.0 5.0 -3.5 -5.0 5.0 -5.0 5.5 5.5 -3.0 -4.5 6 -4.5 V V V V V V PARAMETER CONDITION MIN TYP MAX UNIT
September 1991
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Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
SYMBOL Supply current (THD + N)/S (THD + N)/S (THD + N)/S (THD + N)/S S/N S/N fCLK Tamb
PARAMETER
CONDITION 1 kHz; notes 2 and 3 - - f = 20 Hz to 20 kHz; notes 2 and 4 f = 1 kHz; notes 2 and 3 f = 1 kHz; notes 2 and 3 pattern 0101..; notes 2 and 5 pattern 0101..; notes 2 and 5 f = 1 kHz - - - -
MIN
TYP -101 -101 -88 -48 111 113 - 115 -
MAX -96 -84 -44 - - 10 - 70
UNIT
THD + Noise; 0 dB THD + Noise; 0 dB THD + Noise; -20 dB THD + Noise; -60 dB signal-to-noise ratio signal-to-noise ratio; "A"-weighting maximum clock frequency channel separation operating ambient temperature
dB dB % dB dB dB dB MHz dB C
0.0009 0.0016 % 0.0009 -
109 - - 101 -20
Notes to the quick reference data 1. Output level tracks linearly with both the clock frequency and the reference voltage (Vref L or Vref R). 2. Device measured in differential mode with external components as shown in Fig.5. 3. Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 1 kHz digital sinewave. Measured over a 20 Hz to 20 kHz bandwidth. 4. Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 20 Hz to 20 kHz digital sinewave. Measured over a 20 Hz to 20 kHz bandwidth. 5. The specified signal-to-noise ratio includes noise introduced by the application components as shown in Fig.5. FUNCTIONAL DESCRIPTION Both channels are completely separated to reach the desired high crosstalk suppression level. Each channel consists of the following functional parts: - One-bit input, which latches the incoming data to the system clock. - Switch driver circuit, which generates the non-overlapping clock- and data-signals that control the DAC switched capacitor networks. - Switched capacitor network, this forms the actual DAC function, it supplies charge packets to the low-pass filter, under control of the incoming one-bit code. - Two high performance operational amplifiers, that perform the charge packet to voltage conversion and deliver a differential output signal. The first pole of the low-pass filter is built around them. THERMAL RESISTANCE SYMBOL Rth j-a from junction to ambient PARAMETER MAX. 60 UNIT K/W
September 1991
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handbook, full pagewidth
September 1991
V DDD L n.c. (+5 V) (+5 V) clock input left (- 3.5 V) positive DAC output n.c. negative output VSSD L AGND DAC L (0 V) Vref L (- 4 ) negative DAC output AGND L (0 V) positive output VDDA 29 28 27 26 25 24 23 22 21 20 19 18 17
Philips Semiconductors
VSSD (- 5 V)
VSUB (- 5 V)
data input left
32
31
30
Dual top-performance bitstream DAC
ONE-BIT INPUT
SWITCH DRIVERS
SWITCHED CAPACITOR NETWORK
LEFT CHANNEL
7
SWITCH DRIVERS SWITCHED CAPACITOR NETWORK RIGHT CHANNEL 4 5 6 7 8 9 10 11 12 13 14 15 16
MCD293
TDA1547
ONE-BIT INPUT
1
2
3
(0 V) DGND (- 3.5 V) VSSD R (+5 V) VDDD R (- 4 V) Vref R (0 V) AGND DAC R n.c.
data input right
clock input right
positive DAC output (0 V) AGND R
n.c.
negative output positive output (- 5 V) VSSA
(+5 V) V DDD
negative DAC output
Product specification
TDA1547
Fig.2 Block diagram.
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134) SYMBOL VSUB VDDD L. R VDDD VSSD L. R VSSD VDDA VSSA VDDD L. R - VSSD L. R Ptot Vref L. R VCLK L. R VI L VI R Tamb Tstg TXTAL VES PARAMETER negative substrate voltage; pin 32 positive digital supply voltage; pins 27 and 6 positive digital supply voltage; pin 2 negative digital supply voltage; pins 26 and 7 negative digital supply voltage; pin 31 positive analog supply voltage; pin 17 negative analog supply voltage; pin 16 supply voltage difference between pins 27, 6 and pins 26, 7 total power dissipation input reference voltage; pins 25 and 8 input voltage clock; pins 28 and 5 input voltage channel; pin 30 input voltage channel; pin 3 operating ambient temperature storage temperature maximum crystal temperature electrostatic handling note 2 Tamb = 70 C CONDITIONS note 1 - - -4.0 -5.5 - -6.0 - - -6.0 -0.5 -0.5 -0.5 -20 -40 - - MIN -7.0 - 5.5 5.5 - - 6.0 - 9.0 1300
TDA1547
MAX. V V V V V V V V
UNIT
mW V
VDDD+0.5 V VDDD+0.5 V VDDD+0.5 V 70 150 150 2000 C C C V
Notes to the limiting values 1. The substrate voltage must be lower than or equal to the lowest supply voltage. 2. Equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor.
September 1991
8
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
CHARACTERISTICS VDDD, VDDD L. R, VDDA = +5 V; VSSD, VSSA = -5 V, VSSD L. R = -3.5 V; Vref L. R = -4 V; Tamb = 25 C; fCLK = 8.46 MHz; unless otherwise specified SYMBOL Supply VSUB VDDD L. R VDDD VSSD L. R VSSD VDDA VSSA VDDD L. R - VSSD L, R VSSD L. R - VSSD IDDD L. R IDDD ISSD L. R ISSD -IDDA ISSA PSSR1 PSSR2 PSSR3 PSSR4 PSSR5 PSSR6 Ptot Clock - Input VIL VIH IIL input voltage LOW input voltage HIGH input current LOW Vi = 0.5 V - 4.5 -10 - - - 0.5 - 10 V V A negative substrate voltage; pin 32 positive digital supply voltage for one channel; pins 27 and 6 digital supply voltage for both channels; pin 2 negative digital supply voltage for one channel; pins 26 and 7 negative digital supply voltage for both channels; pin 31 positive analog supply voltage; pin 17 negative analog supply voltage; pin 16 supply voltage difference between pins 27, 6 and pins 26, 7 supply voltage difference between pins 26, 7 and pin 31 positive digital supply current for one channel; pins 27 and 6 digital supply current for both channels; pin 2 negative digital supply current for one channel; pins 26 and 7 negative supply current for both channels; pin 31 positive analog supply current; pin 17 negative analog supply current; pin 16 power supply rejection ratio power supply rejection ratio power supply rejection ratio power supply rejection ratio power supply rejection ratio power supply rejection ratio total power dissipation VDDD; note 6 VSSD L, R; note 6 VSSD; note 6 VDDA; note 6 VSSA; note 6 - -45 - -63.0 VDDD L, R; note 6 50 50 60 50 60 60 - note 1 -7.0 4.5 4.5 -4.0 -5.5 4.5 -6.0 - 1.3 - - 5.0 5.0 -3.5 -5.0 5.0 -5.0 - - 0.1 29.0 -0.1 -28.0 51.0 -51.0 - - - - - - 800 -4.5 5.5 5.5 -3.0 -4.5 6.0 -4.5 9.0 - - 46 - - 63 - - - - - - - - V V V V V V V V V mA mA mA mA mA mA dB dB dB dB dB dB mW PARAMETER CONDITIONS MIN TYP MAX UNIT
September 1991
9
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
SYMBOL IIH Ci fCLK VIL VIH IIL IIH Ci Vref Audio outputs VOUT(RMS) (THD + N)/S (THD + N)/S (THD + N)/S (THD + N)/S S/N S/N Timing tr tf tCLK L tCLK H tr tf tHD tSU
PARAMETER input current HIGH clock input capacitance clock input frequency
CONDITIONS Vi = 4.5 V - - - - Vi = 0.5 V Vi = 4.5 V note 2
MIN -10 - 5 - -
TYP -
MAX 10 10
UNIT A pF MHz
Channel left/right inputs input voltage LOW input voltage HIGH input current LOW input current HIGH channel input capacitance; pins 3, 30 reference input voltage; pins 8, 25 0.5 10 10 - - V V A A pF V 4.5 - - 5 -4 0.4
-10 -10 - -
output voltage (RMS value); pins 14, 19; pins 15, 18 THD + Noise; 0 dB THD + Noise; 0 dB THD + Noise; -20 dB THD + Noise; -60 dB signal-to-noise ratio signal-to-noise ratio; "A"-weighting channel separation
notes 2 and 3 f = 1 kHz; notes 3 and 4 20 Hz - 20 kHz; notes 3 and 5 f = 1 kHz; notes 3 and 4 f = 1 kHz; notes 3 and 4 pattern 0101; notes 3 and 7 pattern 0101; notes 3 and 7 f = 1 kHz
0.85 - - - - - - 109 - 101 - - 45 45
1.0 -101 0.0009 -101 0.0009 -88 -48 111 113 115
1.15 -96 0.0016 - - -84 -44 - - -
V dB % dB % dB dB dB dB dB
rise time clock input fall time clock input clock input LOW time clock input HIGH time channel input rise time channel input fall time channel input hold time channel input set-up time
CL = 20 pF CL = 20 pF
5 5 - - 10 10 - -
10 10 - - 15 15 - -
ns ns ns ns ns ns ns ns
CL = 20 pF CL = 20 pF
- - 25 0
September 1991
10
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
Notes to the characteristics 1. The substrate voltage must be lower than or to equal than the lowest supply voltage.
TDA1547
2. Output level tracks linearly with both the clock frequency and the reference voltage (Vref L or Vref R). 3. Device measured in differential mode with external components as shown in Fig.5. 4. Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 1 kHz digital sinewave. Measured over a 20 Hz to 20 kHz bandwidth. 5. Measured with a one-bit data signal generated by the SAA7350 from an 8 fs (352.8 kHz), 20-bit, 20 Hz to 20 kHz digital sinewave. Measured over a 20 Hz to 20 kHz bandwidth. 6. Power supply rejection ratio measured with fripple = 1 kHz and vripple = 100 mV. 7. The specified signal-to-noise ratio includes noise introduced by the application components as shown in Fig.5. TIMING
handbook, full pagewidth
tr
t CLK H VIH
tf
t CLK L
V DDD - 1.0 V CLK 1.0 V V IL
t SU VIH DATA INPUT CHANNEL L, CHANNEL R V IL
t HD
VDDD - 1.0 V DATA STABLE V IL 1.0 V
MCD295
Fig.3 Timing waveform.
September 1991
11
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
APPLICATION INFORMATION
TDA1547
system clock f = 16.9 MHz
system clock f = 16.9 MHz L channel
DIGITAL FILTER 16-bit audio data, f = 44.1 kHz s 8 x upsampling digital filter, Astop > 110 dB 20-bit, f s = 352.8 kHz
SAA7350
1-bit, f s = 8.47 MHz
TDA1547
R channel 24 x upsampling by zero-order hold, 3rd order noise shaping, 1-bit end quantization 1-bit high-performance DAC converter
3rd order analog postfilter, f o = 55 kHz Butterworth response
MCD296
Fig.4 CD-range bitstream reconstruction system (192 fs over-sampling).
September 1991
12
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
handbook, full pagewidth
bitclock SCKI wordclock WSI data left SDI1 data right SDI2 IDF1 = LOW
10
9 DIGITAL FILTER INTERFACE INPUTS 8 1-BIT DAC INTERFACE OUTPUTS 42 DOL X SYS 2 CLK stereo 1-bit data to TDA1547
SONY or NPC 8 x Fs simultaneous mode 20-bit input format
7
43
5 INPUT DATA MODE SELECT
44
DOR
IDF2 = HIGH
4
IDF3 = HIGH
3
SAA7350
10 1 +5V (digital) 10 2 C DOR (IN R) 3 LOGIC AND DRIVERS LOGIC AND DRIVERS 30 31 (IN L) DOL C 32 C 10 -5V (digital) -5V (digital)
4
29
+5V (digital)
10 C
CLK R
5
28
CLK L
10 C
+5V (digital)
6
27
-5V (digital)
1.5 k 7 3.3 k C 8 3.3 k 220 F SWITCHED CAPACITOR NETWORK SWITCHED CAPACITOR NETWORK 26 C 25 C 24 23 220 F 3.3 k
1.5 k 3.3 k
-5V (digital)
-5V (analog)
560
C 9 10
560
-5V (analog)
11
22
12 to analog output stage 13 14
21 to analog output stage 20 19
15 4.7 - 5 V (analog) C RIGHT CHANNEL LEFT CHANNEL 16
18 4.7
TDA1547
17 C
+ 5 V (analog)
Fig.5 Application diagram.
C = 100 nF (chip capacitor)
MCD297
September 1991
13
220 pF 56 pF 100 H 10 k 2.2 nF 10 k 1 k 1.62 k 2.61 k 100 F 47 audio output left
Product specification
TDA1547
Fig.6 Post-filter for 192 fs application (f0 = 55 kHz).
handbook, full pagewidth
September 1991
3.3 k 470 560 pF 3.3 nF 19 3.3 k 33 nF 18 kill 1.5 k
13 k
Philips Semiconductors
220 pF
820 pF
13 k
23
22
21
Dual top-performance bitstream DAC
1-BIT DAC LEFT
de-emphasis
TDA1547
14
56 pF 100 H 10 k 14 10 k 1 k 1.62 k 15 2.2 nF 2.61 k 3.3 k 470 3.3 nF 3.3 k 33 nF 560 pF de-emphasis
1-BIT DAC RIGHT
10
11
12
100 F
47
820 pF
13 k 1.5 k
audio output right
220 pF
kill
13 k
220 pF
MCD298
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
handbook, full pagewidth
- 80
MCD299
0.01
(THD + N) / S (dB)
(THD + N) / S (%)
- 100 level =0 dB
0.001
- 120 10 Hz
100 Hz
1 kHz
10 kHz
f signal
0.0001 100 kHz
Fig.7 (THD + N)/S as a function of signal frequency.
Note: Graph constructed from average measurements values of a small amount of engineering samples. No guarantee for typical values is implied.
MCD300
handbook, halfpage
- 110
(THD + N) / S (dB) - 90
- 70
- 50
- 30
- 10 - 100
- 80
- 60
- 40
- 20 0 signal level (dB)
Fig.8 (THD + N)/S as a function of test signal level.
Note: Graph constructed from average measurement values of a small amount of engineering samples. No guarantee for typical values is implied. September 1991 15
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
TDA1547
MCD301
handbook, full pagewidth
- 115 crosstalk (dB) - 120 R L L R
- 125
- 130
10 Hz
100 Hz
1 kHz
10 kHz f test signal
100 kHz
Fig.9 Inter-channel crosstalk as a function of signal frequency.
Note: Graph constructed from average measurements values of a small amount of engineering samples. No guarantee for typical values is implied.
September 1991
16
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
PACKAGE OUTLINE SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
TDA1547
SOT232-1
D seating plane
ME
A2 A
L
A1 c Z e b 32 17 b1 wM (e 1) MH
pin 1 index E
1
16
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 92-11-17 95-02-04
September 1991
17
Philips Semiconductors
Product specification
Dual top-performance bitstream DAC
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA1547
The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
September 1991
18

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