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TEA2164S
SWITCH MODE POWER SUPPLY PRIMARY CIRCUIT
. . . . . . .
POSITIVE AND NEGATIVE OUTPUT CURRENT UP TO 1.2A AND - 1.7A A TWO LEVEL COLLECTOR CURRENT LIMITATION COMPLETE TURN OFF AFTER LONG DURATION OVERLOADS UNDER AND OVER VOLTAGE LOCK-OUT SOFT START BY PROGRESSIVE CURRENT LIMITATION DOUBLE PULSE SUPPRESSION BURST MODE OPERATION UNDER STANDBY CONDITIONS
DESCRIPTION In a master slave architecture,the TEA2164Scontrol IC achieves the slave function. Primarily designed for TV receivers and monitors applications, this circuit provides an easy synchronization and smart solution for low power stand by operation. Located at the primary side the TEA2164S control IC ensures : - the power supply start-up - the power supply control under stand-by conditions - the process of the regulation signals sent by the master circuit located at the secondary side - direct base drive of the bipolar switching transistor - the protection of the transistor and the power supply under abnormal conditions. For more details, refer to application note AN409. PIN CONNECTIONS
GROUND I COPY LONG OVERLOAD CAPACITOR SUBSTRATE SUBSTRATE PULSE INPUT OSCILLATOR TIMING RESISTOR OSCILLATOR TIMING CAPACITOR 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VCC SUPPLY VOLTAGE OUTPUT STAGE POSITIVE SUPPLY VOLTAGE OUTPUT (BASE CURRENT) SUBSTRATE SUBSTRATE IC(Max.) SENSE
2164S-01.EPS
POWERDIP16 (Plastic Package) ORDER CODE : TEA2164S
LOW FREQUENCY OSCILLATOR CAPACITOR FEEDBACK INPUT IN BURST MODE
January 1998
1/16
TEA2164S
BLOCK DIAGRAM
R1 9 C1 10 Soft Start tON LIMITATION VLF OSCILLATOR Valid Sawtooth Return R Q 13% S IC(Max.) 11 12 IC(M3) IC(Max.) DETECTION IC(M2) IC(M1) 1 VCC 16V Internal VCC VCC MONITORING V13 OUT 14 V+ 15 VCC 16
TEA2164S
1
V+
+ AMP
&
S
Q
IC COPY
&
1
R
Q
DELAY
AMP
& Sawtooth Return RC OSCILLATOR SYNC Positive Pulse Negative Pulse R Q S
VCC < 4.6V REPETITIVE OVERCURRENT PROTECTION
V-
SYNC SWITCH
PULSE SHAPER
8 COSC
7 ROSC
6 IN
5 V-
4
3 C2
2 ICOPY
1 GND
Figure 1 : Simplified Application Diagram
VCC IN
VOUT OUT
TEA2164S
SLAVE I.C.
TEA5170
MASTER I.C.
VREF
PWM
SYNC. INPUT
2/16
2164S-03.EPS
2164S-02.EPS
TEA2164S
ABSOLUTE MAXIMUM RATINGS
Symbol VCC V+ V- VCC - V- V+ - V- Iout+ Iou t- Tj Tstg Parameter Positive Power Supply V16-V1 Positive Power Supply of the Output Stage V15-V1 Negative Power Supply V4, 5, 12, 13-V1 Total Power Supply V16-V4, 5, 12, 13 or V15-V4, 5, 12, 13 Positive Output Current Negative Output Current Junction Temperature Storage Temperature Value 18 18 -5 20 1.5 2 150 - 40, + 150 Unit V V V V A C C
2164S-01.TBL 2164S-03.TBL 2164S-02.TBL
A
THERMAL DATA
Symbol Rth(j-c) Parameter Junction Case Thermal Resistance Value 11 Unit C/W
MAXIMUM POWER DISSIPATION
Ptot (W) 3.5 3.0 2.5 2.0 1.5
2164S-04.EPS
45C/W
1.0 0.5 Tamb (C) 0 50 100
RECOMMANDED OPERATING CONDITIONS
Symbol VCC V- VCC - V- Iout+ Iou t- Fsw Ro Co C1 C2 Vin Toper Positive Power Supply Negative Power Supply (see Figure 2) Total Power Supply Positive Output Current Negative Output Current Switching Frequency Oscillator Resistor Range Oscillator Capacitor Range Starting Oscillator Capacitor Range Repetitive Overload Protection Capacitor Input Pulses Amplitude (peak) (derivated pulses - time constant = 1 s) Operating Ambiant Temperature 30 470 0.1 1 0.5 - 20 -5 Parameter Min. Typ. 10 Max. 14 0 18 1.2 1.7 50 150 2700 4.7 22 1 70 Unit V V V A A khz k pF F F V C
3/16
TEA2164S
Figure 2 : Substrat Biasing
Vsubstrat = Vor Vsubstrat = 0
VV+ IB > 0
12 13 15 12 13 15
V+ IB > 0 IB > 0 IB > 0
TEA2164S
1 4 5
14
TEA2164S
IB < 0
1 4 5
14
IB < 0
IB < 0
IB < 0
ELECTRICAL OPERATING CHARACTERISTICS Tamb = 25oC, VCC = 10V, VCC- = 0V, potentials referenced to ground (Pin 1) (unless otherwise specified)
Symbol POWER SUPPLY VCC (start) VCC (stop) VCC Vccmax Iccstart Starting Voltage (VCC increasing) Stopping Voltage (VCC decreasing) Hysteresis (V CC start - VCC stop) Overvoltage Lock-out Starting Positive Supply Current 8 5 2 14.8 0.5 9 6.2 2.8 15.5 0.8 9.6 7.4 3.5 16.2 1.5 V V V V mA Parameter Min. Typ. Max. Unit
CURRENT LIMITATION AND PROTECTION (Pin 11) VCM1 Pulse by Pulse Current Limitation Threshold (see Note) TEA2164SL (Low range) TEA2164SH (high range) Current Monitoring 2nd Threshold VCM = VCM2 - VCM1 (L or H) -1 -0.875 1200 300 -0.925 -0.775 1350 500 -0.825 -0.700 1500 700 V V mV mV
VCM2 VCM
REPETITIVE OVERCURRENT PROTECTION VCM3 VCM3 - VCM1 VC2 I3 disch I3 ch. Repetitive Overcurrent Threshold (Pin 11) VCM3 - VCM1 (L or H) Lock-out Voltage on Pin 3 Capacitor C2 Discharge Current (synchronized mode) Capacitor C2 Charge Current -1.1 -0.16 2.4 10 50 -0.9 0.05 3 20 80 -0.7 0.16 3.6 30 110 V V V A A s %
OSCILLATOR, MAX DUTY CYCLE, SYNCHRONIZATION To Ton(max) Tsyn TO OUTPUT STAGE I14/I 2 IBON Ic Copy Current Gain Base Current Starting Pulse 1000 300 mA
2164S-04.TBL
Oscillator Initial Accuracy (RT = 50k, CT = 1nF) Maximum Duty Cycle (Tsyn = 1.05 To) Synchronization Window
19.3 60 1.0
21 70
22.7 85 1.5
VERY LOW FREQUENCY OSCILLATOR Burst Duty Cycle 13 %
Note : For the best accuracy of VCM1 value the TEA2164S is marked as follows : TEA2164SL (low range) or TEA2164SH (high range).
4/16
2164S-05.EPS
V-
Capacitive Coupling
TEA2164S
I - FIELD OF APPLICATION The TEA2164S control circuit has been designed primarily for discontinuous mode flyback built with a master-slave architecture, whatever the field of application. But due to its capability to synchronize the transistor switching-off with an external signal (line flyback) and due to an adaptedburst-mode operation for a low power stand-by operation, the TEA2164 offers a smart solution for monitors and TV sets applications. Power supply main features : - maximum output power 140W (transistor forced gain : 3.5) Figure 3 : Master Slave Power Supply Architecture
AUDIO OUTPUT STAGE R Muting Control
- stand-by mode output power (1W Psb 6W ; efficiency > 50%) - operating frequency up to 50kHz - power-switch : bipolar transistor Adapted master-circuit : - Monitor application TEA5170 - Standard TV application TEA2028B TEA2029C TEA2128 TEA5170 - Digital TV application TEA5170 (TEA2028B, TEA2029C and TEA2128 are deflection processors with built-in PWM generator).
P1 Mains Input C P2 VOLTAGE REGULATOR Synchronization SCANNING DEVICE
Remote Standby
Remote Standby
VCC
TEA2164S
TEA5170
P
INFRA-RED RECEIVER
P1 : Output voltage adjustment in normal mode P2 : Output voltage adjustment in standby
Power primary ground Second ground (isolated from mains)
5/16
2164S-06.EPS
TEA2164S
II - GENERAL DESCRIPTION In a master slave architecture,the TEA2164SControl IC, located at the primary side of an off line power supplyachievesthe slavefunction; whereas the master circuit is located at the secondary side. The link between both circuits is realizedby a small pulse transformer (Figure 4). In the operation of the master-slave architecture, four majors cases must be considered : - normal operating - stand-by mode - power supply start-up - abnormal conditions : off load, short circuit, ... II.1 - Normal Operating (master slave mode) In this configuration,the master circuit generates a pulse width modulatedsignal issued from the monitoring of the output voltage which needs the best accuracy (in TV applications : the horizontal deflectionstage supply voltage). Themaster circuit power supply can be supplied by another output. Figure 4 : System Description Waveforms
VCC(START)
TEA2164S VCC Voltage
The PWM signal are sent towards the primary side through small differentiating transformer. For the TEA2164Spositive pulses are transistorswitchingon commands ; and negative pulses are transistor switching-off commands (Figure 5). In this configuration, only by synchronizing the master oscillator, the switching transistor may be synchronized with an external signal. II.2 - Stand-by Mode In this configuration the master circuit no longer sends PWM signals, the structure is not synchronized ; and the TEA2164Soperates in burst mode. The average power consumption at the secondary side may be very low 1W P 6W (as it is consumed in TV set during stand by). By action on the maximum duty cycle control, a primary loop maintains a semi-regulation of the output voltages.Voltage on feed-backis applied on Pin 9. BurstperiodisexternallyprogrammedbycapacitorC1.
VCC(STOP) 0 t t BURST
Collector Current Envelop
0
B
B
b
b
b
b
t
Output Voltage
0
TEA5170 Output Voltage Envelop
t
0 1 0 Start-up Standby
t
1 P Supply Voltage 2 Standby
tDELAY 2 t1 Normal Operation t2 t Standby
2164S-07.EPS
tBURST : burst period t DELAY : time constant generated by P
B : burst envelop (out of regulation) b : burst envelop (with standby regulation)
t1, t2 : commands issued by P
6/16
TEA2164S
II - GENERAL DESCRIPTION (continued) Figure 5 : Master Slave Mode Waveforms
Sync. Pulses
Synchronization PWM Signal
SLAVE CIRCUIT
MASTER CIRCUIT
Pulse Input
Figure 6 : Burst Mode Waveforms
Collector Current Envelop 0 4V P2 C1 10 9 0 Tb Voltage (Pin 10) Soft Start
t
1V t
TEA2164S
ton T Tb Tb
Max.
3.3 - 1.6 (V9) C1 3.3 106 (C in Farad)
Output Voltage 0 t
2164S-09.EPS
0.13
II.3 - Power Supply Start-up After the mains have been switched-on, the VCC storage capacitor of the TEA2164S is charged through a high value resistor connected to the rectified high voltage. When Vcc reaches VCC start threshold (9V typ), the TEA2164 starts operating in burst mode. Since available output power is low in burst mode the output power consumption must remain low before complete setting-up of output voltage. In TV application it can be achieved by maintaining the TV in stand-by mode during start-up (Figure 7).
7/16
2164S-08.EPS
Base Current
TEA2164S
II - GENERAL DESCRIPTION (continued) Figure 7 : Power Supply Start-up
VCC(START) TEA2164S VCC Voltage 0 Collector Current Envelop 0 Tch
VCC(STOP) t tBURST
t B T1 B b b Regulated Standby b b
Tch 1s (typ.) T1 0.3s (typ.)
TSTART-UP = Tch + T1 T1 : necessary time for voltage setting-up
II.4 - Abnormal conditions : safety functions
Overvoltage Protection When VCC exceeds VCC max, an internal flip-flop stops output conduction signals. The circuit will start again after the capacitor C1 discharge ; it means : after loss of synchronization or after VCC stop crossing (Figure 8). In flyback converters, this function protects the power supply against output voltage runaway. Under Voltage Lock-out The TEA2164S control circuit stops operating when VCC goes under VCC stop. Power Limitation, Current Protection, Long Duration Overload Protection - Output power limitation : by a pulse by pulse collector current limitation the TEA2164S limits the maximum output power. VCM1 is the corresponding voltage threshold, its detection is memorized up to the next period. - Current protection (transistor protection) Under particular conditions a hard overload or short circuit may induce a flux runaway in spite of the current limitation (VCM1). The TEA2164S control circuit features a second
current protection, VCM2. When this threshold is reached an internal flip-flop memorizes it and output conduction signals are inhibited. The circuit will send base drives again after capacitor C1 discharge (Figure 8). - Long duration overload protection : (Figure 9) An overload is detected when the sense-voltage on Pin 11 reaches VCM3 before a negative pulse has been applied to Pin 6. In this case the capacitor C2 (connected to Pin 3) is charged with I3 ch up to the end of the period and discharged with I3 disch until a next VCM3 detector. By this way in case of long duration overload, the capacitor keeps charging at each period and its voltage encreases gradually. When the voltage on Pin 3 exceeds VC2, the TEA2164S control circuit stops sending base drives and memorizes this event. No restart is allowed as long as Vpin 3 is higher than VC2 and VCC higher than 4.8V.
* Remark : - The harder is the overload the faster is the protection - The capacitor keeps charging between two burst after VCM2 detection.
8/16
2164S-10.EPS
TEA2164S
II - GENERAL DESCRIPTION (continued) Figure 8 : Overvoltages Lock-out
VCC > VCC(Max.) IC > ICM2 1 : discharge S Q R S OUTPUT FLIP-FLOP R
R
Synchro "off"
Figure 9 : Long Duration Overload Monitoring Circuit
I3 ch. + I3 disch. Q C2
3
S R
1 : VCM3 detection before negative pulse occurence sawtooth return
I3 disch.
VC2 VCC < 4.8V
S R Q
2164S-11.EPS
I3 dischr. = 0 in burst mode
Figure 10 : Long Duration Overload Detection
Collector Current Envelop
ICM1
0
Capacitor C2 Voltage 0 TEA2164S VCC Voltage
VC2
0 Overload
9/16
2164S-13.EPS
VCC(START) VCC(STOP)
2164S-11.EPS
BURST OSCILLATOR
VCC STOP CROSSING
TEA2164S
II - GENERAL DESCRIPTION (continued) Figure 11 : Repetitive Over-current Protection
Collector Current Envelop 0 ICM2
t Tburst
Capacitor C2 Voltage
VC2
2164S-14.EPS
t 0
III - SWITCHING OSCILLATOR AND SYNCHRONIZATION III.1. Switching oscillator When the TEA2164S control circuit operates in burst mode, the switching frequency is fixed by the free frequency oscillator. The period is determined by two external components CO and RO. III.2. Synchronization When the master-circuit starts to send pulses both oscillators are not synchonuous. Figure 12 : Free Frequency Running
5V CURRENT MIRROR 15k IO 3.2V IO 0 Tcharge RR 1k
7 8
In order to avoid any erratic conduction of the power transistor, the first synchronizationpulse will arrive simultanously with the sawtooth return of the TEA2164S oscillator. To get synchronization the free frequency must be higher than the synchronization frequency. TO < Tsync. < 1.50 TO
TR
V8 2.74V 1.66V
TR
7.5k TR
TO
RO
CO
9.1k
TO ~ Tcharge + TR TO ~ 0.4 ROCO + 0.47 COR R RR ~ 1000 CO in Farad, R O in Ohms Q conductingin burst mode
Q
2164S-15.EPS
13.4k
10/16
TEA2164S
III - SWITCHING OSCILLATOR AND SYNCHRONIZATION (continued) Figure 13 : Synchronization Pulse Shaper and Synchronization
2 VD MONO
6
R 2 VD + 0.4V MONO
Q
To Output Flip-Flop Reset
OSCILLATOR SECTION Pulse Transformer 9.1k Sawtooth Return
S
Q
Synchro "OFF" VD ~ 0.65V
Figure 14 : Operation after Synchronization
1 - NORMAL OPERATION Synchro Pulse Synchro Pulse 2 - NEGATIVE PULSE MISSING
T
3.3V
V8
2.5V
V8
3.3V
1.66V
2.66V 0V
1.66V
Base Current T : Synchronization Window
Base Current
Transistor turn-off is ensured by VCM1 current limitation crossing or by an internal t ON(Max.) limitation set by a 2.5V threshold.
4 - fsynchro < 0.65 fO Synchro Pulse
3 - ERRATIC POSITIVE PULSES Synchro Pulse
P1
P2
T
P1
3.3V
V8
1.66V
2.66V
V8
1.66V 0V
0V
Base Current
S1
Base Current
P1 and P2 are masked dur to the synchronization window.
Signal S1 triggers burst oscillator capacitor discharge. The TEA2164S restarts in burst mode.
11/16
2164S-17.EPS
2164S-16.EPS
13.4k
Q
TEA2164S
IV - MAXIMUM DUTY CYCLE LIMITATION Burst mode : The maximum duty cycle is controlled by the voltage on Pin 9 (Figure 15). Synchronized mode : Normally the maximum duty cycle is set by the master circuit. However the maximum conducting time will never exceed the value given by the comparison of the oscillator wave-form with the 2.5V internal threshold. V - OUTPUT STAGE TEA2164S output stage has been designed to drive switching bipolar transistor. - Each base drive begins with a positive pulse IBON that realizes an efficient transistor turn-on. Figure 15 : Maximum Duty Cycle Limitation
- After the starting pulse I BON, the base current is proportional to the collector current. The current gain is easily fixed by a resistor RB (Figure 16). - A fast and safe transistor turn-off is realized by a fast positive base current cut-off and by applying a negative base drive which draws stored carriers. Atypical 0.7s delay prevents from cross-conduction of positive and negative output stages. Remark : In order to reduce power dissipation on the positive output stage with the low gain transistors, for high base currents the positive output stage operates in saturated mode (Figure 17). This can be achieved by using a resistor between VCC and V+.
Synchro "ON" 6 IO
9
S V1 2.5V R OUTPUT FLIP-FLOP
e
OSC V1 = 4.5V - 1.25 x (e) ; IO = 2.5V RO
2164S-18.EPS
Figure 16 : Output Stage Architecture and Base Drive
IB
16 15
I BON
t
CURRENT MIRROR IB
14
I Cmax
IC
Virtual Ground V2 Pins 4-5-12-13 RB IC
GF = t
RS
IC IB
@ GF IC IB
RS = RB 1000 x R S
V CM1
2164S-19.EPS
I Cmax
=
12/16
TEA2164S
V - OUTPUT STAGE (continued) Figure 17 : Power Supply Start-up and Normal Operation
TEA2164S VCC Voltage Collector Current Envelop
0
VCC(START) VCC(STOP) Tb Burst normal duration t
1 2
Output Voltage
0 1 2
t
t Power Supply Start-up Normal Mode
VI - MONITOR APPLICATIONS In most of monitor applications, the power supply must start-up under full load conditions and the stand -by mode is no longer useful. The energy of the starting burst must be high enough to ensure start-up, then the capacitor C1 must be higher in these applications than on TV application (typ. : 1F).
13/16
2164S-20.EPS
Master Circuit 0 Output
1k
470k 1 1k 2 +25V VCR Switch 1.5k 1k 22nF 1nF 14 8 9 21 47nF 22 390 BA157 2.2 BY218 470F 10kW 100nF 220 F
7
21 LINE YOKE
1k
110k
12k
22nF
10 2.2nF 47F 150pF BU508A 470 1.8k 220 18 503 kHz 220 19 0.27 3.9k 22 4.7F 7 330 20
5.6kW
3 x 1N404 + VCC 17 BA159 10F 10 220 4 16 23 13
Horizontal Phase Adjust
10
12
13
3
11
2
6
14
2H
2.2F 220 100
3.32k (1%)
TEA2164S
3.3nF
390
330
1k
100nF
6.8k
100nF
220nF
8.2k
100nF
4.7nF
14/16
OREGA G.4173.04
TEA2164S
FUSE 1.6A BY218 +135V / 0.6A 100F 220pF +200V 100k 20 2N1711 6 680 13V + VCC BA157 2.2 9 19 1000F BY218 27 SMPS Output Voltage Adjust 220pF 33k 150k
220VAC MAINS INPUT 3 13
4 x 1N4007
EHT TRANSFORMER
300k
2 x 47F (385V)
100k (2W)
LINE FLYBACK +24V
6.8
500H
1.2nF
220mF + VCC 470k
8
7
9
5
4
1
15
16
0.47F
4.7F
ESM 740
BA157
FRAME YOKE 120H 60W
1N4444
1nF 1.5nF
6 820 3.3k 2 220 1 820 3 2.7M 3.3k 33
Frame Amplitude Adjust 4.7
TEA2029C
Primary Ground (connected to mains) Secondary ground (isolated from mains)
15nF
100
6.8k 220 5 470nF 1k 82k
+24V
24
5.6kW 15kW
15 1N4148
27
26
25
12
11
28
220k 200V 2.2k 10k Frame Phase Adjust
+ VCC
COMPLETE APPLICATION DIAGRAM (SMPS + DEFLECTION) (with stand-by function)
AGC PULSE
MUTE OUT & 50/60Hz IDENTIFICATION
VIDEO INPUT
SUPER SANDCASTLE LINE OUTPUT FLYBACK
E/W CORRECTION
2164S-21.EPS
4 x 1N4007 3 100F (250V) P1 100k 100k 470F (25V) 2.2k 7.5V BY218-100 5.6 (1W) 7 BC550C 22 25V BY218-100 21 1000F (40V) 560 pF 75k 16 17 220F 25V 1000F (25V) 10k Stand-by Control 20 6 4.7 (2W) BA157 9 14 19 PLR811 13
G4453-02 BY218-600 135V
VIN = 220 VAC 20% 120k (2W)
150F (385V)
1nF
P2 22k
68k
100nF
10
9
4
5
12
13
15
TEA2164S
18 BZX85C-3V0 47F SGSF344 10F 16V 2 4 6 5 2 2.2F 14
7
8
6
1
3
11
100k 1% 1N4148 BA159 470 (8W)
4.7F
560 pF 2%
16V 3
TEA5170
7 560 pF 8 1 47nF
STAND-ALONE 32kHz POWER SUPPLY ELECTRICAL DIAGRAM
330 330
1nF 0.24 (1W) 2.7nF 1kV
270 100
1N4148
150pF
Sync. Input 100k 6.8k
POUT : 120W
f : 32kHz Pulse Transformer
TEA2164S
15/16
2164S-22.EPS
TEA2164S
PACKAGE MECHANICAL DATA 16 PINS - PLASTIC POWERDIP
Dimensions a1 B b b1 D E e e3 F I L Z
Min. 0.51 0.85 0.38
Millimeters Typ.
Max. 1.40
Min. 0.020 0.033 0.015
Inches Typ.
Max. 0.055
0.50 0.50 20.0 8.80 2.54 17.78 7.10 5.10 3.30 1.27
0.020 0.020 0.787 0.346 0.100 0.700
DIP16PW.TBL
0.280 0.201 0.130 0.050
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This pu blication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1998 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
16/16
PM-DIP16.EPS

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