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W83194BR-97
200MHZ CLOCK FOR CAMINO CHIPSET
1.0 GENERAL DESCRIPTION
The W83194BR-97 is a Clock Synthesizer for Intel Camino 820 chipset. W83194BR-97 provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 sets of different frequencies of CPU, PCI, 3V66, IOAPIC clocks or stepless frequecies programming by M/N value via 2 I C registers. All clocks are externally selectable with smooth transitions. The W83194BR-97 provides I C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.5% and 0.25% center type spread spectrum to reduce EMI. The W83194BR-97 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 pF loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 pF loads as maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate.
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2.0 PRODUCT FEATURES
* * * * * * * * * * * * * * * * * 2 CPU clock outputs One CPU/2 output as reference input to DRCG 3 3V66 clock outputs 3 IOAPIC clock outputs 8 PCI synchronous clocks. Optional single or mixed supply: (VddQ2 = VddQ3 = 3.3V or VddQ3=3.3V, VddQ2=2.5V) CPU to 3V66 offset 0 to 1.5 ns 3V66 to PCI offset 1.5 to 4.0 ns Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200MHz 2 Stepless programmable frequencies by I C register9 ~ register12 2 2 I C 2-Wire serial interface and I C read back 0.5% and 0.75% center type spread spectrum Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) 48 MHz pins for USB 24 MHz for super I/O 48-pin SSOP package
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Publication Release Date: Dec. 1999 Revision 0.35
W83194BR-97
PRELIMINARY
3.0 PIN CONFIGURATION
VSSR REF0 REF1/*SEL24_48# VDDR Xin Xout VSSP PCICLK_F/ *FS0 PCICLK1/ *FS1 VDDP PCICLK2/ *FS2 PCICLK3/ *FS3 VSSPCI PCICLK4 PCICLK5 VDDP PCICLK6 PCICLK7 VSSPCI PCICLK8 PCICLK9 PCICLK10 VDDPCI PD#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VddA IOAPIC0 IOAPIC1 VSSA IOAPIC2 VDDC/2 CPU/2 VSSC/2 CPUCLK0 VDDCPU CPUCLK1 CPUCLK2 VSSCPU VDD66 3V66-0 3V66-1 3V66-2 VSS66 *SDATA *SDCLK VDD48 48MHz/ *FS4 24_48MHz/FREQ_APIC* VSS48
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Publication Release Date: Dec. 1999 Revision 0.35
W83194BR-97
PRELIMINARY
4.0 FREQUENCY SELECTION BY HARDWARE
FS4 FS3 FS2 FS1 FS0
CPU (MHz) 103.00 105.00 100.30 100.90 107.00 109.00 112.00 114.00 116.10 118.00 133.30 120.00 122.00 125.10 128.20 130.00 133.00 133.90 138.00 142.00 146.00 150.00 153.00 156.00 159.10 162.00 165.00 168.00 171.00 174.00 177.00 180.00
CPU/2 3V66/ CPU 51.50 52.50 50.15 50.45 53.50 54.50 56.00 57.00 58.05 59.00 66.65 60.00 61.00 62.55 64.10 65.00 66.50 66.95 69.00 71.00 73.00 75.00 76.50 78.00 79.55 81.00 82.50 84.00 85.50 87.00 88.50 90.00 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.50 0.67 0.67 0.67 0.67 0.67 0.67 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50
3V66 (MHz) 68.67 70.00 66.87 67.27 71.33 72.67 74.67 76.00 77.40 78.67 66.65 80.00 81.33 83.40 85.47 86.67 88.67 66.95 69.00 71.00 73.00 75.00 76.50 78.00 79.55 81.00 82.50 84.00 85.50 87.00 88.50 90.00
PCI (MHz) 34.33 35.00 33.43 33.63 35.67 36.33 37.33 38.00 38.70 39.33 33.33 40.00 40.67 41.70 42.73 43.33 44.33 33.48 34.50 35.50 36.50 37.50 38.25 39.00 39.78 40.50 41.25 42.00 42.75 43.50 44.25 45.00
IOAPIC (MHz) FREQ_APIC=1
IOAPIC (MHz) FREQ_APIC=0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
17.17 17.50 16.72 16.82 17.83 18.17 18.67 19.00 19.35 19.67 16.66 20.00 20.33 20.85 21.37 21.67 22.17 16.74 17.25 17.75 18.25 18.75 19.13 19.50 19.89 20.25 20.63 21.00 21.38 21.75 22.13 22.50
34.33 35.00 33.43 33.63 35.67 36.33 37.33 38.00 38.70 39.33 33.33 40.00 40.67 41.70 42.73 43.33 44.33 33.48 34.50 35.50 36.50 37.50 38.25 39.00 39.78 40.50 41.25 42.00 42.75 43.50 44.25 45.00
5.0 SERIAL CONTROL REGISTERS
Publication Release Date: Dec. 1999 Revision 0.35
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W83194BR-97
PRELIMINARY
The Pin column lists the affected pin number and the @PowerUp column gives the state at true power up. Registers are set to the values shown only on true power up. "Command Code" byte and "Byte Count" byte must be sent following the acknowledge of the Address Byte. Although the data (bits) in these two bytes are considered "don't care", they must be sent and will be acknowledge. After that, the below described sequence (Register 0, Register 1, Register 2, ....) will be valid and acknowledged.
Frequency Selection BY I2C
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0
CPU CPU/2 3V66/ (MHz) CPU 103.00 105.00 100.30 100.90 107.00 109.00 112.00 114.00 116.10 118.00 133.30 120.00 122.00 125.10 128.20 130.00 133.00 133.90 138.00 142.00 146.00 150.00 153.00 156.00 159.10 162.00 165.00 168.00 171.00 174.00 177.00 180.00 51.50 52.50 50.15 50.45 53.50 54.50 56.00 57.00 58.05 59.00 66.65 60.00 61.00 62.55 64.10 65.00 66.50 66.95 69.00 71.00 73.00 75.00 76.50 78.00 79.55 81.00 82.50 84.00 85.50 87.00 88.50 90.00 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.67 0.50 0.67 0.67 0.67 0.67 0.67 0.67 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50
3V66 (MHz) 68.67 70.00 66.87 67.27 71.33 72.67 74.67 76.00 77.40 78.67 66.65 80.00 81.33 83.40 85.47 86.67 88.67 66.95 69.00 71.00 73.00 75.00 76.50 78.00 79.55 81.00 82.50 84.00 85.50 87.00 88.50 90.00 3V66 (MHz)
PCI (MHz) 34.33 35.00 33.43 33.63 35.67 36.33 37.33 38.00 38.70 39.33 33.33 40.00 40.67 41.70 42.73 43.33 44.33 33.48 34.50 35.50 36.50 37.50 38.25 39.00 39.78 40.50 41.25 42.00 42.75 43.50 44.25 45.00 PCI (MHz)
IOAPIC (MHz) FREQ_APIC=1
IOAPIC (MHz) FREQ_APIC=0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
17.17 17.50 16.72 16.82 17.83 18.17 18.67 19.00 19.35 19.67 16.66 20.00 20.33 20.85 21.37 21.67 22.17 16.74 17.25 17.75 18.25 18.75 19.13 19.50 19.89 20.25 20.63 21.00 21.38 21.75 22.13 22.50
IOAPIC (MHz) FREQ_APIC=1
34.33 35.00 33.43 33.63 35.67 36.33 37.33 38.00 38.70 39.33 33.33 40.00 40.67 41.70 42.73 43.33 44.33 33.48 34.50 35.50 36.50 37.50 38.25 39.00 39.78 40.50 41.25 42.00 42.75 43.50 44.25 45.00
IOAPIC (MHz) FREQ_APIC=0
SSEL5 SSEL4 SSEL3 SSEL2 SSEL1 SSEL0
CPU CPU/2 3V66/ (MHz) CPU
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Publication Release Date: Dec. 1999 Revision 0.35
W83194BR-97
PRELIMINARY
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 134.00 135.00 136.00 137.00 139.00 140.00 143.00 144.00 145.00 147.00 148.00 149.00 152.00 154.00 155.00 157.00 158.00 160.00 163.00 164.00 166.00 167.00 169.00 170.00 172.00 173.00 175.00 181.00 183.00 185.00 190.00 67.00 67.50 68.00 68.50 69.50 70.00 71.50 72.00 72.50 73.50 74.00 74.50 76.00 77.00 77.50 78.50 79.00 80.00 81.50 82.00 83.00 83.50 84.50 85.00 86.00 86.50 87.50 90.50 91.50 92.50 95.00 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 0.50 67.00 67.50 68.00 68.50 69.50 70.00 71.50 72.00 72.50 73.50 74.00 74.50 76.00 77.00 77.50 78.50 79.00 80.00 81.50 82.00 83.00 83.50 84.50 85.00 86.00 86.50 87.50 90.50 91.50 92.50 95.00 100.00 33.50 33.75 34.00 34.25 34.75 35.00 35.75 36.00 36.25 36.75 37.00 37.25 38.00 38.50 38.75 39.25 39.50 40.00 40.75 41.00 41.50 41.75 42.25 42.50 43.00 43.25 43.75 45.25 45.75 46.25 47.50 50.00 16.75 16.88 17.00 17.13 17.38 17.50 17.88 18.00 18.13 18.38 18.50 18.63 19.00 19.25 19.38 19.63 19.75 20.00 20.38 20.50 20.75 20.88 21.13 21.25 21.50 21.63 21.88 22.63 22.88 23.13 23.75 25.00 33.50 33.75 34.00 34.25 34.75 35.00 35.75 36.00 36.25 36.75 37.00 37.25 38.00 38.50 38.75 39.25 39.50 40.00 40.75 41.00 41.50 41.75 42.25 42.50 43.00 43.25 43.75 45.25 45.75 46.25 47.50 50.00
200.00 100.00 0.50
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Publication Release Date: Dec. 1999 Revision 0.35
W83194BR-97
PRELIMINARY 5.1 Register 0: CPU Frequency Select Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Description 2 SSEL3 ( Frequency table selection by software via I C) 2 SSEL2 ( Frequency table selection by software via I C) 2 SSEL1 ( Frequency table selection by software via I C) 2 SSEL0 ( Frequency table selection by software via I C) 0 = Selection by hardware 2 1 = Selection by software I C - Bit (0,2, 6:4) 2 SSEL4 (Frequency table selection by software via I C ) 0 = Normal 1 = Spread Spectrum enabled 2 SSEL5 ( Frequency table selection by software via I C)
5.2 Register 1 : CPU Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 40 38 37 42 47 46 2 3 Description CPUCLK0(Active / Inactive) CPUCLK1(Active / Inactive) CPUCLK2(Active / Inactive) CPU/2(Active / Inactive) IOAPIC0 (Active / Inactive) IOAPIC1 (Active / Inactive) REF1 (Active / Inactive) REF0 (Active / Inactive)
5.3 Register 2: PCI Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin 18 17 15 14 12 11 9 8 PCICLK7 (Active / Inactive) PCICLK6 (Active / Inactive) PCICLK5 (Active / Inactive) PCICLK4 (Active / Inactive) PCICLK3 (Active / Inactive) PCICLK2 (Active / Inactive) PCICLK1 (Active / Inactive) PCICLK_F (Active / Inactive) Description
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Publication Release Date: Dec. 1999 Revision 0.35
W83194BR-97
PRELIMINARY 5.4 Register 3: 3V66 Clock Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 X 0 0 X X Pin 34 33 32 3V66_0(Active / Inactive) 3V66_1(Active / Inactive) 3V66_2(Active / Inactive) FS1# 0 = 0.25% Center type Spread Spectrum Modulation 1 =0.5% Center type Spread Spectrum Modulation 0 = Running 1 = Tristate all outputs FS3# FS2# Description
5.5 Register 4: PCI Clock Additional Register (1 = Active, 0 = Inactive)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 X 1 1 1 1 X Pin 26 27 22 21 20 24_48MHz(Active / Inactive) 48MHz(Active / Inactive) FS0# PCICLK10 (Active / Inactive) PCICLK9 (Active / Inactive) PCICLK8 (Active / Inactive) Reserve FS4# Description
5.6 Register 5: Skew Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 1 1 1 1 Pin Description Skew2 (CPU to 3V66 skew program bit) Skew1 (CPU to 3V66 skew program bit) Skew0 (CPU to 3V66 skew program bit) Reserve Reserve Reserve Reserve Reserve
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Publication Release Date: Dec. 1999 Revision 0.35
W83194BR-97
PRELIMINARY 5.7 Register 6: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 0 0 1 0 0 0 0 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Description
5.8 Register 7: Winbond Chip ID Register (Read Only)
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 1 0 0 0 0 1 Pin Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Chip ID Winbond Version ID Winbond Version ID Winbond Version ID Winbond Version ID Description
5.9 Register 8: Watchdog Timer Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin Enable Count Description 1 = start timer 0 = stop timer Second timeout status (READ ONLY) Second count 5 Second count 4 Second count 3 Second count 2 Second count 1 Second count 0
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Publication Release Date: Dec. 1999 Revision 0.35
W83194BR-97
PRELIMINARY 5.10 Register 9: M/N Program Register and 3V66 Divisor
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin N value bit 8 3V66 divisor 3V66 divisor M value bit 4 M value bit 3 M value bit 2 M value bit 1 M value bit 0 00: CPU/2 ; 01: CPU/1.5 10: CPU/1 ; 11: CPU/3 Description
5.11 Register 10: M/N Program Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 0 0 0 0 0 0 0 0 Pin N value bit 7 N value bit 6 N value bit 5 N value bit 4 N value bit 3 N value bit 2 N value bit 1 N value bit 0 Description
5.12 Register 11: Divisor Register
Bit 7 6 5 4 3 2 1 0 @PowerUp 1 1 1 1 1 1 1 1 Pin Description Spread spectrum up count[0:3] Spread spectrum up count[0:3] Spread spectrum up count[0:3] Spread spectrum up count[0:3] Spread spectrum down count[0:3] Spread spectrum down count[0:3] Spread spectrum down count[0:3] Spread spectrum down count[0:3]
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Publication Release Date: Dec. 1999 Revision 0.35
W83194BR-97
PRELIMINARY 5.12 Register 12 Divisor Register
Bit 7 @PowerUp 0 Pin 0: use frequency table 1: use M/N register 9~12 to program frequency The equation is CPU freq. = 14.318MHz * (N+4)/ 2*M 6 5 4 3 2 1 0 1 1 1 1 1 1 1 Reserve Reserve Reserve Reserve Reserve Reserve Reserve Description
6.0 ORDERING INFORMATION
Part Number W83194BR-97 Package Type 48 PIN SSOP Production Flow Commercial, 0C to +70C
7.0 HOW TO READ THE TOP MARKING
W83194BR-97 28051234 814GBB
1st line: Winbond logo and the type number: W83194BR-97 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 G B B 814: packages made in '98, week 14 G: assembly house ID; A means ASE, S means SPIL, G means GR B: Winbond internal use code B: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: Dec. 1999 Revision 0.35
W83194BR-97
PRELIMINARY 8.0 PACKAGE DRAWING AND DIMENSIONS
Headquarters
No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, Taiwan TEL: 886-35-770066 FAX: 886-35-789467 www: http://www.winbond.com.tw/
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II 123 Hoi Bun Rd., Kwun Tong Kowloon, Hong Kong TEL: 852-27516023-7 FAX: 852-27552064
Winbond Electronics (North America) Corp.
2730 Orchard Parkway San Jose, CA 95134 U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd. Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502 TLX: 16485 WINTPE
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale.
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Publication Release Date: Dec. 1999 Revision 0.35

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