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| 1. SCOPE 1.1 Scope. This drawing describes a commercially available microcircuit with radiation tolerance. 1.1.1 **RTA** this drawing contains a radiation tolerance assured item and/or processes. All changes to items or processes and all proposed substitutions of items identified as RTA on the drawing, must be evaluated and approved by the Radiation Tolerance Assured Supply And Support Center (RTASSC), Directorate For Applied Technology, Test And Simulation (DATTS), White Sands Missile Range, (WSMR). 1.1.2 Only the item described on this drawing when procured from the vendor(s) listed hereon is approved for use in the application(s) specified hereon. A substitute item shall not be used without prior approval by the RTASSC. 1.2 Part or Identification Number (PIN). The complete part number shall be as shown in the following example. W98 M9640 | | | Drawing number 01 | | | Device Type E | | | Device Class U | | | Case Outline X | | | Lead Finish 1.3 Drawing Number. The drawing number consists of three pieces of information as follows: W98 M 9640 = Indicates White Sands drawing, year 1998. = Radiation Tolerance Designator (3000 rads(Si)). = Semiconductor discrete device, P-channel power MOS field effect transistor 1.4 Device Type. The device type shall identify the circuit function as follows: Device Type 01 Generic # 9640 Circuit Function Switchin on/off time(typ.); Frequency(Test Condition) P-channel power MOSFET 57 ns / 77 ns; 1.0 MHz 1.5 Device class designator. The device class designator is a single letter identifying the product assurance level as follows: Device class E Device requirements documentation Vendor self-certification to the requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A 1.6 Case Outline. The case outline is as designated in MIL-STD-1835 as follows: Outline letter U Terminals 4 Package Style TO-263AB, see Figure 1, Surface Mount 1.7 Lead Finish. The lead finish is as specified in the purchase order (X indicates acceptable lead finishes per manufacturers specification). 1.8 Operating Temperature. The operating temperature range of this device is -55C to +150C. Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 2 2.0 Salient characteristics. 2.1 Maximum operating conditions. The maximum operating conditions shall be as specified in Table I. 2..2 Electrical performance characteristics: 2.2.1 The electrical performance characteristics shall be as specified in Table II. 2.2.2 The Typical characteristics diagrams shall be as specified in diagrams in Figure 2. 2.2.3 Radiation Tolerance Assurance(RTA) data for electrical performance characteristics shall be as specified in Table III. 2.3 2.4 Design and construction. Microcircuits supplied to this WSD shall be as specified herein and on Figure 1. Marking. Microcircuits supplied to this WSD shall be marked with the manufacturer's standard commercial PIN. 3.0 Regulatory requirements. This section is not utilized in this WSD. TABLE I. Maximum operating conditions. Continuous drain current ID, VGS @ 10 V, TC = 25C TC = 100C Pulse drain current IDM 1/ Power dissipation PD @ TC = 25C (PCB Mount) Linear derating factor (PCB Mount) Gate-to-Source voltage VGS Single pulse avalanche energy EAS Avalanche current IAR Repetitive avalanche energy EAS Peak diode recovery dv/dt Operating junction temperature TJ Storage temperature TSTG Soldering temperature for 10 seconds For notes 1/, 3/ and 2/, see footnotes of TABLE II. 2/ 1/ 1/ 3/ -11 A -6.8 A -44 A 125 W 3.0 W 1.0 W/C 0.025 W/C 20 V 700 mJ -11 A 13 mJ 5.0 V/ns -55C to +150C -55C to +150C 300C (1.6mm from case) Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 3 TABLE II. Electrical Performance Characteristics. Conditions TJ = +25C unless otherwise specified Drain-to-source breakdown voltage Breakdown voltage temperature coefficient Static drain-to-source on resistance Gate threshold voltage Forward transconductance Drain-to-source leakage current Gate-to-source forward leakage current Gate-to-source reverse leakage current Total gate charge Gate-to-source charge Gate-to-drain (Miller) charge Turn-on delay time Rise time Turn-off delay time Fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Reverse transfer capacitance See footnotes at end of table. IGSS V(BR)DSS V(BR)DS S/TJ Test Symbol Group A subgroups Room Min -200 Limits Typ Max Units VGS = 0 V, ID = 250 A ID = -1 mA VGS = -10 V, ID = 6.6 A 4/ VDS = VGS, ID = 250 A VDS = -50 V, ID = 6.6 A 4/ VDS = -200 V, VGS = 0 V VDS = -160 V, VGS = 0 V VGS = -20 V VGS = 20 V V -0.20 0.50 V/C R(DS)ON VGS(th) gfs IDSS -2.0 4.1 -4.0 V S -100 Max. Room -500 -100 100 44 7.1 27 14 43 39 4/ 38 4.5 7.5 1200 370 81 A nA Qg Qgs Qgd td(ON) tr td(off) tf LD LS CISS COSS CrSS ID = -11 A VDS = -160 V VGS = -10 V (see Figures 3.6 and 3.13) 4/ VDD = -100 V ID = -11 A RG = 9.1 RG = 8.6 (see Figure 2.10) Between lead, 6 mm (0.25in) from package and center of die contact 5A/ VGS = 0 V VDS = -25 V f = 1.0 MHz (see Figure 2.5) nC ns nH pF Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 4 TABLE II. Electrical performance characteristics- Continued. Conditions TJ = +25C unless otherwise specified Source-Drain Ratings : Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge Forward turn-on time 1/ 2/ 3/ 4/ IS MOSFET symbol showing the integral reverse p-n junction diode 5B/ Room -11 A Test Symbol Group A subgroups Min Limits Typ Max Units ISM VSD trr Qrr ton turn-on is dominated by LS + LD IS = -11 A, VGS = 0 V 4/ IF = -11 A, di/dt = 100 A/s 4/ 250 2.9 -44 -5.0 300 3.6 V ns C intrinsic turn-on is neglible Repetitive rating; pulse width limited by max. Junction temperature (see Figure 2.11) VDD = -50 V, starting TJ = +25C, L = 8.7 mH, RG = 25 , IAS = -11 A (see Figure 2.12). ISD -11 A, di/dt 150 A/s, VDD V(BR)DSS, TJ +150C. Pulse width 300 s; duty cycle 2%. Insert A. Insert B. Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 5 Terminal connections Package Outline Figure 1. Design and construction. Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 6 Tape & Reel Information Figure 1. Design and construction- Continued. Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 7 Figure 2. Typical characteristics diagrams. Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 8 Figure 2. Typical characteristics diagrams - Continued. Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 9 Figure 2. Typical characteristics diagrams - Continued. Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 10 4.0 Quality assurance provisions. 4.1 Responsibility for inspection. Unless otherwise specified in the contract or purchase order, the contractor is responsible for the performance of all inspection, examination, and test requirements specified herein. Except as otherwise specified in the contract or purchase order, the contractor may use his own or any other facilities suitable for the inspection requirements specified herein, unless disapproved by the Government. The Government reserves the right to perform any of the inspections, examinations, or tests set forth in this description where such inspections, examinations, and tests are deemed necessary to assure supplies and services conform to prescribed requirements. 4.2 Contractor certification statement. The contractor shall certify and maintain objective quality evidence that the product offered meets the requirements of this WSD, and that the product conforms to the producer's own drawings, specifications, standards, quality assurances practices, and is the same as the product provided as a bid sample. The acquiring activity reserves the right to require proof of such conformance prior to the first delivery and thereafter as may be otherwise provided for under the provisions of the contract. 4.3 Certificate of conformance. A certificate of conformance shall accompany all microcircuits supplied to this WSD. 5.1 Preservation, packaging, packing, labeling, and marking. Preservation, packaging, labeling, and marking shall be as specified in the contract or purchase order. 6.0 Notes. This section contains relevant information which is useful to buyers, users, and suppliers in the process of acquiring the item, but is not mandatory. 6.1 Radiation Tolerance Assured (RTA) . RTA performance is not covered under the manufacturers warranty. RTA testing has been performed and is an integral part of this drawing. The RTA performance is certified by White Sands Missile Range, Directorate for Applied Technology, Test and Simulation (WSMR, DATTS) to the performance characteristics as specified in TABLE III herein. 6.2 Electrical Performance over Temperature . Electrical performance over temperature ( -55C TA +150C) is covered under the manufacturers warranty. No further temperature testing is required for determining temperature related effects. There is no certification or warrantees by WSMR,DATTS to the performance characteristics specified in TABLE II herein. Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 11 TABLE III. RTA Electrical Performance Characteristics. 1/ Test Symbol Conditions TJ = +25C unless otherwise specified Drain-to-source breakdown voltage Static drain-to-source on resistance Gate threshold voltage Forward transconductance Drain-to-source leakage current Gate-to-source forward leakage current Gate-to-source reverse leakage current Diode forward voltage VSD V(BR)DSS R(DS)ON VGS(th) gfs IDSS IGSS VGS = 0 V, ID = 250 A VGS = -10 V, ID = 6.6 A VDS = VGS, ID = 250 A VDS = -9 V, ID = 6.6 A VDS = -200 V, VGS = 0 V VGS = -20 V VGS = 20 V IS = -11 A, VGS = 0 V -2.0 3.9 -133 -110 110 -5.2 V 2/ Limits Min -200 0.6 -4.4 Max V Units V S A nA 1/ Devices supplied to this drawing will meet and only be tested at the level M of irradiation. When performing post irradiation electrical measurements for any radiation level, TA = +25C. Radiation measurements at the level M are performed for: Gamma total dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3000 Rads(Si) Neutron fluence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5x1012 n/cm2/Mev 2/ All footnotes of Table II shall be applied here unless otherwise specified. Microcircuit, Linear, Dual MOSFET Drivers, Monolithic Silicon SIZE CAGE CODE A DATE: 98-09-23 09WF0 REVISION LEVEL A W98M9640 SHEET 12 6.3 Ordering data. The contract or purchase order shall specify the following: a. WSD document number and revision and WSD PIN. b. Quality assurance provisions. c. Packaging requirements. 6.4 Identification of the approved source(s) of supply hereon is not to be construed as a guarantee of present or continued availability as a source of supply for the item described on the drawing. PART ID NUMBER W98M964001EUX CAGE CODE 09WF0 MANUFACTURER International Rectifier ITEM IDENTIFICATION IRF9640S 09WF0 Commander, USAWSMR ATTN: STEWS-DT-A Building 90121 White Sands NM 88002-5158 Semiconductor Discrete Device, PChannel Power MOS Field Effect Transistor SIZE CAGE CODE A DATE: 98-09-25 09WF0 REVISION LEVEL A SHEET W98M9640 13 |
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