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| A1008U1X WCMA1008U1X 128K x 8 Static RAM Features * High Speed -- 55ns and 70ns availability * Voltage range -- 2.7V-3.6V * Ultra low active power -- Typical active current: 20 mA @ f = fmax (70ns speed) * Low standby power * Easy memory expansion with CE and OE features * Automatic power-down when deselected * CMOS for optimum speed/power ic power-down feature, reducing the power consumption by over 99% when deselected. Writing to the device is accomplished by taking Chip Enable one (CE1) and Write Enable (WE) inputs LOW and the Chip Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). Reading from the device is accomplished by taking Chip Enable one (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable two (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). The WCMA1008U1X is available in a 32 Lead TSOP and STSOP packages. Functional Description The WCMA1008U1X is a high-performance CMOS static RAM organized as 128K words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE) and three-state drivers. These devices have an automat- Logic Block Diagram Pin Configurations A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 25 26 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 STSOP Top View (not to scale) INPUT BUFFER I/O0 I/O1 A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER SENSE AMPS I/O2 I/O3 I/O4 I/O5 512x 256x 8 ARRAY CE 1 CE 2 WE OE COLUMN DECODER POWER DOWN I/O6 I/O7 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TSOP I Top View (not to scale) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 A9 A 10 A 11 A12 A13 A14 A15 A16 WCMA1008U1X Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .................................-65C to +150C Ambient Temperature with Power Applied...............................................55C to +125C Supply Voltage to Ground Potential..... ..........-0.5V to +4.6V DC Voltage Applied to Outputs in High Z State[1]........................................0.5V to VCC + 0.5V DC Input Voltage[1]..................................-0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................20 mA Static Discharge Voltage ..........................................>2001V (per MIL-STD-883, Method 3015) Latch-Up Current ......................................................>200 mA Operating Range Product WCMA1008U1X Range Industrial Ambient Temperature -40C to +85C VCC 2.7V to 3.6V Product Portfolio Power Dissipation (Industrial) Product Min. WCMA1008U1X 2.7V VCC Range Typ.[2] 3.0V Max. 3.6V 70 ns 55 ns Speed Operating, ICC f = fmax Typ.[2] 20 mA Max. 40 mA Standby (ISB2) Typ.[2] 0.4 A Max. 30 A Notes: 1. VIL(min.) = -2.0V for pulse durations less than 20 ns. 2. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C. 2 WCMA1008U1X Electrical Characteristics Over the Operating Range WCMA1008U1X-70/55 Parameter VOH VOL VIH VIL IIX IOZ ICC ISB1 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current-- TTL Inputs GND < VI < VCC GND < VO < VCC, Output Disabled VCC = 3.6V 70ns IOUT = 0 mA 55ns CMOS Levels Max. VCC, CE1VIH, 70ns CE2 ISB2 Automatic CE Power-Down Current-- CMOS Inputs 0.4 30 Capacitance[3] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz,VCC = Vcc(typ) Max. 6 8 Unit pF pF Thermal Resistance Description Thermal Resistance[3] (Junction to Ambient) Thermal Resistance[3] (Junction to Case) Note: 3. Tested initially and after any design or process changes that may affect these parameters. Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 4-layer printed circuit board Symbol JA JC BGA 55 16 Unit C/W C/W 3 WCMA1008U1X AC Test Loads and Waveforms R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC Typ 10% GND Rise Time: 1 V/ns ALL INPUT PULSES 90% 90% 10% Fall time: 1 V/ns Equivalent to: OUTPUT THEVENIN EQUIVALENT RTH VTH Parameters R1 R2 RTH VTH 3.3V 1213 1378 645 1.75 Unit Ohms Ohms Ohms Volts Data Retention Characteristics (Over the Operating Range) Parameter VDR ICCDR tCDR[3] tR[4] Description VCC for Data Retention Data Retention Current Chip Deselect to Data Retention Time Operation Recovery Time VCC = 2V, CE1 VCC - 0.3V, CE2 < 0.3V VIN > VCC - 0.3V or VIN < 0.3V 0 tRC Conditions Min. 1.6 0.4 20 Typ.[2] Max. Unit V A ns ns Data Retention Waveform DATA RETENTION MODE VCC 1.8V tCDR VDR > 1.6V 1.8V tR CE Note: 4. Full Device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 4 WCMA1008U1X Switching Characteristics Over the Operating Range[5] WCMA1008U1X-55 Parameter READ CYCLE tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE [8,] WCMA1008U1X-70 Min. 70 Max. Unit ns 70 10 70 35 10 25 10 25 0 70 70 60 60 0 0 55 30 0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 25 5 ns ns Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low Z [6] [6, 7] [6] Min. 55 Max. 55 5 55 20 10 20 10 20 0 55 55 45 45 0 0 45 25 0 20 5 OE HIGH to High Z CE1 LOW and CE2 HIGH to Low Z CE1 HIGH or CE2 LOW to High Z[6, 7] CE1 LOW and CE2 HIGH to Power-Up CE1 HIGH or CE2 LOW to Power-Down Write Cycle Time CE1 LOW and CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE LOW to High Z[6, 7] WE HIGH to Low Z [6] Notes: 5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30 pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high impedance state. 8. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write. 5 WCMA1008U1X Switching Waveforms Read Cycle No. 1 (Address Transition Controlled) [9, 10] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID Read Cycle No. 2 (OE Controlled) [10, 11] ADDRESS tRC CE1 CE2 tACE OE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZOE tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE DATA OUT Notes: 9. Device is continuously selected. OE, CE1 = VIL, CE2 = VIH. 10. WE is HIGH for read cycle. 11. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH. 6 WCMA1008U1X Switching Waveforms (continued) Write Cycle No. 1(WE Controlled) [8, 12, 14] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tPWE tHA OE tSD DATA I/O NOTE 13 tHZOE DATAIN VALID tHD [8, 12, 14] Write Cycle No. 2 (CE1 or CE2 Controlled) tWC ADDRESS tSCE CE1 tSA CE2 tAW tPWE WE tHA OE tSD DATA I/O DATAIN VALID tHD Notes: 12. Data I/O is high impedance if OE = VIH. 13. During this period, the I/Os are in output state and input signals should not be applied. 14. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state. 7 WCMA1008U1X Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) [14] tWC ADDRESS tSCE CE1 CE2 tAW tSA WE tSD DATAI/O NOTE 13 tHZWE DATAIN VALID tLZWE tHD tPWE tHA 8 WCMA1008U1X Truth Table CE1 H X L L L CE2 X L H H H WE X X H L H OE X X L X H Inputs/Outputs High Z High Z Data Out Data In High Z Mode Deselect/Power-Down Deselect/Power-Down Read Write Output Disabled Power Standby (ISB) Standby (ISB) Active (ICC) Active (ICC) Active (ICC) 9 WCMA1008U1X Ordering Information Speed (ns) 70 55 Ordering Code WCMA1008U1X-TF70 WCMA1008U1X-SF70 WCMA1008U1X-TF55 WCMA1008U1X-SF55 Package Name T32 S32 T32 S32 Package Type 32-Lead TSOP 32-Lead STSOP 32-Lead TSOP 32-Lead STSOP Operating Range Industrial Package Diagrams 32-Lead Thin Small Outline Package, T32 10 WCMA1008U1X Package Diagrams (continued) 32-Lead Shrunk Thin Small Outline Package, S32 11 WCMA1008U1X Document Title: WCMA1008U1X, 128K x 8 Static RAM REV. ** Spec # 38-14023 ECN # 115246 Issue Date 4/24/2002 Orig. of Change MGN Description of Change New Data Sheet 12 |
Price & Availability of WCMA1008U1X-TF70
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