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| ADVANCE INFORMATION WCMC8016V9X 8Mb (512K x 16) Pseudo Static RAM Features * Wide voltage range: 2.70V-3.30V * Access Time: 70ns * Ultra-low active power -- Typical active current: 2.0mA @ f = 1 MHz * * * * * -- Typical active current: 11mA @ f = fmax Ultra low standby power Easy memory expansion with CE, CE2, and OE features Automatic power-down when deselected CMOS for optimum speed/power Offered in a 48 Ball BGA Package This is ideal for providing More Battery Life(R) (MoBL(R) ) in portable applications such as cellular telephones. The device can be put into standby mode reducing power consumption by more than 99% when deselected using CE LOW, CE2 HIGH or both BHE and BLE are HIGH. The input/output pins (I/O 0 through I/O 1 5) are placed in a high-impedance state when: deselected (CE HIGH, CE 2 LOW OE is deasserted HIGH), or during a write operation (Chip Enabled and Write Enable WE LOW). The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling even when the chip is selected (Chip Enable CE LOW, CE2 HIGH and both BHE and BLE are LOW). Reading from the device is accomplished by asserting the Chip Enables ( CE LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O 7. If Byte High Enable ( HE) is LOW, then data from B memory will appear on I/O8 to I/O1 5. See the Truth Table for a complete description of read and write modes Functional Description[1] The WCMC8016V9X is a high-performance CMOS pseudo static RAM organized as 512K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. Logic Block Diagram DATA IN DRIVERS A 10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 512K x 16 RAM Array 1T SENSE AMPS I/O0 -I/O7 I/O8 -I/O15 COLUMN DECODER A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 BHE WE OE BLE CE2 CE Pow er Down Circuit Note: 1. For best-practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress .com. WeidaSemiconductor, Inc. 38-14026 Revised August 2003 ADVANCE INFORMATION Pin Configuration[2, 3, 4] FBGA Top View 1 BLE I/O8 I/O9 VSS VCC I/O14 I/O15 A 18 2 OE BHE I/O10 I/O11 I/O12 I/O13 NC/ 3 A0 A3 A5 A 17 GND A14 A12 A9 4 A1 A4 A6 A7 A16 A15 A13 A10 5 A2 CE I/O1 I/O3 I/O4 I/O5 WE A11 6 CE 2 I/O0 I/O2 Vcc Vss A B C D E F G H WCMC8016V9X I/O6 I/O7 NC/ A8 Note: 2. NC "no connect" - not connected internally to the die. 3. DNU pins are to be left floating or tied to Vss. 4. Ball G2 and H6 are the expansion pins for the 16Mb and 32Mb density resectively. 38-14026 Page - 2 - of 12 ADVANCE INFORMATION Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................ -65C to + 150C Ambient Temperature with Power Applied .............................................. -55C to + 85C Supply Voltage to Ground Potential ................. -0.4V to 4.6V WCMC8016V9X DC Voltage Applied to Outputs in High Z State [5, 6, 7] ........................................-0.2V to 3.3V DC Input Voltage [5, 6, 7] .....................................-0.2V to 3.3V Output Current into Outputs (LOW).............................20 mA Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current .....................................................>200 mA Operating Range[9] Device WCMC8016V9X Range Industrial Ambient Temperature -25C to +85C VCC 2.70V to 3.30V Product Portfolio Power Dissipation Product Min. WCMC8016V9X-FI70 2.70 VCC Range (V) Typ.[8] 3.0 Max. 3.30 70 Speed (ns) Typ. [8] 2 Operating ICC (mA) f = 1MHz Max. 3.5 f = fmax Typ. [8] 11 Max. 17 Standby I SB2 (A) Typ.[8] 55 Max. 80 Notes: 5. VIH(MAX) = VCC + 0.5V for pulse durations less than 20ns. 6. VIL(MIN) = -0.5V for pulse durations less than 20ns. 7. Overshoot and undershoot specifications are characterized and are not 100% tested. 8. Typical values are included for reference only and are not guranteed or tested. Typical values are measured at VC C = VCC (typ) and TA = 25C 9. VCC must be at minimal operational levels before inputs are turned ON. 38-14026 Page - 3 - of 12 ADVANCE INFORMATION Electrical Characteristics Over the Operating Range WCMC8016V9X WCMC8016V9X-70 Parameter VCC VOH VOL VIH VIL IIX IOZ ICC Description Supply Voltage Output HIGH Voltage IOH = -1.0 mA Output LOW Voltage IOL = 2.0mA Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC Operating Supply Current Automatic CE Power-Down Current -- CMOS Inputs VCC= 2.7V to 3.3V VCC= 2.7V to 3.3V(F = 0) GND < VI < VCC GND < VO < VCC , Output Disabled f = fMAX = 1/tRC f = 1 MHz VCC = V CCmax IOUT = 0 mA CMOS levels VCC = 2.70V VCC = 2.70V 0.8*Vcc -0.3 -1 -1 11 2.0 Test Conditions Min. 2.7 2.4 0.4 VCC +0.3V 0.4 +1 +1 17 3.5 400 Typ. [8] Max. 3.3 Unit V V V V V A A mA mA A ISB1 CE > VCC -0.2V or CE2< 0.2V Vcc = 3.3V VIN>VCC -0.2V, VIN <0.2V) f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC=3.30V CE > VCC - 0.2V or CE 2 < Vcc = 3.3V 0.2V, Vcc = 3.0V VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 3.30V Vcc = 2.8V 55 50 45 ISB2 Automatic CE Power-Down Current -- CMOS Inputs 80 70 60 A A A Capacitance[10] Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions T A = 25C, f = 1 MHz, VCC = VCC(typ) Max. 6 8 Unit pF pF Thermal Resistance[10] Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Note: 10. Tested initially and after any design or process changes that may affect these parameters. Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board Symbol JA JC BGA 55 16 Unit C/W C/W 38-14026 Page - 4 - of 12 ADVANCE INFORMATION AC Test Loads and Waveforms R1 VCC OUTPUT 50 pF INCLUDING JIG AND SCOPE R2 VCC 10% GND Rise Time = 1 V/ns ALL INPUT PULSES 90% 90% 10% WCMC8016V9X Fall Time = 1 V/ns Equivalento: t THE VENINEQUIVALENT RTH OUTPUT V Unit V Parameters R1 R2 RTH VTH 3.0V VCC 1179 1941 733 1.87 38-14026 Page - 5 - of 12 ADVANCE INFORMATION Switching Characteristics Over the Operating Range [11] 70 ns Parameter READ CYCLE t RC t AA t OHA t ACE t DOE t LZOE t HZOE t LZCE t HZCE t DBE t LZBE t HZBE tS K WRITE CYCLE t WC t SCE t AW t HA t SA t PWE t BW t SD t HD t HZWE t LZWE [13] WCMC8016V9X Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to LOW Z OE HIGH to High Z [12, 14] [12, 14] Min. 70 Max. Unit ns 70 10 70 35 5 25 5 25 70 5 25 10 70 60 60 0 0 45 60 45 0 25 5 [12, 14] ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CE LOW and CE2 HIGH to Low Z[12, 14] CE HIGH and CE2 LOW to High Z BLE / BHE LOW to Data Valid BLE / BHE LOW to Low Z Address Skew Write Cycle Time CE LOW and CE2 HIGH to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width BLE / BHE LOW to Write End Data Set-Up to Write End Data Hold from Write End WE LOW to High-Z[12, 14] WE HIGH to Low-Z [12, 14] [12, 14] BLE / BHE HIGH to HIGH Z[12, 14] Notes: 11. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1ns/V, timing reference leve ls of V CC(typ)/2, input pulse levels of 0 to VCC (typ.) , and output loading of the specified I OL /I O H as shown in the "AC Test Loads and Waveforms" section.. 12. t HZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedence state. 13. The internal Write time of the memory is defined by the overlap of WE, CE = V IL, BHE and/or BLE = V IL, and CE2 = VIH . All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be refere nced to the edge of the signal that terminates the write. 14. High-Z and Low-Z parameters are characterized and are not 100% tested. 38-14026 Page - 6 - of 12 ADVANCE INFORMATION Switching Waveforms [15] Read Cycle 1 (Address Transition Controlled) WCMC8016V9X t RC ADDRESS t SK tOHA tAA DATA VALID DATA OUT PREVIOUS DATA VALID Read Cycle 2 (O E Controlled) [15] ADDRESS tSK tRC tPD CE CE2 tACE BHE/BLE tHZCE tLZBE OE tDBE tHZBE DATA OUT VCC tLZOE HIGH IMPEDANCE tLZCE tPU tDOE DATA VALID tHZOE HIGH IMPEDANCE I CC Note: 15. WE is HIGH for read cycle. 50% 50% 38-14026 Page - 7 - of 12 ADVANCE INFORMATION Switching Waveforms (continued) Write Cycle 1 (WE Controlled) [13, 14,16, 17, 18] ADDRESS tSCE CE WCMC8016V9X tWC CE2 tAW tSA WE tHA tPWE BHE/BLE tBW OE tSD DATAI/O DON'T CARE [13, 14,16, 17, 18] tHD VALID DATA Write Cycle 2 (CE or CE2 Controlled) tWC ADDRESS tSCE CE CE2 tS A tAW tPWE tHA WE tBW BHE /BLE OE tSD DATAI/O DON'T CARE tHD VALID DATA tHZOE Notes: 16. Data I/O is high impedance if OE = VIH . 17. If Chip Enable goes INACTIVE and CE2 goes LOW simultaneously with WE = V IH, the output remains in a high-impedance state. 18. During the DON'T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. 38-14026 Page - 8 - of 12 ADVANCE INFORMATION Switching Waveforms (continued) Write Cycle 3 (WE Controlled, OE LOW) [17, 18] WCMC8016V9X tWC ADDRESS tSCE CE CE2 BHE /BLE tBW tAW tSA tPWE tHA WE tSD DATA I/O DON'T CARE tHD VALID DATA tHZWE tLZWE Write Cycle 4 (BHE/BLE Controlled, OE LOW)[17, 18] tWC ADDRESS CE CE2 tAW BHE/BLE tS A WE tP W E tSD DATA I/O DON'T CARE tSCE tHA tBW tHD VALID DATA 38-14026 Page - 9 - of 12 ADVANCE INFORMATION Truth Table[19] CE H X X L L L L L L L L L CE2 X L X H H H H H H H H H WE X X X H H H H H H L L L OE X X X L L L H H H X X X BHE X X H L H L L H L L H L BLE X X H L L H H L L L L H Inputs/Outputs High Z High Z High Z Data Out (I/O0 - I/O15) Data Out (I/O0 - I/O7); High Z (I/O8 - I/O15) High Z (I/O0 - I/O7); Data Out (I/O8 - I/O15) High Z High Z High Z Data In (I/O0 - I/O15) Data In (I/O0 - I/O7); High Z (I/O8 - I/O15) High Z (I/O0 - I/O7); Data In (I/O8 - I/O15) Mode WCMC8016V9X Power Standby (I SB) Standby (I SB) Standby (I SB) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Active (ICC) Deselect/Power-Down Deselect/Power-Down Deselect/Power-Down Read Read Read Output Disabled Output Disabled Output Disabled Write Write Write Note: 19. H = V I H, L = V IL , X = Don't Care Ordering Information Speed (ns) 70 Ordering Code WCMC8016V9X-FI70 Package Name BA48K Package Type 48-ball Fine Pitch BGA (6 mm x 8mm x 1.2 mm) Operating Range Industrial 38-14026 Page - 10 - of 12 ADVANCE INFORMATION Package WCMC8016V9X 48-Ball (6 mm x 8mm x 1.2 mm) FBGA BA48K 51-85193-*A MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders 38-14026 Page - 11 - of 12 (c) Weida Semiconductor, Inc., 2002. The information contained herein is subject to change without notice. Weida Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Weida Semiconductor product. Nor does it convey or imply any license under patent or other rights. Weida Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Weida Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Weida Semiconductor against all charges. ADVANCE INFORMATION Document Title: WCMC8016V9X MoBL3(R) 8Mb (512K x 16) Pseudo Static RAM Document Number: 38-14026 REV. ** ECN NO. 130543 Issue Date 10/16/03 Orig. of Change MPR Description of Change New Datasheet WCMC8016V9X 38-14026 Page - 12 - of 12 |
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