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XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
JANUARY 2007 REV. V1.2.0
GENERAL DESCRIPTION
The XRT86VL38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology (Relayless, Reconfigurable, Redundancy). The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL38 provides protection from power failures and hot swapping. The XRT86VL38 contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats. Each Framer block contains its own Transmit and Receive T1/E1/J1 Framing function. There are 3 Transmit HDLC controllers per channel which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames from the incoming T1/E1/J1 data stream and write the contents into the Receive HDLC buffers. Each framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound T1/E1/J1 frames. Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound T1/E1/J1 frames. The XRT86VL38 fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/ E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/ E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loop-backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921. Applications and Features (next page)
FIGURE 1. XRT86VL38 8-CHANNEL DS1 (T1/E1/J1) FRAMER/LIU COMBO
External Data Link Controller
Local PCM Highway
XRT86VL38
1 of 8-channels Tx Serial Data In
Tx Overhead In
Rx Overhead Out
1:2 Turns Ratio TTIP
2-Frame Slip Buffer Elastic Store
Tx Framer
Tx LIU Interface
TRING
Tx Serial Clock
LLB Rx Serial Data Out 2-Frame Slip Buffer Elastic Store Rx Framer
LB
RTIP 1:1 Turns Ratio
ST-BUS
Rx LIU Interface
RRING
Rx Serial Clock
PRBS Generator & Analyser
Performance Monitor
HDLC/LAPD Controllers
LIU & Loopback Control
RxLOS
8kHz sync OSC Signaling & Alarms JTAG DMA Interface
Line Side
Microprocessor Interface
Back Plane 1.544-16.384 Mbit/s
3
System (Terminal) Side
TxON Memory
INT
D[7:0]
P A[14:0] Select
4 WR ALE_AS RD RDY_DTACK
Intel/Motorola P Configuration, Control & Status Monitor
Exar Corporation 48720 Kato Road, Fremont CA, 94538 * (510) 668-7000 * FAX (510) 668-7017 * www.exar.com
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION APPLICATIONS
REV. V1.2.0
* High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems * SONET/SDH terminal or Add/Drop multiplexers (ADMs) * T1/E1/J1 add/drop multiplexers (MUX) * Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 * Digital Access Cross-connect System (DACs) * Digital Cross-connect Systems (DCS) * Frame Relay Switches and Access Devices (FRADS) * ISDN Primary Rate Interfaces (PRA) * PBXs and PCM channel bank * T3 channelized access concentrators and M13 MUX * Wireless base stations * ATM equipment with integrated DS1 interfaces * Multichannel DS1 Test Equipment * T1/E1/J1 Performance Monitoring * Voice over packet gateways * Routers
FEATURES
* Eight independent, full duplex DS1 Tx and Rx Framer/LIUs * Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz
asynchronous back plane connections with jitter and wander attenuation
* Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4-channel
multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
* Programmable output clocks for Fractional T1/E1/J1 * Supports Channel Associated Signaling (CAS) * Supports Common Channel Signalling (CCS) * Supports ISDN Primary Rate Interface (ISDN PRI) signaling * Extracts and inserts robbed bit signaling (RBS) * 3 Integrated HDLC controllers per channel for transmit and receive, each controller having two 96-byte
buffers (buffer 0 / buffer 1)
* HDLC Controllers Support SS7 * Timeslot assignable HDLC * V5.1 or V5.2 Interface * Automatic Performance Report Generation (PMON Status) can be inserted into the transmit LAPD interface
every 1 second or for a single transmission
* Alarm Indication Signal with Customer Installation signature (AIS-CI) * Remote Alarm Indication with Customer Installation (RAI-CI) * Gapped Clock interface mode for Transmit and Receive.
2
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
* Intel/Motorola and Power PC interfaces for configuration, control and status monitoring * Parallel search algorithm for fast frame synchronization * Wide choice of T1 framing structures: SF/D4, ESF, SLC(R)96, T1DM and N-Frame (non-signaling) * Direct access to D and E channels for fast transmission of data link information * PRBS, QRSS, and Network Loop Code generation and detection * Programmable Interrupt output pin * Supports programmed I/O and DMA modes of Read-Write access * Each framer block encodes and decodes the T1/E1/J1 Frame serial data * Detects and forces Red (SAI), Yellow (RAI) and Blue (AIS) Alarms * Detects OOF, LOF, LOS errors and COFA conditions * Loopbacks: Local (LLB) and Line remote (LB) * Facilitates Inverse Multiplexing for ATM * Performance monitor with one second polling * Boundary scan (IEEE 1149.1) JTAG test port * Accepts external 8kHz Sync reference * 1.8V Inner Core Voltage * 3.3V I/O operation with 5V tolerant inputs * 420-pin PBGA package or 484-pin STBGA package with -40C to +85C operation ORDERING INFORMATION
PART NUMBER XRT86VL38IB XRT86VL38IB484 PACKAGE 420 Plastic Ball Grid Array 484 Shrink Thin Ball Grid Array OPERATING TEMPERATURE RANGE -40C to +85C -40C to +85C
3
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
420 BALL - PLASTIC BALL GRID ARRAY (BOTTOM VIEW, SEE PIN LIST FOR DESCRIPTION)
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF
OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO OOOOO
OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOOOOOOO
4
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
484 BALL - SHRINK THIN BALL GRID ARRAY (BOTTOM VIEW - SEE PIN LIST FOR DESCRIPTION)
22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO OOOOOOOOOOOOOOOOOOOOO
O O O O O O O O O O O O O O O O O O O O O O
A B C D E F G H J K L M N P R T U V W Y AA AB
5
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
LIST OF PARAGRAPHS
1.0 PIN LISTS .................................................................................................................................................6 2.0 PIN DESCRIPTIONS ..............................................................................................................................14
I
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
LIST OF FIGURES
Figure 1.: XRT86VL38 8-channel DS1 (T1/E1/J1) Framer/LIU Combo ............................................................................. 1 Figure 2.: ITU G.703 Pulse Template .............................................................................................................................. 58 Figure 3.: DSX-1 Pulse Template (normalized amplitude) .............................................................................................. 59
II
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
LIST OF TABLES
Table 1:: 420 Ball List by Ball Number ............................................................................................................................... 6 Table 2:: 484 Ball List by Ball Number ............................................................................................................................. 10 Table 3:: Pin Description Structure .................................................................................................................................. 14 Table 4:: E1 Receiver Electrical Characteristics .............................................................................................................. 55 Table 5:: T1 Receiver Electrical Characteristics .............................................................................................................. 56 Table 6:: E1 Transmitter Electrical Characteristics .......................................................................................................... 56 Table 7:: E1 Transmit Return Loss Requirement ............................................................................................................. 57 Table 8:: T1 Transmitter Electrical Characteristics .......................................................................................................... 57 Table 9:: Transmit Pulse Mask Specification ................................................................................................................... 58 Table 10:: DSX1 Interface Isolated pulse mask and corner points .................................................................................. 59 Table 11:: AC Electrical Characteristics ........................................................................................................................... 60
III
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN B6 PIN NAME TDO TRST RXCRCSYNC0 RXOHCLK0 TXMSYNC0 TEST TXCHN0_1 RXSERCLK1 RXSER1 RXOH1 RXCHN1_3 VSS NC TXCHN1_2 RXLOS2 GPIO1_3 RXCHN2_1 NC TXSYNC2 VSS TXCHCLK2 VDDPLL18 VDDPLL18 GNDPLL NC ANALOG VSS RXSER0 VDD RXCHN0_2 RXCHN0_3 RXOH0
1.0 PIN LISTS TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B1 B2 B3 B4 B5 PIN NAME DVDD18 DGND AGND MCLKIN TMS RXSERCLK0 TCK RXCHCLK0 TXSYNC0 RXCHN0_4 TXSERCLK0 TXCHCLK0 TXCHN0_2 RXCHCLK1 RXCHN1_2 RXLOS1 TXMSYNC1 TXOH1 TXOHCLK1 TXCHN1_3 TXCHN1_4 RXCHN2_0 RXCASYNC2 RXCHCLK2 VDD RXCHN2_4 VDDPLL18 GNDPLL NC AVDD18 E1MCLKOUT
TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 PIN NAME TXOH0 VSS TXCHN0_4 VDD TXSYNC1 RXCHN1_4 TXCHN1_0 TXSERCLK1 RXSERCLK2 RXSER2 RXCHN2_2 RXCHN2_3 TXMSYNC2 VSS TXCHN2_2 RTIP0 RVDD0 VDDPLL18 JTAG_RING RxTSEL T1MCLKOUT TDI RXCHN0_0 RXSYNC0 VSS TXSER0 TXCHN0_0 RXCRCSYNC1 RXCHN1_0 RXSYNC1 RXOHCLK1 TXSER1
TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN D18 D19 D20 D21 D22 D23 D24 D25 D26 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 E21 E22 E23 PIN NAME TXCHN1_1 RXSYNC2 VSS RXOH2 TXSERCLK2 NC VDD18 TXCHN2_1 RXSER3 RRING0 RGND0 GNDPLL GNDPLL NC SENSE aTEST RXLOS0 RXCHN0_1 RXCASYNC0 TXOHCLK0 VDD18 TXCHN0_3 RXCHN1_1 RXCASYNC1 NC TXCHCLK1 VDD18 NC RXCRCSYNC2 RXOHCLK2 NC TXSER2
B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11
6
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN E24 E25 E26 F1 F2 F3 F4 F5 F22 F23 F24 F25 F26 G1 G2 G3 G4 G5 G22 G23 G24 G25 G26 H1 H2 H3 H4 H5 H22 H23 H24 H25 PIN NAME TXOHCLK2 TXCHN2_4 TXOH2 RTIP1 RVDD1 TTIP0 TVDD0 JTAG_TIP TXCHN2_0 TXCHN2_3 VDD RXCHCLK3 RXOH3 RRING1 RGND1 TTIP1 TRING0 NC GPIO1_2 RXSYNC3 RXOHCLK3 RXCRCSYNC3 RXCHN3_0 RTIP2 RVDD2 TVDD1 TRING1 TGND0 VSS RXCASYNC3 RXLOS3 RXSERCLK3
REV. V1.2.0
TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN H26 J1 J2 J3 J4 J5 J22 J23 J24 J25 J26 K1 K2 K3 K4 K5 K22 K23 K24 K25 K26 L1 L2 L3 L4 L5 L22 L23 L24 L25 L26 M1 PIN NAME RXCHN3_1 RRING2 RGND2 TTIP2 TVDD2 TGND1 TXCHCLK3 RXCHN3_2 VDD18 TXOH3 RXCHN3_3 RTIP3 RVDD3 TTIP3 TRING2 TGND2 TXSYNC3 TXOHCLK3 TXSERCLK3 RXCHN3_4 TXSER3 RRING3 RGND3 TVDD3 TRING3 TGND3 TXCHN3_0 VSS TXMSYNC3 TXCHN3_1 CS RTIP4
TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN M2 M3 M4 M5 M22 M23 M24 M25 M26 N1 N2 N3 N4 N5 N22 N23 N24 N25 N26 P1 P2 P3 P4 P5 P22 P23 P24 P25 P26 R1 R2 R3 PIN NAME RVDD4 TTIP4 TRING4 TGND4 TXCHN3_2 WR TXCHN3_3 DATA7 TXCHN3_4 RRING4 RGND4 TVDD4 NC TGND5 ADDR14 ADDR13 DATA6 DATA5 VDD RTIP5 RVDD5 TTIP5 TRING5 NC ADDR11 BLAST DATA4 ADDR12 VSS RRING5 RGND5 TVDD5
TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN R4 R5 R22 R23 R24 R25 R26 T1 T2 T3 T4 T5 T22 T23 T24 T25 T26 U1 U2 U3 U4 U5 U22 U23 U24 U25 U26 V1 V2 V3 V4 V5 PIN NAME TRING6 TGND6 ALE ADDR9 ADDR10 PTYPE2 INT RTIP6 RVDD6 TTIP6 TVDD6 TGND7 ADDR7 VDD18 ADDR8 DATA2 DATA3 RRING6 RGND6 TTIP7 TRING7 NC ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 RTIP7 RVDD7 TVDD7 NC NC
7
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN AA24 AA25 AA26 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25 AB26 AC1 AC2 AC3 PIN NAME REQ1 VDD fADDR LOP TXCHCLK7 8KSYNC TXCHN7_4 TXSERCLK7 RXSERCLK7 RXSER7 RXCHN7_0 TXSER6 TXCHN6_0 RXSYNC6 RXSERCLK6 RXCHN6_1 TXCHN5_3 TXSER5 TXOHCLK5 RXCHN5_2 GPIO0_2 VSS VDD18 TXSER4 RXCHN4_4 VSS RXCHCLK4 RXCRCSYNC4 REQ0 T1OSCCLK TXOH7 TXCHN7_3
TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN V22 V23 V24 V25 V26 W1 W2 W3 W4 W5 W22 W23 W24 W25 W26 Y1 Y2 Y3 Y4 Y5 Y22 Y23 Y24 Y25 Y26 AA1 AA2 AA3 AA4 AA5 AA22 AA23 PIN NAME VSS DBEN RDY ADDR0 ADDR1 RRING7 RGND7 NC NC NC iADDR PTYPE0 DATA1 RD PTYPE1 VSS VDD TXON RESET E1OSCCLK RXOHCLK4 ACK0 ACK1 PCLK DATA0 VSS 8KEXTOSC NC NC NC RXOH4 VSS
TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN AC4 AC5 AC6 AC7 AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 PIN NAME VDD TXCHN7_0 RXSYNC7 RXCHN7_1 TXMSYNC6 RXCASYNC6 TXOHCLK6 VDD RXLOS6 RXCHN6_0 TXCHN5_4 TXCHN5_0 VSS RXCHN5_3 RXSER5 RXSERCLK5 TXCHN4_2 TXMSYNC4 VSS RXCHN4_3 VDD18 RXSER4 RXLOS4 VDD18 TXCHN7_2 TXCHN7_1 RXLOS7 RXCRCSYNC7 VSS VDD18 TXSYNC6 VSS
TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE1 AE2 AE3 AE4 AE5 AE6 AE7 AE8 AE9 AE10 AE11 AE12 AE13 AE14 AE15 PIN NAME TXCHCLK6 GPIO0_0 RXCHN6_3 GPIO0_1 TXOH5 TXCHN5_1 TXMSYNC5 RXCHN5_4 RXCHN5_0 TXCHN4_4 GPIO0_3 TXCHN4_0 TXCHCLK4 VDD RXCASYNC4 RXCHN4_0 RXSERCLK4 TXOHCLK7 VSS TXSER7 TXSYNC7 RXCHN7_3 TXSERCLK6 RXOHCLK7 TXCHN6_4 TXCHN6_2 RXCRCSYNC6 RXCHCLK6 RXSER6 RXOHCLK6 RXOH6 TXCHN5_2
8
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF1 AF2 AF3 AF4 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 PIN NAME TXCHCLK5 RXOH5 VDD RXCASYNC5 TXCHN4_3 RXCHCLK5 GPIO1_0 TXSERCLK4 GPIO1_1 RXCHN4_1 RXSYNC4 NC TXMSYNC7 RXCHN7_4 RXCHN7_2 RXCHCLK7 RXCASYNC7 RXOH7 TXCHN6_3 TXCHN6_1 TXOH6 RXCHN6_4 RXCHN6_2 VSS VDD18 TXSERCLK5 TXSYNC5 RXOHCLK5 RXCHN5_1 RXSYNC5 RXLOS5 RXCRCSYNC5
REV. V1.2.0
TABLE 1: 420 BALL LIST BY BALL NUMBER
PIN AF22 AF23 AF24 AF25 AF26 PIN NAME TXCHN4_1 TXOHCLK4 TXSYNC4 TXOH4 RXCHN4_2
9
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN B15 B16 B17 B18 B19 B20 B21 B22 C1 C2 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 D1 D2 D3 D4 D8 PIN NAME TXMSYNC1 TXOH1 TXSERCLK1 RXSERCLK2 RXCHN2_0 RXCHCLK2 RXCHN2_4 TXOHCLK2 VDDPLL18 JTAG_RING RXTSEL ATEST RXLOS0 RXCHN0_1 RXCASYNC0 TXSERCLK0 TXCHCLK0 RXCHN1_1 RXLOS1 TXSER1 TXCHN1_0 TXCHN1_3 RXCASYNC2 RXCHN2_1 TXSYNC2 TXCHN2_0 TXCHN2_4 GNDPLL18 VDDPLL18 GNDPLL18 ANALOG TDO
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN A2 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 B1 B3 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 PIN NAME AVDD_LV E1MCLKOUT MCLKIN TRST RXCHN0_0 RXSYNC0 TXMSYNC0 TXOHCLK0 TXCHN0_1 RXSERCLK1 TXCHN0_4 RXOH1 RXCHN1_3 TXCHCLK1 TXOHCLK1 RXSYNC2 GPIO1_3 RXCRCSYNC2 RXOHCLK2 VDDPLL18 AGND DGND TMS RXSER0 RXCRCSYNC0 TXSYNC0 RXCHN0_4 TXCHN0_0 RXCRCSYNC1 RXCHN1_0 RXCASYNC1
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E1 E2 E3 E4 E5 E6 E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 PIN NAME RXSERCLK0 RXCHN0_2 RXOH0 TXCHN0_2 RXCHN1_2 RXOHCLK1 TXCHN1_1 RXLOS2 RXSER2 RXOH2 RXCHN2_3 TXSER2 TXCHN2_3 RXSYNC3 RVDD0 GNDPLL18 VDDPLL18 GNDPLL18 JTAG_TIP SENSE TDI RXCHCLK0 RXCHN0_3 TEST TXOH0 RXSER1 RXCHCLK1 RXSYNC1 TXSERCLK2 TXMSYNC2 TXCHCLK2 TXCHN2_1
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN E21 E22 F1 F2 F3 F4 F5 F9 F10 F11 F12 F13 F14 F15 F16 F17 F19 F20 F21 F22 G1 G2 G3 G4 G17 G18 G19 G20 G21 G22 H1 H2 PIN NAME TXOH2 RXOHCLK3 TRING0 TVDD0 TTIP_0 RGND0 DVDD18 T1MCLKOUT TCK RXOHCLK0 TXSER0 TXCHN0_3 TXSYNC1 TXCHN1_2 RXCHN1_4 RXCHN2_2 TXCHN2_2 RXSER3 RXCASYNC3 RXLOS3 TVDD1 RTIP0 RRING0 TGND0 TXCHN1_4 GPIO1_2 RXCHCLK3 RXCRCSYNC3 RXCHN3_1 TXCHCLK3 RRING1 RTIP1
10
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN H3 H4 H5 H18 H19 H20 H21 H22 J1 J2 J3 J4 J5 J6 J18 J19 J20 J21 J22 K1 K2 K3 K4 K5 K6 K17 K18 K19 K20 K21 K22 L1 PIN NAME RGND1 TTIP1 RVDD1 RXOH3 RXCHN3_0 RXSERCLK3 RXCHN3_3 TXOHCLK3 TRING2 TVDD2 TTIP2 RGND2 TRING1 TGND1 TXOH3 RXCHN3_2 TXSYNC3 TXSERCLK3 RXCHN3_4 TTIP3 RGND3 RRING2 RTIP2 TGND2 RVDD2 TXCHN3_1 TXSER3 TXCHN3_0 TXMSYNC3 CS TXCHN3_2 RRING3
REV. V1.2.0
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN L2 L3 L4 L5 L6 L17 L18 L19 L20 L21 L22 M1 M2 M3 M4 M5 M6 M7 M17 M18 M19 M20 M21 M22 N1 N2 N3 N4 N5 N17 N18 N19 PIN NAME RTIP3 TVDD3 TRING3 TGND3 RVDD3 TXCHN3_4 ADDR13 TXCHN3_3 WR DATA7 ADDR14 RRING4 RTIP4 TRING4 RGND4 TTIP4 TVDD4 RVDD4 BLAST ADDR11 ADDR12 DATA5 DATA6 DATA4 TVDD5 TTIP5 RGND5 RVDD5 TGND4 ADDR1 DATA3 ADDR9
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN N20 N21 N22 P1 P2 P3 P4 P5 P18 P19 P20 P21 P22 R1 R2 R3 R4 R5 R18 R19 R20 R21 R22 T1 T2 T3 T4 T5 T18 T19 T20 T21 PIN NAME ADDR10 PTYPE2 INT RGND6 RRING5 RTIP5 TGND5 TRING5 ADDR0 ADDR7 ADDR8 DATA2 ALE TGND6 TRING6 TVDD6 TTIP6 RVDD6 iADDR RDY ADDR4 ADDR5 ADDR6 TTIP7 RTIP6 RRING6 RGND7 RVDD7 fADDR DATA0 PTYPE1 ADDR2
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN T22 U1 U2 U3 U4 U5 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 PIN NAME ADDR3 TVDD7 TRING7 RRING7 RTIP7 8KEXTOSC TXCHN7_4 RXLOS7 TXSERCLK6 TXSER6 TXOH6 RXOH6 TXOHCLK5 RXCHN5_0 TXCHN4_1 GPIO0_3 TXMSYNC4 RXCHCLK4 REQ0 DATA1 RD DBEN TGND7 LOP T1OSCCLK E1OSCCLK TXCHCLK7 TXOHCLK7 TXSERCLK7 TXCHN7_1 RXCRCSYNC7 RXOH7
11
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN W21 W22 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 PIN NAME RXLOS4 ACK0 RESET TXCHN7_3 RXSYNC7 RXCHN7_2 RXCHCLK7 RXOHCLK7 RXCHN7_0 RXCASYNC6 RXCRCSYNC6 RXLOS6 GPIO0_1 TXCHN5_3 TXCHCLK5 RXOH5 RXSYNC5 TXCHN4_2 TXSYNC4 TXSERCLK4 RXCHN4_4 RXSYNC4 RXCRCSYNC4 REQ1 TXOH7 TXSYNC7 RXCHN7_3 TXSYNC6 TXCHN6_2 RXSYNC6 TXOHCLK6 RXCHCLK6
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 PIN NAME TXCHCLK6 RXCHN6_1 TXSYNC5 RXCHN5_3 GPIO0_2 RXSERCLK5 RXCASYNC4 RXOH4 RXOHCLK4 PTYPE0 ACK1 PCLK TXON 8KSYNC TXSER7 TXCHN7_0 TXMSYNC7 RXSERCLK7 RXCHN7_4 RXCHN7_1 TXCHN6_4 RXCASYNC7 TXCHN6_0 RXSERCLK6 TXCHN5_2 RXCHN5_4 RXLOS5 TXCHN4_0 TXOH4 RXCHN4_2 RXSER4 RXSERCLK4
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN AA9 AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 PIN NAME RXSER6 RXCHN6_0 TXOH5 TXSERCLK5 TXSER5 RXOHCLK5 RXSER5 TXCHN4_4 RXCRCSYNC5 GPIO1_0 TXCHCLK4 GPIO1_1 RXCHN4_1 RXCHN4_0 TXCHN7_2 RXSER7 TXMSYNC6 TXCHN6_3 TXCHN6_1 GPIO0_0 RXCHN6_4 RXCHN6_3 RXCHN6_2 RXOHCLK6 TXCHN5_4 TXCHN5_1 TXCHN5_0 TXMSYNC5 RXCHN5_2 RXCHN5_1 RXCASYNC5 TXCHN4_3
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN AB19 AB20 AB21 AB22 PIN NAME RXCHCLK5 TXOHCLK4 TXSER4 RXCHN4_3 POWER PINS Pin G11 G14 G16 J17 P17 T8 T10 T12 T14 T17 G10 G12 G15 H17 L16 R17 T7 T9 T11 T13 T15 Pin Name VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD18 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD GROUND PINS Pin F6 G6 G7 Pin Name VSS VSS VSS
12
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN G8 G9 G13 H6 H7 H16 J7 J16 K7 K16 L7 M16 N6 N7 N16 P6 P7 P16 R6 R7 R16 T6 T16 U6 H8 H9 H10 H11 H12 H13 H14 H15 PIN NAME VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
REV. V1.2.0
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN J8 J9 J10 J11 J12 J13 J14 J15 K8 K9 K10 K11 K12 K13 K14 K15 L8 L9 L10 L11 L12 L13 L14 L15 M8 M9 M10 M11 M12 M13 M14 M15 PIN NAME VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN N8 N9 N10 N11 N12 N13 N14 N15 P8 P9 P10 P11 P12 P13 P14 P15 R8 R9 R10 R11 R12 R13 R14 R15 PIN NAME VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
TABLE 2: 484 BALL LIST BY BALL NUMBER
PIN D5 D6 D7 E7 E8 F7 F8 G5 B4 F18 PIN NAME NC NC NC NC NC NC NC NC NC NC
NO CONNECT PINS A1 A3 A22 B2 C3 C4 C5 NC NC NC NC NC NC NC
13
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
2.0 PIN DESCRIPTIONS There are six types of pins defined throughout this pin description and the corresponding symbol is presented in table below. The per-channel pin is indicated by the channel number or the letter 'n' which is appended at the end of the signal name, for example, TxSERn, where "n" indicates channels 0 to 7. All output pins are "tristated" upon hardware RESET.
SYMBOL I O I/O GND PWR NC PIN TYPE Input Output Bidirectional Ground Power No Connect
The structure of the pin description is divided into fourteen groups, as presented in the table below TABLE 3: PIN DESCRIPTION STRUCTURE
SECTION Transmit System Side Interface Transmit Overhead Interface Receive Overhead Interface Receive System Side Interface Receive Line Interface Transmit Line Interface Timing Interface GPIO Interface JTAG Interface Microprocessor Interface Power Pins (3.3V) Power Pins (1.8V) Ground Pins No Connect Pins PAGE NUMBER page 15 page 23 page 25 page 26 page 34 page 35 page 36 page 38 page 39 page 40 page 49 page 50 page 51 page 53
14
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxSER0/ TxPOS0 TxSER1/ TxPOS1 TxSER2/ TxPOS2 TxSER3/ TxPOS3 TxSER4/ TxPOS4 TxSER5/ TxPOS5 TxSER6/ TxPOS6 TxSER7/ TxPOS7 420 PKG 484 PKG BALL# BALL # D11 D17 E23 K26 AB21 AB15 AB9 AE3 F12 C15 D20 K18 AB21 AA13 U10 W3 TYPE I OUTPUT DRIVE(MA) DESCRIPTION Transmit Serial Data Input (TxSERn)/Transmit Positive Digital Input (TxPOSn): The exact function of these pins depends on the mode of operation selected, as described below. DS1/E1 Mode - TxSERn These pins function as the transmit serial data input on the system side interface, which are latched on the rising edge of the TxSERCLKn pin. Any payload data applied to this pin will be inserted into an outbound DS1/E1 frame and output to the line. In DS1 mode, the framing alignment bits, facility data link bits, CRC-6 bits, and signaling information can also be inserted from this input pin if configured appropriately. In E1 mode, all data intended to be transported via Time Slots 1 through 15 and Time slots 17 through 31 must be applied to this input pin. Data intended for Time Slots 0 and 16 can also be applied to this input pin If configured accordingly. DS1 or E1 High-Speed Multiplexed Mode* - TxSERn In this mode, these pins are used as the high-speed multiplexed data input pin on the system side. High-speed multiplexed data of channels 0-3 must be applied to TxSER0 and high-speed multiplexed data of channels 4-7 must be applied to TxSER4 in a byte or bit-interleaved way. The framer latches in the multiplexed data on TxSER0 and TxSER4 using TxMSYNC/TxINCLK and demultiplexes this data into 4 serial streams. The LIU block will then output the data to the line interface using TxSERCLKn. DS1 or E1 Framer Bypass Mode - TxPOSn In this mode, TxSERn is used for the positive digital input pin (TxPOSn) to the LIU. NOTE: 1. *High-speed multiplexed modes include (For T1/E1) 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bit-multiplexed mode. In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care). These 8 pins are internally pulled "High" for each channel.
REV. V1.2.0
2.
3.
15
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxSERCLK0/ TxLINECLK0 TxSERCLK1/ TxLINECLK1 TxSERCLK2/ TxLINECLK2 TxSERCLK3/ TxLINECLK3 TxSERCLK4/ TxLINECLK4 TxSERCLK5/ TxLINECLK5 TxSERCLK6/ TxLINECLK6 TxSERCLK7/ TxLINECLK7 420 PKG 484 PKG BALL# BALL # A11 C19 D22 K24 AE23 AF15 AE6 AB5 C11 B17 E17 J21 Y18 AA12 U9 V7 TYPE I/O OUTPUT DRIVE(MA) 12 DESCRIPTION Transmit Serial Clock (TxSERCLKn)/Transmit Line Clock (TxSERCLKn): The exact function of these pins depends on the mode of operation selected, as described below. In Base-Rate Mode (1.544MHz/2.048MHz) - TxSERCLKn: This clock signal is used by the transmit serial interface to latch the contents on the TxSERn pins into the T1/E1 framer on the rising edge of the TxSERCLKn. These pins can be configured as input or output as described below. When TxSERCLKn is configured as Input: These pins will be inputs if the TxSERCLK is chosen as the timing source for the transmit framer. Users must provide a 1.544MHz clock rate to this input pin for T1 mode of operation, and 2.048MHz clock rate in E1 mode. When TxSERCLKn is configured as Output: These pins will be outputs if either the recovered line clock or the MCLK PLL is chosen as the timing source for the T1/E1 transmit framer. The transmit framer will output a 1.544MHz clock rate in T1 mode of operation, and a 2.048MHz clock rate in E1 mode. DS1/E1 High-Speed Backplane Modes* - TxSERCLKn as INPUT ONLY In this mode, TxSERCLK is an optional clock signal input which is used as the timing source for the transmit line interface, and is only required if TxSERCLK is chosen as the timing source for the transmit framer. If TxSERCLK is chosen as the timing source, system equipment should provide 1.544MHz (For T1 mode) or 2.048MHz (For E1 mode) to the TxSERCLKn pins on each channel. TxSERCLK is not required if either the recovered clock or MCLK PLL is chosen as the timing source of the device. High speed or multiplexed data is latched into the device using the TxMSYNC/TxINCLK high-speed clock signal. DS1 or E1 Framer Bypass Mode - TxLINECLKn In this mode, TxSERCLKn is used as the transmit line clock (TxLINECLK) to the LIU. NOTE: *High-speed backplane modes include (For T1/E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bit-multiplexed mode.
NOTE: In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care). NOTE: These 8 pins are internally pulled "High" for each channel.
16
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxSYNC0/ TxNEG0 TxSYNC1/ TxNEG1 TxSYNC2/ TxNEG2 TxSYNC3/ TxNEG3 TxSYNC4/ TxNEG4 TxSYNC5/ TxNEG5 TxSYNC6/ TxNEG6 TxSYNC7/ TxNEG7 420 PKG 484 PKG BALL# BALL # A9 C16 B24 K22 AF24 AF16 AD8 AE4 B9 F14 C20 J20 Y17 V13 AA4 AA2 TYPE I/O OUTPUT DRIVE(MA) 12 DESCRIPTION Transmit Single Frame Sync Pulse (TxSYNCn) / Transmit Negative Digital Input (TxNEGn): The exact function of these pins depends on the mode of operation selected, as described below. DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxSYNCn: These TxSYNCn pins are used to indicate the single frame boundary within an outbound T1/E1 frame. In both DS1 or E1 mode, the single frame boundary repeats every 125 microseconds (8kHz). In DS1/E1 base rate, TxSYNCn can be configured as either input or output as described below. When TxSYNCn is configured as an Input: Users must provide a signal which must pulse "High" for one period of TxSERCLK during the first bit of an outbound DS1/ E1 frame. It is imperative that the TxSYNC input signal be synchronized with the TxSERCLK input signal. When TxSYNCn is configured as an Output: The transmit T1/E1 framer will output a signal which pulses "High" for one period of TxSERCLK during the first bit of an outbound DS1/E1 frame. DS1/E1 High-Speed Backplane Modes* - TxSYNCn as INPUT ONLY: In this mode, TxSYNCn must be an input regardless of the clock source that is chosen to be the timing source for the transmit framer. In 2.048MVIP/4.096/8.192MHz high-speed modes, TxSYNCn pins must be pulsed 'High' for one period of TxSERCLK during the first bit of the outbound T1/E1 frame. In HMVIP mode, TxSYNC0 and TxSYNC4 must be pulsed 'High' for 4 clock cycles of the TxMSYNC/TxINCLK signal in the position of the first two and the last two bits of a multiplexed frame. In H.100 mode, TxSYNC0 and TxSYNC4 must be pulsed 'High' for 2 clock cycles of the TxMSYNC/TxINCLK signal in the position of the first and the last bit of a multiplexed frame. DS1 or E1 Framer Bypass Mode - TxNEGn In this mode, TxSYNCn is used as the negative digital input pin (TxNEG) to the LIU. NOTE: *High-speed backplane modes include (For T1/E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bit-multiplexed mode.
REV. V1.2.0
NOTE: In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care). NOTE: These 8 pins are internally pulled "Low" for each channel.
17
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxMSYNC0/ TxINCLK0 TxMSYNC1/ TxINCLK1 TxMSYNC2/ TxINCLK2 TxMSYNC3/ TxINCLK3 TxMSYNC4/ TxINCLK4 TxMSYNC5/ TxINCLK5 TxMSYNC6/ TxINCLK6 TxMSYNC7/ TxINCLK7 420 PKG 484 PKG BALL# BALL # B10 A17 C24 L24 AC21 AD16 AC8 AF2 A9 B15 E18 K20 U17 AB14 AB3 W5 TYPE I/O OUTPUT DRIVE(MA) 12 DESCRIPTION Multiframe Sync Pulse (TxMSYNCn) / Transmit Input Clock (TxINCLKn) The exact function of these pins depends on the mode of operation selected, as described below. DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) - TxMSYNCn In this mode, these pins are used to indicate the multi-frame boundary within an outbound DS1/E1 frame. In DS1 ESF mode, TxMSYNCn repeats every 3ms. In DS1 SF mode, TxMSYNCn repeats every 1.5ms. In E1 mode, TxMSYNCn repeats every 2ms. If TxMSYNCn is configured as an input, TxMSYNCn must pulse "High" for one period of TxSERCLK during the first bit of an outbound DS1/E1 multi-frame. It is imperative that the TxMSYNC input signal be synchronized with the TxSERCLK input signal. If TxMSYNCn is configured as an output, the transmit section of the T1/E1 framer will output and pulse TxMSYNC "High" for one period of TxSERCLK during the first bit of an outbound DS1/E1 frame. DS1/E1 High-Speed Backplane Modes* - (TxINCLKn as INPUT ONLY) In this mode, this pin must be used as the high-speed input clock pin (TxINCLKn) for the backplane interface to latch in high-speed or multiplexed data on the TxSERn pin. The frequency of TxINCLK is presented in the table below. OPERATION MODE 2.048MVIP non-multiplexed 4.096MHz non-multiplexed 8.192MHz non-multiplexed 12.352MHz Bit-multiplexed (DS1 ONLY) 16.384MHz Bit-multiplexed 16.384 HMVIP Byte-multiplexed 16.384 H.100 Byte-multiplexed NOTES: 1. *High-speed backplane modes include (For T1/E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bit-multiplexed mode. In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care). These 8 pins are internally pulled "Low" for each channel. FREQUENCY OF TXINCLK(MHZ) 2.048 4.096 8.192 12.352
16.384 16.384 16.384
2.
3.
18
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxCHCLK0 TxCHCLK1 TxCHCLK2 TxCHCLK3 TxCHCLK4 TxCHCLK5 TxCHCLK6 TxCHCLK7 420 PKG 484 PKG BALL# BALL # A12 E17 B26 J22 AD22 AE16 AD10 AB2 C12 A16 E19 G22 AA19 Y13 V11 V5 TYPE O OUTPUT DRIVE(MA) 8 DESCRIPTION Transmit Channel Clock Output Signal (TxCHCLKn): The exact function of this pin depends on whether or not the transmit framer enables the transmit fractional/signaling interface to input fractional data, as described below. If transmit fractional/signaling interface is disabled: This pin indicates the boundary of each time slot of an outbound DS1/E1 frame. In T1 mode, each of these output pins is a 192kHz clock which pulses "High" during the LSB of each 24 time slots. In E1 mode, each of these output pins is a 256kHz clock which pulses "High" during the LSB of each 32 time slots. The Terminal Equipment can use this clock signal to sample the TxCHN0 through TxCHN4 time slot identifier pins to determine which time slot is being processed. If transmit fractional/signaling interface is enabled: TxCHCLKn is the fractional interface clock which either outputs a clock signal for the time slot that has been configured to input fractional data, or outputs an enable signal for the fractional time slot so that fractional data can be clocked into the device using the TxSERCLK pin. NOTE: Transmit fractional interface can be enabled by programming to bit 4 - TxFr1544/TxFr2048 bit from register 0xn120 to `1'.
REV. V1.2.0
19
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxCHN0_0/ TxSIG0 TxCHN1_0/ TxSIG1 TxCHN2_0/ TxSIG2 TxCHN3_0/ TxSIG3 TxCHN4_0/ TxSIG4 TxCHN5_0/ TxSIG5 TxCHN6_0/ TxSIG6 TxCHN7_0/ TxSIG7 420 PKG 484 PKG BALL# BALL # D12 C18 F22 L22 AD21 AC15 AB10 AC5 B11 C16 C21 K19 W16 AB13 W11 W4 TYPE I/O OUTPUT DRIVE(MA) 8 DESCRIPTION Transmit Time Slot Octet Identifier Output 0 (TxCHNn_0) / Transmit Serial Signaling Input (TxSIGn): The exact function of these pins depends on whether or not the transmit framer enables the transmit fractional/signaling interface, as described below: If transmit fractional/signaling interface is disabled TxCHNn_0: These output pins (TxCHNn_4 through TxCHNn_0) reflect the five-bit binary value of the current time slot being processed by the transmit serial interface. Terminal Equipment can use the TxCHCLK to sample the five output pins of each channel in order to identify the time slot being processed. This pin indicates the Least Significant Bit (LSB) of the time slot channel being processed. If transmit fractional/signaling interface is enabled TxSIGn: These pins can be used to input robbed-bit signaling data to be inserted within an outbound DS1 frame or to input Channel Associated Signaling (CAS) data within an outbound E1 frame, as described below. T1 Mode: Signaling data (A,B,C,D) of each channel must be provided on bit 4,5,6,7 of each time slot on the TxSIG pin if 16code signaling is used. If 4-code signaling is selected, signaling data (A,B) of each channel must be provided on bit 4, 5 of each time slot on the TxSIG pin. If 2-code signaling is selected, signaling data (A) of each channel must be provided on bit 4 of each time slot on the TxSIG pin. E1 Mode: Signaling data in E1 mode can be provided on the TxSIGn pins on a time-slot-basis as in T1 mode, or it can be provided on time slot 16 only via the TxSIGn input pins. In the latter case, signaling data (A,B,C,D) of channel 1 and channel 17 must be inserted on the TxSIGn pin during time slot 16 of frame 1, signaling data (A,B,C,D) of channel 2 and channel 18 must be inserted on the TxSIGn pin during time slot 16 of frame 2...etc. The CAS multiframe Alignments bits (0000 bits) and the extra bits/alarm bit (xyxx) must be inserted on the TxSIGn pin during time slot 16 of frame 0. NOTE: Transmit fractional interface can be enabled by programming to bit 4 - TxFr1544/TxFr2048 bit from register 0xn120 to `1'. These 8 pins are internally pulled "Low" for each channel.
NOTE:
20
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxCHN0_1/ TxFrTD0 TxCHN1_1/ TxFrTD1 TxCHN2_1/ TxFrTD2 TxCHN3_1/ TxFrTD3 TxCHN4_1/ TxFrTD4 TxCHN5_1/ TxFrTD5 TxCHN6_1/ TxFrTD6 TxCHN7_1/ TxFrTD7 420 PKG 484 PKG BALL# BALL # B12 D18 D25 L25 AF22 AD15 AF9 AD3 A11 D15 E20 K17 U15 AB12 AB5 V8 TYPE I/O OUTPUT DRIVE(MA) 8 DESCRIPTION Transmit Time Slot Octet Identifier Output 1 (TxCHNn_1) / Transmit Serial Fractional Input (TxFrTDn): The exact function of these pins depends on whether or not the transmit framer enables the transmit fractional/signaling interface, as described below: If transmit fractional/signaling interface is disabled TxCHNn_1 These output signals (TxCHNn_4 through TxCHNn_0) reflect the five-bit binary value of the current time slot being processed by the transmit serial interface. Terminal Equipment can use the TxCHCLK to sample the five output pins of each channel in order to identify the time slot being processed. This pin indicates Bit 1 of the time slot channel being processed. If transmit fractional/signaling interface is enabled TxFrTDn These pins are used as the fractional data input pins to input fractional DS1/E1 payload data which will be inserted within an outbound DS1/E1 frame. In this mode, terminal equipment can use either TxCHCLK or TxSERCLK to clock in fractional DS1/E1 payload data depending on the framer configuration. NOTES: 1. Transmit fractional/Signaling interface can be enabled by programming to bit 4 - TxFr1544/ TxFr2048 bit from register 0xn120 to `1'. These 8 pins are internally pulled "Low" for each channel.
REV. V1.2.0
2. TxCHN0_2/ Tx32MHz0 TxCHN1_2/ Tx32MHz1 TxCHN2_2/ Tx32MHz2 TxCHN3_2/ Tx32MHz3 TxCHN4_2/ Tx32MHz4 TxCHN5_2/ Tx32MHz5 TxCHN6_2/ Tx32MHz6 TxCHN7_2/ Tx32MHz7 A13 B19 C26 M22 AC20 AE15 AE9 AD2 D12 F15 F19 K22 Y16 W13 AA5 AB1 O 8
Transmit Time Slot Octet Identifier Output 2 (TxCHNn_2) / Transmit 32.678MHz Clock Output (Tx32MHZ): The exact function of these pins depends on whether or not the transmit framer enables the transmit fractional/signaling interface, as described below: If transmit fractional/signaling interface is disabled TxCHNn_2 These output signals (TxCHNn_4 through TxCHNn_0) reflect the five-bit binary value of the current time slot being processed by the transmit serial interface. Terminal Equipment can use the TxCHCLK to sample the five output pins of each channel in order to identify the time slot being processed. This pin indicates Bit 2 of the time slot channel being processed. If transmit fractional/signaling interface is enabled Tx32MHz These pins are used to output a 32.678MHz clock reference which is derived from the MCLKIN input pin. NOTE: Transmit fractional interface can be enabled by programming to bit 4 - TxFr1544/TxFr2048 bit from register 0xn120 to `1'.
21
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT SYSTEM SIDE INTERFACE
SIGNAL NAME TxCHN0_3/ TxOHSYNC0 TxCHN1_3/ TxOHSYNC1 TxCHN2_3/ TxOHSYNC2 TxCHN3_3/ TxOHSYNC3 TxCHN4_3/ TxOHSYNC4 TxCHN5_3/ TxOHSYNC5 TxCHN6_3/ TxOHSYNC6 TxCHN7_3/ TxOHSYNC7 420 PKG 484 PKG BALL# BALL # E13 A20 F23 M24 AE20 AB14 AF8 AC3 F13 C17 D21 L19 AB18 Y12 AB4 Y2 O TYPE O OUTPUT DRIVE(MA) 8 DESCRIPTION Transmit Time Slot Octet Identifier Output 3 (TxCHNn_3) / Transmit Overhead Synchronization Pulse (TxOHSYNCn): The exact function of these pins depends on whether or not the transmit framer enables the transmit fractional/signaling interface, as described below: If transmit fractional/signaling interface is disabled TxCHNn_3 These output signals (TxCHNn_4 through TxCHNn_0) reflect the five-bit binary value of the current time slot being processed by the transmit serial interface. Terminal Equipment can use the TxCHCLK to sample the five output pins of each channel in order to identify the time slot being processed. This pin indicates Bit 3 of the time slot channel being processed. If transmit fractional/signaling interface is enabled TxOHSYNCn These pins are used to output an Overhead Synchronization Pulse which indicates the first bit of each multi-frame. NOTE: Transmit fractional interface can be enabled by programming to bit 4 - TxFr1544/TxFr2048 bit from register 0xn120 to `1'.
TxCHN0_4 TxCHN1_4 TxCHN2_4 TxCHN3_4 TxCHN4_4 TxCHN5_4 TxCHN6_4 TxCHN7_4
C14 A21 E25 M26 AD19 AC14 AE8 AB4
A13 G17 C22 L17 AA16 AB11 W9 U7
O
8
Transmit Time Slot Octet Identifier Output-Bit 4 (TxCHNn_4): These output signals (TxCHNn_4 through TxCHNn_0) reflect the five-bit binary value of the current time slot being processed by the transmit serial interface. Terminal Equipment can use the TxCHCLK to sample the five output pins of each channel in order to identify the time slot being processed. This pin indicates the Most Significant Bit (MSB) of the time slot channel being processed.
22
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TRANSMIT OVERHEAD INTERFACE
SIGNAL NAME TxOH0 TxOH1 TxOH2 TxOH3 TxOH4 TxOH5 TxOH6 TxOH7 420 PKG BALL # C12 A18 E26 J25 AF25 AD14 AF10 AC2 484 PKG BALL # E13 B16 E21 J18 W17 AA11 U11 AA1 TYPE I OUTPUT DRIVE(MA) DESCRIPTION Transmit Overhead Input (TxOHn): The exact function of these pins depends on the mode of operation selected, as described below. DS1 Mode These pins operate as the source of Datalink bits which will be inserted into the Datalink bits within an outbound DS1 frame if the framer is configured accordingly. Datalink Equipment can provide data to this input pin using the TxOHCLKn clock at either 2kHz or 4kHz depending on the transmit datalink bandwidth selected. NOTE: This input pin will be disabled if the framer is using the Transmit HDLC Controller, or the TxSER input as the source for the Data Link Bits. E1 Mode These pins operate as the source of Datalink bits or Signaling bits depending on the framer configuration, as described below. Sourcing Datalink bits from TxOHn: The E1 transmit framer will output a clock edge on TxOHCLKn for each Sa bit that has been configured to carry datalink information. Terminal equipment can then use TxOHCLKn to provide datalink bits on TxOHn to be inserted into the Sa bits within an outbound E1 frame. Sourcing Signaling bits from TxOHn: Users must provide signaling data on TxOHn pins on time slot 16 only. Signaling data (A,B,C,D) of channel 1 and channel 17 must be inserted on the TxOHn pin during time slot 16 of frame 1, signaling data (A,B,C,D) of channel 2 and channel 18 must be inserted on the TxOHn pin during time slot 16 of frame 2...etc. The CAS multiframe Alignments bits (0000 bits) and the extra bits/alarm bit (xyxx) must be inserted on the TxOHn pin during time slot 16 of frame 0. NOTE: These 8 pins are internally pulled "Low" for each channel.
REV. V1.2.0
23
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT OVERHEAD INTERFACE
SIGNAL NAME TxOHCLK0 TxOHCLK1 TxOHCLK2 TxOHCLK3 TxOHCLK4 TxOHCLK5 TxOHCLK6 TxOHCLK7 420 PKG BALL # E11 A19 E24 K23 AF23 AB16 AC10 AE1 484 PKG BALL # A10 A17 B22 H22 AB20 U13 AA7 V6 TYPE O OUTPUT DRIVE(MA) 8 DESCRIPTION Transmit OH Serial Clock Output Signal(TxOHCLKn) This pin functions as an overhead output clock signal for the transmit overhead interface, and its function is explained below. DS1 Mode If the TxOH pins have been configured to be the source for Datalink bits, the DS1 transmit framer will provide a clock edge for each Data Link Bit. In DS1 ESF mode, the TxOHCLK can either be a 2kHz or 4kHz output signal depending on the selection of Data Link Bandwidth (Register 0xn10A). Data Link Equipment can provide data to the TxOHn pin on the rising edge of TxOHCLK. The framer latches the data on the falling edge of this clock signal. E1 Mode If the TxOH pins have been configured to be the source for Data Link bits, the E1 transmit framer will provide a clock edge for each National Bit (Sa bits) that has been configured to carry data link information. (Register 0xn10A)
24
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
RECEIVE OVERHEAD INTERFACE
SIGNAL NAME RxOH0 RxOH1 RxOH2 RxOH3 RxOH4 RxOH5 RxOH6 RxOH7 420 PKG BALL # C11 B15 D21 F26 AA22 AE17 AE14 AF7 484 PKG BALL # D11 A14 D18 H18 V18 Y14 U12 V10 TYPE O OUTPUT DRIVE(MA) 8 DESCRIPTION Receive Overhead Output (RxOHn): These pins function as the Receive Overhead output, or Receive Signaling Output depending on the receive framer configuration, as described below. DS1 Mode If the RxOH pins have been configured as the destination for the Data Link bits within an inbound DS1 frame, datalink bits will be output to the RxOHn pins at either 2kHz or 4kHz depending on the Receive datalink bandwidth selected. (Register 0xn10C). If configured appropriately, signaling information in the receive signaling array registers (Registers 0xn5000xn51F) can also be output to the RxOHn output pins. E1 Mode These output pins will always output the contents of the National Bits (Sa4 through Sa8) if these Sa bits have been configured to carry Data Link information (Register 0xn10C). The Receive Overhead Output Interface will provide a clock edge on RxOHCLKn for each Sa bit carrying Data Link information. If configured appropriately, signaling information in the receive signaling array registers (Registers 0xn5000xn51F) can also be output to the RxOHn output pins. Receive Overhead Clock Output (RxOHCLKn): This pin functions as an overhead output clock signal for the receive overhead interface, and its function is explained below. DS1 Mode If the RxOH pins have been configured to be the destination for Datalink bits, the DS1 transmit framer will output a clock edge for each Data Link Bit. In DS1 ESF mode, the RxOHCLK can either be a 2kHz or 4kHz output signal depending on the selection of Data Link Bandwidth (Register 0xn10C). Data Link Equipment can clock out datalink bits on the RxOHn pin using this clock signal. E1 Mode The E1 receive framer provides a clock edge for each National Bit (Sa bits) that is configured to carry data link information. Data Link Equipment can clock out datalink bits on the RxOHn pin using this clock signal.
RxOHCLK0 RxOHCLK1 RxOHCLK2 RxOHCLK3 RxOHCLK4 RxOHCLK5 RxOHCLK6 RxOHCLK7
B9 D16 E21 G24 Y22 AF17 AE13 AE7
F11 D14 A21 E22 V19 AA14 AB10 Y6
O
8
25
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxSYNC0/ RxNEG0 RxSYNC1/ RxNEG1 RxSYNC2/ RxNEG2 RxSYNC3/ RxNEG3 RxSYNC4/ RxNEG4 RxSYNC5/ RxNEG5 RxSYNC6/ RxNEG6 RxSYNC7/ RxNEG7 420 PKG BALL# D9 D15 D19 G23 AE26 AF19 AB11 AC6 484 PKG BALL # A8 E16 A18 D22 Y20 Y15 AA6 Y3 TYPE I/O OUTPUT DRIVE (MA) 12 DESCRIPTION Receive Single Frame Sync Pulse (RxSYNCn): The exact function of these pins depends on the mode of operation selected, as described below. DS1/E1 Base Rate Mode (1.544MHz/2.048MHz) RxSYNCn: These RxSYNCn pins are used to indicate the single frame boundary within an inbound T1/E1 frame. In both DS1 or E1 mode, the single frame boundary repeats every 125 microseconds (8kHz). In DS1/E1 base rate, RxSYNCn can be configured as either input or output depending on the slip buffer configuration as described below. When RxSYNCn is configured as an Input: Users must provide a signal which must pulse "High" for one period of RxSERCLK and repeats every 125S. The receive serial Interface will output the first bit of an inbound DS1/E1 frame during the provided RxSYNC pulse. NOTE: It is imperative that the RxSYNC input signal be synchronized with the RxSERCLK input signal. When RxSYNCn is configured as an Output: The receive T1/E1 framer will output a signal which pulses "High" for one period of RxSERCLK during the first bit of an inbound DS1/E1 frame. DS1/E1 High-Speed Backplane Modes* - RxSYNCn as INPUT ONLY: In this mode, RxSYNCn must be an input regardless of the slip buffer configuration. In 2.048MVIP/4.096/ 8.192MHz high-speed modes, RxSYNCn pins must be pulsed 'High' for one period of RxSERCLK during the first bit of the inbound T1/E1 frame. In HMVIP mode, RxSYNCn must be pulsed 'High' for 4 clock cycles of the RxSERCLK signal in the position of the first two and the last two bits of a multiplexed frame. In H.100 mode, RxSYNCn must be pulsed 'High' for 2 clock cycles of the RxSERCLK signal in the position of the first and the last bit of a multiplexed frame. DS1 or E1 Framer Bypass Mode - RxNEGn In this mode, RxSYNCn is used as the Receive negative digital output pin (RxNEG) from the LIU. NOTE: *High-speed backplane modes include (For T1/ E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bitmultiplexed mode. NOTE: In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care).
NOTE: These 8 pins are internally pulled "Low" for each channel.
26
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxCRCSYNC0 RxCRCSYNC1 RxCRCSYNC2 RxCRCSYNC3 RxCRCSYNC4 RxCRCSYNC5 RxCRCSYNC6 RxCRCSYNC7 RxCASYNC0 RxCASYNC1 RxCASYNC2 RxCASYNC3 RxCASYNC4 RxCASYNC5 RxCASYNC6 RxCASYNC7 420 PKG BALL# B8 D13 E20 G25 AB25 AF21 AE10 AD5 E10 E15 A23 H23 AD24 AE19 AC9 AF6 484 PKG BALL # B8 B12 A20 G20 Y21 AA17 Y9 V9 C10 B14 C18 F21 V17 AB17 Y8 W10 TYPE O OUTPUT DRIVE (MA) 12 DESCRIPTION Receive Multiframe Sync Pulse (RxCRCSYNCn): The RxCRCSYNCn pins are used to indicate the receive multi-frame boundary. These pins pulse "High" for one period of RxSERCLK when the first bit of an inbound DS1/E1 Multi-frame is being output on the RxCRCSYNCn pin.
REV. V1.2.0
* In DS1 ESF mode, RxCRCSYNCn repeats every 3ms * In DS1 SF mode, RxCRCSYNCn repeats every 1.5ms * In E1 mode, RxCRCSYNCn repeats every 2ms.
O 12 Receive CAS Multiframe Sync Pulse (RxCASYNCn): - E1 Mode Only The RxCASYNCn pins are used to indicate the E1 CAS Multif-frame boundary. These pins pulse "High" for one period of RxSERCLK when the first bit of an E1 CAS Multi-frame is being output on the RxCASYNCn pin.
27
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxSERCLK0/ RxLINECLK0 RxSERCLK1/ RxLINECLK1 RxSERCLK2/ RxLINECLK2 RxSERCLK3/ RxLINECLK3 RxSERCLK4/ RxLINECLK4 RxSERCLK5/ RxLINECLK5 RxSERCLK6/ RxLINECLK6 RxSERCLK7/ RxLINECLK7 420 PKG BALL# A6 B13 C20 H25 AD26 AC19 AB12 AB6 484 PKG BALL # D9 A12 B18 H20 W20 V16 W12 W6 TYPE I/O OUTPUT DRIVE (MA) 12 DESCRIPTION Receive Serial Clock Signal (RxSERCLKn) / Receive Line Clock (RxLINECLKn): The exact function of these pins depends on the mode of operation selected, as described below. In Base-Rate Mode (1.544MHz/2.048MHz) - RxSERCLKn: These pins are used as the receive serial clock on the system side interface which can be configured as either input or output. The receive serial interface outputs data on RxSERn on the rising edge of RxSERCLKn. When RxSERCLKn is configured as Input: These pins will be inputs if the slip buffer on the Receive path is enabled. System side equipment must provide a 1.544MHz clock rate to this input pin for T1 mode of operation, and 2.048MHz clock rate in E1 mode. When RxSERCLKn is configured as Output: These pins will be outputs if slip buffer is bypassed. The receive framer will output a 1.544MHz clock rate in T1 mode of operation, and a 2.048MHz clock rate in E1 mode. DS1/E1 High-Speed Backplane Modes* - (RxSERCLK as INPUT ONLY) In this mode, this pin must be used as the high-speed input clock for the backplane interface to output highspeed or multiplexed data on the RxSERn pin. The frequency of RxSERCLK is presented in the table below. OPERATION MODE 2.048MVIP non-multiplexed 4.096MHz non-multiplexed 8.192MHz non-multiplexed 12.352MHz Bit-multiplexed (DS1 ONLY) 16.384MHz Bit-multiplexed 16.384 HMVIP Byte-multiplexed 16.384 H.100 Byte-multiplexed NOTES: 1. *High-speed backplane modes include (For T1/ E1) 2.048MVIP, 4.096MHz, 8.192MHz, 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bitmultiplexed mode. 2. For DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care). FREQUENCY OF RXSERCLK(MHZ) 2.048 4.096 8.192 12.352
16.384 16.384 16.384
28
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxSERCLK0/ RxLINECLK0 RxSERCLK1/ RxLINECLK1 RxSERCLK2/ RxLINECLK2 RxSERCLK3/ RxLINECLK3 RxSERCLK4/ RxLINECLK4 RxSERCLK5/ RxLINECLK5 RxSERCLK6/ RxLINECLK6 RxSERCLK7/ RxLINECLK7 RxSER0/ RxPOS0 RxSER1/ RxPOS1 RxSER2/ RxPOS2 RxSER3/ RxPOS3 RxSER4/ RxPOS4 RxSER5/ RxPOS5 RxSER6/ RxPOS6 RxSER7/ RxPOS7 420 PKG BALL# A6 B13 C20 H25 AD26 AC19 AB12 AB6 484 PKG BALL # D9 A12 B18 H20 W20 V16 W12 W6 NOTE: These 8 pins are internally pulled "High" for each channel. TYPE I/O OUTPUT DRIVE (MA) 12 DESCRIPTION (Continued) DS1 or E1 Framer Bypass Mode - RxLINECLKn In this mode, RxSERCLKn is used as the Receive Line Clock output pin (RxLineClk) from the LIU.
REV. V1.2.0
C7 B14 C21 D26 AC25 AC18 AE12 AB7
B7 E14 D17 F20 W19 AA15 AA9 AB2
O
12
Receive Serial Data Output (RxSERn): The exact function of these pins depends on the mode of operation selected, as described below. DS1/E1 Mode - RxSERn These pins function as the receive serial data output on the system side interface, which are updated on the rising edge of the RxSERCLKn pin. All the framing alignment bits, facility data link bits, CRC bits, and signaling information will also be extracted to this output pin. DS1 or E1 High-Speed Multiplexed Mode* - RxSERn In this mode, these pins are used as the high-speed multiplexed data output pin on the system side. High-speed multiplexed data of channels 0-3 will output on RxSER0 and high-speed multiplexed data of channels 4-7 will output on RxSER4 in a byte or bit-interleaved way. The framer outputs the multiplexed data on RxSER0 and RxSER4 using the high-speed input clock (RxSERCLKn). DS1 or E1 Framer Bypass Mode In this mode, RxSERn is used as the positive digital output pin (RxPOSn) from the LIU. NOTE: *High-speed multiplexed modes include (For T1/ E1) 16.384MHz HMVIP, H.100, Bit-multiplexed modes, and (For T1 only) 12.352MHz Bitmultiplexed mode. NOTE: In DS1 high-speed modes, the DS-0 data is mapped into an E1 frame by ignoring every fourth time slot (don't care).
29
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxCHN0_0/ RxSig0 RxCHN1_0/ RxSig1 RxCHN2_0/ RxSig2 RxCHN3_0/ RxSig3 RxCHN4_0/ RxSig4 RxCHN5_0/ RxSig5 RxCHN6_0/ RxSig6 RxCHN7_0/ RxSig7 420 PKG BALL# D8 D14 A22 G26 AD25 AD18 AC13 AB8 484 PKG BALL # A7 B13 B19 H19 AA22 U14 AA10 Y7 TYPE O OUTPUT DRIVE (MA) 8 DESCRIPTION Receive Time Slot Octet Identifier Output (RxCHNn_0) / Receive Serial Signaling Output (RxSIGn): The exact function of these pins depends on whether or not the receive framer enables the receive fractional/signaling interface, as described below: If receive fractional/signaling interface is disabled RxCHNn_0: These output pins (RxCHNn_4 through RxCHNn_0) reflect the five-bit binary value of the current time slot being output by the receive serial interface. System equipment can use the RxCHCLKn to sample the five output pins of each channel to identify the time slot being output on these pins. RxCHNn_0 indicates the Least Significant Bit (LSB) of the time slot channel being output. If receive fractional/signaling interface is enabled RxSIGn: These pins can be used to output robbed-bit signaling data within an inbound DS1 frame or to output Channel Associated Signaling (CAS) data within an inbound E1 frame, as described below. T1 Mode: Signaling data (A,B,C,D) of each channel will be output on bit 4,5,6,7 of each time slot on the RxSIG pin if 16-code signaling is used. If 4-code signaling is selected, signaling data (A,B) of each channel will be output on bit 4, 5 of each time slot on the RxSIG pin. If 2code signaling is selected, signaling data (A) of each channel will be output on bit 4 of each time slot on the RxSIG pin. E1 Mode: Signaling data in E1 mode will be output on the RxSIGn pins on a time-slot-basis as in T1 mode, or it can be output on time slot 16 only via the RxSIGn output pins. In the latter case, signaling data (A,B,C,D) of channel 1 and channel 17 will be output on the RxSIGn pin during time slot 16 of frame 1, signaling data (A,B,C,D) of channel 2 and channel 18 will be output on the RxSIGn pin during time slot 16 of frame 2...etc. The CAS multiframe Alignments bits (0000 bits) and the extra bits/alarm bit (xyxx) will be output on the RxSIGn pin during time slot 16 of frame 0. NOTE: Receive Fractional/signaling interface can be enabled by programming to bit 4 - RxFr1544/ RxFr2048 bit from register 0xn122 to `1'.
30
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxCHN0_1/ RxFrTD0 RxCHN1_1/ RxFrTD1 RxCHN2_1/ RxFrTD2 RxCHN13_1/ RxFrTD3 RxCHN4_1/ RxFrTD4 RxCHN5_1/ RxFrTD5 RxCHN6_1/ RxFrTD6 RxCHN7_1/ RxFrTD7 420 PKG BALL# E9 E14 B22 H26 AE25 AF18 AB13 AC7 484 PKG BALL # C9 C13 C19 G21 AA21 AB16 V12 W8 TYPE O OUTPUT DRIVE (MA) 8 DESCRIPTION Receive Time Slot Octet Identifier Output Bit 1 (RxCHNn_1) / Receive Serial Fractional Output (RxFrTDn): The exact function of these pins depends on whether or not the receive framer enables the receive fractional/signaling interface, as described below: If receive fractional/signaling interface is disabled RxCHNn_1: These output pins (RxCHNn_4 through RxCHNn_0) reflect the five-bit binary value of the current time slot being output by the receive serial interface. System equipment can use the RxCHCLKn to sample the five output pins of each channel to identify the time slot being output on these pins. RxCHNn_1 indicates Bit 1 of the time slot channel being output. If receive fractional/signaling interface is enabled RxFrTDn: These pins are used as the fractional data output pins to output fractional DS1/E1 payload data within an inbound DS1/E1 frame. In this mode, system equipment can use either RxCHCLK or RxSERCLK to clock out fractional DS1/E1 payload data depending on the framer configuration. NOTE: Receive Fractional/Signaling interface can be enabled by programming to bit 4 - RxFr1544/ RxFr2048 bit from register 0xn122 to `1'.
REV. V1.2.0
RxCHN0_2/ RxCHN0 RxCHN1_2/ RxCHN1 RxCHN2_2/ RxCHN2 RxCHN3_2/ RxCHN3 RxCHN4_2/ RxCHN4 RxCHN5_2/ RxCHN5 RxCHN6_2/ RxCHN6 RxCHN7_2/ RxCHN7
C9 A15 C22 J23 AF26 AB17 AF12 AF4
D10 D13 F17 J19 W18 AB15 AB9 Y4
O
8
Receive Time Slot Octet Identifier Output-Bit 2 (RxCHNn_2) / Receive Time Slot Identifier Serial Output (RxCHNn): The exact function of these pins depends on whether or not the receive framer enables the receive fractional/signaling interface, as described below: If receive fractional/signaling interface is disabled RxCHNn_2: These output pins (RxCHNn_4 through RxCHNn_0) reflect the five-bit binary value of the current time slot being output by the receive serial interface. System equipment can use the RxCHCLKn to sample the five output pins of each channel to identify the time slot being output on these pins. RxCHNn_2 indicates Bit 2 of the time slot channel being output. If receive fractional/signaling interface is enabled RxCHNn These pins serially output the five-bit binary value of the time slot being output by the receive serial interface. NOTE: Receive Fractional/Signaling interface can be enabled by programming to bit 4 - RxFr1544/ RxFr2048 bit from register 0xn122 to `1'.
31
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxCHN0_3/ Rx8KHZ0 RxCHN1_3/ Rx8KHZ1 RxCHN2_3/ Rx8KHZ2 RxCHN3_3/ Rx8KHZ3 RxCHN4_3/ Rx8KHZ4 RxCHN5_3/ Rx8KHZ5 RxCHN6_3/ Rx8KHZ6 RxCHN7_3/ Rx8KHZ7 420 PKG BALL# C10 B16 C23 J26 AC23 AC17 AD12 AE5 484 PKG BALL # E11 A15 D19 H21 AB22 V14 AB8 AA3 TYPE O OUTPUT DRIVE (MA) 8 DESCRIPTION Receive Time Slot Octet Identifier Output-Bit 3 (RxCHNn_3) / Receive 8KHz Clock Output (Rx8KHZn): The exact function of these pins depends on whether or not the receive framer enables the receive fractional/signaling interface, as described below: If receive fractional/signaling interface is disabled RxCHNn_3: These output pins (RxCHNn_4 through RxCHNn_0) reflect the five-bit binary value of the current time slot being output by the receive serial interface. System equipment can use the RxCHCLKn to sample the five output pins of each channel to identify the time slot being output on these pins. RxCHNn_3 indicates Bit 3 of the time slot channel being output. If receive fractional/signaling interface is enabled Rx8KHZn: These pins output a reference 8KHz clock signal derived from the MCLKIN input. NOTE: Receive Fractional/Signaling interface can be enabled by programming to bit 4 - RxFr1544/ RxFr2048 bit from register 0xn122 to `1'.
RxCHN0_4/ RxSCLK0 RxCHN1_4/ RxSCLK1 RxCHN2_4/ RxSCLK2 RxCHN3_4/ RxSCLK3 RxCHN4_4/ RxSCLK4 RxCHN5_4/ RxSCLK5 RxCHN6_4/ RxSCLK6 RxCHN7_4/ RxSCLK7
A10 C17 A26 K25 AB22 AD17 AF11 AF3
B10 F16 B21 J22 Y19 W14 AB7 W7
O
8
Receive Time Slot Octet Identifier Output-Bit 4 (RxCHNn_4) / Receive Recovered Line Clock Output (RxSCLKn): The exact function of these pins depends on whether or not the receive framer enables the receive fractional/signaling interface, as described below: If receive fractional/signaling interface is disabled RxCHNn_4: These output pins (RxCHNn_4 through RxCHNn_0) reflect the five-bit binary value of the current time slot being output by the receive serial interface. System equipment can use the RxCHCLKn to sample the five output pins of each channel to identify the time slot being output on these pins. RxCHNn_4 indicates the Most Significant Bit (MSB) of the time slot channel being output. If receive fractional/signaling interface is enabled Receive Recovered Line Clock Output (RxSCLKn): These pins output the recovered T1/E1 line clock (1.544MHz in T1 mode and 2.048MHz in E1 mode) for each channel. NOTE: Receive Fractional/Signaling interface can be enabled by programming to bit 4 - RxFr1544/ RxFr2048 bit from register 0xn122 to `1'.
32
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION RECEIVE SYSTEM SIDE INTERFACE
SIGNAL NAME RxCHCLK0 RxCHCLK1 RxCHCLK2 RxCHCLK3 RxCHCLK4 RxCHCLK5 RxCHCLK6 RxCHCLK7 420 PKG BALL# A8 A14 A24 F25 AB24 AE21 AE11 AF5 484 PKG BALL # E10 E15 B20 G19 U18 AB19 AA8 Y5 TYPE O OUTPUT DRIVE (MA) 8 DESCRIPTION Receive Channel Clock Output (RxCHCLKn): The exact function of this pin depends on whether or not the receive framer enables the receive fractional/signaling interface to output fractional data, as described below. If receive fractional/signaling interface is disabled: This pin indicates the boundary of each time slot of an inbound DS1/E1 frame. In T1 mode, each of these output pins is a 192kHz clock which pulses "High" during the LSB of each 24 time slots. In E1 mode, each of these output pins is a 256kHz clock which pulses "High" during the LSB of each 32 time slots. System Equipment can use this clock signal to sample the RxCHN0 through RxCHN4 time slot identifier pins to determine which time slot is being output. If receive fractional/signaling interface is enabled: RxCHCLKn is the fractional interface clock which either outputs a clock signal for the time slot that has been configured to output fractional data, or outputs an enable signal for the fractional time slot so that fractional data can be clocked out of the device using the RxSERCLK pin. NOTE: Receive fractional interface can be enabled by programming to bit 4 - RxFr1544/RxFr2048 bit from register 0xn122 to `1'.
REV. V1.2.0
33
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
RECEIVE LINE INTERFACE
SIGNAL NAME RTIP0 RTIP1 RTIP2 RTIP3 RTIP4 RTIP5 RTIP6 RTIP7 420 PKG BALL# D1 F1 H1 K1 M1 P1 T1 V1 484 PKG BALL # G2 H2 K4 L2 M2 P3 T2 U4 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Receive Positive Analog Input (RTIPn): RTIP is the positive differential input from the line interface. This input pin, along with the RRING input pin, functions as the "Receive DS1/E1 Line Signal" input for the XRT86VL38 device. The user is expected to connect this signal and the RRING input signal to a 1:1 transformer for proper operation. The center tap of the receive transformer should have a bypass capacitor of 0.1F to ground (Chip Side) to improve long haul application receive capabilities. Receive Negative Analog Input (RRINGn): RRING is the negative differential input from the line interface. This input pin, along with the RTIP input pin, functions as the "Receive DS1/E1 Line Signal" input for the XRT86VL38 device. The user is expected to connect this signal and the RTIP input signal to a 1:1 transformer for proper operation. The center tap of the receive transformer should have a bypass capacitor of 0.1F to ground (Chip Side) to improve long haul application receive capabilities. Receive Loss of Signal Output Indicator (RLOSn): The XRT86VL38 device will assert this output pin (i.e., toggle it "high") anytime (and for the duration that) the Receive DS1/E1 Framer or LIU block declares the LOS defect condition. Conversely, the XRT86VL38 device will negate this output pin (i.e., toggle it "low") anytime (and for the duration that) the Receive DS1/E1 Framer or LIU block is NOT declaring the LOS defect condition. This output pin will toggle "High" (declare LOS) if the Receive Framer or the Receive LIU block associated with Channel N determines that an RLOS condition occurs. In other words, this pin is OR-ed with the LIU RLOS and the Framer RLOS bit. If either the LIU RLOS or the Framer RLOS bit associated with channel N pulses high, the corresponding RLOS pin of that particular channel will be set to "High".
RRING0 RRING1 RRING2 RRING3 RRING4 RRING5 RRING6 RRING7
E1 G1 J1 L1 N1 R1 U1 W1
G3 H1 K3 L1 M1 P2 T3 U3
I
-
RxLOS_0 RxLOS_1 RxLOS_2 RxLOS_3 RxLOS_4 RxLOS_5 RxLOS_6 RxLOS_7
E8 A16 B20 H24 AC26 AF20 AC12 AD4
C8 C14 D16 F22 W21 W15 Y10 U8
O
4
34
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION RECEIVE LINE INTERFACE
SIGNAL NAME RxTSEL 420 PKG BALL# D5 484 PKG BALL # C6 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Receive Termination Control (RxTSEL): Upon power up, the receivers are in "High" impedance. Switching to internal termination can be selected through the microprocessor interface by programming the appropriate channel register. However, to switch control to the hardware pin, RxTCNTL must be programmed to "1" in the appropriate global register (0x0FE2). Once control has been granted to the hardware pin, it must be pulled "High" to switch to internal termination. NOTE: Internally pulled "Low" with a 50k resistor.
REV. V1.2.0
RxTSEL (pin) 0 1
Rx Termination External Internal
Note: RxTCNTL (bit) must be set to "1"
TRANSMIT LINE INTERFACE
SIGNAL NAME TTIP0 TTIP1 TTIP2 TTIP3 TTIP4 TTIP5 TTIP6 TTIP7 420 PKG BALL# F3 G3 J3 K3 M3 P3 T3 U3 484 PKG BALL # F3 H4 J3 K1 M5 N2 R4 T1 TYPE O DESCRIPTION Transmit Positive Analog Output (TTIPn): TTIP is the positive differential output to the line interface. This output pin, along with the corresponding TRING output pin, function as the Transmit DS1/E1 output signal drivers for the XRT86VL38 device. The user is expected to connect this signal and the corresponding TRING output signal to a 1:2 step up transformer for proper operation. This output pin will be tri-stated whenever the user sets the "TxON" input pin or register bit (0xnF02, bit 3) to "0". NOTE: This pin should have a series line capacitor of 0.68F for DC blocking purposes. TRING0 TRING1 TRING2 TRING3 TRING4 TRING5 TRING6 TRING7 G4 H4 K4 L4 M4 P4 R4 U4 F1 J5 J1 L4 M3 P5 R2 U2 O Transmit Negative Analog Output (TRINGn): TRING is the negative differential output to the line interface. This output pin, along with the corresponding TTIP output pin, function as the Transmit DS1/E1 output signal drivers for the XRT86VL38 device. The user is expected to connect this signal and the corresponding TRING output signal to a 1:2 step up transformer for proper operation. NOTE: This output pin will be tri-stated whenever the user sets the "TxON" input pin or register bit (0xnF02, bit 3) to "0".
35
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TRANSMIT LINE INTERFACE
SIGNAL NAME TxON 420 PKG BALL# Y3 484 PKG BALL # W1 TYPE I DESCRIPTION Transmitter On This input pin permits the user to either enable or disable the Transmit Output Driver within the Transmit DS1/E1 LIU Block. If the TxON pin is pulled "Low", all 8 Channels are tri-stated. When this pin is pulled `High', turning on or off the transmitters will be determined by the appropriate channel registers (address 0x0Fn2, bit 3) LOW = Disables the Transmit Output Driver within the Transmit DS1/ E1 LIU Block. In this setting, the TTIP and TRING output pins of all 8 channels will be tri-stated. HIGH = Enables the Transmit Output Driver within the Transmit DS1/ E1 LIU Block. In this setting, the corresponding TTIP and TRING output pins will be enabled or disabled by programming the appropriate channel register. (address 0x0Fn2, bit 3) NOTE:
Whenever the transmitters are turned off, the TTIP and TRING output pins will be tri-stated.
TIMING INTERFACE
SIGNAL NAME MCLKIN 420 PKG BALL# A4 484 PKG BALL # A5 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Master Clock Input: This pin is used to provide the timing reference for the internal master clock of the device. The frequency of this clock is programmable from 8kHz to 16.384MHz in register 0x0FE9. LIU E1 Output Clock Reference This output pin is defaulted to 2.048MHz, but can be programmed to 4.096MHz, 8.192MHz, or 16.384MHz in register 0x0FE4. LIU T1 Output Clock Reference This output pin is defaulted to 1.544MHz, but can be programmed to output 3.088MHz, 6.176MHz, or 12.352MHz in register 0x0FE4. Framer E1 Output Clock Reference This output pin is defaulted to 2.048MHz, but can be programmed to 65.536MHz in register 0x011E. Framer T1 Output Clock Reference This output pin is defaulted to 1.544MHz, but can be programmed to output 49.408MHz in register 0x011E. 8kHz Clock Output Reference This pin is an output reference of 8kHz based on the MCLKIN input. Therefore, the duty cycle of this output is determined by the time period of the input clock reference.
E1MCLKnOUT
B5
A4
O
12
T1MCLKnOUT
D6
F9
O
12
E1OSCCLK
Y5
V4
O
8
T1OSCCLK
AC1
V3
O
8
8KSYNC
AB3
W2
O
8
36
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TIMING INTERFACE
SIGNAL NAME 8KEXTOSC 420 PKG BALL# AA2 484 PKG BALL # U5 TYPE I OUTPUT DRIVE (MA) DESCRIPTION External Oscillator Select For normal operation, this pin should not be used, or pulled "Low". This pin is internally pulled "Low" with a 50k resistor. Factory Test Mode Pin NOTE: For Internal Use Only LOP AB1 V2 I Loss of Power for E1 Only This is a Loss of Power pin in the E1 application only. Upon detecting LOP in E1 mode, the device will automatically transmit the Sa5 and Sa6 bit to a different pattern, so that the Receive terminal can detect a power failure in the network. Please see register 0xn131 for the Transmit SA control. NOTE: For Internal Use Only
REV. V1.2.0
ANALOG
C5
D4
O
SENSE
E6
E6
O
37
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
GPIO INTERFACE
SIGNAL NAME GPIO1_3 GPIO1_2 GPIO1_1 GPIO1_0 420 PKG BALL# B21 G22 AE24 AE22 484PKG BALL # A19 G18 AA20 AA18 TYPE I/O OUTPUT DRIVE (MA) 8 DESCRIPTION General Purpose Input/Output Pins Each of these pins can be configured to function as either a general-purpose input or output pin. The exact function of these pins depend on whether these GPIO pins are configured as input or output pins as follows. If GPIO1_n pins are configured as input pins: The state of these input pins can be monitored by reading the GPIO1_n Control Bits (Bit 3-0) within the "General Purpose Input/Output 1 Control Register (address 0x4102). If GPIO1_n pins are configured as output pins: The state of these output pins can be controlled by writing the appropriate value into the GPIO1_n Control Bits (Bit 30) within the "General Purpose Input/Output 1 Control Register (address 0x4102). Finally, users can configure a given GPIO1_n pin to be an input pin by setting the corresponding GPIO1_nDIR Bit (from Bit 7-4), within the "General Purpose Input/Output 1 Control Register (address 0x4102) to `0'. Conversely, users can configure the GPIO1_ n pin to be an output pin by setting the corresponding GPIO1_nDIR Bit (from Bit 7-4), within the "General Purpose Input/Output 1 Control Register (address 0x4102) to `1'. General Purpose Input/Output Pins Each of these pins can be configured to function as either a general-purpose input or output pin. The exact function of these pins depend on whether these GPIO pins are configured as input or output pins as follows. If GPIO0_n pins are configured as input pins: The state of these input pins can be monitored by reading the GPIO0_n Control Bits (Bit 3-0) within the "General Purpose Input/Output 0 Control Register (address 0x0102). If GPIO0_n pins are configured as output pins: The state of these output pins can be controlled by writing the appropriate value into the GPIO0_n Control Bits (Bit 30) within the "General Purpose Input/Output 0 Control Register (address 0x0102). Finally, users can configure a given GPIO0_n pin to be an input pin by setting the corresponding GPIO0_nDIR Bit (from Bit 7-4), within the "General Purpose Input/Output 0 Control Register (address 0x0102) to `0'. Conversely, users can configure the GPIO0_ n pin to be an output pin by setting the corresponding GPIO0_nDIR Bit (from Bit 7-4), within the "General Purpose Input/Output 0 Control Register (address 0x0102) to `1'.
GPIO0_3 GPIO0_2 GPIO0_1 GPIO0_0
AD20 AB18 AD13 AD11
U16 V15 Y11 AB6
I/O
8
38
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
JTAG INTERFACE The XRT86VL38 device's JTAG features comply with the IEEE 1149.1 standard. Please refer to the industry specification for additional information on boundary scan operations.
SIGNAL NAME TCK 420 PKG BALL# A7 484PKG BALL # F10 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Test clock: Boundary Scan Test clock input: The TCLK signal is the clock for the TAP controller, and it generates the boundary scan data register clocking. The data on TMS and TDI is loaded on the positive edge of TCK. Data is observed at TDO on the falling edge of TCK. Test Mode Select: Boundary Scan Test Mode Select input. The TMS signal controls the transitions of the TAP controller in conjunction with the rising edge of the test clock (TCK). NOTE: TDI D7 E9 I REV. V1.2.0
TMS
A5
B6
I
-
For normal operation this pin must be pulled 'High'.
Test Data In: Boundary Scan Test data input The TDI signal is the serial test data input. NOTE: This pin is internally pulled 'high'.
TDO
B6
D8
O
8
Test Data Out: Boundary Scan Test data output The TDO signal is the serial test data output. Test Reset Input: The TRST signal (Active Low) asynchronously resets the TAP controller to the Test-Logic-Reset state. NOTE: This pin is internally pulled 'high'
TRST
B7
A6
I
-
TEST
B11
E12
I
-
Factory Test Mode Pin NOTE: This pin is internally pulled 'low', and should be pulled 'low' for normal operation.
aTEST
E7
C7
I
-
Factory Test Mode Pin NOTE: This pin is internally pulled 'low', and should be pulled 'low' for normal operation.
JTAG_Ring JTAG_Tip
D4 F5
C2 E5
I I
-
JTAG_Ring Test Pin JTAG_Tip Test Pin
39
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 REQ0 420 PKG BALL# Y26 W24 T25 T26 P24 N25 N24 M25 AB26 484PKG BALL # T19 U20 P21 N18 M22 M20 M21 L21 U19 TYPE I/O OUTPUT DRIVE (MA) 8 DESCRIPTION Bidirectional Microprocessor Data Bus These pins are used to drive and receive data over the bidirectional data bus, whenever the Microprocessor performs READ or WRITE operations with the Microprocessor Interface of the XRT86VL38 device. When DMA interface is enabled, these 8-bit bidirectional data bus is also used by the T1/E1 Framer or the external DMA Controller for storing and retrieving information. DMA Cycle Request Output--DMA Controller 0 (Write): These output pins are used to indicate that DMA transfers (Write) are requested by the T1/E1 Framer. On the transmit side (i.e., To transmit data from external DMA controller to HDLC buffers within the XRT86VL38), DMA transfers are only requested when the transmit buffer status bits indicate that there is space for a complete message or cell. The DMA Write cycle starts by T1/E1 Framer asserting the DMA Request (REQ0) `low', then the external DMA controller should drive the DMA Acknowledge (ACK0) `low' to indicate that it is ready to start the transfer. The external DMA controller should place new data on the Microprocessor data bus each time the Write Signal is Strobed low if the WR is configured as a Write Strobe. If WR is configured as a direction signal, then the external DMA controller would place new data on the Microprocessor data bus each time the Read Signal (RD) is Strobed low. The Framer asserts this output pin (toggles it "Low") when at least one of the Transmit HDLC buffers are empty and can receive one more HDLC message. The Framer negates this output pin (toggles it "High") when the HDLC buffer can no longer receive another HDLC message.
O
8
40
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME REQ1 420 PKG BALL# AA24 484PKG BALL # Y22 TYPE O OUTPUT DRIVE (MA) 8 DESCRIPTION DMA Cycle Request Output--DMA Controller 1 (Read): These output pins are used to indicate that DMA transfers (Read) are requested by the T1/E1 Framer. On the receive side (i.e., To transmit data from HDLC buffers within the XRT86VL38 to external DMA Controller), DMA transfers are only requested when the receive buffer contains a complete message or cell. The DMA Read cycle starts by T1/E1 Framer asserting the DMA Request (REQ1) `low', then the external DMA controller should drive the DMA Acknowledge (ACK1) `low' to indicate that it is ready to receive the data. The T1/E1 Framer should place new data on the Microprocessor data bus each time the Read Signal is Strobed low if the RD is configured as a Read Strobe. If RD is configured as a direction signal, then the T1/E1 Framer would place new data on the Microprocessor data bus each time the Write Signal (WR) is Strobed low. The Framer asserts this output pin (toggles it "Low") when one of the Receive HDLC buffer contains a complete HDLC message that needs to be read by the C/P. The Framer negates this output pin (toggles it "High") when the Receive HDLC buffers are depleted. Interrupt Request Output: This active-low output signal will be asserted when the XRT86VL38 device is requesting interrupt service from the Microprocessor. This output pin should typically be connected to the "Interrupt Request" input of the Microprocessor. The Framer will assert this active "Low" output (toggles it "Low"), to the local P, anytime it requires interrupt service.
REV. V1.2.0
INT
R26
N22
O
8
41
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME PCLK 420 PKG BALL# Y25 484PKG BALL # V22 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Microprocessor Clock Input: This clock input signal is only used if the Microprocessor Interface has been configured to operate in the Synchronous Modes (e.g., Power PC 403 Mode). If the Microprocessor Interface is configured to operate in this mode, then it will use this clock signal to do the following. 1. To sample the CS, WR/R/W, A[14:0], D[7:0], RD/DS and DBEN input pins, and 2. To update the state of the D[7:0] and the RDY/ DTACK output signals. NOTES:
1. 2.
The Microprocessor Interface can work with PCLK frequencies ranging up to 33MHz. This pin is inactive if the user has configured the Microprocessor Interface to operate in either the Intel-Asynchronous or the MotorolaAsynchronous Modes. In this case, the user should tie this pin to GND.
When DMA interface is enabled, the PCLK input pin is also used by the T1/E1 Framer to latch in or latch out receive or output data respectively. iADDR W22 R18 I This Pin Must be Tied "Low" for Normal Operation. This pin is internally pulled "High" with a 50k resistor. This Pin Must be Tied "High" for Normal Operation. This pin is internally pulled "Low" with a 50k resistor. Microprocessor Type Input: These input pins permit the user to specify which type of Microprocessor/Microcontroller to be interfaced to the XRT86VL38 device. The following table presents the three different microprocessor types that the XRT86VL38 supports.
fADDR
AA26
T18
I
-
PTYPE0 PTYPE1 PTYPE2
W23 W26 R25
V20 T20 N21
I
-
PType2
PType1
PType0 0 1 1
MICROPROCESSOR TYPE 68HC11, 8051, 80C188 MOTOROLA 68K IBM POWER PC 403
0 0 1
0 0 0
NOTE: These pins are internally pulled "Low" with a 50k resistor.
42
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME RDY 420 PKG BALL# V24 484PKG BALL # R19 TYPE O OUTPUT DRIVE (MA) 12 DESCRIPTION Ready/Data Transfer Acknowledge Output: The exact behavior of this pin depends upon the type of Microprocessor/Microcontroller the XRT86VL38 has been configured to operate in, as defined by the PTYPE[2:0] pins. Intel Asynchronous Mode - RDY - Ready Output Tis output pin will function as the "active-low" READY output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level, ONLY when the Microprocessor Interface is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "high" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic low level. Motorola Asynchronous Mode - DTACK - Data Transfer Acknowledge Output Tis output pin will function as the "active-low" DTACK output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic low level, ONLY when the Microprocessor Interface is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has determined that this input pin has toggled to the logic "low" level, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "high" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it detects this output pin being toggled to the logic low level.
REV. V1.2.0
43
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME RDY 420 PKG BALL# V24 484PKG BALL # R19 TYPE O OUTPUT DRIVE (MA) 12 DESCRIPTION (Con't) Power PC 403 Mode - RDY Ready Output: This output pin will function as the "active-high" READY output. During a READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to the logic high level, ONLY when the Microprocessor Interface is ready to complete or terminate the current READ or WRITE cycle. Once the Microprocessor has sampled this signal being at the logic "high" level upon the rising edge of PCLK, then it is now safe for it to move on and execute the next READ or WRITE cycle. If (during a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin at a logic "low" level, then the Microprocessor is expected to extend this READ or WRITE cycle, until it samples this output pin being at the logic low level.
NOTE: The Microprocessor Interface will update the state of this output pin upon the rising edge of PCLK.
ADDR0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 DBEN
V25 V26 U22 U23 U24 U25 U26 T22 T24 R23 R24 P22 P25 N23 N22 V23
P18 N17 T21 T22 R20 R21 R22 P19 P20 N19 N20 M18 M19 L18 L22 U22
I
-
Microprocessor Interface Address Bus Input These pins permit the Microprocessor to identify on-chip registers and Buffer/Memory locations within the XRT86VL38 device whenever it performs READ and WRITE operations with the XRT86VL38 device.
NOTE: These pins are internally pulled "Low" with a 50k resistor, except ADDR[8:14].
I
-
Data Bus Enable Input pin. This active-low input pin permits the user to either enable or tri-state the Bi-Directional Data Bus pins (D[7:0]), as described below.
* Setting this input pin "low" enables the Bi-directional
Data bus.
* Setting this input pin "high" tri-states the Bi-directional
Data Bus.
44
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME ALE 420 PKG BALL# R22 484PKG BALL # P22 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Address Latch Enable Input Address Strobe The exact behavior of this pin depends upon the type of Microprocessor/Microcontroller the XRT86VL38 has been configured to operate in, as defined by the PTYPE[2:0] pins. Intel-Asynchronous Mode - ALE This active-high input pin is used to latch the address (present at the Microprocessor Interface Address Bus pins (A[14:0]) into the XRT86VL38 Microprocessor Interface block and to indicate the start of a READ or WRITE cycle. Pulling this input pin "high" enables the input bus drivers for the Address Bus input pins (A[14:0]). The contents of the Address Bus will be latched into the XRT86VL38 Microprocessor Interface circuitry, upon the falling edge of this input signal. Motorola-Asynchronous (68K) Mode - AS This active-low input pin is used to latch the data residing on the Address Bus, A[14:0] into the Microprocessor Interface circuitry of the XRT86VL38 device. Pulling this input pin "low" enables the input bus drivers for the Address Bus input pins. The contents of the Address Bus will be latched into the Microprocessor Interface circuitry, upon the rising edge of this signal. Power PC 403 Mode - No Function -Tie to GND: This input pin has no role nor function and should be tied to GND. Microprocessor Interface--Chip Select Input: The user must assert this active low signal in order to select the Microprocessor Interface for READ and WRITE operations between the Microprocessor and the XRT86VL38 on-chip registers and buffer/memory locations.
REV. V1.2.0
CS
L26
K21
I
-
45
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME RD 420 PKG BALL# W25 484PKG BALL # U21 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Microprocessor Interface--Read Strobe Input: The exact behavior of this pin depends upon the type of Microprocessor/Microcontroller the Framer has been configured to operate in, as defined by the PTYPE[2:0] pins. Intel-Asynchronous Mode - RD - READ Strobe Input: This input pin will function as the RD (Active Low Read Strobe) input signal from the Microprocessor. Once this active-low signal is asserted, then the XRT86VL38 device will place the contents of the addressed register (or buffer location) on the Microprocessor Interface Bi-directional data bus (D[7:0]). When this signal is negated, then the Data Bus will be tristated. Motorola-Asynchronous (68K) Mode - DS - Data Strobe: This input pin will function as the DS (Data Strobe) input signal. Power PC 403 Mode - WE - Write Enable Input: This input pin will function as the WE (Write Enable) input pin. Anytime the Microprocessor Interface samples this activelow input signal (along with CS and WR/R/W) also being asserted (at a logic low level) upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents on the Bi-Directional Data Bus (D[7:0]) into the "target" on-chip register or buffer location within the XRT86VL38 device. Microprocessor Interface--Write Strobe Input The exact behavior of this pin depends upon the type of Microprocessor/Microcontroller the XRT86VL38 has been configured to operate in, as defined by the PTYPE[2:0] pins. Intel-Asynchronous Mode - WR - Write Strobe Input: This input pin functions as the WR (Active Low WRITE Strobe) input signal from the Microprocessor. Once this active-low signal is asserted, then the input buffers (associated with the Bi-Directional Data Bus pin, D[7:0]) will be enabled. The Microprocessor Interface will latch the contents on the Bi-Directional Data Bus (into the "target" register or address location, within the XRT86VL38) upon the rising edge of this input pin. Motorola-Asynchronous Mode - R/W - Read/Write Operation Identification Input Pin: This pin is functionally equivalent to the "R/W" input pin. In the Motorola Mode, a "READ" operation occurs if this pin is held at a logic "1", coincident to a falling edge of the RD/DS (Data Strobe) input pin. Similarly a WRITE operation occurs if this pin is at a logic "0", coincident to a falling edge of the RD/DS (Data Strobe) input pin.
WR
M23
L20
I
-
46
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME WR 420 PKG BALL# M23 484PKG BALL # L20 TYPE I OUTPUT DRIVE (MA) DESCRIPTION (Con't) Power PC 403 Mode - R/W - Read/Write Operation Identification Input: This input pin will function as the "Read/Write Operation Identification Input" pin. Anytime the Microprocessor Interface samples this input signal at a logic "High" (while also sampling the CS input pin "Low") upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents of the Address Bus (A[14:0]) into the Microprocessor Interface circuitry, in preparation for this forthcoming READ operation. At some point (later in this READ operation) the Microprocessor will also assert the DBEN/OE input pin, and the Microprocessor Interface will then place the contents of the "target" register (or address location within the XRT86VL38 device) upon the Bi-Directional Data Bus pins (D[7:0]), where it can be read by the Microprocessor. Anytime the Microprocessor Interface samples this input signal at a logic "Low" (while also sampling the CS input pin a logic "Low") upon the rising edge of PCLK, then the Microprocessor Interface will (upon the very same rising edge of PCLK) latch the contents of the Address Bus (A[14:0]) into the Microprocessor Interface circuitry, in preparation for the forthcoming WRITE operation. At some point (later in this WRITE operation) the Microprocessor will also assert the RD/DS/WE input pin, and the Microprocessor Interface will then latch the contents of the Bi-Directional Data Bus (D[7:0]) into the contents of the "target" register or buffer location (within the XRT86VL38).
REV. V1.2.0
47
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME ACK0 420 PKG BALL# Y23 484PKG BALL # W22 TYPE I OUTPUT DRIVE (MA) DESCRIPTION DMA Cycle Acknowledge Input--DMA Controller 0 (Write): The external DMA Controller will assert this input pin "Low" when the following two conditions are met: 1. After the DMA Controller, within the Framer has asserted (toggled "Low"), the Req_0 output signal. 2. When the external DMA Controller is ready to transfer data from external memory to the selected Transmit HDLC buffer. At this point, the DMA transfer between the external memory and the selected Transmit HDLC buffer may begin. After completion of the DMA cycle, the external DMA Controller will negate this input pin after the DMA Controller within the Framer has negated the Req_0 output pin. The external DMA Controller must do this in order to acknowledge the end of the DMA cycle. DMA Cycle Acknowledge Input--DMA Controller 1 (Read): The external DMA Controller asserts this input pin "Low" when the following two conditions are met: 1. After the DMA Controller, within the Framer has asserted (toggled "Low"), the Req_1 output signal. 2. When the external DMA Controller is ready to transfer data from the selected Receive HDLC buffer to external memory. At this point, the DMA transfer between the selected Receive HDLC buffer and the external memory may begin. After completion of the DMA cycle, the external DMA Controller will negate this input pin after the DMA Controller within the Framer has negated the Req_1 output pin. The external DMA Controller will do this in order to acknowledge the end of the DMA cycle.
NOTE:
ACK1
Y24
V21
This pin is internally pulled "High" with a 50k resistor.
48
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
MICROPROCESSOR INTERFACE
SIGNAL NAME BLAST 420 PKG BALL# P23 484PKG BALL # M17 TYPE I OUTPUT DRIVE (MA) DESCRIPTION Last Cycle of Burst Indicator Input: If the Microprocessor Interface is operating in the Intel-I960 Mode, then this input pin is used to indicate (to the Microprocessor Interface block) that the current data transfer is the last data transfer within the current burst operation. The Microprocessor should assert this input pin (by toggling it "Low") in order to denote that the current READ or WRITE operation (within a BURST operation) is the last operation of this BURST operation.
NOTES:
REV. V1.2.0
1.
If the user has configured the Microprocessor Interface to operate in the Intel-Asynchronous, the Motorola-Asynchronous or the Power PC 403 Mode, then he/she should tie this input pin to GND. This pin is internally pulled "High" with a 50k resistor.
2.
RESET Y4 Y1 I -
Hardware Reset Input Reset is an active low input. If this pin is pulled "Low" for more than 10S, the device will be reset. When this occurs, all output will be `tri-stated', and all internal registers will be reset to their default values.
POWER SUPPLY PINS (3.3V)
SIGNAL NAME VDD 420 PKG BALL# Y2 AC4 AC11 AE18 AD23 AA25 N26 F24 A25 C15 C8 D2 F2 H2 K2 M2 P2 T2 V2 484PKG BALL # G10 G12 G15 H17 L16 R17 T7 T9 T11 T13 T15 E1 H5 K6 L6 M7 N4 R5 T5 TYPE PWR DESCRIPTION Framer Block Power Supply (I/O)
RVDD
PWR
Receiver Analog Power Supply for LIU Section
49
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
POWER SUPPLY PINS (3.3V)
SIGNAL NAME TVDD 420 PKG BALL# F4 H3 J4 L3 N3 R3 T4 V3 484PKG BALL # F2 G1 J2 L3 M6 N1 R3 U1 TYPE PWR DESCRIPTION Transmitter Analog Power Supply for LIU Section
POWER SUPPLY PINS (1.8V)
SIGNAL NAME VDD18 420 PKG BALL# AD1 AD7 AF14 AB20 AC24 T23 J24 D24 E18 E12 A1 B4 D3 C2 B1 C1 484PKG BALL # G11 G14 G16 J17 P17 T8 T10 T12 T14 T17 F5 A2 B1 C1 D2 E3 TYPE PWR DESCRIPTION Framer Block Power Supply
DVDD18 AVDD18 VDDPLL18
PWR PWR PWR
Digital Power Supply for LIU Section Analog Power Supply for LIU Section Analog Power Supply for PLL
50
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
GROUND PINS
SIGNAL NAME VSS 420 PKG BALL# Y1 AA1 AE2 AD6 AD9 AF13 AC16 AB19 AC22 AB23 AA23 V22 P26 L23 H22 C25 B25 D20 B17 C13 D10 C06 484PKG BALL # F6 G6 G7 G8 G9 G13 H6 H7 H16 J7 J16 K7 K16 L7 M16 N6 N7 N16 P6 P7 P16 R6 R7 R16 T6 T16 U6 H8-H15 J8-J15 K8-K15 L8-L15 M8-M15 N8-N15 P8-P15 R8-R15 B5 B3 TYPE GND Framer Block Ground DESCRIPTION
REV. V1.2.0
DGND AGND
A2 A3
GND GND
Digital Ground for LIU Section Analog Ground for LIU Section
51
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
GROUND PINS
SIGNAL NAME RGND 420 PKG BALL# E2 G2 J2 L2 N2 R2 U2 W2 H5 J5 K5 L5 M5 N5 R5 T5 C3 E4 E3 B2 484PKG BALL # F4 H3 J4 K2 M4 N3 P1 T4 G4 J6 K5 L5 N5 P4 R1 V1 D3 E4 D1 E2 TYPE GND DESCRIPTION Receiver Analog Ground for LIU Section
TGND
GND
Transmitter Analog Ground for LIU Section
GNDPLL18
GND
Analog Ground for PLL
52
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
NO CONNECT PINS
SIGNAL NAME NC 420 PKG BALL# B3 B18 B23 C4 D23 E5 E16 E19 E22 G5 N4 P5 U5 V4 V5 W3 W4 W5 AA3 AA4 AA5 AF1 484PKG BALL # A1 A3 A22 B2 C3 C4 C5 D5 D6 D7 E7 E8 F7 F8 G5 B4 F18 TYPE NC No Connection DESCRIPTION
REV. V1.2.0
53
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
ELECTRICAL CHARACTERISTICS
Absolute Maximums
Power Supply..................................................................... VDDIO .. ................................................ -0.5V to +3.465V VDDCORE...............................................-0.5V to +1.890V Storage Temperature ...............................-65C to 150C Operating Temperature Range.................-40C to 85C Supply Voltage ...................... GND-0.5V to +VDD + 0.5V
Power Rating STBGA and PBGA Package.................. 2.4
Input Logic Signal Voltage (Any Pin) .........-0.5V to + 5.5V ESD Protection (HBM)...........................................>2000V Input Current (Any Pin) ...................................... + 100mA
DC ELECTRICAL CHARACTERISTICS
Test Conditions: TA = 25C, VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5% unless otherwise specified SYMBOL ILL VIL VIH VOL VOH IOC IIH IIL PARAMETER Data Bus Tri-State Bus Leakage Current Input Low voltage Input High Voltage Output Low Voltage Output High Voltage Open Drain Output Leakage Current Input High Voltage Current Input Low Voltage Current -10 -10 10 10 2.0 0.0 TBD MIN. -10 TYP. MAX. +10 0.8 VDD 0.4 VDD UNITS A V V V V A A A VIH = VDD VIL = GND IOL = -1.6mA CONDITIONS
XRT86VL38 POWER CONSUMPTION
Test Conditions: TA = 25C, VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, Internal termination, unless otherwise specified MODE T1 E1 E1 IMPEDANCE 100 75 120 MIN. TYP. 2.21 2.07 1.93 MAX. UNITS W W W CONDITIONS QRSS Pattern with All 8 Channels on QRSS Pattern with All 8 Channels on QRSS Pattern with All 8 Channels on
54
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 4: E1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA= -40 to 85C, unless otherwise specified PARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS De-asserted Receiver Sensitivity (Short Haul with cable loss) Receiver Sensitivity (Long Haul with cable loss) Input Impedance Input Jitter Tolerance: 1 Hz 10kHz-100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency (-3dB curve) (JABW=0) (JABW=1) Return Loss: 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz 15 12.5 11 MIN. TYP. MAX. UNIT TEST CONDITIONS Cable attenuation @1024kHz
REV. V1.2.0
32 20 dB % ones dB With nominal pulse amplitude of 3.0V for 120 and 2.37V for 75 application. With nominal pulse amplitude of 3.0V for 120 and 2.37V for 75 application. ITU-G.775, ETSI 300 233
0
43
dB
15
k
37 0.3
UIpp UIpp
ITU G.823
-
20 0.5
kHz dB
ITU G.736
-
10 1.5
-
Hz Hz
ITU G.736
12 8 8
-
-
dB dB dB
ITU-G.703
55
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 5: T1 RECEIVER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40 to 85C, unless otherwise specified PARAMETER Receiver loss of signal: Number of consecutive zeros before RLOS is set Input signal level at RLOS RLOS Clear Receiver Sensitivity (Short Haul with cable loss) Receiver Sensitivity (Long Haul with cable loss) Normal Extended Input Impedance Jitter Tolerance: 1Hz 10kHz - 100kHz Recovered Clock Jitter Transfer Corner Frequency Peaking Amplitude Jitter Attenuator Corner Frequency (-3dB curve) Return Loss: 51kHz - 102kHz 102kHz - 2048kHz 2048kHz - 3072kHz 15 12.5 12 175 MIN. TYP. MAX. UNIT TEST CONDITIONS
20 -
-
dB % ones dB
Cable attenuation @772kHz ITU-G.775, ETSI 300 233 With nominal pulse amplitude of 3.0V for 100 termination
0 0 15 36 45 dB dB k With nominal pulse amplitude of 3.0V for 100 termination
138 0.4
-
-
UIpp
AT&T Pub 62411
-
10
0.1
KHz dB Hz
TR-TSY-000499
6
AT&T Pub 62411
-
14 20 16
-
dB dB dB
TABLE 6: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40 to 85C, unless otherwise specified PARAMETER AMI Output Pulse Amplitude: 75 Application 120 Application Output Pulse Width Output Pulse Width Ratio Output Pulse Amplitude Ratio 2.13 2.70 224 0.95 0.95 2.37 3.00 244 2.60 3.30 264 1.05 1.05 V V ns ITU-G.703 ITU-G.703 MIN. TYP. MAX. UNIT TEST CONDITIONS 1:2 transformer
56
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 6: E1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40 to 85C, unless otherwise specified PARAMETER Jitter Added by the Transmitter Output Output Return Loss: 51kHz -102kHz 102kHz-2048kHz 2048kHz-3072kHz MIN. TYP. 0.025 MAX. 0.05 UNIT UIpp TEST CONDITIONS Broad Band with jitter free TCLK applied to the input.
REV. V1.2.0
15 9 8
-
-
dB dB dB
ETSI 300 166
TABLE 7: E1 TRANSMIT RETURN LOSS REQUIREMENT
FREQUENCY 51-102kHz 102-2048kHz 2048-3072kHz RETURN LOSS ETS 300166 6dB 8dB 8dB
TABLE 8: T1 TRANSMITTER ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=-40 to 85C, unless otherwise specified PARAMETER AMI Output Pulse Amplitude: Output Pulse Width Output Pulse Width Imbalance Output Pulse Amplitude Imbalance Jitter Added by the Transmitter Output Output Return Loss: 51kHz -102kHz 102kHz-2048kHz 2048kHz-3072kHz MIN. 2.4 338 TYP. 3.0 350 0.025 MAX. 3.60 362 20 +200 0.05 UNIT V ns mV UIpp TEST CONDITIONS 1:2 transformer measured at DSX-1. ANSI T1.102 ANSI T1.102 ANSI T1.102 Broad Band with jitter free TCLK applied to the input.
-
17 12 10
-
dB dB dB
57
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION FIGURE 2. ITU G.703 PULSE TEMPLATE
269 ns (244 + 25)
20%
10%
V = 100%
10%
20%
194 ns (244 - 50)
Nominal pulse
50%
244 ns
10%
488 ns (244 + 244) Note - V corresponds to the nominal peak value.
TABLE 9: TRANSMIT PULSE MASK SPECIFICATION
Test Load Impedance Nominal Peak Voltage of a Mark Peak voltage of a Space (no Mark) Nominal Pulse width Ratio of Positive and Negative Pulses Imbalance 75 Resistive (Coax) 2.37V 0 + 0.237V 244ns 0.95 to 1.05 120 Resistive (twisted Pair) 3.0V 0 + 0.3V 244ns 0.95 to 1.05
20%
58
10%
0%
10%
10%
219 ns (244 - 25)
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION FIGURE 3. DSX-1 PULSE TEMPLATE (NORMALIZED AMPLITUDE)
REV. V1.2.0
TABLE 10: DSX1 INTERFACE ISOLATED PULSE MASK AND CORNER POINTS
MINIMUM CURVE TIME (UI) -0.77 -0.23 -0.23 -0.15 0.0 0.15 0.23 0.23 0.46 0.66 0.93 1.16 NORMALIZED AMPLITUDE -.05V -.05V 0.5V 0.95V 0.95V 0.9V 0.5V -0.45V -0.45V -0.2V -0.05V -0.05V TIME (UI) -0.77 -0.39 -0.27 -0.27 -0.12 0.0 0.27 0.35 0.93 1.16 MAXIMUM CURVE NORMALIZED AMPLITUDE .05V .05V .8V 1.15V 1.15V 1.05V 1.05V -0.07V 0.05V 0.05V
59
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION TABLE 11: AC ELECTRICAL CHARACTERISTICS
VDDIO = 3.3V + 5% , VDDCORE = 1.8V + 5%, TA=25C, UNLESS OTHERWISE SPECIFIED PARAMETER SYMBOL MIN. 40 TYP. 50 MAX. 60 UNITS % ppm
MCLKIN Clock Duty Cycle MCLKIN Clock Tolerance
60
XRT86VL38
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
ORDERING INFORMATION
PRODUCT NUMBER XRT86VL38IB XRT86VL38IB484 PACKAGE 420 Plastic Ball Grid Array 484 Shrink Thin Ball Grid Array OPERATING TEMPERATURE RANGE -40C to +85C -40C to +85C
PACKAGE DIMENSIONS FOR 420 PLASTIC BALL GRID ARRAY
E
SYMBOL A A1 A2 A3 D D1 E E1 b e
420 Plastic Ball Grid Array (35.0 mm x 35.0 mm, PBGA)
Rev. 1.00
Note: The control dimension is in millimeter. INCHES MIN MAX 0.085 0.098 0.020 0.028 0.020 0.024 0.045 0.047 1.370 1.386 1.2500 BSC 1.370 1.386 1.2500 BSC 0.024 0.035 0.0500 BSC MILLIMETERS MIN MAX 2.16 2.50 0.50 0.70 0.51 0.61 1.15 1.19 34.80 35.20 31.75 BSC 34.80 35.20 31.75 BSC 0.60 0.90 1.27 TYP.
61
XRT86VL38
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
PACKAGE DIMENSIONS FOR 484 SHRINK THIN BALL GRID ARRAY
4
E
484 Shrink Thin Ball Grid Array (23.0 mm x 23.0 mm, STBGA)
Rev. 1.00
Note: The control dimension is in millimeter. INCHES MIN MAX 0.071 0.082 0.019 0.022 0.019 0.022 0.033 0.037 0.898 0.913 0.8268 BSC 0.898 0.913 0.8268 BSC 0.024 0.028 0.0394 BSC MILLIMETERS MIN MAX 1.80 2.08 0.47 0.57 0.48 0.56 0.85 0.95 22.80 23.20 21.00 BSC 22.80 23.20 21.00 BSC 0.60 0.70 1.00 BSC
SYMBOL A A1 A2 A3 D D1 E E1 b e
62
XRT86VL38
REV. V1.2.0
P4.
OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REVISION HISTORY
REVISION # V1.2.0 DATE January 29, 2007 Released to production. DESCRIPTION
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright 2007 EXAR Corporation Datasheet January 2007. Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
63

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