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TECHNICAL DATA
IN74HC174A
Hex D Flip-Flop with Common Clock and Reset
High-Performance Silicon-Gate CMOS
The IN74HC174A is identical in pinout to the LS/ALS174. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of six D flip-flops with common Clock and Reset inputs. Each flip-flop is loaded with a low-to-high transition of the Clock input. Reset is asynchronous and active-low. * Outputs Directly Interface to CMOS, NMOS, and TTL * Operating Voltage Range: 2.0 to 6.0 V * Low Input Current: 1.0 A * High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION IN74HC174AN Plastic IN74HC174AD SOIC IZ74HC174A Chip TA = -55 to 125 C for all packages
PIN ASSIGNMENT LOGIC DIAGRAM
FUNCTION TABLE
Inputs Reset L PIN 16=VCC PIN 8 = GND H H H H X = Don't care L = LOW voltage level H = HIGH voltage level L Clock X D X H L X X Output Q L H L no change no change
INTEGRAL
1
IN74HC174A
MAXIMUM RATINGS *
Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL
*
Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC Output Current, per Pin DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1,5 mm from Case for 4 Seconds (Plastic DIP or SOIC Package)
Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 20 25 50 750 500 -65 to +150 260
Unit V V V mA mA mA mW C C
Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/C from 65 to 125C SOIC Package: : - 7 mW/C from 65 to 125C
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC =2.0 V VCC =4.5 V VCC =6.0 V Min 2.0 0 -55 0 0 0 Max 6.0 VCC +125 1000 500 400 Unit V V C ns
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
INTEGRAL
2
IN74HC174A
DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND)
VCC Symbol Parameter Test Conditions V
Guaranteed Limit -55C to 25C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 4.0 85 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 40 125 C 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 3.7 5.2 0.1 0.1 0.1 0.4 0.4 1.0 160 A A V Unit
VIH
Minimum High-Level Input Voltage Maximum Low -Level Input Voltage Minimum High-Level Output Voltage
VOUT VCC-0.1 V or 0.1 V IOUT 20 A VOUT0.1 V or VCC-0.1 V IOUT 20 A VIN=VIH or VIL IOUT 20 A VIN=VIH or VIL IOUT 4.0 mA IOUT 5.2 mA
2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0
V
VIL
V
VOH
V
VOL
Maximum Low-Level Output Voltage
VIN= VIL or VIH IOUT 20 A VIN= VIL or VIH IOUT 4.0 mA IOUT 5.2 mA
IIN ICC
Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package)
VIN=VCC or GND VIN=VCC or GND IOUT=0A
INTEGRAL
3
IN74HC174A
AC ELECTRICAL CHARACTERISTICS(CL=50pF, Input t r=t f=6.0 ns, VIL= 0 V, VIH=Vcc)
VCC Symbol Parameter V Guaranteed Limit -55C to 25C 6.0 30 35 110 22 19 110 21 19 75 15 13 10 85C 125C Unit
fmax
Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay, Clock to Q (Figures 1 and 4) Maximum Propagation Delay , Reset to Q (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Input Capacitance Power Dissipation Capacitance (Per Enabled Output)
2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -
4.8 24 28 140 28 24 140 28 24 95 19 16 10
4.0 20 24 165 33 28 160 32 27 110 22 19 10
MHz
tPLH, t PHL
ns
tPHL
ns
tTLH, t THL
ns
CIN
pF
Typical @25C,VCC=5.0 V 62 pF
CPD
Used to determine the no-load dynamic power consumption: PD=CPDVCC2f+ICCVCC
TIMING REQUIREMENTS (CL=50pF,Input t r=t f=6.0 ns, VIL= 0 V, VIH=Vcc)
VCC Symbol tSU Parameter Minimum Setup Time, Data to Clock (Figure 3) Minimum Hold Time, Clock to Data (Figure 3) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) Minimum Pulse Width, Clock (Figure 1) Minimum Pulse Width, Reset (Figure 2) Maximum Input Rise and Fall Times (Figure 1) V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 -55 C to 25C 50 10 9 5 5 5 5 5 5 75 15 13 75 15 13 1000 500 400 Guaranteed Limit 85C 65 13 11 5 5 5 5 5 5 95 19 16 95 19 16 1000 500 400 125C 75 15 13 5 5 5 5 5 5 110 22 19 110 22 19 1000 500 400 Unit ns
th
ns
trec
ns
tw
ns
tw
ns
tr, tf
ns
INTEGRAL
4
IN74HC174A
tw tr CLOCK
90% 50% 10%
tf
VCC GND
RESET tPHL Q
50%
VCC GND
tw 1/fmax tPLH Q
50% 10% 90%
50%
t PHL t rec CLOCK VCC
50%
tTLH
t THL
GND
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
VALID DATA VCC
50%
TEST POINT
GND t su th VCC
50%
DEVICE UNDER TEST
OUTPUT
*
CL
CLOCK
GND
Figure 3. Switching Waveforms
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
INTEGRAL
5
IN74HC174A
CHIP PAD DIAGRAM
Chip marking
15 14 1.3 + 0.03
13
12
11 10 09
16 08 03 04 05 06 07
01 02
1.6 + 0.03
Chip marking :15HC174 Location of marking (mm): left lower corner x = 0.110, y = 0.870; right lower corner x = 0.240, y = 0.900 Chip thickness: 0.46 0.02 mm
PAD LOCATION
Pad No Symbol Location (left lower corner), mm Y 0.340 0.140 0.115 0.115 0.115 0.115 0.140 0.355 0.815 1.045 1.065 1.065 1.065 1.065 1.045 0.660 Pad size, mm
X 01 Reset 0.115 02 Q0 0.115 03 D0 0.325 04 D1 0.580 05 Q1 0.850 06 D2 1.145 07 Q2 1.345 08 GND 1.370 09 Clock 1.365 10 Q3 1.355 11 D3 1.155 12 Q4 0.880 13 D4 0.620 14 D5 0.320 15 Q5 0.125 16 Vcc 0.115 Note: Location is given as per passivation layer
0.12x0.12 0.12x0.12 0.12x0.12 0.12x0.12 0.12x0.12 0.12x0.12 0.12x0.12 0.12x0.16 0.12x0.12 0.12x0.12 0.12x0.12 0.12x0.12 0.12x0.12 0.12x0.12 0.12x0.12 0.12x0.19
INTEGRAL
6

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