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W83194BR-PT WINBOND STEPLESS VIA PT MAIN CLOCK GENERATOR
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Publication Release Date:April 13, 2005 Revision 1.1
W83194BR-PT
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 1 PRODUCT FEATURES .............................................................................................................. 1 PIN CONFIGURATION ............................................................................................................... 2 BLOCK DIAGRAM ...................................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6. 7. Crystal I/O .............................................................................................................................3 CPU, AGP, and PCI, IOAPIC Clock Outputs ......................................................................3 I2C Control Interface .............................................................................................................4 Fixed Frequency Outputs.....................................................................................................4 Power Management Pins.....................................................................................................4 Power Pins............................................................................................................................5 MULTSEL [1:0] selects Function .........................................................................................5
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 6 I2C CONTROL AND STATUS REGISTERS............................................................................... 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 7.18 7.19 Register 0: Frequency Select (Default = C4h) ....................................................................7 Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default = E3h) .......................7 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default = FFh).........................8 Register 3: PCI, REF, 48MHz Clock Control (1 = Enable, 0 = Stopped) (Default = F8h) ..............8 Register 4:MULTISEL1 IOAPIC, AGP Control (1 = Enable, 0 = Stopped) (Default = 7Fh) ...........8 Register 5: Watchdog Control (Default = 80h) ....................................................................9 The Register 6, 7 is reserved for Buffer...............................................................................9 Register 8: Watchdog Timer (Default = 08h).......................................................................9 Register 9: M/N Program (Default = ADh)...........................................................................9 Register 10: M/N Program (Default = 67h)........................................................................10 Register 11: Spread Spectrum Programming (Default = 1Fh) .........................................10 Register 12: Divisor and Step-less Enable Control (Default = 08h) .................................10 Register 13: CPU to IOAPIC Skew Control (Default = A7h).............................................12 Register 14: CPU to PCI and IOAPIC Skew Control (Default = 90h)...............................12 Register 15: SEL24_48 and CPU to CPUCS skew Control (Default = 04h)....................12 Register 16: 24, 48, PCI Slew rate control (Default = FFh) ..............................................13 Register 17: PCI, AGP, REF Slew rate control (Default = FCh).......................................13 Register 18: IOAPIC, CPUCS Slew rate control (Default = FFh) .....................................13 Register 19: Winbond Chip ID (Read Only) (Default = 81h).............................................14 - II -
W83194BR-PT
7.20 8. Register 20: Winbond Chip ID (Read Only) (Default = 7Ch) ............................................14
ACCESS INTERFACE .............................................................................................................. 15 8.1 8.2 8.3 8.4 Block Write protocol............................................................................................................15 Block Read protocol ...........................................................................................................15 Byte Write protocol .............................................................................................................15 Byte Read protocol.............................................................................................................15
9.
SPECIFICATIONS .................................................................................................................... 16 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 Absolute Maximum Ratings ...............................................................................................16 General Operating Characteristics ....................................................................................16 Skew Group Timing Clock .................................................................................................16 CPU 0.7V Electrical Characteristics ..................................................................................17 CPU 1.0V Electrical Characteristics ..................................................................................17 AGP Electrical Characteristics ...........................................................................................17 PCI Electrical Characteristics.............................................................................................18 24M, 48M Electrical Characteristics ..................................................................................18 REF Electrical Characteristics............................................................................................18
10. 11. 12. 13.
ORDERING INFORMATION..................................................................................................... 19 HOW TO READ THE TOP MARKING...................................................................................... 19 PACKAGE DRAWING AND DIMENSIONS.............................................................................. 20 REVISION HISTORY ................................................................................................................ 21
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-PT
1. GENERAL DESCRIPTION
The W83194BR-PT is a Clock Synthesizer for VIA PT chipset. W83194BR-PT provides all clocks required for high-speed microprocessor and provides step-less frequency programming and 32 different frequencies of CPU, PCI, and AGP clocks setting. All clocks are externally selectable with smooth transitions. The W83194BR-PT provides I2C serial bus interface to program the registers to enable or disable each clock outputs and provides -0.5% and +/-0.25% center type spread spectrum or programmable S.S.T. scale to reduce EMI. The W83194BR-PT also has watchdog timer and reset output pin to support auto-reset when systems hanging caused by improper frequency setting. The W83194BR-PT accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
2. PRODUCT FEATURES
* * * * * * * * * * * * * * * * * 2 Differential pairs of CPU clock outputs 1 Differential pairs push pull of CPU_CS clock outputs 3 AGP clock outputs 9 PCI synchronous clocks 24_48Mhz clock output for super I/O. 48 MHz clock output for USB. 2 IOAPIC clock outputs. 1 REF clock output. Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 100 to 200MHz Step-less frequency programming I2C 2-Wire serial interface and support byte read/write and block read/write. -0.5% and +/- 0.25% center type spread spectrum Programmable S.S.T. scale to reduce EMI Programmable registers to enable/stop each output and select modes Watch Dog Timer and RESET# output pins 48-pin SSOP package
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-PT
3. PIN CONFIGURATION
SEL24_48 & /REF VDDR GND XIN XOUT VDDA FS3*/48M Hz FS2*/24_48M Hz GND FS0 & /PCI8 FS1 & /PCI0 MULTISEL0*/PCI1 GND PCI2 PCI3 VDDP PCI4 PCI5 PCI6 GND PCI7 PD#* AGP0 VDDAGP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDI GND IOAPIC 0 IOAPIC 1 GND VDDCS CPUT_CS CPUC_CS CPUCLKT0 CPUCLKC0 VDDC IREF GND CPUCLKT1 CPUCLKC1 VTT_PWRGD# Ratio_1 Ratio_0 RESET# SDATA SCLK AGP2 AGP1 GND
#: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND
4. BLOCK DIAGRAM
PLL2
D iv id er
48M Hz 24_48M H z 2
X IN XOUT
XTAL O SC
R E F 0 :1
PLL1 S p read S p e c tr u m
VCOCLK
CPUT_CS C PU C _C S 2 C P U C L K T 0 :1 C P U C L K C 0 :1 IO A P IC
3
M /N /R a tio ROM
2 D iv id e r
V T T _PW R G D F S (0 :3 ) M U L T IS E L 0 * SE L 24_48#&
A G P 0 :2 L a tc h & POR
9
P C I_ 0 :8 R a tio ( 0 :1 ) RESET#
PD #*
C o n tro l L o g ic & C o n f ig R e g is te r
IREF
R ref
SD ATA* SCLK*
I2 C I n te rf a c e
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W83194BR-PT
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL DESCRIPTION
IN INtp120k INtd120k OUT OD I/O I/OD # * &
Input Latched input at power up, internal 120k pull up. Latched input at power up, internal 120k pull down. Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain. Active Low Internal 120k pull-up Internal 120 k pull-down
5.1 Crystal I/O
PIN PIN NAME TYPE DESCRIPTION
4 5
XIN XOUT
IN OUT
Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318MHz nominally with internal loading capacitors (18pF).
5.2 CPU, AGP, and PCI, IOAPIC Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
34, 35, 39, 40 41,42 23, 26, 27 10
CPUCLKT [0:1] CPUCLKC [0:1] CPUT_CS CPUC_CS AGP0: 2 PCI8 FS0& PCI0
OUT OUT OUT OUT INtd120k OUT INtd120k OUT INtp120k OUT OUT
Low skew (< 250ps) differential clock outputs for host frequencies of CPU Low skew (< 250ps) differential push pull clock outputs for host frequencies of CHIPSET 3.3V AGP clock outputs. 3.3V PCI clock output. Latched input for FS0 at initial power up for H/W selecting the output frequency. This is internal 120K pull down. 3.3V PCI clock output. Latched input for FS1 at initial power up for H/W selecting the output frequency, This is internal 120K pull down. 3.3V PCI clock output. Latched input for MULTSEL at initial power up, internal 120K pull up Low skew (< 250ps) PCI clock outputs. 2.5V PCI/2 clock outputs. Publication Release Date: April 13, 2005 Revision 1.1
11
FS1& PCICLK1
12 14, 15, 17, 18, 19, 21 46, 45
MULTISEL0* PCI [2:7] IOAPIC 0:1
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W83194BR-PT
5.3 I2C Control Interface
PIN PIN NAME TYPE DESCRIPTION
29 28
SDATA* SCLK*
I/OD IN
Serial data of I2C 2-wire control interface with internal pull-up resistor. Serial clock of I2C 2-wire control interface with internal pull-up resistor.
5.4 Fixed Frequency Outputs
PIN PIN NAME TYPE DESCRIPTION
REF 1 SEL24_48 48MHz 7 FS3* 24_48MHz 8 FS2*
&
OUT INtd120k OUT INtp120k OUT INtp120k
14.318MHz output. Latched input for 24MHz or 48MHz select pin. This is internal 120K pull down default 48MHz. In power on reset period, it is a hardwarelatched pin, and it can be R/W by I2C control after power on reset period. Select by register 15 bit 7. 48MHz clock output for USB. Latched input for FS3 at initial power up for H/W selecting the output frequency. This is internal 120K pull up. 24 or 48MHz (default) clock output, In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. Select by register 15 bit 7. Latched input for FS2 at initial power up for H/W selecting the output frequency. This is internal 120K pull up.
5.5 Power Management Pins
PIN PIN NAME TYPE DESCRIPTION
33
VTT_PWR GD# Ratio_1 Ratio_0
IN
Power good input signal comes from ACPI with LOW active. This 3.3V input is level sensitive strobe used to determine FS [4:0] and MULTISEL input are valid and is ready to sample. This pin is LOW active. Gear ratio output to chipset. This output can replace CPU BSEL signal. Gear ratio output to chipset. This output can replace CPU BSEL signal. Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. There are several modes to select different current via power on trapping the Pin 12 (MULTISEL0). The table is show as follows. System reset signal when the watchdog is time out. This pin will generate 250ms low phase when the watchdog timer is timeout. Power Down Function. This is power down pin, low active (PD#). Internal 120K pull up
32 31
OUT OUT
37
IREF
OUT
30 22
RESET# PD#*
OD IN
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W83194BR-PT
5.6 Power Pins
PIN 2 16 24 38 43 48 6 3, 9, 13, 20, 25, 36, 44, 47 PIN NAME VDDR VDDP VDDAGP VDDC VDDCS VDDI VDDA GND TYPE PWR PWR PWR PWR PWR PWR PWR PWR DESCRIPTION 3.3V power supply for REF. 3.3V power supply for PCI. 3.3V power supply for AGP. 3.3V power supply for CPU. 2.5V power supply for CPUCLKT & C _CS. 2.5V power supply for IOAPIC. 3.3V power for Analog power and 48MHz. Ground pin
5.7 MULTSEL [1:0] selects Function
MULTSEL1 BYTE 5 BIT 7 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MULTSEL0 (PIN 12) 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 BOARD TARGET TRACE/TERM Z 50 60 50 60 50 60 50 60 50 60 50 60 50 60 50 60 REFERENCE R, IREF = ADD/(3*RR) Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =221 1% IREF = 5.00mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA Rr =475 1% IREF = 2.32mA OUTPUT CURRENT Ioh=4*IREF Ioh=4*IREF Ioh=5*IREF Ioh=5*IREF Ioh=6*IREF Ioh=6*IREF Ioh=7*IREF Ioh=7*IREF Ioh=4*IREF Ioh=4*IREF Ioh=5*IREF Ioh=5*IREF Ioh=6*IREF Ioh=6*IREF Ioh=7*IREF Ioh=6*IREF VOH @ Z 1.0V @ 50 1.2V @ 60 1.25V @ 50 1.5V @ 60 1.5V @ 50 1.8V @ 60 1.75V @ 50 2.1V @ 50 0.47V @ 50 0.56V @ 50 0.58V @ 50 0.7V @ 60 0.7V @ 50 0.84V @ 60 0.81V @ 50 0.97V @ 60
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-PT
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 0 bit 7 ~ 4, 2).
FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHZ) 101.9 104.9 107.9 111.0 114.0 117.0 120.1 123.1 120.1 123.7 134.0 139.9 143.9 148.0 152.0 156.0 160.1 164.1 166.9 170.2 175.1 120.1 149.8 180.1 100.0 133.3 199.9 166.9 100.2 133.6 200.5 166.9 AGP (MHZ) 67.9 69.9 72.0 74.0 76.0 78.0 80.0 82.1 72.0 74.2 67.0 69.9 72.0 74.0 76.0 78.0 80.0 82.1 66.7 68.1 70.0 60.0 59.9 60.0 66.6 66.6 66.6 66.7 66.8 66.8 66.8 66.7 PCI (MHZ) 34.0 35.0 36.0 37.0 38.0 39.0 40.0 41.0 36.0 37.1 33.5 35.0 36.0 37.0 38.0 39.0 40.0 41.0 33.4 34.0 35.0 30.0 30.0 30.0 33.3 33.3 33.3 33.4 33.4 33.4 33.4 33.4 IOAPIC (MHZ) 17.0 17.5 18.0 18.5 19.0 19.5 20.0 20.5 18.0 18.6 16.8 17.5 18.0 18.5 19.0 19.5 20.0 20.5 16.7 17.0 17.5 15.0 15.0 15.0 16.7 16.7 16.7 16.7 16.7 16.7 16.7 16.7 SPREAD % +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% +/-0.25% -0.5% -0.5% -0.5% -0.5% +/-0.25% +/-0.25% +/-0.25% +/-0.25%
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W83194BR-PT
7. I2C CONTROL AND STATUS REGISTERS 7.1 Register 0: Frequency Select (Default = C4h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1
SSEL [3] SSEL [2] SSEL [1] SSEL [0] EN_SSEL SSEL [4] EN_SPSP
1 1 0 0 Enable software program FS [4:0]. 0 0 = Select frequency by hardware. 1= Select frequency by software I2C - Bit 7~ 4, 2. Frequency selection bit 4 Enable Spread Spectrum in the frequency table. 0 = Normal 1 = Spread Spectrum enabled Enable reload safe frequency when the watchdog is timeout. Frequency selection by software via I2C
1 0
0
EN_SAFE_ FREQ
0
0 = reload the FS [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 5 bit 4~0.
7.2 Register 1: CPU Clock Control (1 = Enable, 0 = Stopped) (Default = E3h)
BIT PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
42, 41 35, 34 40, 39 -
1 1 1 0 X X X X
CPUT / C_CS output control CPUCLKT1 / C1 output control CPUCLKT0 / C0 output control Reserved. Default: 0 (Read only) Invert Power on latched value of FS3 pin. Default: 0 (Read only) Invert Power on latched value of FS2 pin. Default: 0 (Read only) Invert Power on latched value of FS1 pin. Default: 1 (Read only) Invert Power on latched value of FS0 pin. Default: 1 (Read only)
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W83194BR-PT
7.3 Register 2: PCI Clock Control (1 = Enable, 0 = Stopped) (Default = FFh)
BIT PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
21 19 18 17 15 14 12 11
1 1 1 1 1 1 1 1
PCI7 output control PCI6 output control PCI5 output control PCI4 output control PCI3 output control PCI2 output control PCI1 output control PCI0 output control
7.4 Register 3: PCI, REF, 48MHz Clock Control (1 = Enable, 0 = Stopped) (Default = F8h)
BIT PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
7 8 1 10 32 31
1 1 1 1 1 0 X X
48MHZ output control 24_48MHz output control REF output control PCI8 output control Reserved Reserved Invert Ratio_1 read back Invert Ratio_0 read back
7.5
BIT
Register 4:MULTISEL1 IOAPIC, AGP Control (1 = Enable, 0 = Stopped) (Default = 7Fh)
PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
45 46 27 26 23
0 1 1 1 1 1 1 1
MULTISEL1 I2C R/W Reserved Reserved IOAPIC1 output control IOAPIC0 output control AGP2 output control AGP1 output control AGP0 output control
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W83194BR-PT
7.6 Register 5: Watchdog Control (Default = 80h)
BIT NAME PWD DESCRIPTION
7 6
MULTISEL0 EN_WD
X 0
Pin 12 MULTISEL0 power on trapping pin data read back (Default = 1) Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer. Read this bit will return a counting state. If timer continues down count, this bit will return 1. Otherwise, this bit will return 0. Watchdog Timeout Status. If the watchdog is started and timer down counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1, when the watchdog is restart in the next time. This bit is Read Only.
5 4 3 2 1 0
WD_TIMEOUT SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] SAF_FREQ [1] SAF_FREQ [0]
0 0 0 0 0 0
Watchdog safe frequency bits. These bits will be reloaded into FS [4:0], if the watchdog is timeout and enable reload safe frequency bits.
7.7 The Register 6, 7 is reserved for Buffer 7.8 Register 8: Watchdog Timer (Default = 08h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
WD_TIME [7] WD_TIME [6] WD_TIME [5] WD_TIME [4] WD_TIME [3] WD_TIME [2] WD_TIME [1] WD_TIME [0]
0 0 0 0 1 0 0 0
Watchdog timeout time. The bit resolution is 250mS. The default time is 8*250mS = 2.0 seconds. If the watchdog timer is start, this register will be down count. Read this register will return a down count value.
7.9 Register 9: M/N Program (Default = ADh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [8] TEST2 TEST1 M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0]
1 0 1 0 1 1 0 1
Programmable N divisor value. Bit 7 ~0 are defined in the Register 10. Test bit 2. Winbond test bit, do not change them. Test bit 1. Winbond test bit, do not change them.
Programmable M divisor value.
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W83194BR-PT
7.10 Register 10: M/N Program (Default = 67h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [7] N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] N_DIV [0]
0 1 1 0 0 1 1 1 Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 9.
7.11 Register 11: Spread Spectrum Programming (Default = 1Fh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0]
0 0 0 1 1 1 1 1 Spread Spectrum Down Counter bit 3 ~ bit 0 2's complement representation. Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000 Spread Spectrum Up Counter bit 3 ~ bit 0.
7.12 Register 12: Divisor and Step-less Enable Control (Default = 08h)
BIT NAME PWD DESCRIPTION
0: use frequency table 1: use M/N register to program frequency 7 EN_MN_PROG 0 The equation is VCO freq. = 14.318MHz * (N+4)/ M. When the watchdog timer is timeout, this will be clear. In this time, the frequency is set to hardware default latched or safe frequency set by EN_SFAE_FREQ (Register 0 bit 0).
6 5 4 3 2 1 0
RATIO_SEL [4] RATIO_SEL [3] RATIO_SEL [2] RATIO_SEL [1] RATIO_SEL [0] TEST0 Reserved
0 0 0 1 0 0 0 Test bit 0. Winbond test bit, do not change them. CPU, PCI, AGP, ratio selection. The ratio is shown as following table.
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W83194BR-PT
I2C Reg12 Definition
Reg12 Bit6 SSEL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reg12 Bit5 SSEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Reg12 Bit4 SSEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Reg12 Reg12 Bit3 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU Ratio 2 2 3 4 3 6 4 4 4 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 2 3 4 6 2 2 4 4 CPU_CS IOAPIC Ratio 2 2 3 4 3 6 4 4 4 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 2 3 4 6 2 2 4 4 Ratio 20 24 24 24 20 24 24 24 24 16 16 24 24 16 20 16 20 20 20 24 16 14 16 14 16 24 16 16 14 24 14 24 AGP Ratio 5 6 6 6 5 6 6 6 6 8 8 6 6 8 10 8 10 10 10 6 8 7 8 12 8 12 8 8 7 6 7 6 PCI Ratio 10 12 12 12 10 12 12 12 12 16 16 12 12 16 20 16 20 20 20 12 16 14 16 14 16 24 16 16 14 12 14 12 SSEL1 SSEL0
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-PT
7.13 Register 13: CPU to IOAPIC Skew Control (Default = A7h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CPU_IOAPIC_SKEW [2] Reserved SPCNT [5] SPCNT [4] SPCNT [3] SPCNT [2] SPCNT [1] SPCNT [0]
1 0 1 0 0 1 1 1
CPU to IOAPIC SKEW control Reserved
Spread Spectrum Programmable time, the resolution is 280ns
7.14 Register 14: CPU to PCI and IOAPIC Skew Control (Default = 90h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CPU_PCI_SKEW [2] CPU_PCI_SKEW [1] CPU_PCI_SKEW [0] CPU_AGP_SKEW [2] CPU_AGP_SKEW [1] CPU_AGP_SKEW [0] CPU_IOAPIC_SKEW [1] CPU_IOAPIC_SKEW [0]
1 0 0 1 0 0 0 0
CPU to PCI skew, Skew resolution is 340ps Expand the skew direction is same as CPU_PCI_SKEW [2:0] setting CPU to AGP Skew, Skew resolution is 340ps Expand the skew direction is same as CPU_AGP_SKEW [2:0] setting CPU to IOAPIC skew control, Skew resolution is 340ps Expand the skew direction is same as CPU_AGP_IOAPIC [2:0] setting
7.15 Register 15: SEL24_48 and CPU to CPUCS skew Control (Default = 04h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SEL24_48 Reserved FIX_AGP_PCI SEL [1] SEL [0] CPU_CPUCS_SKEW [2] CPU_CPUCS_SKEW [1] CPU_CPUCS_SKEW [0]
X 0 0 0 0 1 0 0
In power on reset period, it is a hardware-latched pin, and it can be R/W by I2C control after power on reset period. 1> 24 MHz, 0->48MHz. Default is 48Mhz Reserved 0:normal mode, 1: fix mode AGP & PCI FIX frequency (PCI = AGP/2) SEL [1:0] for AGP 00: 72MHZ 01:64MHZ 10: 77NHZ 11: 67MHZ CPU to CPUCS Skew, Skew resolution is 340ps Expand the skew direction is same as CPU_CPUCS_SKEW [2:0] setting
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W83194BR-PT
7.16 Register 16: 24, 48, PCI Slew rate control (Default = FFh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
P24SW [1] P24SW [0] P48SW [1] P48SW [0] PCIASW [1] PCIASW [0] PCIBSW [1] PCIBSW [0]
1 1 1 1 1 1 1 1
Pin 8, 24-48MHz clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak Pin 7, 48MHz clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak Pin 11,12,14,15, PCI [0:3] clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak Pin 17,18,20,21,20, PCI [4:7] clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak
7.17 Register 17: PCI, AGP, REF Slew rate control (Default = FCh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
PCI8SW [1] PCI8SW [0] AGPASW [1] AGPASW [0] AGPBSW [1] AGPBSW [0] REFSW [1] REFSW [0]
1 1 1 1 1 1 0 0
Pin 10, PCI8 clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak Pin 27, AGP2 clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak Pin 23,26, AGP [0:1] clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak REF clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak
7.18 Register 18: IOAPIC, CPUCS Slew rate control (Default = FFh)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
IOAPICSW [1] IOAPICSW [0] CPUCSW [1] CPUCSW [0] Reserved Reserved Reserved Reserved
1 1 1 1 1 1 1 1
Pin 46,45, IOAPIC [0:1] clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak Pin 41,42 CPUC/T_CS clock slew rate control 11: strong, 10: normal, 01:normal, 00:weak Reserved Reserved
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-PT
7.19 Register 19: Winbond Chip ID (Read Only) (Default = 81h)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0]
1 0 0 0 0 0 0 1
Winbond Chip ID. W83194BR-PT is 0x81. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID. Winbond Chip ID.
7.20 Register 20: Winbond Chip ID (Read Only) (Default = 7Ch)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
MAS_ID [1] MAS_ID [0] SUB_ID [1] SUB_ID [0] MAS_VER_ID [1] MAS_VER_ID [0] SUB_VER_ID [1] SUB_VER_ID [0]
0 1 1 1 1 1 0 0
MASK definition for master body *A****: 01, *B****: 10, *C****: 11, *D****:00 MASK definition for code body *A****001: 01, *A****002: 10, *A****003: 11, *A****004:00 MASK version definition for master body *A****001AA: 00, *A****001AB: 01, *A****001AC: 10, *A****001AD: 11. MASK version definition for code body *A****001A: 00, *A****001B: 01 *A****001C: 10, *A****001D: 11
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W83194BR-PT
8. ACCESS INTERFACE
The W83194BR-PT provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-PT is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2. Block Read and Block Write Protocol
8.1 Block Write protocol
8.2 Block Read protocol
## In block mode, the command code must filled 8'h00
8.3 Byte Write protocol
8.4 Byte Read protocol
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-PT
9. SPECIFICATIONS 9.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
PARAMETER RATING
Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD Protection (Human body model)
-0.5V to +4.6V - 0.5 V to + 4.6 V 3.135V to 3.465V 3.135V to 3.465V - 65C to + 150C - 55C to + 125C 0C to + 70C 2000V
9.2 General Operating Characteristics
VDDA=VDDAGP=VDDC=VDDR=VDDP= 3.3V 5 %, TA = 0C to +70C, Cl=10pF
PARAMETER
SYM.
MIN.
MAX.
UNITS
TEST CONDITIONS
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Operating Supply Current Input pin capacitance Output pin capacitance Input pin inductance
VIL VIH VOL VOH Idd Cin Cout Lin
0.8 2.0 0.4 2.4 350 5 6 7
Vdc Vdc Vdc Vdc mA pF pF nH
All outputs using 3.3V power All outputs using 3.3V power CPU = 100 to 200 MHz PCI = 33.3 Mhz with load
9.3 Skew Group Timing Clock
VDDA=VDDAGP=VDDC=VDDR=VDDP= 3.3V 5 %, TA = 0C to +70C, Cl=10pF
PARAMETER
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
AGP to PCI Skew CPU to CPU Skew AGP to AGP Skew PCI to PCI Skew 48MHz to 48MHz Skew REF to REF Skew
1.5
2.6
3.5 200 250 500 1000 500
ns ps ps ps ps ps
Measured at 1.5V Crossing point Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V
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W83194BR-PT
9.4 CPU 0.7V Electrical Characteristics
VDDA=VDDC= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=10pF, Vr=475, IREF=2.32mA, Ioh=6*IREF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Absolute crossing point Voltages Cycle to Cycle jitter Duty Cycle
175 175 250
700 700 550 150
ps ps mV ps %
100 to 200 Mhz 100 to 200Mhz 100 to 200Mhz 100 to 200Mhz 100 to 200Mhz
45
55
9.5 CPU 1.0V Electrical Characteristics
VDDA=VDDC= 3.3V 5 %, TA = 0C to +70C, Test load Rs=33, Rp=49.9 Cl=10pF, Vr=221, IREF=5mA, Ioh=4*IREF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Absolute crossing point Voltages Cycle to Cycle jitter Duty Cycle
175 175 510
700 700 760 150
ps ps mV ps %
100 to 200 Mhz 100 to 200Mhz 100 to 200Mhz 100 to 200Mhz 100 to 200Mhz
45
55
9.6 AGP Electrical Characteristics
VDDAGP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF,
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max
500 500 45 -33
2000 2000 250 55 -33
ps ps ps % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
30 38
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-PT
9.7 PCI Electrical Characteristics
VDDP= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF,
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max
500 500 45 -33
2000 2000 250 55 -33
ps ps ps % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
30 38
9.8 24M, 48M Electrical Characteristics
VDDA= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF,
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Long term jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max
500 500 45 -33
2000 2000 500 55 -33
ps ps ps % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
30 38
9.9 REF Electrical Characteristics
VDDR= 3.3V 5 %, TA = 0C to +70C, Test load, Cl=10pF,
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle jitter Duty Cycle Pull-Up Current Min Pull-Up Current Max Pull-Down Current Min Pull-Down Current Max
1000 1000 45 -33
4000 4000 1000 55 -33
ps ps ps % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
30 38
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W83194BR-PT
10. ORDERING INFORMATION
PART NUMBER W83194BR-PT PACKAGE TYPE 48 PIN SSOP PRODUCTION FLOW Commercial, 0C to +70C
11. HOW TO READ THE TOP MARKING
W83194BR-PT 28051234 342GADSA
1st line: Winbond logo and the type number: W83194BR-PT 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G A D SA
320: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR A: Internal use code D: IC revision SA: mask version All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-PT
12. PACKAGE DRAWING AND DIMENSIONS
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W83194BR-PT
13. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
All of the versions before 0.50 are for internal use. 0.5 0.6 0.7 0.8 1.0 1.1 07/07/03 08/19/03 09/30/03 12/18/03 12/27/04 4/13/2005 21 n.a. 11, 12 4, 7~13 7, 8, 9, 18 First published preliminary version. Modify register 14,15 descriptions Modify register 15, add some descriptions Correction IC version, correction some description and default value Update on Web Add disclaimer
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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Publication Release Date: April 13, 2005 Revision 1.1

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