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PRELIMINARY CUSTOMER PROCUREMENT SPECIFICATION
1
Z16C32 SL1660 ONLY
IUSCTM INTEGRATED UNIVERSAL SERIAL CONTROLLER
GENERAL DESCRIPTION
The IUSC (Integrated Universal Serial Controller) is a single-channel multple protocol data communications device with on-chip dual-channel DMA. The integration of a highspeed serial communications channel with a high performance DMA facilitates higher data throughput than is possible with discrete serial/DMA chip combinations. The buffer chaining capabilities combined with features like character counters, frame status block and buffer termination at the end of the frame facilitate sophisticated buffer management that can significantly reduce CPU overhead. The IUSC is software configurable to satisfy a wide variety of serial communications applications. Offered at 20 Mbit/sec, its fast data transfer rate and multiple protocol support make it ideal for applications in todays dynamic environment of changing specifications and ever increasing speed. The many programmable features allow the user to tune the device response to meet system requirements and adapt to future changes with software instead of redesigning hardware. The on-chip DMA channels allow high-speed data transfers for both the receiver and the transmitter. The device supports automatic status transfer through DMA and allows device initialization under DMA control. Each DMA channel can transfer data words in as little as three 50 ns clock cycles and can generate addresses compatible with 32-, 24- or 16-bit memory ranges. The DMA channels may operate in any of four modes: single buffer, pipelined, array-chained, or linked-list. The array-chained and linkedlist modes reduce the problems with segmentation and reassembly of messages in systems. To prevent the DMA from holding bus mastership too long, mastership time may be limited by counting the absolute number of clock cycles, the number of bus transactions, or both. The CPU bus interface is designed for use with any conventional multiplexed or non-multiplexed bus. The device contains a variety of sophisticated internal functions including two baud rate generators, a digital phase-locked loop,
1
character counters, and 32-byte FIFOs for both the receiver and transmitter. The IUSC handles asynchronous formats, synchronous byte-oriented formats (e.g., BISYNC), and synchronous bit-oriented formats such as HDLC. This device supports virtually any serial data transfer application. The IUSC can generate, and check CRC in any synchronous mode and is programmed to check data integrity in various modes. Access to the CRC value allows system software to resend or manipulate it as needed in various applications. The IUSC also has facilities for modem controls. In applications where these controls are not needed, the modem controls can be used for general-purpose I/O. Interrupts are supported by a daisy-chain hierarchy within the serial channel and between the serial channel and the DMA. Support tools are available to aid the designer in efficiently programming the IUSC. The Technical Manual describes in detail all features presented in this Product Specification and gives programming sequence hints. The EPMTM manual (Electronic Programmers Manual) is an MS-DOS, diskbased programming initialization tool, used in conjunction with the Technical Manual. Also, there are assorted application notes and development boards to assist the designer in hardware/software development. Notes: All signals with a preceding front slash, "/", are active Low. For example, B//W (WORD is active Low); /B/W (BYTE is active Low, only). Power connections follow conventional descriptions below: Connection Power Ground Circuit VCC GND Device VDD VSS
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller .
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Host Processor
Bus Interface
16-Bit Internal Data Bus
Transmit DMA
Interrupt Control
Receive DMA
Transmit FIFO Serial Clock Logic Transmitter
Time Slot Assigner DPLL Counters BRG0, BRG1
Receive FIFO
Receiver
Time Slot Assigner
I/O Port
Figure 1. IUSC Block Diagram
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller
B//W /WAIT//RDY Reserved S//D D//C /CS /RESET VCC VCC VCC /AS /DS /RD /WR R//W /INTACK /UAS
1
/BIN /BUSREQ CLK /BOUT GND VCC AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 GND VCC PORT 7
/ABORT /INT IEI IEO GND VCC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND VCC /RxREQ
9 10
1
61 60
PLCC 68 - Pin
26 27
44 43
CP97HHS0100
/TxREQ /RxC /RxD /DCD /TxC /TxD /CTS GND GND GND PORT 0 PORT 1 PORT 2 PORT 3 PORT 4 PORT 5 PORT 6
Figure 2. PLCC 68-Pin Assignments
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64 /UAS /INTACK R/W /WR /RD /DS /AS VCC VCC NC /RESET /CS D//C S//D /Wait//RDY B//W 80 1 65
NC NC NC /BIN NC /BUS REQ CLK /BOUT GND VCC AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 GND VCC NC NC NC PORT 7 60 55 50 45 41 40 PORT 6 PORT 5 PORT 4 PORT 3 PORT 2 PORT 1 PORT 0 GND GND /CTS TxD /TxC /DCD RxD /RxC 25 5 10 15 20 24 /TxREQ
QFP 80 - Pin
1-4
NC NC NC /ABORT NC /INT IEI IEO GND VCC AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 GND VCC /RxREQ NC NC NC
Figure 3. QFP 80-Pin Assignments
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 /AS Bus Timing /DS /RD /WR /CS S//D D//C R//W /INTACK /WAIT//RDY GND GND GND GND GND GND GND
TxD RxD /TxC /RxC /CTS /DCD /RxREQ /ABORT /BUSREQ /TxREQ B//W /UAS /INT IEI IEO PORT 0 PORT 1
Serial Data Channel Clocks Channel I/O
1
Address/ Data Bus
Channel DMA Interface
Channel Interrupt
Z16C32
PORT 2 PORT 3 PORT 4 PORT 5 PORT 6 PORT 7 /BIN /BOUT CLK /RESET VCC VCC VCC VCC VCC VCC VCC
I/O Port
Control
Interrupt
System Clock Device Reset
Ground
Power
Figure 4. Functional Diagram
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ABSOLUTE MAXIMUM RATINGS
SYM VCC TSTG TA Description Supply Voltage Storage Temp Operating Ambient Temp Min -0.3 65 0 Max +70 +150 +70 Unit V C C Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
STANDARD TEST CONDITIONS
The DC Characteristics and Capacitance section below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to GND. Positive current flows into the referenced pin (Standard Test Load). Standard conditions are as follows:
s s s
+5V
1.73 k
+4.5 V < VCC < +5.5 V GND = 0 V
From Output Under Test
50 pF
250 A
TA as specified in Ordering Information
Figure 5. Standard Test Load
CAPACITANCE
Symbol CIN COUT CI/O
Parameter Input Capacitance Output Capacitance Bidirectional Capacitance
Min
Max 10 15 20
Unit pF pF pF
Condition Unmeasured pins returned to ground.
Note: f = 1 MHz, over specified temperature range.
MISCELLANEOUS
Transistor Count - 100,000
TEMPERATURE RANGE
Standard: 0C to +70C
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller
DC CHARACTERISTICS
VCC Symbol VIH VIL VOH1 VOH2 VOL IIL IOL ICC1 Parameter Input High Voltage Input Low Voltage Output High Voltage Output High Voltage Output Low Voltage Input Leakage Output Leakage VCC Supply Current 7 Min 2.2 -0.3 2.4 VCC-0.8 0.4 +10.00 +10.00 50 TA = 0C to +70C Typ Max VCC +0.3 0.8 Unit V V V V V A A mA IOH= -1.6mA IOH= -250 A IOL= +2.0 mA 0.4 < VIN < +2.4V 0.4 < VOUT < +2.4V VCC=5V VIH=4.8V VIL = 0.2V Condition
1
Note: VCC = 5V 10% unless otherwise specified, over specified temperature range.
AC CHARACTERISTICS
Timing Diagrams
/RESET
113 114
/STB
115
Figure 6. Reset Timing
/STB
112 1 1
Note: /STB is any of the following: /DS, /RD, /WD or Pulsed /INTACK.
Figure 7. Bus Cycle Timing
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AC CHARACTERISTICS (Continued)
/CS
12 13
S//D, D//C
14 15
/INTACK (Status)
16 17
/AS
6 2 1 3 7
R//W
20 21
/DS
4 5
AD15-AD0
18 19 8 9 10 11
/RxREQ
22 23
/WAIT//RDY (Wait)
/WAIT//RDY (Ready)
116 79 80
Figure 8. Multiplexed /DS Read Cycle
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller
/CS
12 13
1
14 15
S//D, D//C
/INTACK (Status)
16 17
/AS
2 6 1 7
R//W
20 21
/DS
4 5
AD15-AD0
18 19 24 25
/TxREQ
26 27
/WAIT//RDY (Wait)
/WAIT//RDY (Ready)
116 80
Figure 9. Multiplexed /DS Write Cycle
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AC CHARACTERISTICS (Continued)
/AS
2 98 99 2 98 1 1 99
/INTACK (2-Pulse)
96 97 96 97
AD15-AD0
18 19 18 19 100 101 102
/WAIT//RDY (Ready)
107 79 108
/WAIT//RDY (Wait)
109 110 88
IEI
103 104
IEO
83 105
/INT
106
Figure 10. Multiplexed Double-Pulse Intack Cycle
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller
CLK
123 124 120 121 122
1
/UAS
125 126 127
/AS
128 130 129 135 136
/DS
131 132 133 134
R//W
137
142
143
/RD
138 139 140 141
S//D, D//C
144 149 150 151 152
AD15-AD0
148 145 146 147
/WAIT//RDY (Wait)
153 154
/WAIT//RDY (Ready)
155 156
/BIN
172 173
/ABORT
168 169
Figure 11. Memory Read
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AC CHARACTERISTICS (Continued)
CLK
123 124 120 121 122
/UAS
125 126 127
/AS
128 130 129 159 161
/DS
158 134 160 134
R//W
137 163 165
/WR
162 166 164 166
S//D, D//C
144 149 150 151 152
AD15-AD0
145 145 145 157
/WAIT//RDY (Ready)
153 154
/WAIT//RDY (Wait)
155 156
/BIN
172 173
/ABORT
168 169
Figure 12. Memory Write 1-12 PRELIMINARY CP97HHS0100
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller
AC CHARACTERISTICS Timing Table
VCC No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Symbol Tcyc TwASl TwASh TwDSl TwDSh TdAS(DS) TdDS(AS) TdDS(DRa) TdDS(DRv) TdDS(DRn) TdDS(DRz) TsCS(AS) ThCS(AS) TsADD(AS) ThADD(AS) TsSIA(AS) ThSIA(AS) TsAD(AS) ThAD(AS) TsRW(DS) ThRW(DS) TsDSf(RRQ) TdDSr(RRQ) TsDW(DS) ThDW(DS) TdDSf(TRQ) TdDSr(TRQ) TwRDl TwRDh TdAS(RD) TdRD(AS) TdRD(DRa) TdRD(DRv) TdRD(DRn) TdRD(DRz) TdRDf(RRQ) TdRDr(RRQ) TwWRl TwWRh TdAS(WR) TdWR(AS) TsDW(WR) ThDW(WR) TdWRf(TRQ) Parameter Bus Cycle Time /AS Low Width /AS High Width /DS Low Width /DS High Width /AS Rise to /DS Fall Delay Time /DS Rise to /AS Fall Delay Time /DS Fall to Data Active Delay /DS Fall to Data Valid Delay /DS Rise to Data Not Valid Delay /DS Rise to Data Float Delay /CS to /AS Rise Setup Time /CS to /AS Rise Hold Time Direct Address to /AS Rise Setup Time Direct Address to /AS Rise Hold Time Status /INTACK to /AS Rise Setup Time Status /INTACK to /AS Rise Hold Time Address to /AS Rise Setup Time Address to /AS Rise Hold Time R//W to /DS Fall Setup Time R//W to /DS Fall Hold Time /DS Fall to /RxREQ Inactive Delay /DS Rise to /RxREQ Active Delay Write Data to /DS Rise Setup Time Write Data to DS Rise Hold Time /DS Fall to /TxREQ Inactive Delay /DS Rise to /TxREQ Active Delay /RD Low Width /RD High Width /AS Rise to /RD Fall Delay Time /RD Rise to /AS Fall Delay Time /RD Fall to Data Active Delay /RD Fall to Data Valid Delay /RD Rise to Data Not Valid Delay /RD Rise to Data Float Delay /RD Fall to /RxREQ Inactive Delay /RD Rise to /RxREQ Active Delay /WR Low Width /WR High Width /AS Rise to /WR Fall Delay Time /WR Rise to /AS Fall Delay Time Write Data to /WR Rise Setup Time Write Data to /WR Rise Hold Time /WR Fall to /TxREQ Inactive Delay PRELIMINARY Min 110 30 60 60 50 5 5 0 60 0 20 15 5 15 5 15 5 15 5 0 25 60 0 30 0 65 0 60 50 5 5 0 60 0 20 60 0 60 50 5 5 30 0 65 TA = 0C to +70C Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note(s)
1
1 1
4
5
4
5 1-13
CP97HHS0100
Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller VCC No 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Symbol TdWRr(TRQ) TsCS(DS) ThCS(DS) TsADD(DS) ThADD(DS) TsSIA(DS) ThSIA(DS) TsCS(RD) ThCS(RD) TsADD(RD) ThADD(RD) TsSIA(RD) ThSIA(RD) TsCS(WR) ThCS(WR) TsADD(WR) ThADD(WR) TsSIA(WR) ThSIA(WR) TdDSf(RDY) TdRDY(DRv) TdDSr(RDY) TsIEI(DSI) ThIEI(DSI) TdIEI(IEO) TdAS(IEO) TdDSI(INT) TdDSI(Wf) TdDSI(Wr) TdW(DRv) TdRDf(RDY) TdRDr(RDY) TsIEI(RDI) ThIEI(RDI) TdRDI(INT) TdRDI(Wf) TdRDI(Wr) TwPIAl TwPIAh TdAS(PIA) TdPIA(AS) TdPIA(DRa) TdPIA(DRn) TdPIA(DRz) TsIEI(PIA) ThIEI(PIA) Parameter /WR Rise to /TxREQ Active Delay /CS to /DS Fall Setup Time /CS to /DS Fall Hold Time Direct Address to /DS Fall Setup Time Direct Address to /DS Fall Hold Time Status /INTACK to /DS Fall Setup time Status /INTACK to /DS Fall Hold Time /CS to /RD Fall Setup Time /CS to /RD Fall Hold Time Direct Address to /RD Fall Setup Time Direct Address to /RD Fall Hold Time Status /INTACK to /RD Fall Setup Time Status /INTACK to /RD Fall Hold Time /CS to /WR Fall Setup Time /CS to /WR Fall Hold Time Direct Address to /WR Fall Setup Time Direct Address to /WR Fall Hold Time Status /INTACK to /WR Fall Setup Time Status /INTACK to /WR Fall Hold Time /DS Fall (Intack) to /RDY Fall Delay /RDY Fall to Data Valid Delay /DS Rise to /RDY Rise Delay IEI to /DS Fall (Intack) Setup Time IEI to /DS Rise (Intack) Hold Time IEI to IEO Delay /AS Rise (Intack) to IEO Delay /DS Fall to /INT Inactive Delay /DS Fall (Intack) to /WAIT Fall Delay /DS Fall (Intack) to /WAIT Rise Delay /WAIT Rise to Data Valid Delay /RD Fall (Intack) to /RDY Fall Delay /RD Rise to /RDY Rise Delay IEI to /RD Fall (Intack) Setup Time IEI to /RD Rise (Intack) Hold Time /RD Fall (Intack) to /INT Inactive Delay /RD Fall (Intack) to /WAIT Fall Delay /RD Fall (Intack) to /WAIT Rise Delay Pulsed /INTACK Low Width Pulsed /INTACK High Width /AS Rise to Pulsed /INTACK Fall Delay Time Pulsed /INTACK Rise to /AS Fall Delay Time Pulsed /INTACK Fall to Data Active Delay Pulsed /INTACK Rise to Data Not Valid Delay Pulsed /INTACK Rise to Data Float Delay IEI to Pulsed /INTACK Fall Setup Time IEI to Pulsed /INTACK Rise Hold Time Min 0 0 25 5 25 5 25 0 25 5 25 5 25 0 25 5 25 5 25 200 40 40 10 0 30 60 200 40 200 40 200 40 10 0 200 40 200 60 50 5 5 0 0 20 10 0 TA = 0C to +70C Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Note(s) 2 2 1,2 1,2 2 2 2 2 1,2 1,2 2 2 2 2 1,2 1,2 2 2
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller VCC TA = 0C to +70C Max 60 200 200 40 40 200 200 50 170 60 60 50 50 40 50 25 25 50 5 5 25 20 25 25 20 25 20 25 70 25 30 0 25 20 25 70 25 30 0 TdCLKf(DS) 0 25 25 25 25 10 10 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note(s)
No 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Symbol TdPIA(IEO) TdPIA(INT) TdPIAf(RDY) TdPIAr(RDY) TdPIA(Wf) TdPIA(Wr) TdSIA(INT) TwSTBh TwRESl TwRESh TdRES(STB) TdDSf(RDY) TdWRf(RDY) TdWRr(RDY) TdRDf(RDY) TwCLKl TwCLKh TcCLK TfCLK TrCLK TdCLKr (UAS) TwUASl TdCLKf(UAS) TdCLKr(AS) TwASl TdCLKf(AS) TdAS(DSr) TdCLKr(DS) TwDSlr TdCLKf(DS) TsDR(DS) ThDR(DS) TdCLK(RW) TdAS(RD) TdCLKr(RD) TwRDl TdCLKf(RD) TsDR(RD) ThDR(RD) TdCLK(ADD) TdCLK(AD) ThAD(PC) TdCLK(ADz) TdCLK(ADa) TsAD(UAS) ThAD(UAS)
Parameter Pulsed /INTACK Fall to IEO Delay Pulsed /INTACK Fall to /INT Inactive Delay Pulsed /INTACK Fall to /RDY Fall Delay Pulsed /INTACK Rise to /RDY Rise Delay Pulsed /INTACK Fall to /WAIT Fall Delay Pulsed /INTACK Fall to /WAIT Rise Delay Status /INTACK Fall to IEO Inactive Delay /Strobe High Width /RESET Low Width /RESET High Width /RESET Rise to /STB Fall /DS Fall to /RDY Fall Delay /WR Fall to /RDY Fall Delay /WR Rise to /RDY Rise Delay /RD Fall to /RDY Fall Delay CLK Low Width CLK High Width CLK Cycle Time CLK Fall Time CLK Rise Time CLK Rise to /UAS Fall Delay /UAS Low Width CLK Fall to /UAS Rise Delay CLK Rise to /AS Fall Delay /AS Low Width CLK Fall to /AS Rise Delay /AS Rise to /DS Fall (Read) Delay CLK Rise to /DS Delay /DS (Read) Low Width CLK Fall to /DS Delay Read Data to /DS Rise Setup Time Read Data to /DS Rise Hold Time CLK Rise to R//W Delay /AS Rise to /RD Fall Delay CLK Rise to /RD Delay /RD Low Width CLK Fall to /RD Delay Read Data to /RD Rise Setup Time Read Data to /RD Rise Hold Time CLK Rise to Direct Address Delay CLK Rise to Address Delay Address to CLK Rise Hold Time CLK Rise to Address Float Delay CLK Rise to Address Active Delay Address to /UAS Rise Setup Time Address to /UAS Rise Hold Time
Min
1
2 3
3
6 6,7 6 6 6,7 6 6,8 6 6,9 6 6 6 6 6,8 6 6,9 6 6 6 1,6 6 6 6 6 6 6
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller VCC No 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Symbol TsAD(AS) ThAD(AS) TsW(CLK) ThW(CLK) TsRDY(CLK) ThRDY(CLK) ThDW(CLK) TdAS(DSw) TsDW(DS) TwDSlw ThDW(DS) TdAS(WR) TsDW(WR) TwWRl ThDW(WR) TdCLK(WR) TdCLK(BUSz) TsABT(CLK) ThABT(CLK) TdCLK(BRQ) TdCLK(BUSa) TsBIN(CLK) ThBIN(CLK) TsBRQ(CLK) ThBRQ(CLK) TdBIN(BOT) Parameter Address to /AS Rise Setup Time Address to /AS Rise Hold Time /WAIT to CLK Fall Setup Time /WAIT to CLK Fall Hold Time /READY to CLK Fall Setup Time /READY to CLK Fall Hold Time Write Data to CLK Rise Hold Time /AS Rise to /DS Fall (Write) Delay Write Data to /DS Fall Setup Time /DS (Write) Low Width Write Data to /DS Rise Hold Time /AS Rise to /WR Fall Delay Write Data to /WR Fall Setup Time /WR Low Width Write Data to /WR Rise Hold Time CLK Fall to /WR Delay CLK Rise to Bus Float Delay /ABORT to CLK Rise Setup Time /ABORT to CLK Rise Hold Time CLK Rise to /BUSREQ Delay CLK Rise to Bus Active Delay /BIN to CLK Rise Setup Time /BIN to CLK Rise Hold Time /BUSREQ to CLK Rise Setup Time /BUSREQ to CLK Rise Hold Time /BIN to /BOUT Delay Min 10 10 10 15 10 15 0 40 20 45 20 40 20 45 20 25 25 20 15 25 25 20 15 25 0 60 TA = 0C to +70C Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Note(s) 6 6 6 6 6 6 6 6,10 6, 7 6, 11 6, 8 6, 10 6, 7 6, 11 6, 8 6 6 6 6 6 6 6 6 6 6
Notes: AC Test Conditions: VCC = 5V 10% unless otherwise specified, over specified temperature range. VIH = 2.0V VOH = 2.0V VIL = 0.8V VOL = 0.8V Float = +0.5V 1. Direct Address is any of S//D, D//C or AD15-AD8 used as an address bus. 2. The parameter applies only when /AS is not present. 3. Strobe is any of /DS, /RD, /WR or Pulsed /INTACK. 4. Parameter applies only if read empties the receive FIFO. 5. Parameter applies only if write fills the transmit FIFO. 6. Parameter applies only while the IUSC is bus master. 7. Parameter is clock-cycle dependent, TwCLKh + TfCLK - 5. 8. Parameter is clock-cycle dependent, TwCLKl + TrCLK - 5. 9. Parameter is clock-cycle dependent, TcCLK + TwCLKh + TfCLK - 5. 10. Parameter is clock-cycle dependent, TcCLK - 10. 11. Parameter is clock-cycle dependent, TcCLK -5. Values shown for parameters with notes 7, 8, 9, 10, or 11 are calculated using corresponding equations with minimum values.
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller
AC CHARACTERISTICS General Timing Diagram
1
/RxC, /TxC Receive
1 2 3 4
RxD
5 6
/DCD as /SYNC External
/TxC, /RxC Transmit
7 8
TxD
9 10
/RxC
11
/TxC
12 14 13
/CTS, /DCD
15 15
/DCD as /SYNC Input
16 16
Figure 13. General Timing
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AC CHARACTERISTICS General Timing Table
TA = 0C to +70C No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol TsRxD(RxCr) ThRxD(RxCr) TsRxd(RxCf) ThRxD(RxCf) TsSy(RxC) ThSy(RxC) TdTxCf(TxD) TdTxCr(TxD) TwRxCh TwRxCl TcRxC TwTxCh TwTxCl TcTxC TwExT TWSY Parameter RxD to /RxC Rise Setup Time (x1 Mode) RxD to /RxC Rise Hold Time (x1 Mode) RxD to /RxC Fall Setup Time (x1 Mode) RxD to /RxC Fall Hold Time (x1 Mode) /DCD as /SYNC to /RxC Rise Setup Time /DCD as /SYNC to /RxC Rise Hold Time (x1 Mode) /TxC Fall to TxD Delay /TxC Rise to TxD Delay /RxC High Width /RxC Low Width /RxC Cycle Time /TxC High Width /TxC Low Width /TxC Cycle Time /DCD or /CTS Pulse Width /DCD as /SYNC Input Pulse Width Min 0 20 0 20 0 20 35 35 20 20 50 20 20 50 35 35 Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Note(s) 1 1 1,3 1,3 1 1 2 2,3
AC CHARACTERISTICS System Timing Table
TA = 0C to +70C No 1 2 3 4 5 6 7 Symbol TdRxC(REQ) TdRxC(RxC) TdRxC(INT) TdTxC(REQ) TdTxC(TxC) TdTxC(INT) TdEXT(INT) Parameter /RxC Rise to /RxREQ Valid Delay /TxC Rise to /RxC as Receiver Output Valid Delay /RxC Rise to /INT Valid Delay /TxC Fall to /TxREQ Valid Delay /RxC Fall to /TxC as transmitter Output Valid Delay /TxC Fall to /INT Valid Delay /CTS, /DCD, /TxREQ, /RxREQ transition to /INT Valid Delay Min Max 50 50 50 50 50 50 50 Units ns ns ns ns ns ns ns Note 2 2 2 2 2
Notes: 1. /RxC is /RxC or /TxC, whichever is supplying the receive clock. 2. /TxC is /TxC or /RxC, whichever is supplying the transmit clock. 3. Parameter applies only to FM encoding/decoding
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller
IUSC TECHNICAL MANUAL CORRECTION
There is a typographical error in the Q2/91 printing of the IUSC Technical Manual. The transmit and receive interrupt pending (IP) and interrupt under service (IUS) bits are Register CDIR DICR SDIR Corrected Register Bits RxIUS=D9 RxIUS=D9 TxIUS-D8 TxIUS=D8 RxIP=D1 RxIE=D1 RxIP=D1 TxIP=D0 TxIE=D0 TxIE=D0 shown in reverse order. The correct register bit locations are shown below. The correct bit functions are also shown in the IUSC Product Specification.
1
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AC CHARACTERISTICS System Timing Diagram
/RxC, /TxC Receive
/RxREQ Request
1
/RxC as Receiver Output
2
/INT
3
/RxC, /TxC Transmit
/TxREQ
4
/TxC as Transmitter Output
5
/INT
6
/CTS, /DCD, /TxREQ, /RxREQ
/INT
7
Figure 14. Z16C32 System Timing
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Zilog
Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller
(c) 1997 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc. makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be responsible for any errors that may appear in this document. Zilog, Inc. makes no commitment to update or keep current the information contained in this document.
Zilog's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Zilog, Inc. 210 East Hacienda Ave. Campbell, CA 95008-6600 Telephone (408) 370-8000 FAX 408 370-8056 Internet: http://www.zilog.com
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CP97HHS0100
PRELIMINARY
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Z16C32 SL1660 ONLY IUSCTM Integrated Universal Serial Controller
Zilog
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PRELIMINARY
CP97HHS0100

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