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PRELIMINARY PRODUCT SPECIFICATION*
Z8PE003
FEATURE-ENHANCED Z8PLUS 1K ROM ONE-TIME PROGRAMMABLE (OTP) MICROCONTROLLER
FEATURES
Part Number ROM (kb) RAM* (Bytes) 64 Speed (MHz) 10
* *
16-Bit Programmable Watch-Dog Timer (WDT) Software Programmable Timers Configurable as: - Two 8-Bit Standard Timers and One 16-Bit Standard Timer - One 16-Bit Standard Timer and One 16-Bit Pulse Width Modulator (PWM) Timer
Z8PE003 1 Note: *General-Purpose.
Microcontroller Core Features * * * * * *
All Instructions Execute in one 1-s Instruction Cycle with a 10-MHz Crystal 1K x 8 On-Chip OTP EPROM Memory 64 x 8 General-Purpose Registers (SRAM) Six Vectored Interrupts with Fixed Priority Operating Speed: DC-10 MHz Six Addressing Modes: R, IR, X, D, RA, and IM
Additional Features *
On-Chip Oscillator that accepts External Crystal (XTAL), Ceramic Resonator, Inductor Capacitor (LC), or External Clocks External Resistor Capacitor (RC), an Oscillator Option Voltage Brown-Out/Power-On Reset (VBO/POR) Programmable Options: - EPROM Protect - RC Oscillator Power Reduction Modes: - HALT Mode with Peripheral Units Active - STOP Mode for Minimum Power Dissipation
* * *
Peripheral Features * *
14 Total Input/Output Pins One 8-Bit I/O Port (Port A) - I/O Bit Programmable - Each Bit Programmable as Push-Pull or Open-Drain One 6-Bit I/O Port (Port B) - I/O Bit Programmable - Includes Special Functionality: Stop-Mode Recovery Input, Comparator Inputs, Selectable Edge Interrupts, and Timer Output One Analog Comparator
*
*
CMOS/Technology Features * * *
Low-Power Consumption 3.0V to 5.5V Operating Range @ 0C to +70C 4.5V to 5.5V Operating Range @ -40C to +105C 18-Pin DIP, SOIC, and 20-Pin SSOP Packages
*
GENERAL DESCRIPTION
The Z8PE003 is the newest member of the Z8Plus Microprocessor (MPU) family. Similar to the Z8E000 and Z8E001, the Z8PE003 offers easy software development, debug, prototyping, and an attractive One-Time Programmable (OTP) solution.
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For applications demanding powerful I/O capabilities, the Z8PE003's dedicated input and output lines are grouped into two ports, and are configurable under software control.
*This document is considered preliminary until the completion of full characterization.
Z8PE003 Z8Plus OTP Microcontroller
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GENERAL DESCRIPTION (Continued)
Both the 8-bit and 16-bit on-chip timers, with several userselectable modes, administer real-time tasks such as counting/timing and I/O data communications.
Note: All signals with an overline are active Low. For example, B/W, in which WORD is active Low; and B/W, in which BYTE is active Low.
Power connections follow conventional descriptions below:
Connection Power Ground Circuit VCC GND Device VDD VSS
XTAL VCC GND
Two 8-Bit Timers or One 16-Bit PWM Timer
Machine Timing
One 16-Bit Standard Timer
ALU
FLAGS
Interrupt Control
WDT
OTP Program Memory
Register Pointer One Analog Comparator RAM Register File Program Counter
POR & VBO
Port A
Port B
I/O
I/O
Figure 1. Functional Block Diagram
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AD 9-0 Z8Plus Core AD 9-0 Address MUX AD 9-0 Address Counter EPROM D7-0 Data MUX D7-0 Port A
Option Bits
PGM + Test Mode Logic
PGM ADCLK XTAL
ADCLR/VPP
Figure 2. EPROM Programming Mode Block Diagram
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PIN DESCRIPTION
PB1 PB2 PB3 PB4 PB5 PA7 PA6 PA5 PA4
1
18
18-Pin DIP/SOIC
9
10
PB0 XTAL1 XTAL2 VSS VCC PA0 PA1 PA2 PA3
Figure 3. 18-Pin DIP/SOIC Pin Identification
Table 1. Standard Programming Mode Pin # 1-5 6-9 10-13 14 15 16 17 18 Symbol PB1-PB5 PA7-PA4 PA3-PA0 VCC VSS XTAL2 XTAL1 PB0 Function Port B, Pins 1,2,3,4,5 Port A, Pins 7,6,5,4 Port A, Pins 3,2,1,0 Power Supply Ground Crystal Oscillator Clock Crystal Oscillator Clock Port B, Pin 0 Output Input Input/Output Direction Input/Output Input/Output Input/Output
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PGM GND GND GND ADCLR/VPP D7 D6 D5 D4
1
18
18-Pin DIP/SOIC
9
10
ADCLK XTAL1 NC GND VDD D0 D1 D2 D3
Figure 4. 18-Pin DIP/SOIC Pin Identification
Table 2. EPROM Programming Mode Pin # 1 2-4 5 6-9 10-13 14 15 16 17 18 Symbol PGM GND ADCLR/VPP D7-D4 D3-D0 VDD GND NC XTAL1 ADCLK Function Program Mode Ground Clear Clock/Program Voltage Data 7,6,5,4 Data 3,2,1,0 Power Supply Ground No Connection 1-MHz Clock Address Clock Direction Input Input Input/Output Input/Output
Input Input
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PIN DESCRIPTION (Continued)
PB1 PB2 PB3 PB4 PB5 NC PA7 PA6 PA5 PA4
1
20
20-Pin SSOP
10
11
PB0 XTAL1 XTAL2 VSS VCC NC PA0 PA1 PA2 PA3
Figure 5. 20-Pin SSOP Pin Identification
Table 3. Standard Programming Mode Pin # 1-5 6 7-10 11-14 15 16 17 18 19 20 Symbol PB1-PB5 NC PA7-PA4 PA3-PA0 NC VCC VSS XTAL2 XTAL1 PB0 Function Port B, Pins 1,2,3,4,5 No Connection Port A, Pins 7,6,5,4 Port A, Pins 3,2,1,0 No Connection Power Supply Ground Crystal Oscillator Clock Crystal Oscillator Clock Port B, Pin 0 Output Input Input/Output Direction Input/Output Input/Output Input/Output
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PGM GND GND GND ADCLR/VPP NC D7 D6 D5 D4
1
20
20-Pin SSOP
ADCLK XTAL1 NC GND VDD NC D0 D1 D2 D3
10
11
Figure 6. 20-Pin SSOP Pin Identification/EPROM Programming Mode
Table 4. EPROM Programming Mode Pin # 1 2-4 5 6 7-10 11-14 15 16 17 18 19 20 Symbol PGM GND ADCLR/VPP NC D7-D4 D3-D0 NC VDD GND NC XTAL1 ADCLK Function Program Mode Ground Clear Clock/Program Voltage No Connection Data 7,6,5,4 Data 3,2,1,0 No Connection Power Supply Ground No Connection 1-MHz Clock Address Clock Direction Input Input Input/Output Input/Output
Input Input
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ABSOLUTE MAXIMUM RATINGS
Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to VSS Voltage on VDD Pin with Respect to VSS Voltage on PB5 Pin with Respect to VSS Total Power Dissipation Maximum Allowable Current out of VSS Maximum Allowable Current into VDD Maximum Allowable Current into an Input Pin Maximum Allowable Current into an Open-Drain Pin Maximum Allowable Output Current Sunk by Any I/O Pin Maximum Allowable Output Current Sourced by Any I/O Pin Maximum Allowable Output Current Sunk by Port A Maximum Allowable Output Current Sourced by Port A Maximum Allowable Output Current Sunk by Port B Maximum Allowable Output Current Sourced by Port B -600 -600 Min -40 -65 -0.6 -0.3 -0.6 Max +105 +150 +7 +7 VDD+1 880 40 40 +600 +600 25 25 40 40 40 40 Units C C V V V mW mA mA A A mA mA mA mA mA mA 2 3 3 4 5 Note
1
3 3 3 3
Notes: 1. Applies to all pins except the PB5 pin and where otherwise noted. 2. There is no input protection diode from pin to VDD. 3. Peak Current. Do not exceed 25mA average current in either direction. 4. Excludes XTAL pins. 5. Device pin is not at an output Low state.
Stresses greater than those listed under Absolute Maximum Ratings can cause permanent damage to the device. This rating is a stress rating only. Functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period
can affect device reliability. Total power dissipation should not exceed 880 mW for the package. Power dissipation is calculated as follows:
Total Power Dissipation = VDD x [IDD - (sum of IOH)] + sum of [(VDD - VOH) x IOH] + sum of (VOL x IOL)
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STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 7).
From Output Under Test
150 pF
Figure 7. Test Load Diagram
CAPACITANCE TA = 25C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
Parameter Input capacitance Output capacitance I/O capacitance Min 0 0 0 Max 12 pF 12 pF 12 pF
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DC ELECTRICAL CHARACTERISTICS
Table 5. DC Electrical Characteristics TA = 0C to +70C Standard Temperatures Sym VCH Parameter Clock Input High Voltage VCC
1
Min 0.7VCC 0.7VCC VSS-0.3 VSS-0.3 0.7VCC 0.7VCC VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4
Max VCC+0.3 VCC+0.3 0.2VCC 0.2VCC VCC+0.3 VCC+0.3 0.2VCC 0.2VCC
Typical2 @ 25C Units Conditions 1.3 2.5 0.7 1.5 1.3 2.5 0.7 1.5 3.1 4.8 V V V V V V V V V V V V V V mV mV A A A A V V 200 200 2.60 kOhm V IOH = -2.0 mA IOH = -2.0 mA IOL = +4.0 mA IOL = +4.0 mA IOL = +6 mA IOL = +12 mA Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes
3.0V 5.5V
VCL
Clock Input Low Voltage
3.0V 5.5V
VIH VIL VOH VOL1 VOL2
Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage
3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
0.6 0.4 1.2 1.2 25.0 25.0 2.0 2.0 2.0 2.0 VCC-1.0 VCC-1.0
0.2 0.1 0.5 0.5 10.0 10.0 0.064 0.064 0.114 0.114
VOFFSET Comparator Input Offset Voltage IIL IOL VICR Input Leakage Output Leakage Comparator Input Common Mode Voltage Range PB5 Pull-up Resistor VCC Low-Voltage Protection
-1.0 -1.0 -1.0 -1.0 VSS-0.3 VSS-0.3 100 100 2.45
VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC 3 3 4
RPB5 VLV
2.85
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.0V; the VCC voltage specification of 5.5V guarantees 5.0V 0.5V. 2. Typical values are measured at VCC = 3.3V and VCC = 5.0V; VSS = 0V = GND. 3. For the analog comparator input when the analog comparator is enabled. 4. No protection diode is provided from the pin to VCC. External protection is recommended. 5. All outputs are unloaded and all inputs are at the VCC or VSS level. 6. CL1 = CL2 = 22 pF. 7. Same as note 5, except inputs are at VCC.
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ZiLOG Table 5. DC Electrical Characteristics (Continued) TA = 0C to +70C Standard Temperatures Sym ICC ICC1 Parameter Supply Current Standby Current VCC
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Z8PE003 Z8Plus OTP Microcontroller
Min
Max 2.5 6.0 2.0 4.0 500
Typical2 @ 25C Units Conditions 2.0 3.5 1.0 2.5 150 mA mA mA mA nA @ 10 MHz @ 10 MHz HALT mode VIN = 0V, VCC @ 10 MHz HALT mode VIN = 0V, VCC @ 10 MHz STOP mode VIN = 0V, VCC
Notes 5,6 5,6 5,6 5,6 7
3.0V 5.5V 3.0V 5.5V
ICC2
Standby Current
Notes: 1. The VCC voltage specification of 3.0V guarantees 3.0V; the VCC voltage specification of 5.5V guarantees 5.0V 0.5V. 2. Typical values are measured at VCC = 3.3V and VCC = 5.0V; VSS = 0V = GND. 3. For the analog comparator input when the analog comparator is enabled. 4. No protection diode is provided from the pin to VCC. External protection is recommended. 5. All outputs are unloaded and all inputs are at the VCC or VSS level. 6. CL1 = CL2 = 22 pF. 7. Same as note 5, except inputs are at VCC.
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DC ELECTRICAL CHARACTERISTICS (Continued)
Table 6. DC Electrical Characteristics TA = -40C to +105C Extended Temperatures Sym VCH Parameter Clock Input High Voltage VCC
1
Min 0.7 VCC 0.7 VCC VSS-0.3 VSS-0.3 0.7 VCC 0.7 VCC VSS-0.3 VSS-0.3 VCC-0.4 VCC-0.4
Max VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC VCC+0.3 VCC+0.3 0.2 VCC 0.2 VCC
Typical2 @ 25C Units Conditions 2.5 2.5 1.5 1.5 2.5 2.5 1.5 1.5 4.8 4.8 V V V V V V V V V V V V V V mV mV A A A A V V 200 200 2.60 4.0 4.0 kOhm V mA mA @ 10 MHz @ 10 MHz IOH = -2.0 mA IOH = -2.0 mA IOL = +4.0 mA IOL = +4.0 mA IOL = +12 mA IOL = +12 mA Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator Driven by External Clock Generator
Notes
4.5V 5.5V
VCL
Clock Input Low Voltage
4.5V 5.5V
VIH VIL VOH VOL1 VOL2 VOFFSET IIL IOL VICR
Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output Low Voltage Comparator Input Offset Voltage Input Leakage Output Leakage Comparator Input Common Mode Voltage Range PB5 Pull-up Resistor VCC Low-Voltage Protection Supply Current
4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V 4.5V 5.5V
0.4 0.4 1.2 1.2 25.0 25.0 2.0 2.0 2.0 2.0 VCC -1.5V VCC -1.5V
0.1 0.1 0.5 0.5 10.0 10.0 <1.0 <1.0 <1.0 <1.0
-1.0 -1.0 -1.0 -1.0 0 0 100 100 2.45
VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC VIN = 0V, VCC 3 3 4
RPB5 VLV ICC
2.85 7.0 7.0
4.5V 5.5V
5,6 5,6
Notes: 1. The VCC voltage specification of 4.5V and 5.5V guarantees 5.0V 0.5V. 2. Typical values are measured at VCC = 5.0V; VSS = 0V = GND. 3. For analog comparator input when analog comparator is enabled. 4. No protection diode is provided from the pin to VCC. External protection is recommended. 5. All outputs are unloaded and all inputs are at VCC or VSS level. 6. CL1 = CL2 = 22 pF. 7. Same as note 5, except inputs are at VCC.
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ZiLOG Table 6. DC Electrical Characteristics (Continued) TA = -40C to +105C Extended Temperatures Sym ICC1 Parameter Standby Current VCC
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Z8PE003 Z8Plus OTP Microcontroller
Min
Max 2.0 2.0 700 700
Typical2 @ 25C Units Conditions 1.0 1.0 250 250 mA mA nA nA HALT mode VIN = 0V, VCC @ 10 MHz HALT mode VIN = 0V, VCC @ 10 MHz STOP mode VIN = 0V,VCC STOP mode VIN = 0V,VCC
Notes 5,6 5,6 7 7
4.5V 5.5V
ICC2
Standby Current
4.5V 5.5V
Notes: 1. The VCC voltage specification of 4.5V and 5.5V guarantees 5.0V 0.5V. 2. Typical values are measured at VCC = 5.0V; VSS = 0V = GND. 3. For analog comparator input when analog comparator is enabled. 4. No protection diode is provided from the pin to VCC. External protection is recommended. 5. All outputs are unloaded and all inputs are at VCC or VSS level. 6. CL1 = CL2 = 22 pF. 7. Same as note 5, except inputs are at VCC.
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AC ELECTRICAL CHARACTERISTICS
1
3
Clock
2
2
3
IRQ N
4
5
Figure 8. AC Electrical Timing Diagram
Table 7. Additional Timing TA = 0C to +70C TA = -40C to +105C @ 10 MHz No 1 2 3 4 5 6 7 8 Symbol TPC TRC,TFC TWC TWIL TWIH TWSM TOST TPOR Parameter Input Clock Period Clock Input Rise and Fall Times Input Clock Width Int. Request Input Low Time Int. Request Input High Time STOP mode Recovery Width Spec. Oscillator Start-Up Time Power-On Reset Time VCC1 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V 3.0V 5.5V
Notes: 1. The VDD voltage specification of 3.0V guarantees 3.0V. The VDD voltage specification of 5.5V guarantees 5.0V 0.5V. 2. Timing Reference uses 0.7 VCC for a logical 1 and 0.2 VCC for a logical 0.
Min 100 100
Max DC DC 15 15
Units ns ns ns ns ns ns ns ns
Notes 2 2 2 2 2 2 2 2 2 2
50 50 70 70 5TpC 5TpC 25 25 5TpC 5TpC 128 TPC + TOST
ns ns
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Z8PE003 Z8Plus OTP Microcontroller
Z8PLUS CORE
The device is based on the ZiLOG Z8Plus Core Architecture. This core is capable of addressing up to 64KB of program memory and 4 KB of RAM. Register RAM is accessed as either 8- or 16-bit registers using a combination of 4-, 8-, and 12-bit addressing modes. The architecture supports up to 15 vectored interrupts from external and internal sources. The processor decodes 44 CISC instructions using 6 addressing modes. See the Z8Plus User's Manual for more information.
RESET
This section describes the Z8Plus reset conditions, reset timing, and register initialization procedures. Reset is generated by the Voltage Brown-Out/Power-On Reset (VBO/POR), Watch-Dog Timer (WDT), and Stop-Mode Recovery (SMR). A system reset overrides all other operating conditions and puts the Z8Plus device into a known state. To initialize the chip's internal logic, the POR device counts 64 internal clock cycles after the oscillator stabilizes. The control registers and ports are not reset to their default conditions after wakeup from a STOP mode or WDT time-out. During RESET, the value of the program counter is 0020H. The I/O ports and control registers are configured to their default reset state. Resetting the device does not affect the contents of the general-purpose registers. The RESET circuit initializes the control and peripheral registers, as shown in Table 8. Specific reset values are indicated by a 1 or a 0, while bits whose states are unchanged or unknown from Power-Up are indicated by the letter U. Program execution starts 10 External Crystal (XTAL) clock cycles after the POR delay. The initial instruction fetch is from location 0020H. Figure 9 indicates reset timing. After a reset, the first routine executed must be one that initializes the TCTLHI control register to the required system configuration This activity is followed by initialization of the remaining control registers.
Table 8. Control and Peripheral Registers* Bits Register (HEX) FF FE FD FC FB FA F9-F0 EF-E0 DF-D8 D7 D6 Register Name Stack Pointer Reserved Register Pointer Flags Interrupt Mask Interrupt Request Reserved Virtual Copy Reserved Port B Special Function Port B Directional Control Port B Output 7 0 U U 0 0 6 0 U U 0 0 5 U U U 0 0 4 U U U 0 0 3 U 0 U 0 0 2 U 0 U 0 0 1 U 0 * 0 0 0 Comments
U Stack pointer is not affected by RESET. 0 * 0 0 Register pointer is not affected by RESET. Only WDT & SMR flags are affected by RESET. All interrupts masked by RESET. All interrupt requests cleared by RESET. Virtual copy of the current working register set.
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
Deactivates all port special functions after RESET. Defines all bits as inputs in PortB after RESET.
D5 U U U U U U U U Output register not affected by RESET. Note: *The SMR and WDT flags are set to indicate the source of the RESET.
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RESET (Continued)
Table 8. Control and Peripheral Registers* (Continued) Bits Register (HEX) D4 D3 D2 Register Name Port B Input Port A Special Function Port A Directional Control Port A Output Port A Input Reserved Reserved T1VAL T0VAL T3VAL T2VAL T3AR T2AR T1ARHI T0ARHI T1ARLO T0ARLO WDTHI WDTLO TCTLHI 7 U 0 0 6 U 0 0 5 U 0 0 4 U 0 0 3 U 0 0 2 U 0 0 1 U 0 0 0 Comments
U Current sample of the input pin following RESET. 0 Deactivates all port special functions after RESET. 0 Defines all bits as inputs in PortA after RESET. U Output register not affected by RESET U Current sample of the input pin following RESET.
D1 D0 CF CE CD CC CB CA C9 C8 C7 C6 C5 C4 C3 C2 C1
U U
U U
U U
U U
U U
U U
U U
U U U U U U U U U U 1 1 1
U U U U U U U U U U 1 1 1
U U U U U U U U U U 1 1 1
U U U U U U U U U U 1 1 1
U U U U U U U U U U 1 1 1
U U U U U U U U U U 1 1 0
U U U U U U U U U U 1 1 0
C0 TCTLLO 0 0 0 0 0 0 0 Note: *The SMR and WDT flags are set to indicate the source of the RESET.
U U U U U U U U U U 1 1 0 WDT enabled in HALT mode, WDT time-out at maximum value, STOP mode disabled. 0 All standard timers are disabled.
Table 9. Flag Register Bit D1, D0 D1 0 0 1 1 D0 0 1 0 1 Reset Source VBO/POR SMR Recovery WDT Reset Reserved
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First Machine Cycle Clock
Internal Reset 128 XTAL Clock Cycles 10 XTAL CLOCK CYCLES First Instruction Fetch
Figure 9. Reset Timing
TCTLHI D6,D5,D4
3
WDT Tap Select
XTAL
/64
16-Bit Timer
WDTRST
Watch-Dog Timer
SMR (PB0) 64 SCLK POR Delay
SMR Logic
VBO/POR
Figure 10. Reset Circuitry with POR, WDT, VBO, and SMR
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INTERRUPT SOURCES
Table 10 presents the interrupt types, sources, and vectors available in the Z8Plus. Other processors from the Z8Plus family may define the interrupts differently.
Table 10. Interrupt Types, Sources, and Vectors Name IREQ0 IREQ1 IREQ2 IREQ3 IREQ4 IREQ5 IREQ6-IREQ15 Sources Timer0 Time-out PB4 High-to-Low Transition Timer1 Time-out PB2 High-to-Low Transition PB4 Low-to-High Transition Timer2 Time-out Reserved Vector Location 2,3 4,5 6,7 8,9 A,B C,D Comments Internal Fixed Priority 1 (Highest)
External (PB4), Edge 2 Triggered Internal 3 External (PB2), Edge 4 Triggered External (PB4), Edge 5 Triggered Internal 6 (Lowest) Reserved for future expansion
External Interrupt Sources
External sources can be generated by a transition on the corresponding Port pin. The interrupt may detect a rising edge, a falling edge, or both.
Notes: The interrupt sources and trigger conditions are device dependent. See the device product specification to determine available sources (internal and external), triggering edge options, and exact programming details. Although interrupts are edge triggered, minimum interrupt request Low and High times must be observed for proper operation. See the device product specification for exact timing requirements on external interrupt requests (TWIL, TWIH).
details. For more details on the interrupt sources, refer to the chapters describing the timers, comparators, I/O ports, and other peripherals.
Interrupt Mask Register (IMASK) Initialization
The IMASK register individually or globally enables or disables the interrupts (Table 11). When bits 0 through 5 are set to 1, the corresponding interrupt requests are enabled. Bit 7 is the master enable bit and must be set before any of the individual interrupt requests can be recognized. Resetting bit 7 disables all the interrupt requests. Bit 7 is set and reset by the EI and DI instructions. It is automatically set to 0 during an interrupt service routine and set to 1 following the execution of an Interrupt Return (IRET) instruction. The IMASK registers are reset to 00h, disabling all interrupts.
Notes: It is not good programming practice to directly assign a value to the master enable bit. A value change should always be accomplished by issuing the EI and DI instructions. Care should be taken not to set or clear IMASK bits while the master enable is set.
Internal Interrupt Sources
Internal interrupt sources and trigger conditions are device dependent. On-chip peripherals may set interrupt under various conditions. Some peripherals always set their corresponding IREQ bit while others must be specifically configured to do so. See the device product specification to determine available sources, triggering edge options, and exact programming
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ZiLOG Table 11. Interrupt Mask Register--IMASK (FBh) Bit R/W Reset 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0
Z8PE003 Z8Plus OTP Microcontroller
Interrupt Request (IREQ) Register Initialization
IREQ (Table 12) is a register that stores the interrupt re-
R = Read W = Write X = Indeterminate U = Undefined/ Undetermined
quests for both vectored and polled interrupts. When an interrupt is issued, the corresponding bit position in the register is set to 1. Bits 0 to 5 are assigned to interrupt requests IREQ0 to IREQ5, respectively. Whenever RESET is executed, the IREQ resistor is set to
00h. Table 12. Interrupt Request Register-IREQ (FAh) Bit R/W Reset 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0
Bit Position 7 6 5 4 3 2 1 0
R/W
Value 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1
Description Disables Interrupts Enables Interrupts Reserved, must be 0 Disables IRQ5 Enables IRQ5 Disables IRQ4 Enables IRQ4 Disables IRQ3 Enables IRQ3 Disables IRQ2 Enables IRQ2 Disables IRQ1 Enables IRQ1 Disables IRQ0 Enables IRQ0
R = Read W = Write X = Indeterminate U = Undefined/ Undetermined
Bit Position 7 6 5 4 3 2 1 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Value 0 0 0 1 0 1 0 1 0 1 0 1 0 1
Description Reserved, must be 0 Reserved, must be 0 IRQ5 reset IRQ5 set IRQ4 reset IRQ4 set IRQ3 reset IRQ3 set IRQ2 reset IRQ2 set IRQ1 reset IRQ1 set IRQ0 reset IRQ0 set
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IREQ SOFTWARE INTERRUPT GENERATION
IREQ can be used to generate software interrupts by specifying IREQ as the destination of any instruction referencing the Z8Plus Standard Register File. These software interrupts (SWI) are controlled in the same manner as hardware generated requests. In other words, the IMASK controls the enabling of each SWI.
Nesting of Vectored Interrupts
Nesting vectored interrupts allows higher priority requests to interrupt a lower priority request. To initiate vectored interrupt nesting, perform the following steps during the interrupt service routine:
To generate a SWI, the request bit in IREQ is set by the following statement:
OR IREQ,#NUMBER
* * * * * * *
PUSH the old IMASK on the stack
Load IMASK with a new mask to disable lower priority interrupts Execute an EI instruction Proceed with interrupt processing Execute a DI instruction after processing is complete Restore the IMASK to its original value by POPing the previous mask from the stack Execute IRET
The immediate data variable, NUMBER, has a 1 in the bit position corresponding to the required level of SWI. For example, an SWI must be issued when an IREQ5 occurs. Bit 5 of NUMBER must have a value of 1.
OR IREQ, #00100000B
If the interrupt system is globally enabled, IREQ5 is enabled, and there are no higher priority requests pending, control is transferred to the service routine pointed to by the IREQ5 vector.
Note: Software may modify the IREQ register at any time. Care should be taken when using any instruction that modifies the IREQ register while interrupt sources are active. The software writeback always takes precedence over the hardware. If a software writeback takes place on the same cycle as an interrupt source tries to set an IREQ bit, the new interrupt is lost.
Depending on the application, some simplification of the above procedure may be possible.
RESET Conditions
The IMASK and IREQ registers initialize to 00h on RESET.
PROGRAMMABLE OPTIONS
EPROM Protect. When selecting the DISABLE EPROM PROTECT/ENABLE TESTMODE option, the user can read
the software code in the program memory. ZiLOG's internal factory test mode, or any of the standard test mode methods, are useful for reading or verifying the code in the microcontroller when using an EPROM programmer. If the user should select the ENABLE EPROM PROTECT/DISABLE TESTMODE option, it is not possible to read the code using a tester, programmer, or any other standard method. As a result, ZiLOG is unable to test the EPROM memory at any time after customer delivery.
This option bit only affects the user's ability to read the code and has no effect on the operation of the part in an application. ZiLOG tests the EPROM memory before customer delivery whether or not the ENABLE EPROM PROTECT/DISABLE TESTMODE option is selected; ZiLOG provides a standard warranty for the part.
System Clock Source. When selecting the RC OSCILLATOR ENABLE option, the oscillator circuit on the micro-
controller is configured to work with an external RC circuit. When selecting the Crystal/Other Clock Source option, the oscillator circuit is configured to work with an external crystal, ceramic resonator, or LC oscillator.
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WATCH-DOG TIMER
The Watch-Dog Timer (WDT) is a retriggerable one-shot 16-bit timer that resets the device if it reaches its terminal count. The WDT is driven by the XTAL2 clock pin. To provide the longer time-out periods required in applications, the watch-dog timer is only updated every 64th clock cycle. When operating in the RUN or HALT modes, a WDT timeout reset is functionally equivalent to an interrupt vectoring the PC to 0020H, and setting the WDT flag to 1. Coming out of RESET, the WDT is fully enabled with its time-out value set at minimum, unless otherwise programmed during the first instruction. Subsequent executions of the WDT instruction reinitialize the watch-dog timer registers (C2h and C3h) to their initial values as defined by bits D6, D5, and D4 of the TCTLHI register. The WDT cannot be disabled except on the first cycle after RESET and when the device enters STOP mode. The WDT instruction should be executed often enough to provide some margin of time to allow the WDT registers to approach 0. Because the WDT time-out periods are relatively long, a WDT RESET occurs in the unlikely event that the WDT times out on exactly the same cycle that the WDT instruction is executed.
RESET clears both the WDT and SMR flags. A WDT timeout sets the WDT flag, and the STOP instruction sets the SMR flag. This function enables software to determine whether a WDT time-out or a return from STOP mode occurred. Reading the WDT and SMR flags does not reset the flag to 0; therefore, the user must clear the flag via software. Note: Failure to clear the SMR flag can result in unexpected behavior.
0C1
TCTLHI D6 D5 D4 D3 D2 D1 D0
D7
Reserved (must be 0) 0 = STOP mode enabled 1 = STOP mode disabled* D6 ---0 0 0 0 1 1 1 1 D5 ---0 0 1 1 0 0 1 1 D4 WDT TIMEOUT VALUE ---- -------------------------------0 Disabled 1 65,536 TpC* 0 131,072 TpC 1 262,144 TpC 0 524,288 TpC 1 1,048,576 TpC 0 2,097,152 TpC 1 8,388,608 TpC
(XTAL clocks to time-out) 1 = WDT enabled in HALT mode* 0 = WDT disabled in HALT mode
*Designates the default value after RESET.
Figure 11. TCTLHI Register for Control of WDT
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ZiLOG STOP MODE (D3). Coming out of RESET, the device STOP mode is disabled. If an application requires use of STOP mode, bit D3 must be cleared immediately at leaving RESET. If bit D3 is set, the STOP instruction executes as a NOP. If bit D3 is cleared, the STOP instruction enters STOP
Note: The WDT can only be disabled via software if the first instruction out of the RESET performs this function. Logic within the device detects that it is in the process of executing the first instruction after the processor leaves RESET. During the execution of this instruction, the upper five bits of the TCTLHI register can be written. After this first instruction, hardware does not allow the upper five bits of this register to be written.
mode.
Bits 2, 1 and 0. These bits are reserved and must be 0. Table 13. WDT Time-Out
The TCTLHI bits for control of the WDT are described below:
WDT Time Select (D6, D5, D4). Bits 6, 5, and 4 determine
D6
D5
D4
Crystal Clocks* to Timeout
Time-Out Using a 10-MHz Crystal
the time-out period. Table 13 indicates the range of timeout values that can be obtained. The default values of D6, D5, and D4 are 001, which sets the WDT to its minimum time-out period when coming out of RESET.
WDT During HALT (D7). This bit determines whether or not the WDT is active during HALT mode. A 1 indicates active during HALT mode. A 0 prevents the WDT from resetting the part while halted. Coming out of RESET, the WDT is enabled during HALT mode.
0 0 0 Disabled Disabled 0 0 1 65,536 TpC 6.55 ms 0 1 0 131,072 TpC 13.11 ms 0 1 1 262,144 TpC 26.21 ms 1 0 0 524,288 TpC 52.43 ms 1 0 1 1,048,576 TpC 104.86 ms 1 1 0 2,097,152 TpC 209.72 ms 1 1 1 8,388,608 TpC 838.86 ms Note: *TpC is an XTAL clock cycle. The default at reset is 001.
POWER-DOWN MODES
In addition to the standard RUN mode, the Z8Plus MCU supports two Power-Down modes to minimize device current consumption. The two modes supported are HALT and
STOP.
HALT MODE OPERATION
The HALT mode suspends instruction execution and turns off the internal CPU clock. The on-chip oscillator circuit remains active so the internal clock continues to run and is applied to the timers and interrupt logic. To enter HALT mode, the device only requires a HALT instruction. It is not necessary to execute a NOP instruction immediately before the HALT instruction.
7F HALT ; enter HALT mode HALT mode can be exited by servicing an external or inter-
nal interrupt. The first instruction executed is the interrupt service routine. At completion of the interrupt service routine, the user program continues from the instruction after the HALT instruction. The HALT mode can also be exited via a RESET activation or a Watch-Dog Timer (WDT) time-out. In these cases, program execution restarts at 0020H, the reset restart address.
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STOP MODE OPERATION
The STOP mode provides the lowest possible device standby current. This instruction turns off the on-chip oscillator and internal system clock. To enter the STOP mode, the Z8Plus only requires a STOP instruction. It is not necessary to execute a NOP instruction immediately before the STOP instruction.
6F STOP ;enter STOP mode
The Z8Plus provides a dedicated Stop-Mode Recovery (SMR) circuit. In this case, a low-level applied to input pin PB0 (I/O Port B, bit 0) triggers an SMR. To use this mode, pin PB0 must be configured as an input and the special function selected before the STOP mode is entered. The Low level on PB0 must be held for a minimum pulse width TWSM. Program execution starts at address 20h, after the POR delay.
Notes: 1. The PB0 input, when used for Stop-Mode Recovery, does not initialize the control registers. The STOP mode current (ICC2) is minimized when: * VCC is at the low end of the device's operating range * Output current sourcing is minimized * All inputs (digital and analog) are at the Low or High rail voltages 2. For detailed information about flag settings, see the
The STOP mode is exited by any one of the following resets: POR or a Stop-Mode Recovery source. At reset generation, the processor always restarts the application program at address 0020H, and the STOP mode flag is set. Reading the STOP mode flag does not clear it. The user must clear the STOP mode flag with software.
Note: Failure to clear the STOP mode flag can result in undefined behavior.
Z8Plus User's Manual.
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CLOCK
The Z8Plus MCU derives its timing from on-board clock circuitry connected to pins XTAL1 and XTAL2. The clock circuitry consists of an oscillator, a glitch filter, and a divide-by-two shaping circuit. Figure 12 illustrates the clock circuitry. The oscillator's input is XTAL1 and its output is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock, or an external clock source. By selecting the RC OSCILLATOR option in the graphical user interface (GUI), the circuit may instead be driven by an external Resistor and Capacitor (RC) oscillator. Figure 13 illustrates this configuration. This design is limited to no more than 4 MHz to restrict EMI noise.
Note: The reduced drive strength of this configuration also allows the clock circuit to use a micropower-type crystal (also known as a tuning fork) without reduction resistors.
R XTAL1 Note: 4 MHz max.
Glitch Filter /2
XTAL2
C VSS Pin
Figure 13. Z8Plus in RC Oscillator Mode
XTAL1
Glitch Filter
/2
Machine Clock (SCLK) (5 cycles per instruction) Timer Clock (TCLK)
XTAL2
/4
/8
WDT Clock
Figure 12. Clock Circuit
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OSCILLATOR OPERATION
The Z8Plus MCU uses a Pierce oscillator with an internal feedback resistor (Figure 14). The advantages of this circuit are low-cost, large output signal, low-power level in the crystal, stability with respect to VCC and temperature, and low impedances (not disturbed by stray effects). increases until the oscillator reaches a point where it ceases to operate. For fast and reliable oscillator start-up over the manufacturing process range, the load capacitors should be sized as low as possible without resulting in overtone operation.
Layout
Z8Plus A V1 RI V0 VSS
Traces connecting crystal, caps, and the Z8Plus oscillator pins should be as short and wide as possible to reduce parasitic inductance and resistance. The components (caps, the crystal, and resistors) should be placed as close as possible to the oscillator pins of the Z8Plus. The traces from the oscillator pins of the integrated circuit (IC) and the ground side of the lead caps should be guarded from all other traces (clock, VCC, address/data lines, and system ground) to reduce cross talk and noise injection. Guarding is usually accomplished by keeping other traces and system ground trace planes away from the oscillator circuit, and by placing a Z8Plus device VSS ground ring around the traces/components. The ground side of the oscillator lead caps should be connected to a single trace to the Z8Plus device VSS (GND) pin. It should not be shared with any other system-ground trace or components except at the Z8Plus device VSS pin. The objective is to prevent differential system ground noise injection into the oscillator (Figure 15).
XTAL1
XTAL2
C1
C2
Figure 14. Pierce Oscillator with Internal Feedback Circuit
One drawback to the Pierce oscillator is the requirement for high gain in the amplifier to compensate for feedback path losses. The oscillator amplifies its own noise at start-up until it settles at the frequency that satisfies the gain/phase requirements. A x B = 1; where A = VO/VI is the gain of the amplifier, and B = VI/VO is the gain of the feedback element. The total phase shift around the loop is forced to 0 (360 degrees). VIN must be in phase with itself; therefore, the amplifier/inverter provides a 180-degree phase shift, and the feedback element is forced to provide the other 180-degree phase shift.
R1 is a resistive component placed from output to input of
Indications of an Unreliable Design
There are two major indicators that are used in working designs to determine their reliability over full lot and temperature variations. They are:
Start-Up Time. If start-up time is excessive, or varies widely from unit to unit, there is probably a gain problem. To fix the problem, the C1 and C2 capacitors require reduction. The amplifier gain is either not adequate at frequency, or the crystal R's are too large. Output Level. The signal at the amplifier output should swing from ground to VCC to indicate adequate gain in the
the amplifier. The purpose of this feedback is to bias the amplifier in its linear region and provide the start-up transition. Capacitor C2, combined with the amplifier output resistance, provides a small phase shift. It also provides some attenuation of overtones. Capacitor C1, combined with the crystal resistance, provides an additional phase shift. Start-up time may be affected if C1 and C2 are increased dramatically in size. As C1 and C2 increase, the start-up time
amplifier. As the oscillator starts up, the signal amplitude grows until clipping occurs. At that point, the loop gain is effectively reduced to unity, and constant oscillation is achieved. A signal of less than 2.5 volts peak-to-peak is an indication that low gain can be a problem. Either C1 or C2 should be made smaller, or a low-resistance crystal should be used.
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OSCILLATOR OPERATION (Continued) Circuit Board Design Rules
The following circuit board design rules are suggested: and the internal system clock output should be separated as much as possible.
*
To prevent induced noise, the crystal and load capacitors should be physically located as close to the Z8Plus as possible. Signal lines should not run parallel to the clock oscillator inputs. In particular, the crystal input circuitry
* *
VCC power lines should be separated from the clock oscillator input circuitry.
*
Resistivity between XTAL1 or XTAL2 (and the other pins) should be greater than 10 meg-Ohms.
XTAL1 17 C1 Z8Plus XTAL2 16 C2 VSS 15 Clock Generator Circuit Signals A B (Parallel traces must be avoided) Signal C
Z8Plus
PB0
X1 X2
VSS VCC
Board Design Example (Top View)
XTAL1 17
Z8Plus
XTAL2 16
Figure 15. Circuit Board Design Rules
Crystals and Resonators
Crystals and ceramic resonators (Figure 16) should exhibit the following characteristics to ensure proper oscillation:
Crystal Cut Mode Crystal Capacitance Load Capacitance Resistance 26 AT (crystal only) Parallel, fundamental mode <7pF 10pF < CL < 220 pF, 15 typical 100 Ohms maximum
Depending on the operation frequency, the oscillator may require additional capacitors, C1 and C2, as illustrated in Figure 16 and Figure 17. The capacitance values are dependent on the manufacturer's crystal specifications.
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VSS Z8Plus XTAL1 RF XTAL2 RD
tal/ceramic resonator manufacturer. The RD can be increased to decrease the amount of drive from the oscillator output to the crystal. It can also be used as an adjustment to avoid clipping of the oscillator signal to reduce noise. The RF can be used to improve the start-up of the crystal/ceramic resonator. The Z8Plus oscillator already locates an internal shunt resistor in parallel to the crystal/ceramic resonator.
C1
C2
XTAL1
Figure 16. Crystal/Ceramic Resonator Oscillator
N/C
Z8Plus VSS XTAL2
XTAL1 C1 L Z8Plus VSS XTAL2 C2
Figure 18. External Clock
Figure 16, Figure 17, and Figure 18 recommend that the load capacitor ground trace connect directly to the VSS (GND) pin of the Z8Plus. This requirement assures that no system noise is injected into the Z8Plus clock. This trace should not be shared with any other components except at the VSS pin of the Z8Plus.
Note: A parallel-resonant crystal or resonator manufacturer specifies a load capacitor value that is a series combination of C1 and C2, including all parasitics (PCB and holder).
Figure 17. LC Clock
In most cases, the RD is 0 Ohms and RF is infinite. These specifications are determined and specified by the crys-
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LC OSCILLATOR
The Z8Plus oscillator can use an inductor capacitor oscillator (LC) network to generate an XTAL clock (Figure 17). The frequency stays stable over VCC and temperature. The oscillation frequency is determined by the equation:
Frequency = 1 2 (LCT) 1/2 1/ CT If C1 1/CT C1 = = = = 1/C1 + 1/C2 C2 2/C1 2CT
where L is the total inductance including parasitics, and CT is the total series capacitance including parasitics. Simple series capacitance is calculated using the equation at the top of the next column.
A sample calculation of capacitance C1 and C2 for 5.83MHz frequency and inductance value of 27 H is displayed as follows:
5.83 (10^6) = 1 2 [27 (10-6) CT] 1/2
CT = 27.6 pF
Thus, C1 = 55.2 pF and C2 = 55.2 pF.
TIMERS
Two 8-bit timers, timer 0 (T0) and timer 1 (T1) are available to function as a pair of independent 8-bit standard timers. They may also be cascaded to function as a 16-bit PulseWidth Modulator (PWM) timer. Two additional 8-bit timers (T2 and T3) are provided, but they can only operate as one 16-bit standard timer.
OSC/8
Enable TCTLL0 (D5) IRQ5 (T23)
16-bit Down Counter
T3VAL
T3AR
T2AR
T2VAL
Internal Data Bus
Figure 19. 16-Bit Standard Timer
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Internal Data Bus
8-bit Standard Timer
T1ARHI
T1ARLO
T1VAL
OSC/8
(Not used in this mode)
8-bit Down Counter
IRQ2 (T1) Enable TCTLL0 (D2-D0)
(Not used in this mode)
8-bit Down Counter
Enable TCTLL0 (D2-D0) IRQ2 (T0)
8-bit Standard Timer
T0ARHI
T0ARLO
T0VAL
OSC/8
Internal Data Bus
Figure 20. 8-Bit Standard Timers
Internal Data Bus
T1ARHI
T1ARLO
T1VAL
T1
16-Bit Down Counter
T0
High Side PWM Low Side
Edge Detect Logic
IRQ0 IRQ2
OSC/8
T OUT
T0ARHI
T0ARLO
T0VAL
Internal Data Bus
Figure 21. 16-Bit Standard PWM Timer
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TIMERS (Continued)
0C0 D7 D6 D5 D4 TCTLLO D3 D2 D1 D0
D2 ---0 0 0 0 1 1 1 1
D1 ---0 0 1 1 0 0 1 1
D0 ---0 1 0 1 0 1 0 1
TIMER STATUS T0 T1 T01 ------------- ------------- --------------Disabled Disabled Enabled Disabled Disabled Enabled Enabled Enabled Enabled* Enabled* Disabled Disabled Enabled* Enabled* Enabled*
NOTE: (*) indicates auto-reload is active.
Reserved (must be 0) 1 = T23 16-Bit Timer Enabled with Auto-Reload Active 0 = T2 and T3 Timers Disabled Reserved (must be 0)
Note: Timer T01 is a 16-bit PWM Timer formed by cascading 8-bit timers T1 (MSB) and T0 (LSB). T23 is a standard 16-bit timer formed by cascading 8-bit timers T3 (MSB) and T2 (LSB).
Figure 22. TCTLLO Register
A pair of READ/WRITE registers is utilized for each 8-bit timer. One register is defined to contain the auto-initialization value for the timer. The second register contains the current value for the timer. When a timer is enabled, the timer decrements the value in its count register and continues decrementing until it reaches 0. An interrupt is generated, and the contents of the auto-initialization register are optionally copied into the count value register. If auto-initialization is not enabled, the timer stops counting when the value reaches 0. Control logic clears the appropriate control register bit to disable the timer. This operation is referred to as a single-shot. If auto-initialization is enabled, the timer counts from the initialization value. Software must not attempt to use timer registers for any other function. User software is allowed to write to any WRITE register at any time; however, care should be taken if timer registers are updated while the timer is enabled. If software changes the count value while the timer is in operation, the timer continues counting from the updated value.
Note: Unpredictable behavior can occur if the value updates at the same time that the timer reaches 0.
Similarly, if user software changes the initialization value register while the timer is active, the next time that the timer reaches 0, the timer initializes to the changed value.
Note: Unpredictable behavior can occur if the initialization value register is changed while the timer is in the process of being initialized.
The initialization value is determined by the exact timing of the WRITE operation. In all cases, the Z8Plus assigns a higher priority to the software WRITE than to a decrementer write-back. However, when hardware clears a control register bit for a timer that is configured for single-shot operation, the clearing of the control bit overrides a software WRITE. A READ of either register can be conducted at any time, with no effect on the functionality of the timer.
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If a timer pair is defined to operate as a single 16-bit entity, the entire 16-bit value must reach 0 before an interrupt is generated. In this case, a single interrupt is generated, and the interrupt corresponds to the even 8-bit timer.
Example: Timers T2 and T3 are cascaded to form a single 16bit timer. The interrupt for the combined timer is defined to be generated by timer T2 rather than T3. When a timer pair is specified to act as a single 16bit timer, the even timer registers in the pair (timer T0 or T2) is defined to hold the timer's least significant byte. In contrast, the odd timer in the pair holds the timer's most significant byte.
ization value is composed of the concatenation of T1ARLO and T0ARLO. The second auto-initialization value is composed of the concatenation of T1ARHI and T0ARHI. When T01 times out, it alternately initializes its count value using the Low auto-init pair, followed by the High auto-init pair. This functionality corresponds to a PWM. That is, the T1 interrupt defines the end of the High section of the waveform, and the T0 interrupt marks the end of the Low portion of the PWM waveform. The PWM begins counting with whatever data is held in the count registers. After this value expires, the first reload depends on the state of the PB1 pin if TOUT mode is selected. Otherwise, the Low value is applied first. After the auto-initialization is completed, decrementing occurs for the number of counts defined by the PWM_LO registers. When decrementing again reaches 0, the T0 interrupt is asserted; and auto-init using the PWM_HI registers occurs. Decrementing occurs for the number of counts defined by the PWM_HI registers until reaching 0. From there, the T1 interrupt IRQ2 is asserted, and the cycle begins again. The internal timers can be used to trigger external events by toggling the PB1 output when generating an interrupt. This functionality can only be achieved in conjunction with the port unit defining the appropriate pin as an output signal with the timer output special function enabled. In this mode, the port output is toggled when the timer count reaches 0, and continues toggling each time that the timer times out.
In parallel with the posting of the interrupt request, the interrupting timer's count value is initialized by copying the contents of the auto-initialization value register to the count value register.
Note: Any time that a timer pair is defined to act as a single 16bit timer, the auto-reload function is performed automatically.
All 16-bit timers continue counting while their interrupt requests are active and operate independently of each other. If interrupts are disabled for a long period of time, it is possible for the timer to decrement to 0 again before its initial interrupt is responded to. This condition is termed a degenerate case, and hardware is not required to detect it. When the timer control register is written, all timers that are enabled by the WRITE begin counting from the value in the count register. In this case, an auto-initialization is not performed. All timers can receive an internal clock source input only. Each enabled timer is updated every 8th XTAL clock cycle. If T0 and T1 are defined to work independently, then each works as an 8-bit timer with a single auto-initialization register (T0ARLO for T0, and T1ARLO for T1). Each timer asserts its predefined interrupt when it times out, optionally performing the auto-initialization function. If T0 and T1 are cascaded to form a single 16-bit timer, then the single 16bit timer is capable of performing as a Pulse-Width Modulator (PWM). This timer is referred to as T01 to distinguish it as having special functionality that is not available when T0 and T1 act independently. When T01 is enabled, it can use a pair of 16-bit auto-initialization registers. In this mode, one 16-bit auto-initial-
TOUT Mode
The PortB special function register PTBSFR (0D7H; Figure 23) is used in conjunction with the Port B directional control register PTBDIR (0D6; Figure 24) to configure PB1 for TOUT operation for T0. In order for TOUT to function, PB1 must be defined as an output line by setting PTBDIR bit 1 to 1. Configured in this way, PB1 is capable of being a clock output for T0, toggling the PB1 output pin on each T0 timeout. At end-of-count, the interrupt request line (IRQ0), clocks a toggle flip-flop. The output of this flip-flop drives the TOUT line, PB1. In all cases, when T0 reaches its end-of-count, TOUT toggles to its opposite state (Figure 25). If, for example, T0 is in Continuous Counting Mode, TOUT exhibits a 50-percent duty cycle output. If the timer pair is selected (T01) as a PWM, the duty cycle depends on the High and Low reload values. At the end of each High time, PB1 toggles Low. At the end of each Low time, PB1 toggles HI.
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TIMERS (Continued)
0D7 D7 D6 D5 D4 PTBSFR D3 D2 D1 D0
1 = Enable Bit 0 as SMR input 0 = No special functionality 1 = Enable Bit 1 as T0 output 0 = No special functionality 1 = Enable Bit 2 as IRQ2 input 0 = No special functionality D4 D3 Comparator Interrupts --- --- -------------- ------------------0 0 Disabled Disabled 0 1 Enabled Disabled 1 0 Disabled Enabled 1 1 Enabled Enabled BIT 3: Comparator reference input BIT 4: Comparator signal input/IRQ0/IRQ2 Reserved (must be 0)
Figure 23. PortB Special Function Register
0D6 D7 D6 D5 D4
PTBDIR D3 D2 D1 D0
1 = Bit n set as output 0 = Bit n set as input
Reserved (must be 0)
Figure 24. Port B Directional Control Register
IRQ0 (T0 End-of-Count)
/2
PB1
TOUT
Figure 25. Timer T0 Output Through TOUT
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RESET CONDITIONS
After a RESET, the timers are disabled. See Table 8 for timer control, value, and auto-initialization register status after RESET.
I/O PORTS
The Z8Plus dedicates 14 lines to input and output. These lines are grouped into two ports known as Port A and Port B. Port A is an 8-bit port, bit programmable as either inputs or outputs. Port B can be programmed to provide either standard input/output, or the following special functions: T0 output, comparator input, SMR input, and external interrupt inputs. All pins except PB5 include push-pull CMOS outputs. In addition, the outputs of Port A on a bit-wise basis can be configured for open-drain operation.The ports operate on a bit-wise basis. As such, the register values for/at a given bit position only affect the bit in question. Each port is defined by a set of four control registers (Figure 26).
PTASFR Bit n N = 0...7 PTADIR Bit n N = 0...7 PA0-PA7 PIN
PTAOUT Bit n N = 0...7
PTAIN Bit n N = 0...7
Figure 26. Port A Configuration with Open-Drain Capability and Schmitt-Trigger
Directional Control and Special Function Registers
Each port on the Z8Plus features a dedicated directional control register that determines (on a bit-wise basis) if a given port bit operates as input or output. Each port on the Z8Plus features a special function register (SFR) that, in conjunction with the directional control register, implements (on a bit-by-bit basis) any special functionality that can be defined for each particular port bit.
Table 14. I/O Ports Registers Register Port B Special Function Port B Directional Control Port B Output Value Port B Input Value Port A Special Function Port A Directional Control Port A Output Value Port A Input Value Address 0D7H 0D6H 0D5H 0D4H 0D3H 0D2H 0D1H 0D0H Identifier PTBSFR PTBDIR PTBOUT PTBIN PTASFR PTADIR PTAOUT PTAIN
Input and Output Value Registers
Each port features an Output Value Register and an input value register. For port bits configured as an input by means of the directional control register, the input value register
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for that bit position contains the current synchronized input value. For port bits configured as an output by means of the directional control register, the value held in the corresponding bit of the Output Value Register is driven directly onto
the output pin. The opposite register bit for a given pin (the output register bit for an input pin and the input register bit for an output pin) holds their previous value. These bits are not changed and do not exhibit any effect on the hardware.
READ/WRITE OPERATIONS
The control for each port is done on a bit-by-bit basis. All bits are capable of operating as inputs or outputs, depending on the setting of the port's directional control register. If configured as an input, each bit is provided a Schmitt-trigger. The output of the Schmitt-trigger is latched twice to perform a synchronization function, and the output of the synchronizer is fed to the port input register, which can be read by software. A WRITE to a port input register carries the effect of updating the contents of the input register, but subsequent READs do not necessarily return the same value that was written. If the bit in question is defined as an input, the input register for that bit position contains the current synchronized input value. WRITEs to that bit position are overwritten on the next clock cycle with the newly sampled input data. However, if the particular bit is programmed as an output, the input register for that bit retains the software-updated value. The port bits that are programmed as outputs do not sample the value being driven out. Any bit in either port can be defined as an output by setting the appropriate bit in the directional control register. In this instance, the value held in the appropriate bit of the port output register is driven directly onto the output pin.
Note: The preceding result does not necessarily reflect the actual output value. If an external error is holding an output pin either High or Low against the output driver, the software READ returns the requested value, not the actual state caused by the contention. When a bit is defined as an output, the Schmitt-trigger on the input is disabled to save power.
Updates to the output register take effect based on the timing of the internal instruction pipeline; however, this timing is referenced to the rising edge of the clock. The output register can be read at any time, and returns the current output value that is held. No restrictions are placed on the timing of READs and/or WRITEs to any of the port registers with respect to the others.
Note: Care should be taken when updating the directional control and special function registers.
When updating a directional control register, the special function register (SFR) should first be disabled. If this precaution is not taken, unpredicted events could occur as a result of the change in the port I/O status. This precaution is especially important when defining changes in Port B, as the unpredicted event referred to above could be one or more interrupts. Clearing of the SFR register should be the first step in configuring the port, while setting the SFR register should be the final step in the port configuration process. To ensure unpredictable results, the SFR register should not be written until the pins are being driven appropriately, and all initialization is completed.
PORT A
Port A is a general-purpose port. Figure 27 features a block diagram of Port A. Each of its lines can be independently programmed as input or output via the Port A directional control register (PTADIR at 0D2H) as seen in Figure 26. A bit set to a 1 in PTADIR configures the corresponding bit in Port A as an output, while a bit cleared to 0 configures the corresponding bit in Port A as an input. The input buffers are Schmitt-triggered. Bits programmed as outputs can be individually programmed as either pushpull or open-drain by setting the corresponding bit in the special function register (PTASFR, Figure 26).
Register 0D2H PTADIR Register D7 D6 D5 D4 D3 D2 D1 D0 1 = Output 0 = Input
Figure 27. Port A Directional Control Register 34 PRELIMINARY DS007500-Z8X0399
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PORT A REGISTER DIAGRAMS
Register 0D0H D7 D6 D5 D4 PTAIN D3 D2 D1 D0
Port A Bit n current input value (only updated for pins in input mode)
Figure 28. Port A Input Value Register
Register 0D1H D7 D6 D5 D4
PTAOUT D3 D2 D1 D0
Port A Bit n currentoutput value
Figure 29. Port A Output Value Register
Register 0D2H D7 D6 D5 D4
PTADIR D3 D2 D1 D0
1 = Bit n set as an output 0 = Bit n set as an input
Figure 30. Port A Directional Control Register
Register 0D3H D7 D6 D5 D4
PTASFR D3 D2 D1 D0
1 = Bit n in open-drain mode 0 = Bit n in push-pull mode
Figure 31. Port A Special Function Register
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PORT B Port B Description
Port B is a 6-bit (bidirectional), CMOS-compatible I/O port. These six I/O lines can be configured under software control to be an input or output. Each bit is configured independently from the other bits. That is, one bit may be set to INPUT while another bit is set to OUTPUT. In addition to standard input/output capability, five pins of Port B provide special functionality as indicated in Table 15.
Table 15. Port B Special Functions Port Pin PB0 PB1 PB2 PB3 PB4 Input Special Function Stop Mode Recovery Input None IRQ3 Comparator Reference Input Comparator Signal Input/IRQ1/IRQ4 Output Special Function None T0 Output None None None
Special functionality is invoked via the Port B special function register. Port B, bit 5, is an open-drain-only pin when in output mode. There is no high-side driver on the output stage, nor is there any high-side protection device, because PB5 acts as the VPP pin for EPROM programming mode. The user should always place an external protection diode on this pin. See Figure 32.
Register 0D7H D7 D6 D5 D4
PTBSFR D3 D2 D1 D0
1 = Enable PB0 as SMR Input 0 = No Special Functionality 1 = Enable PB1 as T0 Output 0 = No Special Functionality 1 = Enable PB2 as IRQ3 Input 0 = No Special Functionality 1 = Analog Comparator on PB3 and PB4 0 = Digital Inputs on PB3 and PB4 1 = PB4 Interrupts Enabled 0 = PB4 Interrupts Disabled Reserved (must be 0) Figure 32. Port B Special Function Register
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PORT B--PIN 0 CONFIGURATION
PTBDIR Bit 0 PTBIN Bit 0
SMR RESET
PTBSFR Bit 0 SMR Flag
PTBDIR Bit 0 PB0 PIN
PTBOUT Bit 0
Figure 33. Port B Pin 0 Diagram
PTBDIR Bit 5 PTBIN Bit 5 VCC
See Note PTBDIR Bit 5 approx 200 kOhms
PB5 PIN
PTBOUT Bit 5
Note: There is no high-side protection device. The user should always place an external protection diode as shown.
Figure 34. Port B Pin 5 Diagram DS007500-Z8X0399 PRELIMINARY 37
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PORT B--PIN 1 CONFIGURATION
PTBDIR Bit 1 PTBIN Bit 1
PTBDIR Bit 1 PB1 PIN
PTBOUT Bit 1 T0 Output
M U X
PTBSFR Bit 1 Figure 35. Port B Pin 1 Diagram
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PORT B--PIN 2 CONFIGURATION
PTBDIR Bit 2 PTBIN Bit 2 IRQ3 Edge Detect Logic PTBSFR Bit 2
PTBDIR Bit 2 PB2 PIN
PTBOUT Bit 2
Figure 36. Port B Pin 2 Diagram
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PORT B--PINS 3 AND 4 CONFIGURATION
PTBDIR Bit 4 PTBIN Bit 4 IRQ1 IRQ4 M U X +
-
Edge Detect Logic PTBSFR Bit 4 PTBSFR Bit 3
AN IN REF
PTBDIR Bit 3 PTBIN Bit 3
PTBDIR Bit 3 PB3 PIN
PTBOUT Bit 3
PTBDIR Bit 4 PB4 PIN
PTBOUT Bit 4
Figure 37. Port B Pins 3 and 4 Diagram
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PORT B CONTROL REGISTERS
Register 0D4H D7 D6 D5 D4 PTBIN D3 D2 D1 D0
Port B Bit n current input value (only updated for pins in input mode) Reserved (must be 0) Figure 38. Port B Input Value Register
Register 0D5H D7 D6 D5 D4
PTBOUT D3 D2 D1 D0
Port B Bit n current output value Reserved (must be 0) Figure 39. Port B Output Value Register
Register 0D6H D7 D6 D5 D4
PTBDIR D3 D2 D1 D0
1 = Bit n set as output 0 = Bit n set as input Reserved (must be 0) Figure 40. Port B Directional Control Register
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PORT B CONTROL REGISTERS (Continued)
Register 0D7H D7 D6 D5 D4 PTBSFR D3 D2 D1 D0
1 = Enable PB0 as SMR Input 0 = No Special Functionality 1 = Enable PB1 as T0 Output 0 = No Special Functionality 1 = Enable PB2 as IRQ3 Input 0 = No Special Functionality 1 = Analog Comparator on PB3 and PB4 0 = Digital Inputs on PB3 and PB4 1 = PB4 Interrupts Enabled 0 = PB4 Interrupts Disabled Reserved (must be 0) Figure 41. Port B Special Function Register
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I/O PORT RESET CONDITIONS Full Reset
Port A and Port B output value registers are not affected by
RESET.
overwrites the previously held data with the current sample of the input pins. On RESET, the Port A and Port B special function registers are cleared to 00h, which deactivates all port special functions.
Note: The SMR and WDT time-out events are not full device resets. The port control registers are not affected by either of these events.
On RESET, the Port A and Port B directional control registers are cleared to all zeros, which defines all pins in both ports as inputs. On RESET, the directional control registers redefine all pins as inputs, and the Port A and Port B input value registers
ANALOG COMPARATOR
The device includes one on-chip analog comparator. Pin PB4 features a comparator front end. The comparator reference voltage is on pin PB3. When the analog comparator function is enabled, bit 4 of the input register is defined as holding the synchronized output of the comparator, while bit 3 retains a synchronized sample of the reference input. If the interrupts for PB4 are enabled when the comparator special function is selected, the output of the comparator generates interrupts.
Comparator Description
The on-chip comparator can process an analog signal on PB4 with reference to the voltage on PB3. The analog function is enabled by programming the Port B special function register bits 3 and 4.
COMPARATOR OPERATION
The comparator output reflects the relationship between the analog input to the reference input. If the voltage on the analog input is higher than the voltage on the reference input, then the comparator output is at a High state. If the voltage on the analog input is lower than the voltage on the reference input, then the analog output is at a Low state.
IIO For the CMOS voltage comparator input, the input offset current (IIO) is the leakage current of the CMOS input gate.
HALT Mode
The analog comparator is functional during HALT mode. If the interrupts are enabled, an interrupt generated by the comparator causes a return from HALT mode.
Comparator Definitions
VICR
The usable voltage range for the positive input and reference input is called the Comparator Input Common Mode Voltage Range (VICR).
Note: The comparator is not guaranteed to work if the input is outside of the VICR range. VOFFSET
STOP Mode
The analog comparator is disabled during STOP mode. The comparator is powered down to prevent it from drawing any current.
Low Voltage Protection. An on-board Voltage Comparator checks that the VCC is at the required level to ensure
correct operation of the device. A reset is globally driven if VCC is below the specified voltage (Low Voltage Protection). The device functions normally at or above 3.0V under all conditions, and is guaranteed to function normally at supply voltages above the Low Voltage Protection trip point. Below 3.0V, the device functions normally until the Low Volt-
The absolute value of the voltage between the positive input and the reference input required to make the comparator output voltage switch is the Comparator Input Offset Voltage (VOFFSET).
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COMPARATOR OPERATION (Continued)
age Protection trip point (VLV) is reached. The actual LowVoltage Protection trip point is a function of process parameters. Low-Voltage Protection is active in RUN and HALT modes only, but is disabled in STOP mode (Figure 42).
VCC (Volts)
3.00
2.80 Typical VLV in RUN and HALT modes
2.60
2.40
2.20
2.00
1.80
1.60 -60
-40
-20
0
20
40
60
80
100
120
140
Temperature (C)
Figure 42. Typical Low Voltage Protection vs. Temperature
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INPUT PROTECTION
All I/O pins feature diode input protection. There is a diode from the I/O pad to VCC and VSS (Figure 43).
VCC PIN PB5
However, the PB5 pin features only the input protection diode, from the pad to VSS (Figure 44).
PIN VSS
Figure 44. PB5 Pin Input Protection
VSS
The high-side input protection diode was removed on this pin to allow the application of high voltage during the OTP programming mode. For better noise immunity in applications that are exposed to system EMI, a clamping diode to VSS from this pin should be used to prevent entering the OTP programming mode or to prevent high voltage from damaging this pin.
Figure 43. I/O Pin Diode Input Protection
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PACKAGE INFORMATION
Figure 45. 18-Pin DIP Package Diagram
Figure 46. 18-Pin SOIC Package Diagram
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Figure 47. 20-Pin SSOP Package Diagram
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ORDERING INFORMATION
Standard Temperature 18-Pin DIP 18-Pin SOIC 20-Pin SSOP Extended Temperature 18-Pin DIP 18-Pin SOIC 20-Pin SSOP Z8PE003PZ010EC Z8PE003SZ010EC Z8PE003CZ010EC Z8PE003PZ010SC Z8PE003SZ010SC Z8PE003HZ010SC
For fast results, contact your local ZiLOG sales office for assistance in ordering the part(s) required.
Codes Preferred Package Longer Lead Time Speed Standard Temperature Extended Temperature Environmental Flow PZ = Plastic DIP SZ = SOIC HZ = SSOP 010 = 10 MHz S = 0C to +70C E = -40C to +105C C = Plastic Standard
Example:
The Z8PE003PZ010SC is a 10-MHz DIP, 0C to 70C, with Plastic Standard Flow.
Z 8PE 003 PZ 010 SC ZiLOG Prefix Z8Plus Product Product Number Package Designation Code Speed Temperature and Environmental Flow
Pre-Characterization Product: The product represented by this document is newly introduced and ZiLOG has not completed the full characterization of the product. The document states what ZiLOG knows about this product at this time, but additional features or non-conformance (c)1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of 48
with some aspects of the document may be found, either by ZiLOG or its customers in the course of further application and characterization work. In addition, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield issues. life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights. ZiLOG, Inc. 910 East Hamilton Avenue, Suite 110 Campbell, CA 95008 Telephone (408) 558-8500 FAX 408 558-8300 Internet: http://www.zilog.com
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