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FEATURES Wide Bandwidth: 60 MHz at Gain of -1 Wide Bandwidth: 33 MHz at Gain of -10 Very High Output Slew Rate: Up to 2000 V/ s 20 MHz Full Power Bandwidth, 20 V p-p, RL = 500 Fast Settling: 100 ns to 0.1% (10 V Step) Differential Gain Error: 0.03% at 4.4 MHz Differential Phase Error: 0.158 at 4.4 MHz High Output Drive: 650 mA into 50 Load Low Offset Voltage: 150 mV Max (B Grade) Low Quiescent Current: 6.5 mA Available in Tape and Reel in Accordance with EIA-481A Standard APPLICATIONS Flash ADC Input Amplifiers High-Speed Current DAC Interfaces Video Buffers and Cable Drivers Pulse Amplifiers PRODUCT DESCRIPTION
NULL 1 -IN 2 +IN 3 -VS 4
60 MHz, 2000 V/ s Monolithic Op Amp AD844
CONNECTION DIAGRAMS 8-Lead Plastic (N), and Cerdip (Q) Packages 16-Lead SOIC (R) Package
NC 1 OFFSETNULL 2 -IN 3 NC 4 +IN 5 NC 6 V- 7 NC 8
AD844
8 7 6
NULL +VS OUTPUT
AD844
16 NC 15 OFFSETNULL 14 V+ 13 NC 12 OUTPUT 11 TZ
TOP VIEW 5 TZ (Not to Scale)
10 NC TOP VIEW 9 NC (Not to Scale)
NC = NO CONNECT
The AD844 is a high-speed monolithic operational amplifier fabricated using Analog Devices' junction isolated complementary bipolar (CB) process. It combines high bandwidth and very fast large signal response with excellent dc performance. Although optimized for use in current to voltage applications and as an inverting mode amplifier, it is also suitable for use in many noninverting applications. The AD844 can be used in place of traditional op amps, but its current feedback architecture results in much better ac performance, high linearity and an exceptionally clean pulse response. This type of op amp provides a closed-loop bandwidth which is determined primarily by the feedback resistor and is almost independent of the closed-loop gain. The AD844 is free from the slew rate limitations inherent in traditional op amps and other current-feedback op amps. Peak output rate of change can be over 2000 V/s for a full 20 V output step. Settling time is typically 100 ns to 0.1%, and essentially independent of gain. The AD844 can drive 50 loads to 2.5 V with low distortion and is short circuit protected to 80 mA. The AD844 is available in four performance grades and three package options. In the 16-lead SOIC (R) package, the AD844J is specified for the commercial temperature range of 0C to 70C. The AD844A and AD844B are specified for the industrial temperature range of -40C to +85C and are available in the cerdip (Q)
package. The AD844A is also available in an 8-lead plastic mini-DIP (N). The AD844S is specified over the military temperature range of -55C to +125C. It is available in the 8-lead cerdip (Q) package. "A" and "S" grade chips and devices processed to MIL-STD-883B, REV. C are also available.
PRODUCT HIGHLIGHTS
1. The AD844 is a versatile, low cost component providing an excellent combination of ac and dc performance. 2. It is essentially free from slew rate limitations. Rise and fall times are essentially independent of output level. 3. The AD844 can be operated from 4.5 V to 18 V power supplies and is capable of driving loads down to 50 , as well as driving very large capacitive loads using an external network. 4. The offset voltage and input bias currents of the AD844 are laser trimmed to minimize dc errors; VOS drift is typically 1 V/C and bias current drift is typically 9 nA/C. 5. The AD844 exhibits excellent differential gain and differential phase characteristics, making it suitable for a variety of video applications with bandwidths up to 60 MHz. 6. The AD844 combines low distortion, low noise and low drift with wide bandwidth, making it outstanding as an input amplifier for flash A/D converters.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD844-SPECIFICATIONS (@ T = 25 C and V =
A S
15 V dc, unless otherwise noted)
Min AD844B Typ 50 75 1 4 4 10 10 150 750 9 175 220 90 110 100 300 3 80 100 90 130 Max 150 200 5 10 10 20 20 250 1100 15 200 240 110 150 200 500 7 100 120 120 190 AD844S Min Typ Max 50 125 1 4 4 10 10 200 1900 20 175 220 90 120 100 800 7 80 120 90 140 300 500 5 20 20 35 35 450 2500 30 250 300 160 200 400 1300 15 150 200 150 200 Unit V V V/C V/V V/V V/V V/V nA nA nA/C nA/V nA/V nA/V nA/V nA nA nA/C nA/V nA/V nA/V nA/V
Model INPUT OFFSET VOLTAGE1 TMIN-TMAX vs. Temperature vs. Supply Initial TMIN-TMAX vs. Common Mode Initial TMIN-TMAX INPUT BIAS CURRENT -Input Bias Current1 TMIN-TMAX vs. Temperature vs. Supply Initial TMIN-TMAX vs. Common Mode Initial TMIN-TMAX +Input Bias Current1 TMIN-TMAX vs. Temperature vs. Supply Initial TMIN-TMAX vs. Common Mode Initial TMIN-TMAX INPUT CHARACTERISTICS Input Resistance -Input +Input Input Capacitance -Input +Input Input Voltage Range Common Mode INPUT VOLTAGE NOISE INPUT CURRENT NOISE -Input +Input OPEN LOOP TRANSRESISTANCE TMIN-TMAX Transcapacitance DIFFERENTIAL GAIN ERROR2 DIFFERENTIAL PHASE ERROR2 FREQUENCY RESPONSE Small Signal Bandwidth Gain = -13 Gain = -104 TOTAL HARMOMIC DISTORTION SETTLING TIME 10 V Output Step Gain = -1, to 0.1%5 Gain = -10, to 0.1%6 2 V Output Step Gain = -1, to 0.1%5 Gain = -10, to 0.1%6
Conditions
Min
AD844J/A Typ Max 50 75 1 300 500
5 V-18 V 4 4 VCM = 10 V 10 10 200 800 9 5 V-18 V 175 220 VCM = 10 V 90 110 150 350 3 5 V-18 V 80 100 VCM = 10 V 90 130 150 150 160 400 700 250 35 20
450 1500
7
50 10 2 2
65 7
50 10 2 2
65 7
50 10 2 2
65
M pF pF V
10 f 1 kHz f 1 kHz f 1 kHz VOUT = 10 V RLOAD = 500 2.2 1.3 2 10 12 3.0 2.0 4.5 0.03 0.15
10 2 10 12 2.8 1.6 3.0 2.0 4.5 0.03 0.15
10 2 10 12 2.2 1.3 3.0 1.6 4.5 0.03 0.15
nV/Hz pA/Hz pA/Hz M M pF % Degree
f = 4.4 MHz f = 4.4 MHz
60 33 f = 100 kHz, 2 V rms5 15 V Supplies 100 100 5 V Supplies 110 100 0.005
60 33 0.005
60 33 0.005
MHz MHz %
100 100 110 100
100 100 110 100
ns ns ns ns
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AD844
Model OUTPUT SLEW RATE FULL POWER BANDWIDTH VOUT = 20 V p-p5 VOUT = 2 V p-p5 OUTPUT CHARACTERISTICS Voltage Short Circuit Current TMIN-TMAX Output Resistance POWER SUPPLY Operating Range Quiescent Current TMIN-TMAX Conditions Overdriven Input VS = 15 V VS = 5 V THD = 3% RLOAD = 500 Open Loop 4.5 6.5 7.5 10 Min AD844J/A Typ Max 2000 20 20 Min 1200 AD844B Typ 2000 20 20 Max AD844S Min Typ Max 1200 2000 20 20 Unit V/s MHz MHz
1200
11 80 60 15 18 7.5 8.5
10
11 80 60 15 18 7.5 8.5
10
11 80 60 15 18 7.5 9.5
V mA mA V mA mA
4.5 6.5 7.5
+4.5 6.5 8.5
NOTES 1 Rated performance after a 5 minute warmup at T A = 25C. 2 Input signal 285 mV p-p carrier (40 IRE) riding on 0 mV to 642 mV (90 IRE) ramp. R L= 100 ; R1, R2 = 300 . 3 Input signal 0 dBm, C L = 10 pF, RL = 500 , R1 = 500 , R2 = 500 in Figure 2. 4 Input signal 0 dBm, C L =10 pF, R L = 500 , R1 = 500 , R2 = 50 in Figure 2. 5 CL = 10 pF, RL = 500 , R1 = 1 k, R2 = 1 k in Figure 2. 6 CL = 10 pF, RL = 500 , R1 = 500 , R2 = 50 in Figure 2. Specifications subject to change without notice. All min and max specifications are guaranteed.
ABSOLUTE MAXIMUM RATINGS 1
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Power Dissipation2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 W Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite Common-Mode Input Voltage . . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 6 V Inverting Input Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 mA Storage Temperature Range (Q) . . . . . . . . . -65C to +150C Storage Temperature Range (N, R) . . . . . . . -65C to +125C Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 V
ORDERING GUIDE
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-Lead Plastic Package: JA = 90C/W 8-Lead Cerdip Package: JA = 110C/W 16-Lead SOIC Package: JA = 100C/W
METALIZATION PHOTOGRAPH
Contact factory for latest dimensions. Dimension shown in inches and (mm).
Model AD844AN AD844ACHIPS AD844AQ AD844BQ AD844JR-16 AD844JR-16-REEL AD844JR-16-REEL7 AD844SCHIPS AD844SQ AD844SQ/883B 5962-8964401PA
*N
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C 0C to 70C 0C to 70C 0C to 70C -55C to +125C -55C to +125C -55C to +125C -55C to +125C
Package Option* N-8 Die Q-8 Q-8 R-16 13" Tape and Reel 7" Tape and Reel Die Q-8 Q-8 Q-8
= Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).
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AD844-Typical Characteristics (T = 25 C and V =
A S
70 -60 -70
15 V, unless otherwise noted)
5 RL =
HARMONIC DISTORTION - dB
-3dB BANDWIDTH - MHz
4 -80 1V rms -90 -100 -110 2ND HARMONIC -120
TRANSRESISTANCE - M
60
RL = 500 3
50
2 RL = 50 1
40
30
0
10 15 5 SUPPLY VOLTAGE - V
20
-130 100
3RD HARMONIC 10k 1k INPUT FREQUENCY - Hz 100k 0 -50 0 50 100 TEMPERATURE - C 150
TPC 1. -3 dB Bandwidth vs. Supply Voltage R1 = R2 = 500
MAGNITUDE OF THE OUTPUT VOLTAGE - V TA = 25 C MAGNITUDE OF THE OUTPUT VOLTAGE - V 20
TPC 2. Harmonic Distortion vs. Frequency, R1 = R2 = 1 k
20 RL = 500 TA = 25 C 15
10
TPC 3. Transresistance vs. Temperature
9
15
SUPPLY CURRENT - mA
8
10
10
7 VS = 6 VS = 5 5V 15V
5
5
0
0
10 15 5 SUPPLY VOLTAGE - V
20
0
0
10 15 5 SUPPLY VOLTAGE - V
20
4 -60 -40 -20
0 20 40 60 80 100 120 140 TEMPERATURE - C
TPC 4. Noninverting Input Voltage Swing vs. Supply Voltage
TPC 5. Output Voltage Swing vs. Supply Voltage
TPC 6. Quiescent Supply Current vs. Temperature and Supply Voltage
40 VS = 15V
2
100
INPUT BIAS CURRENT - A
35
OUTPUT IMPEDANCE -
1
10 5V SUPPLIES 1
-3dB BANDWIDTH - MHz
30
0
IBP
25
VS =
5V
20
-1
IBN
0.1
15
0.01 10k
-2 -50
0
50 100 TEMPERATURE - C
150
100k
1M
10M
100M
10 -60 -40 -20
0
20 40
60 80 100 120 140
FREQUENCY - Hz
TEMPERATURE - C
TPC 7. Inverting Input Bias Current (IBN) and Noninverting Input Bias Current (IBP) vs. Temperature
TPC 8. Output Impedance vs. Frequency, Gain = -1, R1 = R2 = 1 k
TPC 9. -3 dB Bandwidth vs. Temperature, Gain = -1, R1 = R2 = 1 k
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AD844 Inverting Gain-of-1 AC Characteristics
+VS 0.22 F 4.7 R1
GAIN - dB
0 PHASE - Degrees R1 = R2 = 1k 6 R1 = R2 = 500
-180
-210 R1 = R2 = 500 -240
R2 VIN -
-6
AD844
+ RL 0.22 F 4.7 -VS
VOUT
-12
-270 R1 = R2 = 1k -300
CL
-18
-24 100k
-330
1M 10M FREQUENCY - Hz 100M
0
25 FREQUENCY - MHz
50
TPC 10. Inverting Amplifier, Gain of -1 (R1 = R2)
TPC 11. Gain vs. Frequency for Gain = -1, RL = 500 , CL = 0 pF
TPC 12. Phase vs. Frequency Gain = -1, RL = 500 , CL = 0 pF
TPC 13. Large Signal Pulse Response, Gain = -1, R1 = R2 = 1 k
TPC 14. Small Signal Pulse Response, Gain = -1, R1 = R2 = 1 k
Inverting Gain-of-10 AC Characteristics
26
-180
RL = 500
+VS 0.22 F 4.7 500
20
-210
RL = 50
14
PHASE - Degrees
GAIN - dB
-240
RL = 500
50 VIN
-
8
-270 RL = 50 -300
AD844
+
VOUT
2
RL 0.22 F 4.7 -VS
CL
-4 100k 1M 10M 100M
-330 0 25 FREQUENCY - MHz 50
FREQUENCY - Hz
TPC 15. Gain of -10 Amplifier
TPC 16. Gain vs. Frequency, Gain = -10
TPC 17. Phase vs. Frequency, Gain = -10
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AD844 Inverting Gain-of-10 Pulse Response
TPC 18. Large Signal Pulse Response, Gain = -10, RL = 500
TPC 19. Small Signal Pulse Response, Gain = -10, RL = 500
Noninverting Gain-of-10 AC Characteristics
26 RL = 500 4.7 0.22 F 20
PHASE - Degrees
-180
+VS
-210
GAIN - dB
450 - 50 VIN VOUT
14
RL = 50
-240 RL = 50k
RL = 500
AD844
+ 0.22 F RL
8
-270
CL
2
-300
4.7 -VS -4 100k 1M 10M FREQUENCY - Hz 100M
-330 0 25 FREQUENCY - MHz 50
TPC 20. Noninverting Gain of +10 Amplifier
TPC 21. Gain vs. Frequency, Gain = +10
TPC 22. Phase vs. Frequency, Gain = +10
TPC 23. Noninverting Amplifier Large Signal Pulse Response, Gain = +10, RL = 500
TPC 24. Small Signal Pulse Response, Gain = +10, RL = 500
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AD844
UNDERSTANDING THE AD844 Response as an Inverting Amplifier
The AD844 can be used in ways similar to a conventional op amp while providing performance advantages in wideband applications. However, there are important differences in the internal structure which need to be understood in order to optimize the performance of the AD844 op amp.
Open Loop Behavior
Figure 1 shows a current feedback amplifier reduced to essentials. Sources of fixed dc errors such as the inverting node bias current and the offset voltage are excluded from this model and are discussed later. The most important parameter limiting the dc gain is the transresistance, Rt, which is ideally infinite. A finite value of Rt is analogous to the finite open loop voltage gain in a conventional op amp. The current applied to the inverting input node is replicated by the current conveyor so as to flow in resistor Rt. The voltage developed across Rt is buffered by the unity gain voltage follower. Voltage gain is the ratio Rt / RIN. With typical values of Rt = 3 M and RIN = 50 , the voltage gain is about 60,000. The open loop current gain is another measure of gain and is determined by the beta product of the transistors in the voltage follower stage (see Figure 4); it is typically 40,000.
Figure 2 shows the connections for an inverting amplifier. Unlike a conventional amplifier the transient response and the small signal bandwidth are determined primarily by the value of the external feedback resistor, R1, rather than by the ratio of R1/R2 as is customarily the case in an op amp application. This is a direct result of the low impedance at the inverting input. As with conventional op amps, the closed loop gain is -R1/R2. The closed loop transresistance is simply the parallel sum of R1 and Rt. Since R1 will generally be in the range 500 to 2 k and Rt is about 3 M the closed loop transresistance will be only 0.02% to 0.07% lower than R1. This small error will often be less than the resistor tolerance. When R1 is fairly large (above 5 k) but still much less than Rt, the closed loop HF response is dominated by the time constant R1Ct. Under such conditions the AD844 is over-damped and will provide only a fraction of its bandwidth potential. Because of the absence of slew rate limitations under these conditions, the circuit will exhibit a simple single pole response even under large signal conditions. In Figure 2, R3 is used to properly terminate the input if desired. R3 in parallel with R2 gives the terminated resistance. As R1 is lowered, the signal bandwidth increases, but the time constant R1Ct becomes comparable to higher order poles in the closed loop response. Therefore, the closed loop response becomes complex, and the pulse response shows overshoot. When R2 is much larger than the input resistance, RIN, at Pin 2, most of the feedback current in R1 is delivered to this input; but as R2 becomes comparable to RIN, less of the feedback is absorbed at Pin 2, resulting in a more heavily damped response. Consequently, for low values of R2 it is possible to lower R1 without causing instability in the closed loop response. Table I lists combinations of R1 and R2 and the resulting frequency response for the circuit of Figure 2. TPC 13 shows the very clean and fast 10 V pulse response of the AD844.
R1
+1
IIN RIN IIN
Rt
Ct
+1
Figure 1. Equivalent Schematic
The important parameters defining ac behavior are the transcapacitance, Ct, and the external feedback resistor (not shown). The time constant formed by these components is analogous to the dominant pole of a conventional op amp, and thus cannot be reduced below a critical value if the closed loop system is to be stable. In practice, Ct is held to as low a value as possible (typically 4.5 pF) so that the feedback resistor can be maximized while maintaining a fast response. The finite RIN also affects the closed loop response in some applications as will be shown. The open loop ac gain is also best understood in terms of the transimpedance rather than as an open loop voltage gain. The open loop pole is formed by Rt in parallel with Ct. Since Ct is typically 4.5 pF, the open loop corner frequency occurs at about 12 kHz. However, this parameter is of little value in determining the closed loop response.
VIN R2 R3 OPTIONAL
AD844
RL
VOUT
CL
Figure 2. Inverting Amplifier
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AD844
Table I.
ISIG R1
Gain -1 -1 -2 -2 -5 -5 -10 -10 -20 -100 +100
R1 1 k 500 2 k 1 k 5 k 500 1 k 500 1 k 5 k 5 k
R2 1 k 500 1 k 500 1 k 100 100 50 50 50 50
BW (MHz) 35 60 15 30 5.2 49 23 33 21 3.2 9
GBW (MHz) 35 60 30 60 26 245 230 330 420 320 900
CS
AD844
RL
VOUT
CL
Figure 3. Current-to-Voltage Converter
Circuit Description of the AD844
Response as an I-V Converter
The AD844 works well as the active element in an operational current to voltage converter, used in conjunction with an external scaling resistor, R1, in Figure 3. This analysis includes the stray capacitance, CS, of the current source, which might be a high speed DAC. Using a conventional op amp, this capacitance forms a "nuisance pole" with R1 which destabilizes the closed loop response of the system. Most op amps are internally compensated for the fastest response at unity gain, so the pole due to R1 and CS reduces the already narrow phase margin of the system. For example, if R1 were 2.5 k a CS of 15 pF would place this pole at a frequency of about 4 MHz, well within the response range of even a medium speed operational amplifier. In a current feedback amp this nuisance pole is no longer determined by R1 but by the input resistance, RIN. Since this is about 50 for the AD844, the same 15 pF forms a pole 212 MHz and causes little trouble. It can be shown that theresponse of this system is:
VOUT = - Isig K R1 (1 + sTd )(1 + sTn )
A simplified schematic is shown in Figure 4. The AD844 differs from a conventional op amp in that the signal inputs have radically different impedance. The noninverting input (Pin 3) presents the usual high impedance. The voltage on this input is transferred to the inverting input (Pin 2) with a low offset voltage, ensured by the close matching of like polarity transistors operating under essentially identical bias conditions. Laser trimming nulls the residual offset voltage, down to a few tens of microvolts. The inverting input is the common emitter node of a complementary pair of grounded base stages and behaves as a current summing node. In an ideal current feedback op amp the input resistance would be zero. In the AD844 it is about 50 . A current applied to the inverting input is transferred to a complementary pair of unity-gain current mirrors which deliver the same current to an internal node (Pin 5) at which the full output voltage is generated. The unity-gain complementary voltage follower then buffers this voltage and provides the load driving power. This buffer is designed to drive low impedance loads such as terminated cables, and can deliver 50 mA into a 50 load while maintaining low distortion, even when operating at supply voltages of only 6 V. Current limiting (not shown) ensures safe operation under short circuited conditions.
7 +VS
where K is a factor very close to unity and represents the finite dc gain of the amplifier, Td is the dominant pole and Tn is the nuisance pole:
IB
K=
Rt Rt + R1
+IN 3
2 -IN
TZ
5
6 OUT
Td = KR1Ct Tn = RINCS (assuming RIN << R1) Using typical values of R1 = 1 k and Rt = 3 M, K is 0.9997; in other words, the "gain error" is only 0.03%. This is much less than the scaling error of virtually all DACs and can be absorbed, if necessary, by the trim needed in a precise system. In the AD844, Rt is fairly stable with temperature and supply voltages, and consequently the effect of finite "gain" is negligible unless high value feedback resistors are used. Since that would result in slower response times than are possible, the relatively low value of Rt in the AD844 will rarely be a significant source of error.
IB
4 -VS
Figure 4. Simplified Schematic
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AD844
It is important to understand that the low input impedance at the inverting input is locally generated, and does not depend on feedback. This is very different from the "virtual ground" of a conventional operational amplifier used in the current summing mode which is essentially an open circuit until the loop settles. In the AD844, transient current at the input does not cause voltage spikes at the summing node while the amplifier is settling. Furthermore, all of the transient current is delivered to the slewing (TZ) node (Pin 5) via a short signal path (the grounded base stages and the wideband current mirrors). The current available to charge the capacitance (about 4.5 pF) at TZ node, is always proportional to the input error current, and the slew rate limitations associated with the large signal response of op amps do not occur. For this reason, the rise and fall times are almost independent of signal level. In practice, the input current will eventually cause the mirrors to saturate. When using 15 V supplies, this occurs at about 10 mA (or 2200 V/s). Since signal currents are rarely this large, classical "slew rate" limitations are absent. This inherent advantage would be lost if the voltage follower used to buffer the output were to have slew rate limitations. The AD844 has been designed to avoid this problem, and as a result the output buffer exhibits a clean large signal transient response, free from anomalous effects arising from internal saturation.
Response as a Noninverting Amplifier
+VS 4.7 OFFSET TRIM CPK 3nF 20 R1 499
- R2 4.99 VIN
8
0.22 F
AD844
+ 0.22 F 4.7 RL
-VS
Figure 5. Noninverting Amplifier Gain = 100, Optional Offset Trim Is Shown
46 VS = 40 15V
Since current feedback amplifiers are asymmetrical with regard to their two inputs, performance will differ markedly in noninverting and inverting modes. In noninverting modes, the large signal high speed behavior of the AD844 deteriorates at low gains because the biasing circuitry for the input system (not shown in Figure 4) is not designed to provide high input voltage slew rates. However, good results can be obtained with some care. The noninverting input will not tolerate a large transient input; it must be kept below 1 V for best results. Consequently this mode is better suited to high gain applications (greater than x10). TPC 20 shows a noninverting amplifier with a gain of 10 and a bandwidth of 30 MHz. The transient response is shown in TPCs 23 and 24. To increase the bandwidth at higher gains, a capacitor can be added across R2 whose value is approximately the ratio of R1 and R2 times Ct.
Noninverting Gain of 100
GAIN - dB
34 VS = 5V
28
22
16 100k 1M FREQUENCY - Hz 10M 20M
Figure 6. AC Response for Gain = 100, Configuration Shown in Figure 5
USING THE AD844 Board Layout
The AD844 provides very clean pulse response at high noninverting gains. Figure 5 shows a typical configuration providing a gain of 100 with high input resistance. The feedback resistor is kept as low as practicable to maximize bandwidth, and a peaking capacitor (CPK) can optionally be added to further extend the bandwidth. Figure 6 shows the small signal response with CPK = 3 nF, RL = 500 , and supply voltages of either 5 V or 15 V. Gain bandwidth products of up to 900 MHz can be achieved in this way. The offset voltage of the AD844 is laser trimmed to the 50 V level and exhibits very low drift. In practice, there is an additional offset term due to the bias current at the inverting input (IBN) which flows in the feedback resistor (R1). This can optionally be nulled by the trimming potentiometer shown in Figure 5.
As with all high frequency circuits considerable care must be used in the layout of the components surrounding the AD844. A ground plane, to which the power supply decoupling capacitors are connected by the shortest possible leads, is essential to achieving clean pulse response. Even a continuous ground plane will exhibit finite voltage drops between points on the plane, and this must be kept in mind in selecting the grounding points. Generally speaking, decoupling capacitors should be taken to a point close to the load (or output connector) since the load currents flow in these capacitors at high frequencies. The +IN and -IN circuits (for example, a termination resistor and Pin 3) must be taken to a common point on the ground plane close to the amplifier package. Use low impedance capacitors (AVX SR305C224KAA or equivalent) of 0.22 F wherever ac coupling is required. Include either ferrite beads and/or a small series resistance (approximately 4.7 ) in each supply line.
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AD844
Input Impedance
At low frequencies, negative feedback keeps the resistance at the inverting input close to zero. As the frequency increases, the impedance looking into this input will increase from near zero to the open loop input resistance, due to bandwidth limitations, making the input seem inductive. If it is desired to keep the input impedance flatter, a series RC network can be inserted across the input. The resistor is chosen so that the parallel sum of it and R2 equals the desired termination resistance. The capacitance is set so that the pole determined by this RC network is about half the bandwidth of the op amp. This network is not important if the input resistor is much larger than the termination used, or if frequencies are relatively low. In some cases, the small peaking that occurs without the network can be of use in extending the -3 dB bandwidth.
Driving Large Capacitive Loads
Schottky diodes, to create the error signal and limit the input signal to the oscilloscope. For measuring settling time, the ratio of R6/R5 is equal to R1/R2. For unity gain, R6 = R5 = 1 k, and RL = 500 . For the gain of -10, R5 = 50 , R6 = 500 and R L was not used since the summing network loads the output with approximately 275 . Using this network in a unity-gain configuration, settling time is 100 ns to 0.1% for a -5 V to +5 V step with CL = 10 pF.
TO SCOPE (TEK 7A11 FET PROBE) R5 D1 D2 R1 R6
Capacitive drive capability is 100 pF without an external network. With the addition of the network shown in Figure 7, the capacitive drive can be extended to over 10,000 pF, limited by internal power dissipation. With capacitive loads, the output speed becomes a function of the overdriven output current limit. Since this is roughly 100 mA, under these conditions, the maximum slew rate into a 1000 pF load is 100 V/s. Figure 8 shows the transient response of an inverting amplifier (R1 = R2 = 1 k) using the feed forward network shown in Figure 7, driving a load of 1000 pF.
VIN R2 R3 RL CL
AD844
VOUT
D1, D2 IN6263 OR EQUIV. SCHOTTKY DIODE
Figure 9. Settling Time Test Fixture
DC Error Calculation
AD844
VOUT
CL 750 22pF
Figure 10 shows a model of the dc error and noise sources for the AD844. The inverting input bias current, IBN, flows in the feedback resistor. IBP, the noninverting input bias current, flows in the resistance at Pin 3 (RP), and the resulting voltage (plus any offset voltage) will appear at the inverting input. The total error, VO, at the output is:
R1 VO = (IBP RP + VOS + IBN RIN )1 + + I BN R1 R2
Figure 7. Feed Forward Network for Large Capacitive Loads
Since IBN and IBP are unrelated both in sign and magnitude, inserting a resistor in series with the noninverting input will not necessarily reduce dc error and may actually increase it.
R1
R2
+
VN
~
INN
RIN IBN VOS
INP
IBP
RP
AD844
Figure 8. Driving 1000 pF CL with Feed Forward Network of Figure 7
Settling Time
Figure 10. Offset Voltage and Noise Model for the AD844
Settling time is measured with the circuit of Figure 9. This circuit employs a false summing node, clamped by the two
-10-
REV. D
Applications-AD844
Noise
0.3 IRE = 7.14mV
R1 2 2 2 VON = ((Inp RP ) + Vn )1 + + (Inn R1) R2
Overall noise can be reduced by keeping all resistor values to a minimum. With typical numbers, R1 = R2 = 1 k, R P = 0, Vn = 2 nV/Hz, Inp = 10 pA/Hz, Inn = 12 pA/Hz, V ON calculates to 12 nV/Hz. The current noise is dominant in this case, as it will be in most low gain applications.
Video Cable Driver Using 5 Volt Supplies
2
DIFFERENTIAL PHASE - Degree
Noise sources can be modeled in a manner similar to the dc bias currents, but the noise sources are INN, INP, VN, and the amplifier induced noise at the output, VON, is:
0.2
0.1
0
-0.1
-0.2
-0.3 0 18 36 54 VOUT - IRE 72 90
DIFFERENTIAL PHASE - Degree
The AD844 can be used to drive low impedance cables. Using 5 V supplies, a 100 load can be driven to 2.5 V with low distortion. Figure 11a shows an illustrative application which provides a noninverting gain of 2, allowing the cable to be reverse-terminated while delivering an overall gain of +1 to the load. The -3 dB bandwidth of this circuit is typically 30 MHz. Figure 11b shows a differential gain and phase test setup. In video applications, differential-phase and differential-gain characteristics are often important. Figure 11c shows the variation in phase as the load voltage varies. Figure 11d shows the gain variation.
+5V 2.2 F VIN 50 3 2 7 4 2.2 F 300 -5V 300 50 ZO = 50 RL 50 VOUT
Figure 11c. Differential Phase for the Circuit of Figure 11a
0.06 IRE = 7.14mV 0.04
0.02
0
-0.02
6
-0.04
-0.06 0 18 36 54 72 90
VOUT - IRE
Figure 11d. Differential Gain for the Circuit of Figure 11a Figure 11a. The AD844 as a Cable Driver
High Speed DAC Buffer
HP8753A NETWORK ANALYZER
RF OUT R
IN OUT HP11850C SPLITTER OUT
OUT
VIN VIN
CIRCUIT UNDER TEST
VOUT
EXT TRIG SYNC OUT HP3314A STAIRCASE GENERATOR OUT
50 (TERMINATOR)
470
Figure 11b. Differential Gain/Phase Test Setup Figure
The AD844 performs very well in applications requiring current-to-voltage conversion. Figure 12 shows connections for use with the AD568 current output DAC. In this application the bipolar offset is used so that the full-scale current is 5.12 mA, which generates an output of 5.12 V usingdecoupling and grounding techniques to achieve the full 12-bit accuracy and realize the fast settling capabilities of the system. The unmarked capacitors in this figure are 0.1 F ceramic (for the 1 k application resistor on the AD568. Figure 13 shows the full-scale transient response. Care is needed in power supply example, AVX Type SR305C104KAA), and the ferrite inductors should be about 2.5 H (for example, Fair-Rite Type 2743002122). The AD568 data sheet should be consulted for more complete details about its use.
REV. D
-11-
AD844
1 2 3 4 5
MSB
+15V 24 * * * *
+15V
REFCOM 23 -15V 22 IBPD 21 IOUT 20
-15V
AD844
RI
VOUT
DIGITAL INPUTS
6 7 8 9 10 11 12
AD568 RL
19
ACOM 18 LCOM 17 SPAN 16 SPAN 15 THCOM 14 LSB VTH 13
ANALOG SUPPLY GROUND
GROUND 100pF *0.22 F POWER SUPPLY BYPASS CAPACITORS -5V
DIGITAL SUPPLY
TOP VIEW (Not to Scale)
Figure 12. High Speed DAC Amplifier
+VS TYP+6V @15 A
10 0.22 F INPUTS VX 0 TO 3V VY 2V FS 3nF
1 16
10 0.22 F
TOP VIEW (Not to Scale)
AD844
AD539
OUTPUT VW VW = -VXVY 2V
I/P GND
0.22 F
8 9
10 -VS TYP+6V @15 A
Figure 13. DAC Amplifier Full-Scale Transient Response
20 MHz Variable Gain Amplifier
0.22 F 10 *VX AND VY INPUTS MAY OPTIONALLY BE TERMINATED - TYPICALLY BY USING A 50 OR 75 RESISTOR TO GROUND.
The AD844 is an excellent choice as an output amplifier for the AD539 multiplier, in all of its connection modes. (See AD539 data sheet for full details.) Figure 14 shows a simple multiplier providing the output: VV VW = - X Y 2V where VX is the "gain control" input, a positive voltage of from 0 V to 3.2 V (max) and VY is the "signal voltage," nominally 2 V FS but capable of operation up to 4.2 V. The peak output in this configuration is thus 6.7 V. Using all four of the internal application resistors provided on the AD539 in parallel results in a feedback resistance of 1.5 k, at which value the bandwidth of the AD844 is about 22 MHz, and is essentially independent of VX. The gain at VX = 3.16 V is +4 dB.
Figure 14. 20 MHz VGA Using the AD539
Figure 15 shows the small signal response for a 50 dB gain control range (VX = 10 mV to 3.16 V). At small values of VX, capacitive feedthrough on the PC board becomes troublesome, and very careful layout techniques are needed to minimize this problem. A ground strip between the pins of the AD539 will be helpful in this regard. Figure 16 shows the response to a 2 V pulse on VY for VX = 1 V, 2 V, and 3 V. For these results, a load resistor of 500 was used and the supplies were 9 V. The multiplier will operate from supplies between 4.5 V and 16.5 V. Disconnecting Pins 9 and 16 on the AD539 alters the denominator in the above expression to 1 V, and the bandwidth will be approximately 10 MHz, with a maximum gain of 10 dB. Using only Pin 9 or Pin 16 results in a denominator of 0.5 V, a bandwidth of 5 MHz and a maximum gain of 16 dB.
-12-
REV. D
AD844
+4 VX = 3.15V -6 VX = 1.0V -16
GAIN - dB
VX = 0.316V -26 VX = 0.10V -36 VX = 0.032V -46
-56 100k 1M FREQUENCY - Hz 10M 60M
Figure 15. VGA AC Response
Figure 16. VGA Transient Response with VX = 1 V, 2 V, and 3 V
REV. D
-13-
AD844
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
Mini-DIP (N) Package (N-8)
0.430 (10.92) 0.348 (8.84)
8 5
0.280 (7.11) 0.240 (6.10) 0.325 (8.25) 0.300 (7.62) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN 0.015 (0.381) 0.008 (0.204) 0.195 (4.95) 0.115 (2.93)
1
4
PIN 1
0.100 (2.54) BSC
0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93)
0.022 (0.558) 0.070 (1.77) SEATING 0.014 (0.356) 0.045 (1.15) PLANE
Cerdip (Q) Package (Q-8)
0.005 (0.13) MIN
8
0.055 (1.4) MAX
5
PIN 1
1 4
0.310 (7.87) 0.220 (5.59)
0.100 (2.54) BSC 0.405 (10.29) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 15 0 0.015 (0.38) 0.008 (0.20) 0.320 (8.13) 0.290 (7.37)
SEATING 0.023 (0.58) 0.070 (1.78) PLANE 0.014 (0.36) 0.030 (0.76)
16-Lead SOIC (R) Package (R-16)
0.4133 (10.50) 0.3977 (10.00)
16
9
0.2992 (7.60) 0.2914 (7.40)
1 8
0.4193 (10.65) 0.3937 (10.00)
PIN 1
0.050 (1.27) BSC
0.1043 (2.65) 0.0926 (2.35)
0.0291 (0.74) 0.0098 (0.25)
45
0.0118 (0.30) 0.0040 (0.10)
8 0.0192 (0.49) SEATING 0 0.0125 (0.32) PLANE 0.0138 (0.35) 0.0091 (0.23)
0.0500 (1.27) 0.0157 (0.40)
-14-
REV. D
AD844 Revision History
Location Data Sheet changed from REV. B to REV. C. Page
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
REV. D
-15-
-16-
C00897-0-11/01(D)
PRINTED IN U.S.A.

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