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ASAHI KASEI
[AK5700]
16-Bit Mono ADC with PLL & MIC-AMP
GENERAL DESCRIPTION The AK5700 features a 16-bit mono ADC. Input circuits include a Microphone-Amplifier and an ALC (Auto Level Control) circuit that is suitable for portable application with recording function. On-chip PLL supports base-band clock of mobile phone, therefore it is easy to connect with DSP. The AK5700 is available in a 24pin QFN, utilizing less board space than competitive offerings. FEATURES 1. Resolution: 16bits 2. Recording Function - Input Selector - Full-differential or Single-ended Input - MIC Amplifier (+30dB/+15dB or 0dB) - Input Voltage: 1.8Vpp@AVDD=3.0V (= 0.6 x AVDD) - ADC Performance: S/(N+D): 78dB, DR, S/N: 89dB@MGAIN=0dB S/(N+D): 77dB, DR, S/N: 87dB@MGAIN=+15dB S/(N+D): 72dB, DR, S/N: 77dB@MGAIN=+30dB - Digital HPF for DC-offset cancellation (fc=3.4Hz@fs=44.1kHz) - Digital ALC (Automatic Level Control) (+36dB -54dB, 0.375dB Step, Mute) 3. Sampling Rate: - PLL Slave Mode (EXLRCK pin): 7.35kHz 48kHz - PLL Slave Mode (EXBCLK pin): 7.35kHz 48kHz - PLL Slave Mode (MCKI pin): 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz - PLL Master Mode: 8kHz, 11.025kHz, 12kHz, 16kHz, 22.05kHz, 24kHz, 32kHz, 44.1kHz, 48kHz - EXT Slave Mode: 7.35kHz 48kHz (256fs), 7.35kHz 26kHz (512fs), 7.35kHz 13kHz (1024fs) 4. PLL Input Clock: - MCKI pin: 27MHz, 26MHz, 24MHz, 19.2MHz, 13.5MHz, 13MHz, 12.288MHz, 12MHz, 11.2896MHz - EXLRCK pin: 1fs - EXBCLK pin: 32fs/64fs 5. Master/Slave mode 6. Audio Interface Format: MSB First, 2's complement - DSP Mode, 16bit MSB justified, I2S 7. P I/F: 3-wire Serial 8. Power Supply: - AVDD: 2.4 3.6V - DVDD: 1.6 3.6V 9. Power Supply Current: 6mA 10. Ta = -30 85C 11. Package: 24pin QFN (4mm x 4mm) 12. Pin and Register compatible with AK5701 Stereo Version
AK5700
MS0569-E-01 -1-
2006/12
ASAHI KASEI
[AK5700]
Block Diagram
DVDD DVSS PDN AIN1/AIN+ AIN- AIN2 S E L ADC HPF ALC or IVOL Audio I/F Controller S E L LRCK BCLK SDTO
MPWR VCOM AVDD AVSS VCOC PLL
Control Register
EXLRCK EXBCLK EXSDTI
MCKO
MCKI
CSP
CSN CCLK CDTI
Figure 1. Block Diagram
MS0569-E-01 -2-
2006/12
ASAHI KASEI
[AK5700]
Ordering Guide
AK5700VN AKD5700 24pin QFN (0.5mm pitch) -30 +85C Evaluation board for AK5700
Pin Layout
15
14
MPWR TEST AIN2 AIN AIN1 / AIN+ VCOC
19 20 21 22 23 24 1 2 3 4 5 6
13 12 11
18
17
16
EXBCLK
CCLK
MCKI
CDTI
PDN
CSN
EXLRCK EXSDTI MCKO CSP SDTO LRCK
AK5700VN
Top View
10 9 8 7
VCOM
DVDD
AVDD
DVSS
AVSS
Comparison with AK5701VN
Function ADC channel Number Input Selector Audio I/F Format AK5701VN 2 channel 2 Stereo Input Selector DSP Mode 0, DSP Mode 1, Left justified, I2S AK5700VN 1channel 2 Mono Input Selector DSP Mode 0, Left justified, I2S
MS0569-E-01 -3-
BCLK
2006/12
ASAHI KASEI
[AK5700]
PIN/FUNCTION
Function Common Voltage Output Pin, 0.5 x AVDD 1 VCOM O Bias voltage of ADC inputs. 2 AVSS Analog Ground Pin 3 AVDD Analog Power Supply Pin 4 DVDD Digital Power Supply Pin 5 DVSS Digital Ground Pin 6 BCLK O Audio Serial Data Clock Pin 7 LRCK O Input / Output Channel Clock Pin 8 SDTO O Audio Serial Data Output Pin Chip Select Polarity Pin 9 CSP I "H": CSN pin = "H" active, C1-0 = "01" "L": CSN pin = "L" active, C1-0 = "10" 10 MCKO O Master Clock Output Pin 11 EXSDTI I External Audio Serial Data Input Pin 12 EXLRCK I External Input / Output Channel Clock Pin 13 EXBCLK I External Audio Serial Data Clock Pin 14 MCKI I External Master Clock Input Pin 15 CDTI I Control Data Input Pin 16 CCLK I Control Data Clock Pin (Internal Pull-down at CSP pin = "H") 17 CSN I Chip Select Pin Power-Down Mode Pin 18 PDN I "H": Power-up, "L": Power-down, reset and initializes the control register. 19 MPWR O MIC Power Supply Pin Test Pin 20 TEST This pin should be left floating. 21 AIN2 I Analog Input 2 Pin 22 AIN- I Negative Input Pin AIN1 I Analog Input 1 Pin (MDIF1 bit = "0": Single-ended Input) 23 AIN+ I Positive Input Pin (MDIF1 bit = "1": Full-differential Input) Output Pin for Loop Filter of PLL Circuit 24 VCOC O This pin should be connected to AVSS with one resistor and capacitor in series. Note 1. All input pins except analog input pins (AIN1, AIN1-, AIN2) should not be left floating. No. Pin Name I/O
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name MPWR, VCOC, AIN1/AIN+, AIN-, AIN2 BCLK, LRCK, SDTO, MCKO MCKI, EXBCLK, EXLRCK, EXSDTI Setting These pins should be open. These pins should be open. These pins should be connected to DVSS.
MS0569-E-01 -4-
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ASAHI KASEI
[AK5700]
ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS=0V; Note 2) Parameter Symbol min Power Supplies: Analog AVDD -0.3 Digital DVDD -0.3 |AVSS - DVSS| (Note 3) GND Input Current, Any Pin Except Supplies IIN Analog Input Voltage (Note 4) VINA -0.3 Digital Input Voltage (Note 5) VIND -0.3 Ambient Temperature (powered applied) Ta -30 Storage Temperature Tstg -65
Note 2. All voltages with respect to ground. Note 3. AVSS and DVSS must be connected to the same analog ground plane. Note 4. AIN1/AIN+, AIN-, AIN2 pins Note 5. PDN, CSN, CCLK, CDTI, CSP, MCKI, EXSDTI, EXLRCK, EXBCLK pins
max 4.6 4.6 0.3 10 AVDD+0.3 DVDD+0.3 85 150
Units V V V mA V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V; Note 2) Parameter Power Supplies Analog (Note 6) Digital Symbol AVDD DVDD min 2.4 1.6 typ 3.0 3.0 Max 3.6 AVDD Units V V
Note 2. All voltages with respect to ground. Note 6. The power-up sequence between AVDD and DVDD is not critical. When only AVDD is powered OFF, the power supply current of DVDD at power-down mode may be increased. DVDD should not be powerd OFF while AVDD is powered ON. * AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0569-E-01 -5-
2006/12
ASAHI KASEI
[AK5700]
ANALOG CHARACTERISTICS (Ta=25C; AVDD, DVDD=3.0V; AVSS=DVSS=0V; PLL Master Mode; MCKI=12MHz, fs=44.0995kHz, BCLK=64fs; Signal Frequency=1kHz; 16bit Data; Measurement frequency=20Hz 20kHz; unless otherwise specified) Min Typ max Units Parameter MIC Amplifier: AIN1, AIN2 pins; MDIF1 bit = "0" (Single-ended inputs) Input MGAIN1-0 bits = "00" 40 60 80 k Resistance MGAIN1-0 bits = "01" or "10" 20 30 40 k MGAIN1-0 bits = "00" 0 dB Gain MGAIN1-0 bits = "01" +15 dB MGAIN1-0 bits = "10" +30 dB MIC Amplifier: AIN+, AIN- pins; MDIF1 bit = "1" (Full-differential input) Input Voltage (Note 7) MGAIN1-0 bits = "01" 0.37 Vpp MGAIN1-0 bits = "10" 0.066 Vpp MIC Power Supply: MPWR pin Output Voltage (Note 8) 2.02 2.25 2.48 V Load Resistance 1.0 k Load Capacitance 30 pF ADC Analog Input Characteristics: AIN1/AIN2 pins (Single-ended inputs) ADC IVOL, MGAIN=+15dB, IVOL=0dB, ALC=OFF Resolution 16 Bits MGAIN=+30dB 0.057 Vpp Input Voltage (Note 9) MGAIN=+15dB 0.27 0.32 0.37 Vpp MGAIN=0dB 1.53 1.80 2.07 Vpp 67 77 dB S/(N+D) (-0.5dBFS) (Note 10) 79 87 dB D-Range (-60dBFS, A-weighted) (Note 11) S/N (A-weighted) (Note 11) 79 87 dB Power Supplies: Power Supply Current: AVDD+DVDD Power Up (PDN pin = "H") (Note 12) 6 12 mA Power Down (PDN pin = "L") (Note 13) 1 20 A
Note 7. The voltage difference between AIN+ and AIN- pins. AC coupling capacitor should be inserted in series at each input pin. Full-differential input is not available at MGAIN1-0 bits = "00". Maximum input voltage of AIN+, AIN- pins is proportional to AVDD voltage, respectively. Vin = |(AIN+) - (AIN-)| = 0.123 x AVDD (max)@MGAIN1-0 bits = "01", 0.022 x AVDD (max)@MGAIN1-0 bits = "10". When the signal larger than above value is input to AIN+, AIN- pin, ADC does not operate normally. Note 8. Output voltage is proportional to AVDD voltage. Vout = 0.75 x AVDD (typ). Note 9. Input voltage is proportional to AVDD voltage. Vin = 0.107 x AVDD (typ)@MGAIN1-0 bits = "01" (+15dB), Vin = 0.6 x AVDD(typ)@MGAIN1-0 bits = "00" (0dB). Note 10. 80dB(typ)@MGAIN=0dB, 70dB(typ)@MGAIN=+30dB Note 11. 89dB(typ)@MGAIN=0dB, 75dB(typ)@MGAIN=+30dB Note 12. PLL Master Mode (MCKI=12MHz), PMADC = PMVCM = PMPLL = PMMP = M/S bits = "1" and MCKO bit = "0". MPWR pin outputs 0mA. AVDD=4.5mA(typ), DVDD=1.5mA(typ). EXT Slave Mode (PMPLL = M/S = MCKO bits = "0"): AVDD=3.8mA(typ), DVDD=1.2mA(typ). Bypass Mode (THR bit = "1", PMADC = M/S bits = "0"), fs=8kHz: AVDD=1A(typ), DVDD=150A(typ). Note 13. All digital input pins are fixed to DVDD or DVSS.
MS0569-E-01 -6-
2006/12
ASAHI KASEI
[AK5700]
FILTER CHARACTERISTICS (Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V; fs=44.1kHz) Parameter Symbol min ADC Digital Filter (Decimation LPF): PB 0 Passband (Note 14) 0.1dB -1.0dB -3.0dB Stopband (Note 14) SB 25.7 Passband Ripple PR Stopband Attenuation SA 65 Group Delay (Note 15) GD Group Delay Distortion GD ADC Digital Filter (HPF): HPF1-0 bits = "00" Frequency Response (Note 14) -3.0dB FR -0.5dB -0.1dB
typ 20.0 21.1 18 0 3.4 10 22
max 17.4 0.1 -
Units kHz kHz kHz kHz dB dB 1/fs s Hz Hz Hz
Note 14. The passband and stopband frequencies scale with fs (system sampling rate). For example, PB=0.454*fs (@-1.0dB). Each response refers to that of 1kHz. Note 15. The calculated delay time caused by digital filtering. This time is from the input of analog signal to setting of the 16-bit data from the input register to the output register of the ADC. This time includes the group delay of the HPF.
DC CHARACTERISTICS (Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V) Parameter Symbol min High-Level Input Voltage Except CSP pin; 2.2V DVDD 3.6V VIH 70%DVDD Except CSP pin; 1.6V DVDD <2.2V VIH 80%DVDD CSP pin VIH 90%DVDD Low-Level Input Voltage Except CSP pin; 2.2V DVDD 3.6V VIL Except CSP pin; 1.6V DVDD <2.2V VIL CSP pin VIL High-Level Output Voltage (Iout= -200A) VOH DVDD-0.2 Low-Level Output Voltage (Iout= 200A) VOL Input Leakage Current (Note 16) Iin -
typ -
max 30%DVDD 20%DVDD 10%DVDD 0.2 10
Units V V V V V V V V A
Note 16. When CSP pin is "H", CCLK pin has internal pull-down device, normally 100k.
MS0569-E-01 -7-
2006/12
ASAHI KASEI
[AK5700]
SWITCHING CHARACTERISTICS (Ta=25C; AVDD=2.4 3.6V; DVDD=1.6 3.6V; CL=20pF; unless otherwise specified) Parameter Symbol min typ PLL Master Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output Timing Frequency fMCK 0.2352 Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 256fs at fs=32kHz, 29.4kHz dMCK 33 LRCK Output Timing Frequency fs 7.35 DSP Mode: Pulse Width High tLRCKH tBCK Except DSP Mode: Duty Cycle Duty 50 BCLK Output Timing Period BCKO1-0 bit = "01" tBCK 1/(32fs) BCKO1-0 bit = "10" tBCK 1/(64fs) Duty Cycle dBCK 50 PLL Slave Mode (PLL Reference Clock = MCKI pin) MCKI Input Timing Frequency fCLK 11.2896 Pulse Width Low tCLKL 0.4/fCLK Pulse Width High tCLKH 0.4/fCLK MCKO Output Timing Frequency fMCK 0.2352 Duty Cycle Except 256fs at fs=32kHz, 29.4kHz dMCK 40 50 256fs at fs=32kHz, 29.4kHz dMCK 33 EXLRCK Input Timing Frequency fs 7.35 DSP Mode: Pulse Width High tLRCKH tBCK-60 Except DSP Mode: Duty Cycle Duty 45 EXBCLK Input Timing Period tBCK 1/(64fs) Pulse Width Low tBCKL 0.4 x tBCK Pulse Width High tBCKH 0.4 x tBCK PLL Slave Mode (PLL Reference Clock = EXLRCK pin) EXLRCK Input Timing Frequency fs 7.35 DSP Mode: Pulse Width High tLRCKH tBCK-60 Except DSP Mode: Duty Cycle Duty 45 EXBCLK Input Timing Period tBCK 1/(64fs) Pulse Width Low tBCKL 0.4 x tBCK Pulse Width High tBCKH 0.4 x tBCK -
max
Units
27 12.288 60 48 -
MHz ns ns MHz % % kHz ns % ns ns %
27 12.288 60 48 1/fs - tBCK 55 1/(32fs) -
MHz ns ns MHz % % kHz ns % ns ns ns
48 1/fs - tBCK 55 1/(32fs) -
kHz ns % ns ns ns
MS0569-E-01 -8-
2006/12
ASAHI KASEI
[AK5700]
Parameter Symbol PLL Slave Mode (PLL Reference Clock = EXBCLK pin) EXLRCK Input Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty EXBCLK Input Timing Period PLL3-0 bits = "0010" tBCK PLL3-0 bits = "0011" tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Slave Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH EXLRCK Input Timing Frequency 256fs fs 512fs fs 1024fs fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty EXBCLK Input Timing Period tBCK Pulse Width Low tBCKL Pulse Width High tBCKH External Master Mode MCKI Input Timing Frequency 256fs fCLK 512fs fCLK 1024fs fCLK Pulse Width Low tCLKL Pulse Width High tCLKH LRCK Output Timing Frequency fs DSP Mode: Pulse Width High tLRCKH Except DSP Mode: Duty Cycle Duty BCLK Output Timing Period BCKO1-0 bit = "01" tBCK BCKO1-0 bit = "10" tBCK Duty Cycle dBCK
min
typ
max
Units
7.35 tBCK-60 45 0.4 x tBCK 0.4 x tBCK
1/(32fs) 1/(64fs) -
48 1/fs - tBCK 55 -
kHz ns % ns ns ns ns
1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK 7.35 7.35 7.35 tBCK-60 45 312.5 130 130
-
12.288 13.312 13.312 48 26 13 1/fs - tBCK 55 -
MHz MHz MHz ns ns kHz kHz kHz ns % ns ns ns
1.8816 3.7632 7.5264 0.4/fCLK 0.4/fCLK 7.35 -
tBCK 50 1/(32fs) 1/(64fs) 50
12.288 13.312 13.312 48 -
MHz MHz MHz ns ns kHz ns % ns ns %
MS0569-E-01 -9-
2006/12
ASAHI KASEI
[AK5700]
Parameter Audio Interface Timing (DSP Mode) Master Mode LRCK "" to BCLK "" (Note 17) LRCK "" to BCLK "" (Note 18) BCLK "" to SDTO (BCKP bit = "0") BCLK "" to SDTO (BCKP bit = "1") Slave Mode EXLRCK "" to EXBCLK "" (Note 17) EXLRCK "" to EXBCLK "" (Note 18) EXBCLK "" to EXLRCK "" (Note 17) EXBCLK "" to EXLRCK "" (Note 18) EXBCLK "" to SDTO (BCKP bit = "0") EXBCLK "" to SDTO (BCKP bit = "1") Audio Interface Timing (Left justified & I2S) Master Mode BCLK "" to LRCK Edge (Note 19) LRCK Edge to SDTO (MSB) (Except I2S mode) BCLK "" to SDTO Slave Mode EXLRCK Edge to EXBCLK "" (Note 19) EXBCLK "" to EXLRCK Edge (Note 19) EXLRCK Edge to SDTO (MSB) (Except I2S mode) EXBCLK "" to SDTO
Symbol
min
typ
Max
Units
tDBF tDBF tBSD tBSD tLRB tLRB tBLR tBLR tBSD tBSD
0.5 x tBCK - 40 0.5 x tBCK - 40 -70 -70 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK 0.4 x tBCK -
0.5 x tBCK 0.5 x tBCK -
0.5 x tBCK + 40 0.5 x tBCK + 40 70 70 80 80
ns ns ns ns ns ns ns ns ns ns
tMBLR tLRD tBSD tLRB tBLR tLRD tBSD
-40 -70 -70 50 50 -
-
40 70 70 80 80
ns ns ns ns ns ns ns
Note 17. MSBS, BCKP bits = "00" or "11" Note 18. MSBS, BCKP bits = "01" or "10" Note 19. EXBCLK rising edge must not occur at the same time as EXLRCK edge.
MS0569-E-01 - 10 -
2006/12
ASAHI KASEI
[AK5700]
Parameter Control Interface Timing (CSP pin = "L") CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "H" Time CSN "" to CCLK "" CCLK "" to CSN "" Control Interface Timing (CSP pin = "H") CCLK Period CCLK Pulse Width Low Pulse Width High CDTI Setup Time CDTI Hold Time CSN "L" Time CSN "" to CCLK "" CCLK "" to CSN "" Power-down & Reset Timing PDN Pulse Width (Note 20) PMADC "" to SDTO valid (Note 21) HPF1-0 bits = "00" HPF1-0 bits = "01" HPF1-0 bits = "10"
Symbol tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tCCK tCCKL tCCKH tCDS tCDH tCSW tCSS tCSH tPD tPDV tPDV tPDV
min 142 56 56 28 28 150 50 50 142 56 56 28 28 150 50 50 150 -
typ 3088 1552 784
max -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1/fs 1/fs 1/fs
Note 20. The AK5700 can be reset by the PDN pin = "L". Note 21. This is the count of LRCK "" from the PMADC bit = "1".
MS0569-E-01 - 11 -
2006/12
ASAHI KASEI
[AK5700]
Timing Diagram
1/fCLK VIH MCKI VIL tCLKH 1/fs tCLKL
LRCK tLRCKH tBCK tLRCKL
50%DVDD
Duty = tLRCKH x fs x 100 tLRCKL x fs x 100
BCLK tBCKH tBCKL 1/fMCK
50%DVDD
dBCK = tBCKH / tBCK x 100 tBCKL / tBCK x 100
MCKO tMCKL
50%DVDD dMCK = tMCKL x fMCK x 100
Figure 2. Clock Timing (PLL/EXT Master mode)
tLRCKH
LRCK tDBF tBCK dBCK BCLK (BCKP = "0")
50%DVDD
50%DVDD
BCLK (BCKP = "1") tBSD
50%DVDD
SDTO
MSB
50%DVDD
Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = "0")
MS0569-E-01 - 12 -
2006/12
ASAHI KASEI
[AK5700]
tLRCKH
LRCK tDBF tBCK dBCK BCLK (BCKP = "1")
50%DVDD
50%DVDD
BCLK (BCKP = "0") tBSD
50%DVDD
SDTO
MSB
50%DVDD
Figure 4. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = "1")
LRCK
50%DVDD
tMBLR
tBCKL 50%DVDD
BCLK tLRD
tBSD
SDTO
50%DVDD
Figure 5. Audio Interface Timing (PLL/EXT Master mode & Except DSP mode)
MS0569-E-01 - 13 -
2006/12
ASAHI KASEI
[AK5700]
1/fs VIH VIL tLRCKH tBCK VIH EXBCLK (BCKP = "0") tBCKH tBCKL VIH EXBCLK (BCKP = "1") VIL VIL tBLR
EXLRCK
Figure 6. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 0)
1/fs VIH VIL tLRCKH tBCK VIH EXBCLK (BCKP = "1") tBCKH tBCKL VIH EXBCLK (BCKP = "0") VIL VIL tBLR
EXLRCK
Figure 7. Clock Timing (PLL Slave mode; PLL Reference Clock = EXLRCK or EXBCLK pin & DSP mode; MSBS = 1)
MS0569-E-01 - 14 -
2006/12
ASAHI KASEI
[AK5700]
1/fCLK VIH MCKI VIL tCLKH 1/fs VIH EXLRCK VIL tLRCKH tBCK tLRCKL Duty = tLRCKH x fs x 100 = tLRCKL x fs x 100 VIH EXBCLK VIL tBCKH fMCK tBCKL tCLKL
MCKO tMCKL
50%DVDD
dMCK = tMCKL x fMCK x 100
Figure 8. Clock Timing (PLL Slave mode; PLL Reference Clock = MCKI pin & Except DSP mode)
tLRCKH VIH EXLRCK tLRB VIL
VIH EXBCLK (BCKP = "0") VIH EXBCLK (BCKP = "1") tBSD VIL VIL
SDTO
MSB
50%DVDD
Figure 9. Audio Interface Timing (PLL Slave mode & DSP mode; MSBS = 0)
MS0569-E-01 - 15 -
2006/12
ASAHI KASEI
[AK5700]
tLRCKH VIH EXLRCK tLRB VIL
VIH EXBCLK (BCKP = "1") VIH EXBCLK (BCKP = "0") tBSD VIL VIL
SDTO
MSB
50%DVDD
Figure 10. Audio Interface Timing (PLL Slave mode, DSP mode; MSBS = 1)
1/fCLK VIH MCKI VIL tCLKH 1/fs VIH EXLRCK VIL tLRCKH tBCK VIH EXBCLK VIL tBCKH tBCKL tLRCKL Duty = tLRCKH x fs x 100 tLRCKL x fs x 100 tCLKL
Figure 11. Clock Timing (EXT Slave mode)
MS0569-E-01 - 16 -
2006/12
ASAHI KASEI
[AK5700]
VIH EXLRCK VIL tBLR tLRB VIH EXBCLK VIL tLRD tBSD
SDTO
MSB
50%DVDD
Figure 12. Audio Interface Timing (PLL/EXT Slave mode)
MS0569-E-01 - 17 -
2006/12
ASAHI KASEI
[AK5700]
VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCCK tCDH VIH R/W VIL
Figure 13. WRITE Command Input Timing (CSP pin = "L")
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI D2 D1 D0 VIL
Figure 14. WRITE Data Input Timing (CSP pin = "L")
MS0569-E-01 - 18 -
2006/12
ASAHI KASEI
[AK5700]
VIH CSN VIL tCSS tCCKL tCCKH VIH CCLK VIL tCDS CDTI C1 C0 tCCK tCDH VIH R/W VIL
Figure 15. WRITE Command Input Timing (CSP pin = "H")
tCSW VIH CSN VIL tCSH VIH CCLK VIL
VIH CDTI D2 D1 D0 VIL
Figure 16. WRITE Data Input Timing (CSP pin = "H")
MS0569-E-01 - 19 -
2006/12
ASAHI KASEI
[AK5700]
PMADC bit tPDV
SDTO
50%DVDD
Figure 17. Power Down & Reset Timing 1
tPD PDN VIL
Figure 18. Power Down & Reset Timing 2
MS0569-E-01 - 20 -
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ASAHI KASEI
[AK5700]
OPERATION OVERVIEW System Clock
There are the following five clock modes to interface with external devices (see Table 1 and Table 2.) Mode PMPLL bit M/S bit PLL3-0 bits Figure PLL Master Mode (Note 22) 1 1 See Table 4 Figure 19 PLL Slave Mode 1 1 0 See Table 4 Figure 20 (PLL Reference Clock: MCKI pin) PLL Slave Mode 2 1 0 See Table 4 Figure 21 (PLL Reference Clock: EXLRCK or EXBCLK pin) EXT Slave Mode 0 0 x Figure 22 EXT Master Mode (Note 23) 0 0 x Figure 23 Note 22. If M/S bit = "1", PMPLL bit = "0" and MCKO bit = "1" during the setting of PLL Master Mode, the invalid clocks are output from MCKO pin when MCKO bit is "1". Note 23. In case of EXT Master Mode, the register should be set as Figure 45. Table 1. Clock Mode Setting (x: Don't care) Mode PLL Master Mode PLL Slave Mode (PLL Reference Clock: MCKI pin) PLL Slave Mode (PLL Reference Clock: EXLRCK or EXBCLK pin) EXT Slave Mode EXT Master Mode MCKO bit 0 1 0 1 0 0 0 MCKO pin "L" Selected by PS1-0 bits "L" Selected by PS1-0 bits "L" "L" "L" MCKI pin Selected by PLL3-0 bits Selected by PLL3-0 bits GND Selected by FS1-0 bits Selected by FS1-0 bits BCLK pin, LRCK pin, EXBCLK pin EXLRCK pin
BCLK pin (Selected by BCKO1-0 bits)
LRCK pin (1fs)
EXBCLK pin EXLRCK pin (1fs) ( 32fs) EXBCLK pin EXLRCK pin (Selected by (1fs) PLL3-0 bits) EXBCLK pin EXLRCK pin (1fs) ( 32fs)
BCLK pin (Selected by BCKO1-0 bits)
LRCK pin (1fs)
Table 2. Clock pins state in Clock Mode
Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = "1" selects master mode and "0" selects slave mode. When the AK5700 is power-down mode (PDN pin = "L") and exits reset state, the AK5700 is slave mode. After exiting reset state, the AK5700 goes to master mode by changing M/S bit = "1". M/S bit 0 1 Mode Used pins Slave Mode EXBCLK, EXLRCK Master Mode BCLK, LRCK Table 3. Select Master/Salve Mode
Default
MS0569-E-01 - 21 -
2006/12
ASAHI KASEI
[AK5700]
PLL Mode
When PMPLL bit is "1", a fully integrated analog phase locked loop (PLL) generates a clock that is selected by the PLL3-0 and FS3-0 bits. The PLL lock time is shown in Table 4, whenever the AK5700 is supplied to a stable clocks after PLL is powered-up (PMPLL bit = "0" "1") or sampling frequency changes. 1) Setting of PLL Mode
Mode
PLL3 bit 0 0 0 0 0 0 0 1 1 1 1 1 1
PLL2 Bit 0 0 0 1 1 1 1 0 0 1 1 1 1
PLL1 bit 0 1 1 0 0 1 1 0 0 0 0 1 1
PLL0 bit 0 0 1 0 1 0 1 0 1 0 1 0 1
PLL Reference Clock Input Pin EXLRCK pin EXBCLK pin EXBCLK pin
Input Frequency 1fs 32fs 64fs
R and C of VCOC pin R[] C[F] 6.8k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 10k 220n 4.7n 10n 4.7n 10n 4.7n 4.7n 4.7n 4.7n 4.7n 4.7n 10n 10n 220n 220n
0 2 3 4 5 6 7 8 9 12 13 14 15
MCKI pin 11.2896MHz MCKI pin 12.288MHz MCKI pin 12MHz MCKI pin 24MHz MCKI pin 19.2MHz MCKI pin 12MHz (Note24) Default MCKI pin 13.5MHz MCKI pin 27MHz MCKI pin 13MHz MCKI pin 26MHz Others Others N/A Note 24. See Table 5 regarding the difference between PLL3-0 bits = "0110"(Mode 6) and "1001"(Mode 9). Clock jitter is lower in Mode9 than Mode6 respectively. Table 4. Setting of PLL Mode (*fs: Sampling Frequency) 2) Setting of sampling frequency in PLL Mode When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined in Table 5. Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency 0 0 0 0 0 8kHz 1 0 0 0 1 12kHz 2 0 0 1 0 16kHz 3 0 0 1 1 24kHz 7.35kHz 4 0 1 0 0 7.349918kHz (Note25) 11.025kHz 5 0 1 0 1 11.024877kHz (Note25) 14.7kHz 6 0 1 1 0 14.69984kHz (Note25) 22.05kHz 7 0 1 1 1 22.04975kHz (Note25) 32kHz 10 1 0 1 0 48kHz 11 1 0 1 1 29.4kHz 14 1 1 1 0 29.39967kHz (Note25) 44.1kHz 15 1 1 1 1 Default 44.0995kHz (Note25) Others Others N/A Note 25. In case of PLL3-0 bits = "1001" Table 5. Setting of Sampling Frequency at PMPLL bit = "1" and Reference Clock=MCKI pin
PLL Lock Time (max) 80ms 2ms 4ms 2ms 4ms 40ms 40ms 40ms 40ms 40ms 40ms 40ms 40ms 60ms 60ms
MS0569-E-01 - 22 -
2006/12
ASAHI KASEI
[AK5700]
When PLL reference clock input is EXLRCK or EXBCLK pin, the sampling frequency is selected by FS3 and FS2 bits (See Table 6). FS3 bit FS2 bit Sampling Frequency Mode FS1 bit FS0 bit Range 0 0 Don't care Don't care 7.35kHz fs 12kHz 0 0 1 Don't care Don't care 1 12kHz < fs 24kHz 1 Don't care Don't care Don't care 2 24kHz < fs 48kHz Default Others Others N/A Table 6. Setting of Sampling Frequency at PMPLL bit = "1" and Reference=EXLRCK/EXBCLK
PLL Unlock State
1) PLL Master Mode (PMPLL bit = "1", M/S bit = "1") In this mode, LRCK and BCLK pins go to "L" and irregular frequency clock is output from MCKO pins at MCKO bit is "1" before the PLL goes to lock state after PMPLL bit = "0" "1". If MCKO bit is "0", MCKO pin goes to "L" (see Table 7). In DSP Mode 0, BCLK and LRCK start to output corresponding to Ach data after PLL goes to lock state by setting PMPLL bit = "0" "1". When MSBS and BCKP bits are "01" or "10" in DSP Mode 0, BCLK "H" time of the first pulse becomes shorter by 1/(256fs) than "H" time except for the first pulse. When sampling frequency is changed, BCLK and LRCK pins do not output irregular frequency clocks but go to "L" by setting PMPLL bit to "0". MCKO pin BCLK pin MCKO bit = "0" MCKO bit = "1" After that PMPLL bit "0" "1" "L" Output Invalid "L" Output PLL Unlock (except above case) "L" Output Invalid Invalid PLL Lock "L" Output See Table 9 See Table 10 Table 7. Clock Operation at PLL Master Mode (PMPLL bit = "1", M/S bit = "1") PLL State 2) PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = "0" "1". After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC outputs invalid data when the PLL is unlocked. MCKO pin MCKO bit = "0" MCKO bit = "1" After that PMPLL bit "0" "1" "L" Output Invalid PLL Unlock (except above case) "L" Output Invalid PLL Lock "L" Output See Table 9 Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = "1", M/S bit = "0") PLL State LRCK pin "L" Output Invalid 1fs Output
MS0569-E-01 - 23 -
2006/12
ASAHI KASEI
[AK5700]
PLL Master Mode (PMPLL bit = "1", M/S bit = "1")
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 13.5MHz, 19.2MHz, 24MHz, 26MHz or 27MHz) is input to MCKI pin, the MCKO, BCLK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is selected by PS1-0 bits (see Table 9) and the output is enabled by MCKO bit. The BCLK output frequency is selected among 32fs or 64fs, by BCKO1-0 bits (see Table 10).
11.2896MHz, 12MHz, 12.288MHz, 13MHz 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
AK5700
MCKI MCKO BCLK LRCK SDTO 256fs/128fs/64fs/32fs 32fs, 64fs 1fs
DSP or P
MCLK BCLK LRCK SDTI
Figure 19. PLL Master Mode Mode PS1 bit PS0 bit MCKO pin 0 0 0 256fs Default 1 0 1 128fs 2 1 0 64fs 3 1 1 32fs Table 9. MCKO Output Frequency (PLL Mode, MCKO bit = "1") BCKO1 bit BCLK Output Frequency 0 0 N/A 0 1 32fs Default 1 0 64fs 1 1 N/A Table 10. BCLK Output Frequency at Master Mode BCKO0 bit
MS0569-E-01 - 24 -
2006/12
ASAHI KASEI
[AK5700]
PLL Slave Mode (PMPLL bit = "1", M/S bit = "0")
A reference clock of PLL is selected among the input clocks to MCKI, EXBCLK or EXLRCK pin. The required clock to the AK5700 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (see Table 4). a) PLL reference clock: MCKI pin EXBCLK and EXLRCK inputs should be synchronized with MCKO output. The phase between MCKO and EXLRCK dose not matter. MCKO pin outputs the frequency selected by PS1-0 bits (see Table 9) and the output is enabled by MCKO bit. Sampling frequency can be selected by FS3-0 bits (see Table 5).
11.2896MHz, 12MHz, 12.288MHz, 13MHz 13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
AK5700
MCKI MCKO EXBCLK EXLRCK SDTO 256fs/128fs/64fs/32fs 32fs 1fs
DSP or P
MCLK BCLK LRCK SDTI
Figure 20. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin) The external clocks (MCKI, EXBCLK and EXLRCK) should always be present whenever the ADC is in operation (PMADC bit = "1"). If these clocks are not provided, the AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC should be in the power-down mode (PMADC bit = "0"). b) PLL reference clock: EXBCLK or EXLRCK pin Sampling frequency corresponds to 7.35kHz to 48kHz by changing FS3-0 bits (see Table 6).
AK5700 DSP or P
MCKI EXBCLK EXLRCK SDTO 32fs, 64fs 1fs BCLK LRCK SDTI
Figure 21. PLL Slave Mode 2 (PLL Reference Clock: EXLRCK or EXBCLK pin)
MS0569-E-01 - 25 -
2006/12
ASAHI KASEI
[AK5700]
EXT Slave Mode (PMPLL bit = "0", M/S bit = "0")
When PMPLL bit is "0", the AK5700 becomes EXT mode. Master clock is input from MCKI pin, the internal PLL circuit is not operated. This mode is compatible with I/F of the normal audio CODEC. The clocks required to operate are MCKI (256fs, 512fs or 1024fs), EXLRCK (fs) and EXBCLK (32fs). The master clock (MCKI) should be synchronized with EXLRCK. The phase between these clocks does not matter. The input frequency of MCKI is selected by FS1-0 bits (see Table 11). Mode 0 1 2 3 MCKI Input Sampling Frequency Frequency Range Don't care 0 0 256fs 7.35kHz 48kHz Don't care 0 1 1024fs 7.35kHz 13kHz Don't care 1 0 512fs 7.35kHz 26kHz Don't care 1 1 256fs 7.35kHz 48kHz Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = "0", M/S bit = "0") FS3-2 bits FS1 bit FS0 bit
Default
The external clocks (MCKI, EXBCLK and EXLRCK) should always be present whenever the ADC is in operation (PMADC bit = "1"). If these clocks are not provided, the AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If the external clocks are not present, the ADC should be in the power-down mode (PMADC bit = "0").
AK5700
MCKO 256fs, 512fs or 1024fs MCKI EXBCLK EXLRCK SDTO 32fs 1fs MCLK BCLK LRCK SDTI
DSP or P
Figure 22. EXT Slave Mode
MS0569-E-01 - 26 -
2006/12
ASAHI KASEI
[AK5700]
EXT Master Mode (PMPLL bit = "0", M/S bit = "1", TE3-0 bits = "0101", TMASTER bit = "1")
The AK5700 becomes EXT Master Mode by setting as Figure 45. Master clock is input from MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of MCKI is selected by FS1-0 bits (see Table 12). Mode 0 1 2 3 FS3-2 bits
Don't care Don't care Don't care Don't care
MCKI Input Sampling Frequency Frequency Range 0 0 256fs 7.35kHz 48kHz 0 1 1024fs 7.35kHz 13kHz 1 0 512fs 7.35kHz 26kHz 1 1 256fs 7.35kHz 48kHz Table 12. MCKI Frequency at EXT Master Mode FS1 bit FS0 bit
Default
MCKI should always be present whenever the ADC is in operation (PMADC bit = "1"). If MCKI is not provided, the AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic internally. If MCKI is not present, the ADC should be in the power-down mode (PMADC bits = "0").
AK5700
MCKO 256fs, 512fs or 1024fs MCKI BCLK LRCK SDTO 32fs or 64fs 1fs MCLK BCLK LRCK SDTI
DSP or P
Figure 23. EXT Master Mode BCKO1 bit BCLK Output Frequency 0 0 N/A 0 1 32fs Default 1 0 64fs 1 1 N/A Table 13. BCLK Output Frequency at Master Mode BCKO0 bit
MS0569-E-01 - 27 -
2006/12
ASAHI KASEI
[AK5700]
Bypass Mode
When THR bit = "1", M/S bit = "0" and PMADC bit = "0" input clocks and data of EXLRCK, EXBCLK and EXSDTI pins are bypassed to LRCK, BCLK and SDTO pins, respectively. When THR bit = "1", M/S bit = "0" and PMADC bit = "1" input clocks of EXLRCK and EXBCLK pins are bypassed to LRCK and BCLK pins, and ADC data is output from SDTO pin.
THR bit 0
M/S bit 0 1 0
1 1
PMADC bit 0 1 0 1 0 1 0 1
BCLK/LRCK SDTO "L" "L" "L" ADC data Output "L" Output ADC data EXBCLK/EXLRCK EXSDTI EXBCLK/EXLRCK ADC data N/A N/A Output ADC data Table 14. Bypass Mode Select
Mode Power down Slave mode Power down Master mode Bypass mode Slave & Bypass N/A Master mode
Figure Default
Figure 24 Figure 25
DSP or P
32fs BCLK LRCK SDTI 1fs
AK5700
32fs BCLK LRCK SDTO EXBCLK EXLRCK EXSDTI 1fs
DSP or P
BCLK LRCK SDTO
Figure 24. Bypass Mode
DSP or P
32fs BCLK LRCK SDTI 1fs
AK5700
32fs BCLK LRCK SDTO EXBCLK EXLRCK AIN 1fs
DSP or P
BCLK LRCK
Analog In
Figure 25. Slave & Bypass Mode
MS0569-E-01 - 28 -
2006/12
ASAHI KASEI
[AK5700]
Audio Interface Format
Fore types of data format are available and are selected by setting the DIF1-0 bits (see Table 15). In all modes, the serial data is MSB first, 2's complement format. Audio interface formats can be used in both master and slave modes. LRCK, BCLK and SDTO pins are used in master mode. EXLRCK, EXBCLK and SDTO pins are used in slave mode. In modes 2 and 3, the SDTO is clocked out on the falling edge ("") of BCLK/EXBCLK. SDTO pin outputs same data two times in one period of EXLRCK/LRCK. Mode 0 1 2 3 DIF1 bit 0 0 1 1 DIF0 bit 0 1 0 1 SDTO BCLK, EXBCLK DSP Mode 0 32fs Reserved MSB justified 32fs I2S compatible 32fs Table 15. Audio Interface Format Figure See Table 16 Figure 30 Figure 31
Default
In Mode 0 (DSP mode 0), the audio I/F timing is changed by BCKP and MSBS bits. When BCKP bit is "0", SDTO data is output by rising edge ("") of BCLK/EXBCLK. When BCKP bit is "1", SDTO data is output by falling edge ("") of BCLK/EXBCLK. MSB data position of SDTO can be shifted by MSBS bit. The shifted period is a half of BCLK/EXBCLK. DIF1 DIF0 MSBS 0 0 0 0 1 BCKP 0 1 0 Audio Interface Format MSB of SDTO is output by the rising edge ("") of the first BCLK/EXBCLK after the rising edge ("") of LRCK/EXLRCK (Figure 26). MSB of SDTO is output by the falling edge ("") of the first BCLK/EXBCLK after the rising edge ("") of LRCK/EXLRCK (Figure 27). MSB of SDTO is output by next rising edge ("") of the falling edge ("") of the first BCLK/EXBCLK after the rising edge ("") of LRCK/EXLRCK (Figure 28). MSB of SDTO is output by next falling edge ("") of the rising edge ("") of the first BCLK/EXBCLK after the rising edge ("") of LRCK/EXLRCK (Figure 29). Table 16. Audio Interface Format in Mode 0
1
1
If 16-bit data that ADC outputs is converted to 8-bit data by removing LSB 8-bit, "-1" at 16bit data is converted to "-1" at 8-bit data. And when the DAC playbacks this 8-bit data, "-1" at 8-bit data will be converted to "-256" at 16-bit data and this is a large offset. This offset can be removed by adding the offset of "128" to 16-bit data before converting to 8-bit data.
MS0569-E-01 - 29 -
2006/12
ASAHI KASEI
[AK5700]
EXLRCK / LRCK (M/S=0) EXLRCK / LRCK (M/S=1)
15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 14 15 16 17 18 13 30 31
EXBCLK(32fs) BCLK(32fs)
SDTO(o)
15 14
8
2
1
0
15 14
2
1
0
15 14
8
2
1
0
15 14
2
1
0
1/fs 15:MSB, 0:LSB
1/fs
Figure 26. Mode 0 Timing (BCKP = "0", MSBS = "0", M/S = "0" or "1")
EXLRCK / LRCK (M/S=0) EXLRCK / LRCK (M/S=1)
15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 14 15 16 17 18 13 30 31
EXBCLK(32fs) BCLK(32fs)
SDTO(o)
15 14
8
2
1
0
15 14
2
1
0
15 14
8
2
1
0
15 14
2
1
0
1/fs 15:MSB, 0:LSB
1/fs
Figure 27. Mode 0 Timing (BCKP = "1", MSBS = "0", M/S = "0" or "1")
EXLRCK / LRCK (M/S=0) EXLRCK / LRCK (M/S=1)
15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 14 15 16 17 18 13 30 31
EXBCLK(32fs) BCLK(32fs)
SDTO(o)
15 14
8
2
1
0
15 14
2
1
0
15 14
8
2
1
0
15 14
2
1
0
1/fs 15:MSB, 0:LSB
1/fs
Figure 28. Mode 0 Timing (BCKP = "0", MSBS = "1", M/S = "0" or "1")
EXLRCK / LRCK (M/S=0) EXLRCK / LRCK (M/S=1)
15 0 1 2 8 14 15 16 17 18 29 30 31 0 1 2 8 14 15 16 17 18 13 30 31
EXBCLK(32fs) BCLK(32fs)
SDTO(o)
15 14
8
2
1
0
15 14
2
1
0
15 14
8
2
1
0
15 14
2
1
0
1/fs 15:MSB, 0:LSB
1/fs
Figure 29. Mode 0 Timing (BCKP = "1", MSBS = "1", M/S = "0" or "1") Note : The data from 0 to 15 bits is the same as from 16 to 31 bits at the Figure 26, Figure 27, Figure 28, Figure 29
MS0569-E-01 - 30 -
2006/12
ASAHI KASEI
[AK5700]
EXLRCK LRCK
0 1 2 3 8 9 10 11 12 13 14 15 0 1 2 3 8 9 10 11 12 13 14 15 0 1
EXBCLK(32fs) BCLK(32fs)
SDTO(o)
0
15 14 13
1 2 3
8
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15 14 13
1 2 3
8
7
14
6
15
5
16
4
17
3
18
2
1
31
0
0
15
1
EXBCLK(64fs) BCLK(64fs)
SDTO(o)
15 14 13
13 2
1
0
15 14 13
1 2
2
1
0
15
15:MSB, 0:LSB 1/fs
Figure 30. Mode 2 Timing (MSB justified, M/S = "0" or "1")
EXLRCK LRCK
EXBCLK(32fs) BCLK(32fs)
0
1
2
3
4
9
10
11
12
13
14
15
0
1
2
3
4
9
10
11
12
13
14
15
0
1
SDTO(o)
0
0
1
15
2
14 13
3 4
7
14
7
15
6
16
5
17
4
18
3
2
31
1
0
0
1
15 14 13
2 3 4
7
14
7
15
6
16
5
17
4
18
3
2
31
1
0
0
1
EXBCLK(64fs) BCLK(64fs)
SDTO(o)
15 14 13
2
1
0
15 14 13
2
2
1
0
15:MSB, 0:LSB 1/fs
Figure 31. Mode 3 Timing (I2S, M/S = "0" or "1") Note : The data from 0 to 15 bits is the same as when LRCK is "H" or "L" at the Figure 30, Figure 31
MS0569-E-01 - 31 -
2006/12
ASAHI KASEI
[AK5700]
Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is selected by HPF1-0 bits (see Table 17) and scales with sampling rate (fs). The default value is 3.4Hz (@fs=44.1kHz). HPF1 bit 0 0 1 1 HPF0 bit 0 1 0 1 fc fs=44.1kHz fs=22.05kHz 3.4Hz 1.7Hz 6.8Hz 3.4Hz 13.6Hz 6.8Hz N/A N/A Table 17. Digital HPF Cut-off Frequency
fs=11.025kHz 0.85Hz 1.7Hz 3.4Hz N/A
Default
MIC/LINE Input Selector
The AK5700 has input selector. When MDIF1 bit is "0", AIN bit selects AIN1or AIN2. When MDIF1 bit is "1", AIN1pin become AIN+ pin . In this case, full-differential input is available (Figure 33). When full-differential input is used, the signal should not be input to the pins marked by "X" in Table 19.
MDIF1 bit
0
1
Ach AIN1 0 AIN1 AIN2 1 AIN2 0 AIN1 1 N/A N/A x AIN+/- x AIN+/- Table 18. MIC/Line In Path Select
AIN bit
Default
Pin AIN1 MDIF1 bit AIN2 AIN1- AIN1+ 0 O O 1 O X O Table 19. Handling of MIC/Line Input Pins ("-": N/A; "X": Signal should not be input.)
AK5700
AIN1/AIN+ pin AIN bit
Register
ADC AIN- pin MDIF1 bit
AIN2 pin
Figure 32. Mic/Line Input Selector
MS0569-E-01 - 32 -
2006/12
ASAHI KASEI
[AK5700]
AK5700 MPWR pin 1k AIN+ pin AIN- pin 1k
MIC-Amp
Figure 33. Connection Example for Full-differential Mic Input (MDIF1bit = "1")
MIC Gain Amplifier
The AK5700 has a gain amplifier for microphone input. The gain of MIC-Amp is selected by the MGAIN1-0 bits (see Table 20). The typical input impedance is 60k(typ)@MGAIN1-0 bits = "00" or 30k(typ)@MGAIN1-0 bits = "01" or "10". MGAIN1 bit 0 0 1 1 MGAIN0 bit Input Gain 0 0dB 1 +15dB 0 +30dB 1 N/A Table 20. Mic Input Gain
Default
MIC Power
When PMMP bit = "1", the MPWR pin supplies power for the microphone. This output voltage is typically 0.75 x AVDD and the load resistance is minimum 1.0k. In case of using two sets of mono mic, the load resistance is minimum 2.0k for each channel. No capacitor must not be connected directly to MPWR pin (see Figure 34). PMMP bit MPWR pin 0 Hi-Z 1 Output Table 21. MIC Power
Default
MIC Power MPWR pin
2k
2k
Microphone AIN1 pin
Microphone AIN2 pin
Figure 34. MIC Block Circuit
MS0569-E-01 - 33 -
2006/12
ASAHI KASEI
[AK5700]
ALC Operation
The ALC (Automatic Level Control) is done by ALC block when ALC bit is "1". 1. ALC Limiter Operation
During the ALC limiter operation, when the output exceeds the ALC limiter detection level (Table 22), the IVL value is attenuated automatically by the amount defined by the ALC limiter ATT step (Table 23). When ZELMN bit = "0" (zero cross detection is enabled), the IVL value is changed by ALC limiter operation at the individual zero crossing point of zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both ALC limiter and recovery operation (Table 24). When ZELMN bit = "1" (zero cross detection is disabled), IVL value is immediately (period: 1/fs) changed by ALC limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMAT1-0 bits. The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level (Table 22) or less. After completing the attenuation operation, unless ALC bit is changed to "0", the operation repeats when the input signal level exceeds LMTH1-0 bits. LMTH1 0 0 1 1 LMTH0 ALC Limier Detection Level ALC Recovery Waiting Counter Reset Level 0 ALC Output -2.5dBFS -2.5dBFS > ALC Output -4.1dBFS 1 ALC Output -4.1dBFS -4.1dBFS > ALC Output -6.0dBFS 0 ALC Output -6.0dBFS -6.0dBFS > ALC Output -8.5dBFS 1 ALC Output -8.5dBFS -8.5dBFS > ALC Output -12dBFS Table 22. ALC Limiter Detection Level / Recovery Counter Reset Level ZELMN 0 1 LMAT1 0 0 1 1 x LMAT0 ALC Limiter ATT Step 0 1 step 0.375dB 1 2 step 0.750dB 0 4 step 1.500dB 1 8 step 3.000dB x 1step 0.375dB Table 23. ALC Limiter ATT Step
Default
Default
ZTM1 0 0 1 1
ZTM0 0 1 0 1
Zero Crossing Timeout Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 24. ALC Zero Crossing Timeout Period
Default
MS0569-E-01 - 34 -
2006/12
ASAHI KASEI
[AK5700]
2.
ALC Recovery Operation
The ALC recovery operation waits for the WTM1-0 bits (Table 25) to be set after completing the ALC limiter operation. If the input signal does not exceed "ALC recovery waiting counter reset level" (Table 22) during the wait time, the ALC recovery operation is done. The IVL value is automatically incremented by RGAIN1-0 bits (Table 26) up to the set reference level (Table 27) with zero crossing detection which timeout period is set by ZTM1-0 bits (Table 24). The ALC recovery operation is done at a period set by WTM1-0 bits. If ZTM1-0 is longer than WTM1-0 and no zero crossing occurs, the ALC recovery operation is done at a period set by ZTM1-0 bits. For example, when the current IVOL value is 30H and RGAIN1-0 bits are set to "01", IVOL is changed to 32H by the auto limiter operation and then the input signal level is gained by 0.75dB (=0.375dB x 2). When the IVOL value exceeds the reference level (REF7-0), the IVOL values are not increased. When "ALC recovery waiting counter reset level (LMTH1-0) Output Signal < ALC limiter detection level (LMTH1-0)" during the ALC recovery operation, the waiting timer of ALC recovery operation is reset. When "ALC recovery waiting counter reset level (LMTH1-0) > Output Signal", the waiting timer of ALC recovery operation starts. The ALC operation corresponds to the impulse noise. When the impulse noise is input, the ALC recovery operation becomes faster than a normal recovery operation. When large noise is input to microphone instantaneously, the quality of small level in the large noise can be improved by this fast recovery operation. WTM1 0 0 1 1 WTM0 0 1 0 1 ALC Recovery Operation Waiting Period 8kHz 16kHz 44.1kHz 128/fs 16ms 8ms 2.9ms 256/fs 32ms 16ms 5.8ms 512/fs 64ms 32ms 11.6ms 1024/fs 128ms 64ms 23.2ms Table 25. ALC Recovery Operation Waiting Period RGAIN0 GAIN STEP 0 1 step 0.375dB 1 2 step 0.750dB 0 3 step 1.125dB 1 4 step 1.500dB Table 26. ALC Recovery GAIN Step
Default
RGAIN1 0 0 1 1
Default
REF7-0 GAIN(dB) Step F1H +36.0 F0H +35.625 EFH +35.25 : : E2H +30.375 0.375dB E1H +30.0 Default E0H +29.625 : : 03H -53.25 02H -53.625 01H -54.0 00H MUTE Table 27. Reference Level at ALC Recovery operation
MS0569-E-01 - 35 -
2006/12
ASAHI KASEI
[AK5700]
3.
Example of ALC Operation
Table 28 shows the examples of the ALC setting for mic recording. Register Name LMTH ZELMN ZTM1-0 WTM1-0 REF7-0 IVL7-0 LMAT1-0 RGAIN1-0 ALC Comment fs=8kHz Operation -4.1dBFS Enable 16ms fs=44.1kHz Operation -4.1dBFS Enable 11.6ms 11.6ms +30dB 0dB 1 step 1 step Enable
Limiter detection Level Limiter zero crossing detection Zero crossing timeout period Recovery waiting period *WTM1-0 bits should be the same data 00 16ms as ZTM1-0 bits Maximum gain at recovery operation E1H +30dB Gain of IVOL 91H 0dB Limiter ATT step 00 1 step Recovery GAIN step 00 1 step ALC enable 1 Enable Table 28. Example of the ALC setting
Data 01 0 00
Data 01 0 10 10 E1H 91H 00 00 1
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC operation is finished by ALC bit = "0" or PMADC bit = "0". * LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN
Example: Limiter = Zero crossing Enable Recovery Cycle = 16ms@8kHz Limiter and Recovery Step = 1 Maximum Gain = +30.0dB Limiter Detection Level = -4.1dBFS Manual Mode * The value of IVOL should be the same or smaller than REF's WR (ZTM1-0, WTM1-0) (2) Addr=1AH, Data=00H ALC bit = "1"
WR (IVL7-0)
(1) Addr=18H, Data=91H
WR (REF7-0)
(3) Addr=1BH, Data=E1H
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC= "1")
(4) Addr=1CH, Data=81H
ALC Operation
Note : WR : Write Figure 35. Registers set-up sequence at ALC operation
MS0569-E-01 - 36 -
2006/12
ASAHI KASEI
[AK5700]
Input Digital Volume (Manual Mode)
The input digital volume becomes a manual mode when ALC bit is "0". This mode is used in the case shown below. 1. 2. 3. After exiting reset state, set-up the registers for the ALC operation (ZTM1-0, LMTH and etc) When the registers for the ALC operation (Limiter period, Recovery period and etc) are changed. For example; when the change of the sampling frequency. When IVOL is used as a manual volume.
IVL7-0 bits set the gain of the volume control (Table 29). The IVOL value is changed at zero crossing or timeout. Zero crossing timeout period is set by ZTM1-0 bits. If IVL7-0 bits are written during PMADC bit = "0", IVOL operation starts with the written values at the end of the ADC initialization cycle after PMADC bit is changed to "1". IVL7-0 F1H F0H EFH : 92H 91H 90H : 03H 02H 01H 00H GAIN (dB) Step
+36.0 +35.625 +35.25 : +0.375 0.375dB 0.0 -0.375 : -53.25 -53.625 -54 MUTE Table 29. Input Digital Volume Setting
Default
MS0569-E-01 - 37 -
2006/12
ASAHI KASEI
[AK5700]
When writing to the IVL7-0 bits continuouslly, the control register should be written by an interval more than zero crossing timeout. If not, IVL is not changed since zero crossing counter is reset at every write operation. If the same register value as the previous write operation is written to IVL, this write operation is ignored and zero crossing counter is not reset. Therefore, IVL can be written by an interval less than zero crossing timeout.
ALC bit
ALC Status
Disable
Enable
Disable
IVL7-0 bits (1) Internal IVL E1H(+30dB)
E1H(+30dB) (2) E1(+30dB) --> F1(+36dB) E1(+30dB)
Figure 36. IVOL value during ALC operation (1) The wait time from ALC bit = "1" to ALC operation start by IVL7-0 bits is at most recovery time (WTM1-0 bits) plus zerocross timeout period (ZTM1-0 bits). (2) Writing to IVL register (18H) is ignored during ALC operation. After ALC is disabled, the IVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be set to "1" by an interval more than zero crossing timeout period after ALC bit = "0".
System Reset
Upon power-up, the AK5700 should be reset by bringing the PDN pin = "L". This ensures that all internal registers reset to their initial values. The ADC enters an initialization cycle that starts when the PMADC bit is changed from "0" to "1". The initialization cycle time is 3088/fs=70.0ms@fs=44.1kHz when HPF1-0 bits are "00" (see Table 30). During the initialization cycle, the ADC digital data outputs of both channels are forced to a 2's complement, "0". The ADC output reflects the analog input signal after the initialization cycle is complete. HPF1 bit 0 0 1 1 HPF0 bit 0 1 0 1 Init Cycle fs=44.1kHz fs=22.05kHz 70.0ms 140.0ms 35.2ms 17.8ms 70.4ms
(Recommendation)
Cycle 3088/fs 1552/fs 784/fs
fs=11.025kHz 280.1ms 140.8ms 71.1ms
(Recommendation)
(Recommendation)
Default
35.6ms
N/A N/A N/A Table 30. ADC Initialization Cycle
N/A
MS0569-E-01 - 38 -
2006/12
ASAHI KASEI
[AK5700]
Serial Control Interface
Internal registers may be written by using the 3-wire P interface pins (CSN, CCLK and CDTI). CSP pin selects the polarity of CSN pin and chip address. 1) CSP pin = "L" The data on this interface consists of a 2-bit Chip address (Fixed to "10"), Read/Write (Fixed to "1"), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge ("") of CCLK. Address and data are latched on the 16th CCLK rising edge ("") after CSN falling edge(""). Clock speed of CCLK is 7MHz (max). The value of internal registers are initialized by PDN pin = "L".
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 "1" "0" "1"
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (C1 = "1", C0 = "0"); Fixed to "10" READ/WRITE ("1": WRITE, "0": READ); Fixed to "1" Register Address Control data
Figure 37. Serial Control I/F Timing (CSP pin = "L") 2) CSP pin = "H" The data on this interface consists of a 2-bit Chip address (Fixed to "01"), Read/Write (Fixed to "1"), Register address (MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge ("") of CCLK. Address and data are latched on the 16th CCLK rising edge ("") after CSN rising edge(""). Clock speed of CCLK is 7MHz (max). The value of internal registers are initialized by PDN pin = "L".
CSN
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CCLK CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 "0" "1" "1"
C1-C0: R/W: A4-A0: D7-D0:
Chip Address (C1 = "0", C0 = "1"); Fixed to "01" READ/WRITE ("1": WRITE, "0": READ); Fixed to "1" Register Address Control data
Figure 38. Serial Control I/F Timing (CSP pin = "H")
MS0569-E-01 - 39 -
2006/12
ASAHI KASEI
[AK5700]
Register Map
Addr 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH Register Name Power Management PLL Control Signal Select Mic Gain Control Audio Format Select fs Select Clock Output Select Reserved Input Volume Control Reserved Timer Select ALC Mode Control 1 ALC Mode Control 2 Mode Control 1 Mode Control 2 D7 0 0 0 0 0 HPF1 0 0 IVL7 1 0 REF7 ALC TE3 0 D6 0 0 0 0 0 HPF0 0 0 IVL6 0 0 REF6 ZELMN TE2 0 D5 0 PLL3 0 0 1 BCKO1 0 0 IVL5 0 0 REF5 LMAT1 TE1 0 D4 0 PLL2 PMMP 0 0 BCKO0 0 0 IVL4 1 0 REF4 LMAT0 TE0 0 D3 0 PLL1 0 0 MSBS FS3 THR 0 IVL3 0 ZTM1 REF3 RGAIN1 0 0 D2
PMVCM
PLL0 MDIF1 0 BCKP FS2 MCKO 0 IVL2 0 ZTM0 REF2 RGAIN0 0 0
D1 0 M/S 0
MGAIN1
D0 PMADC PMPLL AIN
MGAIN0
DIF1 FS1 PS1 0 IVL1 0 WTM1 REF1 LMTH1 0
TMASTER
DIF0 FS0 PS0 1 IVL0 1 WTM0 REF0 LMTH0 0 0
Note 26. PDN pin = "L" resets the registers to their default values. Note 27. "0" must be sent to the register written as "0" and "1" must be sent to the register written as "1". For addresses except for 10H to 1EH, data must not be written.
MS0569-E-01 - 40 -
2006/12
ASAHI KASEI
[AK5700]
Register Definitions
Addr 10H Register Name Power Management Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 PMVCM 0 D1 0 0 D0 PMADC 0
PMADC: MIC-Amp and ADC Power Management 0: Power down (Default) 1: Power up When the PMADC bit is changed from "0" to "1", the initialization cycle (3088/fs=70.0ms@fs= 44.1kHz, HPF1-0 bits = "00") starts. After initializing, digital data of the ADC is output. PMVCM: VCOM Power Management 0: Power down (Default) 1: Power up When any blocks are powered-up, the PMVCM bit must be set to "1". PMVCM bit can be set to "0" only when PMADC=PMPLL=PMMP=MCKO bits = "0". Each block can be powered-down respectively by writing "0" in each bit of this address. When the PDN pin is "L", all blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value. When PMVCM, PMADC, PMPLL and MCKO bits are "0", all blocks are powered-down. The register values remain unchanged. Power supply current is 20A(typ) in this case. For fully shut down (typ. 1A), PDN pin should be "L". When the ADC is not used, external clocks may not be present. When ADC is used, external clocks must always be present.
Addr 11H
Register Name PLL Control Default
D7 0 0
D6 0 0
D5 PLL3 1
D4 PLL2 0
D3 PLL1 0
D2 PLL0 1
D1 M/S 0
D0 PMPLL 0
PMPLL: PLL Power Management 0: EXT Mode and Power Down (Default) 1: PLL Mode and Power up M/S: Master / Slave Mode Select 0: Slave Mode (Default) 1: Master Mode PLL3-0: PLL Reference Clock Select (See Table 4) Default: "1001"(MCKI pin=12MHz)
MS0569-E-01 - 41 -
2006/12
ASAHI KASEI
[AK5700]
Addr 12H
Register Name Signal Select Default
D7 0 0
D6 0 0
D5 0 0
D4 PMMP 0
D3 0 0
D2 MDIF1 0
D1 0 0
D0 AIN 0
AIN: ADC Input Source Select 0: AIN1 pin (Default) 1: AIN2 pin MDIF1: ADC Input Type Select 0: Single-ended input (AIN1/AIN2 pin: Default) 1: Full-differential input (AIN+/AIN- pin) PMMP: MPWR pin Power Management 0: Power down: Hi-Z (Default) 1: Power up
Addr 13H Register Name Mic Gain Control Default D7 0 0 D6 0 0 D5 0 0 D4 0 0 D3 0 0 D2 0 0 D1
MGAIN1
D0
MGAIN0
0
1
MGAIN1-0: MIC-Amp Gain Control (See Table 20) Default: "01"(+15dB)
Addr 14H Register Name Audio Format Select Default D7 0 0 D6 0 0 D5 1 1 D4 0 0 D3 MSBS 0 D2 BCKP 0 D1 DIF1 1 D0 DIF0 1
DIF1-0: Audio Interface Format (See Table 15) Default: "11" (I2S) BCKP: BCLK/EXBCLK Polarity at DSP Mode (See Table 16) "0": SDTO is output by the rising edge ("") of BCLK/EXBCLK. (Default) "1": SDTO is output by the falling edge ("") of BCLK/EXBCLK. MSBS: LRCK/EXLRCK Polarity at DSP Mode (See Table 16) "0": The rising edge ("") of LRCK/EXLRCK is half clock of BCLK/EXBCLK before the channel change. (Default) "1": The rising edge ("") of LRCK/EXLRCK is one clock of BCLK/EXBCLK before the channel change.
MS0569-E-01 - 42 -
2006/12
ASAHI KASEI
[AK5700]
Addr 15H
Register Name fs Select Default
D7 HPF1 0
D6 HPF0 0
D5 BCKO1 0
D4 BCKO0 1
D3 FS3 1
D2 FS2 1
D1 FS1 1
D0 FS0 1
FS3-0: Sampling Frequency Select (See Table 5 and Table 6) and MCKI Frequency Select (See Table 11) Default: "1111" (44.1kHz) FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode. BCKO1-0: BCLK Output Frequency Select at Master Mode (See Table 10) Default: "01" (32fs) HPF1-0: Offset Cancel HPF Cut-off Frequency and ADC Initialization Cycle (See Table 17, Table 30) Default: "00" (fc=3.4Hz@fs=44.1kHz, Init Cycle=3088/fs)
Addr 16H
Register Name Clock Output Select Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 THR 0
D2 MCKO 0
D1 PS1 0
D0 PS0 0
PS1-0: MCKO Output Frequency Select (See Table 9) Default: "00"(256fs) MCKO: Master Clock Output Enable 0: Disable: MCKO pin = "L" (Default) 1: Enable: Output frequency is selected by PS1-0 bits. THR: Bypass Mode (Table 14) 0: OFF (Default) 1: ON
Addr 18H
Register Name Input Volume Control Default
D7 IVL7 1
D6 IVL6 0
D5 IVL5 0
D4 IVL4 1
D3 IVL3 0
D2 IVL2 0
D1 IVL1 0
D0 IVL0 1
IVL7-0: Input Digital Volume; 0.375dB step, 242 Level (See Table 29) Default: "91H" (0dB)
MS0569-E-01 - 43 -
2006/12
ASAHI KASEI
[AK5700]
Addr 1AH
Register Name Timer Select Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 ZTM1 0
D2 ZTM0 0
D1 WTM1 0
D0 WTM0 0
WTM1-0: ALC Recovery Waiting Period (see Table 25) Default: "00" (128/fs) ZTM1-0: ALC Limiter/Recovery Operation Zero Crossing Timeout Period (see Table 24) Default: "00" (128/fs)
Addr 1BH
Register Name ALC Mode Control 1 Default
D7 REF7 1
D6 REF6 1
D5 REF5 1
D4 REF4 0
D3 REF3 0
D2 REF2 0
D1 REF1 0
D0 REF0 1
REF7-0: Reference Value at ALC Recovery Operation. 0.375dB step, 242 Level (See Table 27) Default: "E1H" (+30.0dB)
Addr 1CH
Register Name ALC Mode Control 2 Default
D7 ALC 0
D6 ZELMN 0
D5 LMAT1 0
D4 LMAT0 0
D3
RGAIN1
D2
RGAIN0
0
0
D1 LMTH1 0
D0 LMTH0 0
LMTH1-0: ALC Limiter Detection Level / Recovery Counter Reset Level (see Table 22) Default: "00" RGAIN1-0: ALC Recovery GAIN Step (see Table 26) Default: "00" LMAT1-0: ALC Limiter ATT Step (see Table 23) Default: "00" ZELMN: Zero Crossing Detection Enable at ALC Limiter Operation 0: Enable (Default) 1: Disable ALC: ALC Enable 0: ALC Disable (Default) 1: ALC Enable
MS0569-E-01 - 44 -
2006/12
ASAHI KASEI
[AK5700]
Addr 1DH
Register Name Mode Control 1 Default
D7 TE3 1
D6 TE2 0
D5 TE1 1
D4 TE0 0
D3 0 0
D2 0 0
D1 0 0
D0 0 0
TE3-0: EXT Master Mode Enable When TE3-0 bits is set to "0101", the write operation to addr=1EH is enabled. TE3-0 bits should be set to "1010" except for EXT Master Mode. TE3-0 bits must not be set to the value except for "1010" and "0101". Default: "1010"
Addr 1EH
Register Name Mode Control 2 Default
D7 0 0
D6 0 0
D5 0 0
D4 0 0
D3 0 0
D2 0 0
D1
TMASTER
0
D0 0 0
TMASTER: EXT Master Mode The write operation to TMASTER bit is enabled when TE3-0 bits = "0101". 0: Except EXT Master Mode (Default) 1: EXT Master Mode
MS0569-E-01 - 45 -
2006/12
ASAHI KASEI
[AK5700]
SYSTEM DESIGN
Figure 39 and Figure 40 shows the system connection diagram for the AK5700. An evaluation board [AKD5700] is available which demonstrates the optimum layout, power supply arrangements and measurement results.
P
18
17
16
15
14 MCKI
EXBCLK 13
CCLK
2.2k
2.2k
CDTI
PDN
CSN
DSP
19 MPWR 20 TEST External MIC 1u 21 AIN2 22 AIN Internal MIC 1u Rp Cp 23 AIN1 24 VCOC VCOM DVDD AVDD DVSS AVSS 0.1 x Cp (Note)
EXLRCK 12 EXSDTI 11
AK5700VN
Top View
MCKO 10 CSP SDTO LRCK BCLK 9 8 7 DSP
1
2
3
4
5 10u 0.1u
0.1u
Power Supply 2.4 3.6V
2.2u
10u 0.1u
Power Supply 1.6 3.6V
6
Analog Ground
Digital Ground
Notes: - AVSS and DVSS of the AK5700 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK5700 is EXT mode (PMPLL bit = "0"), a resistor and capacitor of VCOC pin is not needed. - When the AK5700 is PLL mode (PMPLL bit = "1"), a resistor and capacitor of VCOC pin is shown in Table 4. 0.1 x Cp in parallel with Cp+Rp improves PLL jitter characteristics. - Mic input AC coupling capacitor should be 1F or less to start the recording within 100ms. Figure 39. Typical Connection Diagram (MIC Input)
MS0569-E-01 - 46 -
2006/12
ASAHI KASEI
[AK5700]
P
18
17
16
15
14 MCKI
EXBCLK 13
CCLK
CDTI
PDN
CSN
DSP
19 MPWR 20 TEST 21 AIN2 Line In 22 AIN 23 AIN1 24 VCOC VCOM DVDD AVDD DVSS AVSS 0.1 x Cp (Note) Rp Cp
EXLRCK 12 EXSDTI 11
AK5700VN
Top View
MCKO 10 CSP SDTO LRCK BCLK 9 8 7 DSP
1
2
3
4
5 10u 0.1u
0.1u
Power Supply 2.4 3.6V
2.2u
10u 0.1u
Power Supply 1.6 3.6V
6
Analog Ground
Digital Ground
Notes: - AVSS and DVSS of the AK5700 should be distributed separately from the ground of external controllers. - All digital input pins should not be left floating. - When the AK5700 is EXT mode (PMPLL bit = "0"), a resistor and capacitor of VCOC pin is not needed. - When the AK5700 is PLL mode (PMPLL bit = "1"), a resistor and capacitor of VCOC pin is shown in Table 4. 0.1 x Cp in parallel with Cp+Rp improves PLL jitter characteristics. Figure 40. Typical Connection Diagram (Line Input)
MS0569-E-01 - 47 -
2006/12
ASAHI KASEI
[AK5700]
1. Grounding and Power Supply Decoupling The AK5700 requires careful attention to power supply and grounding arrangements. AVDD and DVDD are usually supplied from the system's analog supply. If AVDD and DVDD are supplied separately, the power-up sequence is not critical. AVSS and DVSS of the AK5700 should be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5700 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference VCOM is a signal ground of this chip. A 2.2F electrolytic capacitor in parallel with a 0.1F ceramic capacitor attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5700. 3. Analog Inputs The analog inputs are single-ended or full-differential and input resistance is 60k (typ)@MGAIN1-0 bits = "00", 30k (typ)@MGAIN1-0 bits = "01" or "10". The input signal range scales with 0.6 x AVDD Vpp(typ)@MGAIN 1-0 bits = "00" centered around the internal common voltage (0.5 x AVDD). Usually the input signal is AC coupled using a capacitor. The cut-off frequency is fc = (1/2RC). The ADC output data format is 2's complement. The DC offset including the ADC's own DC offset is removed by the internal HPF (fc=3.4Hz@ HPF1-0 bits = "00", fs=44.1kHz). The AK5700 can accept input voltages from AVSS to AVDD at single-ended.
MS0569-E-01 - 48 -
2006/12
ASAHI KASEI
[AK5700]
CONTROL SEQUENCE Clock Set up
When ADC is powered-up, the clocks must be supplied. 1. PLL Master Mode.
Example:
Power Supply
(1)
PDN pin
(2) (3)
Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz
PMVCM bit
(Addr:10H, D2) (4)
(1) Power Supply & PDN pin = "L"
"H"
MCKO bit
(Addr:16H, D2)
PMPLL bit
(Addr:11H, D0) (5)
MCKI pin
(2)Addr:11H, Data:12H Addr:14H, Data:23H Addr:15H, Data:2FH
Input
M/S bit
(Addr:11H, D1) 40msec(max) (6)
(3)Addr:10H, Data:04H
BCLK pin LRCK pin
40msec(max) (8)
Output
(4)Addr:16H, Data:04H Addr:11H, Data:13H
MCKO pin
(7)
Output
MCKO, BCLK and LRCK output
Figure 41. Clock Set Up Sequence (1) (1) After Power Up, PDN pin "L" "H" "L" time of 150ns or more is needed to reset the AK5700. (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period as follows. (2a) M/S bit = "1" and setting of PLL3-0, FS3-0, BCKO1-0 bits. (2b) Setting of DIF1-0 bits. (3) Power UpVCOM: PMVCM bit = "0" "1" VCOM should first be powered-up before the other block operates. (4) In case of using MCKO output: MCKO bit = "1" In case of not using MCKO output: MCKO bit = "0" (5) PLL operation starts after PMPLL bit changes from "0" to "1" and MCKI is supplied from an external source. PLL lock time is 40ms(max) at MCKI=12MHz (Table 4). (6) The AK5700 starts to output the LRCK and BCLK clocks after the PLL becomes stable. Then normal operation starts. (7) The invalid frequency is output from MCKO pin during this period if MCKO bit = "1". (8) The normal clock is output from MCKO pin after the PLL is locked if MCKO bit = "1".
MS0569-E-01 - 49 -
2006/12
ASAHI KASEI
[AK5700]
2. PLL Slave Mode (EXLRCK or EXBCLK pin)
Example:
Power Supply
(1)
Audio I/F Format : I2S PLL Reference clock: EXBCLK EXBCLK frequency: 64fs Sampling Frequency: 44.1kHz
PDN pin
(2) (3)
4fs ofPower Supply & PDN pin = "L" (1)
"H"
PMVCM bit
(Addr:10H, D2)
PMPLL bit
(Addr:11H, D0)
(2) Addr:11H, Data:0CH Addr:14H, Data:23H Addr:15H, Data:2FH
Input
(4)
EXLRCK pin EXBCLK pin Internal Clock
(3) Addr:10H, Data:04H
(5)
(4) Addr:11H, Data:0DH
Figure 42. Clock Set Up Sequence (2) (1) After Power Up: PDN pin "L" "H" "L" time of 150ns or more is needed to reset the AK5700. (2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = "0" "1" VCOM should first be powered up before the other block operates. (4) PLL starts after the PMPLL bit changes from "0" to "1" and PLL reference clock (EXLRCK or EXBCLK pin) is supplied. PLL lock time is 160ms(max) when EXLRCK is a PLL reference clock. PLL lock time is 2ms(max) when EXBCLK is a PLL reference clock and the external circuit at VCOC pin is 10k+4.7nF (Table 4). (5) Normal operation stats after that the PLL is locked.
MS0569-E-01 - 50 -
2006/12
ASAHI KASEI
[AK5700]
3. PLL Slave Mode (MCKI pin)
Example:
Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz MCKO: Enable Sampling Frequency: 44.1kHz
Power Supply
(1)
(1) Power Supply & PDN pin = "L"
"H"
PDN pin
(2) (3)
PMVCM bit
(Addr:10H, D2) (4)
(2)Addr:11H, Data:10H Addr:14H, Data:23H Addr:15H, Data:2FH (3)Addr:10H, Data:04H
MCKO bit
(Addr:16H, D2)
PMPLL bit
(Addr:11H, D0) (5)
MCKI pin
Input
40msec(max) (6)
(4)Addr:16H, Data:04H Addr:11H, Data:11H
MCKO pin
(7) (8)
Output
MCKO output start
EXBCLK pin EXLRCK pin
Input
EXBCLK and EXLRCK input start
Figure 43. Clock Set Up Sequence (3) (1) After Power Up: PDN pin "L" "H" "L" time of 150ns or more is needed to reset the AK5700. (2) DIF1-0, PLL3-0, FS3-0, BCKO1-0 and M/S bits should be set during this period. (3) Power Up VCOM: PMVCM bit = "0" "1" VCOM should first be powered up before the other block operates. (4) Enable MCKO output: MCKO bit = "1" (5) PLL starts after that the PMPLL bit changes from "0" to "1" and PLL reference clock (MCKI pin) is supplied. PLL lock time is 40ms(max) at MCKI=12MHz (Table 4). (6) The normal clock is output from MCKO after PLL is locked. (7) The invalid frequency is output from MCKO during this period. (8) EXBCLK and EXLRCK clocks should be synchronized with MCKO clock.
MS0569-E-01 - 51 -
2006/12
ASAHI KASEI
[AK5700]
4. EXT Slave Mode
Example:
Audio I/F Format: I2S Input MCKI frequency: 256fs Sampling Frequency: 44.1kHz MCKO: Disable
Power Supply
(1)
(1) Power Supply & PDN pin = "L"
"H"
PDN pin
(2) (3)
PMVCM bit
(Addr:10H, D2) (4)
(2) Addr:11H, Data:00H Addr:14H, Data:23H Addr:15H, Data:2FH
Input
(4)
MCKI pin EXLRCK pin EXBCLK pin
(3) Addr:10H, Data:04H
Input
MCKI, EXBCLK and EXLRCK input
Figure 44. Clock Set Up Sequence (4) (1) After Power Up: PDN pin "L" "H" "L" time of 150ns or more is needed to reset the AK5700. (2) DIF1-0 and FS1-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = "0" "1" VCOM should first be powered up before the other block operates. (4) Normal operation starts after the MCKI, EXLRCK and EXBCLK are supplied.
MS0569-E-01 - 52 -
2006/12
ASAHI KASEI
[AK5700]
5. EXT Master Mode
Power Supply
(1)
PDN pin
(2) (3)
Example:
Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select: 256fs Sampling Frequency: 44.1kHz
PMVCM bit
(Addr:10H, D2)
MCKI pin
Input
(1) Power Supply & PDN pin = "L"
"H"
M/S bit
(Addr:11H, D1)
TE3-0 bits
(Addr:1DH, D7-4)
"1010"
"0101"
TMASTER bit
(Addr:1EH, D1)
(2)Addr:11H, Data:26H Addr:14H, Data:23H Addr:15H, Data:2FH Addr:1DH, Data:50H Addr:1EH, Data:02H BCLK and LRCK output
BCLK pin LRCK pin
Output
(3)Addr:10H, Data:04H
Figure 45. Clock Set Up Sequence (5) (1) After Power Up: PDN pin "L" "H" "L" time of 150ns or more is needed to reset the AK5700. (2) DIF1-0, FS1-0, BCKO1-0, M/S, TE3-0 and TMASTER bits should be set during this period as follows. (2a) M/S bit = "1", setting of FS3-0 and BCKO1-0 bits. (2b) Setting of DIF1-0 bits. (2c) TE3-0 bits = "0101" (2d) TMASTER bit = "1": BCLK and LRCK start to output. (3) Power Up VCOM: PMVCM bit = "0" "1" VCOM should first be powered up before the other block operates. When the clock mode is changed from EXT Master Mode to other modes, the register should be set as above table after PDN pin = "L" to "H" or TE3-0 bits = "1010".
MS0569-E-01 - 53 -
2006/12
ASAHI KASEI
[AK5700]
6. Slave & Bypass Mode
Example:
Power Supply
(1)
Audio I/F Format : I2S PLL Reference clock: EXBCLK EXBCLK frequency: 64fs Sampling Frequency: 44.1kHz
PDN pin
(2) (3)
4fs ofPower Supply & PDN pin = "L" (1)
"H"
PMVCM bit
(Addr:10H, D2)
PMPLL bit
(Addr:11H, D0)
(2) Addr:11H, Data:0CH Addr:14H, Data:23H Addr:15H, Data:2FH Addr:16H, Data:08H
Input
(4)
EXLRCK pin EXBCLK pin Internal Clock
(3) Addr:10H, Data:04H
(5)
(4) Addr:11H, Data:0DH
Figure 46. Clock Set Up Sequence (6) (1) After Power Up: PDN pin "L" "H" "L" time of 150ns or more is needed to reset the AK5700. (2) THR bit should be set to "1" and DIF1-0, FS3-0 and PLL3-0 bits should be set during this period. (3) Power Up VCOM: PMVCM bit = "0" "1" VCOM should first be powered up before the other block operates. (4) PLL starts after the PMPLL bit changes from "0" to "1" and PLL reference clock (EXLRCK or EXBCLK pin) is supplied. PLL lock time is 160ms(max) when EXLRCK is a PLL reference clock. PLL lock time is 2ms(max) when EXBCLK is a PLL reference clock and the external circuit at VCOC pin is 10k+4.7nF (Table 4). (5) Normal operation stats after that the PLL is locked.
MS0569-E-01 - 54 -
2006/12
ASAHI KASEI
[AK5700]
7. Bypass Mode
Power Supply
(1)
PDN pin
(2)
(1) Power Supply & PDN pin = "L"
"H"
THR bit
(Addr:16H, D3)
(2) Addr:16H, Data:08H
(3)
EXLRCK pin EXBCLK pin EXSDTI pin
Input
MCKI, EXBCLK and EXLRCK input
Figure 47. Clock Set Up Sequence (7) (1) After Power Up: PDN pin "L" "H" "L" time of 150ns or more is needed to reset the AK5700. (2) THR bit should be set to "1". (3) After EXLRCK, EXBCLK and EXSDTI are input, LRCK, BCLK and SDTO start to output.
MS0569-E-01 - 55 -
2006/12
ASAHI KASEI
[AK5700]
MIC Input Recording
Example:
PLL Master Mode Audio I/F Format:I2S Sampling Frequency:44.1kHz Pre MIC AMP:+15dB MIC Power On ALC setting:Refer to Figrure 37 ALC bit = "1"
(1) Addr:15H, Data:2FH
FS3-0 bits
(Addr:15H, D3-0)
X,XXX
(1)
1111
(2) Addr:12H, Data:10H Addr:13H, Data:01H
MIC Control
(Addr:12H, D4 & Addr:13H, D1-0)
0, 01
(2)
1, 01
(3) Addr:1AH, Data:0AH
Timer Control
(Addr:1AH)
XXH
(3)
0AH
(4) Addr:1BH, Data:E1H
ALC Control 1
(Addr:1BH)
XXH
(4)
E1H 81H
(5) (8)
(5) Addr:1CH, Data:81H
ALC Control 2
(Addr:1CH)
XXH ALC Disable
01H ALC Disable
(6) Addr:10H, Data:05H
ALC State PMADC bit
(Addr:10H, D0)
ALC Enable
Recording (7) Addr:10H, Data:04H
3088 / fs (6) (7)
ADC Internal State
Power Down
Initialize Normal State Power Down
(8) Addr:1CH, Data:01H
Figure 48. MIC Input Recording Sequence This sequence is an example of ALC setting at fs=44.1kHz. If the parameter of the ALC is changed, please refer to "Figure 35. Registers set-up sequence at ALC operation". At first, clocks should be supplied according to "Clock Set Up" sequence. (1) Set up a sampling frequency (FS3-0 bit). When the AK5700 is PLL mode, MIC and ADC should be powered-up in consideration of PLL lock time after a sampling frequency is changed. (2) Set up MIC input (Addr: 12H&13H) (3) Set up Timer Select for ALC (Addr: 1AH) (4) Set up REF value for ALC (Addr: 1BH) (5) Set up LMTH1-0, RGAIN1-0, LMAT1-0 and ALC bits (Addr: 1CH) (6) Power Up MIC and ADC: PMADC bit = "0" "1" The initialization cycle time of ADC is 3088/fs=70.0ms@fs=44.1kHz, HPF1-0 bits = "00". After the ALC bit is set to "1" and MIC&ADC block is powered-up, the ALC operation starts from IVOL default value (0dB). To start the recording within 100ms, the following sequence is required. (6a) PMVCM=PMMP bits = "1". (6b) Wait for 2ms, then PMPLL bit = "1". (6c) Wait for 6ms, then PMADC bit = "1". (7) Power Down MIC and ADC: PMADC bit = "1" "0" When the registers for the ALC operation are not changed, ALC bit may be keeping "1". The ALC operation is disabled because the MIC&ADC block is powered-down. If the registers for the ALC operation are also changed when the sampling frequency is changed, it should be done after the AK5700 goes to the manual mode (ALC bit = "0") or MIC&ADC block is powered-down (PMADC bit = "0"). IVOL gain is not reset when PMADC = "0", and then IVOL operation starts from the setting value when PMADC bit is changed to "1". (8) ALC Disable: ALC bit = "1" "0"
MS0569-E-01 - 56 -
2006/12
ASAHI KASEI
[AK5700]
Stop of Clock
Master clock can be stopped when ADC is not used. 1. PLL Master Mode
Example:
(1)
PMPLL bit
(Addr:11H, D0)
Audio I/F Format: I2S BCLK frequency at Master Mode: 64fs Input Master Clock Select at PLL Mode: 11.2896MHz Sampling Frequency: 44.1kHz
M/S bit
(Addr:11H, D1) (2)
(1) Addr:11H, Data:10H
"H" or "L"
MCKO bit
(Addr:16H, D2)
(2) Addr:16H, Data:00H
(3)
External MCKI
Input
(3) Stop an external MCKI
Figure 49. Clock Stopping Sequence (1) (1) Power down PLL: PMPLL=M/S bits = "1" "0" (2) Stop MCKO clock: MCKO bit = "1" "0" (3) Stop an external master clock. 2. PLL Slave Mode (EXLRCK, EXBCLK pin)
Example
(1)
PMPLL bit
(Addr:11H, D0) (2)
Audio I/F Format : I2S PLL Reference clock: EXBCLK BCLK frequency: 64fs Sampling Frequency: 44.1kHz
EXBCLK EXLRCK
Input
(2)
(1) Addr:11H, Data:0CH
Input
(2) Stop the external clocks
Figure 50. Clock Stopping Sequence (2) (1) Power down PLL: PMPLL bit = "1" "0" (2) Stop the external EXBCLK and EXLRCK clocks * Clock stop sequence is the same for Slave&Bypass Mode.
MS0569-E-01 - 57 -
2006/12
ASAHI KASEI
[AK5700]
3. PLL Slave Mode (MCKI pin)
Example
Audio I/F Format: I2S PLL Reference clock: MCKI EXBCLK frequency: 64fs Sampling Frequency: 44.1kHz
(1)
PMPLL bit
(Addr:11H, D0) (2)
(1) Addr:11H, Data:10H (2) Addr:16H, Data:00H
(3)
MCKO bit
(Addr:16H, D2)
External MCKI
Input
(3) Stop the external clocks
Figure 51. Clock Stopping Sequence (3) (1) Power down PLL: PMPLL bit = "1" "0" (2) Stop MCKO output: MCKO bit = "1" "0" (3) Stop the external master clock. 4. EXT Slave Mode
(1)
External MCKI EXBCLK EXLRCK
Input
Example
(1)
Input
(1)
Audio I/F Format :I2S Input MCKI frequency:256fs Sampling Frequency:44.1kHz
Input
(1) Stop the external clocks
Figure 52. Clock Stopping Sequence (4) (1) Stop the external MCKI, EXBCLK and EXLRCK clocks. * Clock stop sequence is the same for Bypass Mode. 5. EXT Master Mode
(1)
External MCKI BCLK LRCK
Input
Example
Output Output
"H" or "L" "H" or "L"
Audio I/F Format :I2S Input MCKI frequency:256fs Sampling Frequency:44.1kHz
(1) Stop MCKI
Figure 53. Clock Stopping Sequence (5) (1) Stop MCKI. BCLK and LRCK are fixed to "H" or "L".
MS0569-E-01 - 58 -
2006/12
ASAHI KASEI
[AK5700]
Power down
Power supply current is typ. 20A by stopping clocks and setting PMVCM bit = "0" after all blocks except for VCOM are powered-down. Power supply current can be shut down (typ. 1A) by stopping clocks and setting PDN pin = "L". When PDN pin = "L", the registers are initialized.
MS0569-E-01 - 59 -
2006/12
ASAHI KASEI
[AK5700]
PACKAGE
24pin QFN (Unit: mm)
4.0 0.1
13 12
A
2.4 0.15
18 19
2.4 0.15
4.0 0.1
Exposed Pad
7 6
B
24
0.40 0.1
1
0.23 0.05
0.10 M
PIN #1 ID
(0.35 x 45 )
0.5
Note) The exposed pad on the bottom surface of the package must be open or connected to the ground.
Material & Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
MS0569-E-01 - 60 -
0.75 0.05
0.08
0.2
2006/12
ASAHI KASEI
[AK5700]
MARKING
5700
XXXX
1
XXXX : Date code identifier (4 digits)
Revision History
Date (YY/MM/DD) 06/11/16 06/12/25 Revision 00 01 Reason First Edition Error correct Page 40 Contents Register Map (Addr=17H) Bit (D0) value was changed: 0 1
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: a. A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. b. A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. MS0569-E-01 - 61 2006/12

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