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| Micro Networks An Integrated Circuit Systems Company M2004-01 Preliminary Specifications M2004-01 Frequency Synthesizer DESCRIPTION The M2004-01 integrates a high performance Phase Locked Loop (PLL) with a Voltage Controlled SAW Oscillator (VCSO) to provide a low jitter Frequency Translator in a 9mm x 9mm surface mount package. The internal high "Q" SAW filter provides low jitter signal performance and determines the maximum output frequency of the VCSO. A programmable output divider can divide the VCSO frequency to achieve an output as low as 38.88MHz. FEATURES Output Clock Frequency up to 700MHz Differential LVPECL Outputs Internal Low-jitter SAW-based Oscillator Intrinsic Jitter <1ps rms (12kHz - 20MHz) Jitter Attenuation of Input Reference Clock Dual Input MUX Parallel Programming Tunable Loop Filter Response Differential LVPECL Outputs 3.3V Operation Small 9mm x 9mm SMT Package The input to the Frequency Translator is provided by selecting between one of two output reference clocks. The output frequency is an integer multiple of the input reference frequency. Parallel and serial control of the output and feedback dividers is provided via the configuration logic. An external loop filter sets the PLL bandwidth which can be optimized to provide jitter attenuation of the input reference clock. The M2004-01 is available at SONET/SDH and 10GbE frequencies up to 700MHz. APPLICATIONS ABSOLUTE MAX RATINGS Inputs, VI : ................................................. -0.5 to VCC+0.5V Output, VO : ................................................. -0.5 to VCC+0.5V Supply Voltage, VDD : ......................................................... 4.6 V Storage Temperature, TSTO : ............................ -45C to +100C Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. SONET / SDH / 10GbE System Synchronization Add / Drop Muxes, Access and Edge Switches Line Card System Clock Cleaner / Translator Optical Module Clock Cleaner / Translator ISO 9001 Registered Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 1 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company FUNCTIONAL BLOCK DIAGRAM M2004-01 Preliminary Specifications The internal PLL will adjust the VCSO output frequency to be M times the selected input reference clock frequency. Note that the product of M x input frequency must be such that it falls within the "lock" range of the VCSO. The N output divider can be programmed to divide the VCSO output frequency by 1, 2, 4, or 8 and provide a 50% output duty cycle. RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP RPOST nOP_OUT nVC VC SAW Delay Line The relationship between the VCSO frequency, the input REF_CLK , and the M divider is defined as follows: F VCSO = F REF_CLK x M When the N output divider is included, the complete relationship for the output frequency is defined as: FOUT= F VCSO = F REF_CLK x M N N The M value and the required logic states of M0 through M5 are shown in Table 5B, Programmable VCSO Frequency Function Table. (i.e. For an output frequency of 622.0800MHz and an input frequency of 19.44MHz the M value would be 32 and the N value would be 1. Similarly, for an output frequency of 311.04MHz and an input frequency of 19.44 MHz the M value would be 32 and the N value would be 2.) Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider when S_LOAD transitions from LOW-to-HIGH. The M divider and N output divide values are latched on the HIGH-to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output divider on each rising edge of S_CLOCK. External Loop Filter Components M2004-01 MUX OP_IN nOP_IN OP_OUT REF_CLK1 REF_CLK0 REF_SEL Phase Detector RIN RIN 1 0 Loop Filter Amplifier M Divider M = 3-1023 N Divider N = 1,2,4,8 Serial / Parallel Configuration Register Phase Shifter VCSO S_DATA S_CLK S_LOAD nP_LOAD FOUT nFOUT 6 M5:0 2 N1:0 MR The M2004-01 supports both parallel and serial operating modes for programming the M divider and N output divider. Figure 1 shows the timing diagram for each mode. In the parallel mode the nP_LOAD input is initially LOW. The data on inputs M0 through M5 and N0 and N1 is passed directly to the M divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up. FIGURE 1 S_DATA Low Low Null N1 N0 Null Null Null M5 M4 M3 M2 M1 M0 S_CLK S_LOAD Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 2 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company FUNCTIONAL DESCRIPTION LOOP FILTER FIGURE 2 Rloop OP_IN Cloop M2004-01 Preliminary Specifications The M2004-01 requires the use of an external loop filter via the provided filter pins. Due to the differential design, the implementation requires two identical RC filters as shown in Figure 2. Rpost nVc Cpost nOP_OUT OP_OUT Cpost nOP_IN Rloop Cloop Rpost Vc TABLE 1. RECOMMENDED LOOP FILTER VALUES REF_CLK Frequency VCSO Frequency M N FOUT Rloop Cloop Rpost Cpost 19.44MHz 622.0800MHz 32 1 622.0800MHz 5k 1MF 50k 100pf Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 3 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company PIN DESCRIPTIONS TABLE 2 Pin Number Name M2004-01 Preliminary Specifications 1, 2, 3 4, 9 5, 8 6, 7 10, 14, 26 11, 19, 33 12, 13 15, 16 17 GND OP_IN, nOP_IN nOP_OUT, OP_OUT nVC, VC GND VDD N0, N1 FOUT, nFOUT MR I/O GND Configuration Description Power Supply Ground Analog I/O Analog I/O Input GND Power Input Output Input Pull - down Unterminated Pull - down VCSO Used for external loop filter. See Figure 2. Used for external loop filter. See Figure 2 Differential Control Voltage Input Pair Power Supply Ground Positive Supply Pins Determines the output divider value as defined in table 3C. LVCMOS / LVTTL interface levels. Differential output, 3.3V LVPECL levels. Logic HIGH resets the reference frequency and N output dividers. Logic LOW enables the outputs. LVCMOS / LVTTL interface levels. 18 S_CLOCK Input Pull - down Clocks in serial data present at S_DATA input into the shift register on the rising edge of S_CLOCK. 20 21 22 S_DATA S_LOAD nP_LOAD Input Input Input Pull - down Pull - down Pull - down Shift register serial input. Data is sampled on the rising edge of S_CLOCK. Controls transition of data from shift register into the dividers. LVCMOS / LVTTL interface levels Parallel load input. Determines when data present at M5:M0 is loaded into Mdivider, and when data present at N1:N0 sets the N output divider value. LVCMOS / LVTTL interface levels. 23 24 25 REF_ CLK 1 REF_ CLK 0 REF_SEL Input Input Input Pull - down Pull - down Pull - down Input reference clock. LVCMOS / LVTTL interface levels. Input reference clock. LVCMOS / LVTTL interface levels. Selects between the different reference clock inputs as the PLL reference source. See table 3D. LVCMOS / LVTTL interface levels. 27, 28, 29, 30, 31 M0, M1, M2, M3, M4 Input Pull - down M divider inputs. Data is latched on LOW-to-HIGH transition of nP_LOAD input. LVCMOS/ LVTTL interface levels. 32 34, 35, 36 M5 DNC Input Pull - down Do not connect. Internal test pins must be left floating. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 4 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company PIN CHARACTERISTICS TABLE 4 Symbol Parameter Test Conditions Min Typical M2004-01 Preliminary Specifications Max Units CIN RPULLUP RPULLDOWN Input Capacitance Input Pullup Resistor Input Pulldown Resistor 51 51 4 pF k k PARALLEL & SERIAL MODES FUNCTION TABLE 5A MR nP Load M Inputs N S Load S Clock S Data Conditions Reset, Forces outputs LOW. H L L X L X Data Data X Data Data X X L X X X X X X Data on M and N inputs passed directly to the M divider and N output divider. TEST output forced LOW. Data is latched into input registers and remains loaded until next LOW transition or until a serial event occurs. L L L L L H H H H H X X X X X X X X X X L Data Data Data X Data Serial input mode. Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK Contents of the shift register are passed to the M divider and N output divider. M divider and N output divider values are latched. Parallel or serial input do not affect shift registers. S_DATA passed directly to M divider as it is clocked. L L X L H Note: L = Low; H = High; X = Don't care; = Rising Edge Transition; = Falling Edge Transition PROGRAMMABLE VCSO FREQUENCY FUNCTION TABLE 5B VCSO Frequency (MHz) 32 M Divide M5 16 M4 8 M3 4 M2 2 M1 1 M0 325 350 375 400 * * 600 625 650 13 14 15 16 * * 24 25 26 0 0 0 0 * * 0 0 0 0 0 0 1 * * 1 1 1 1 1 1 0 * * 1 1 1 1 1 1 0 * * 0 0 0 0 1 1 0 * * 0 0 1 1 0 1 0 * * 0 1 0 NOTE 1: These M divide values and the resulting frequencies correspond to a reference frequency of 25MHz. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 5 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company PARALLEL MODE FUNCTION TABLE 5C Inputs N Divider Output Frequency (MHz) N1 N0 Value Min Max TABLE 5D M2004-01 Preliminary Specifications SERIAL MODE FUNCTION Inputs REF SEL Reference 0 0 1 1 0 1 0 1 1 2 4 8 311 155.5 77.75 38.875 700 350 175 87.5 0 1 DIFF_REF REF_CLK POWER SUPPLY DC CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units VDD IDD Power Supply Voltage Power Supply Current 3.135 3.3 162 3.465 V mA VCC= 3.3V 5%, TA= 0C to 70C LVCMOS/LVTTL DC CHARACTERISTICS Symbol Parameter REF_SEL, S_LOAD, S_ DATA, S_CLOCK Test Conditions Min Max Units VCC + 0.3 V VIH Input High Voltage 2 2 -0.3 -0.3 VDD = VIN = 3.465V VDD = VIN = 3.465V nP_LOAD, N0:N1, M0:M5, MR REF_CLK0, REF_CLK1 VCC + 0.3 0.8 1.3 5 150 V V V A A REF_SEL, S_LOAD, S_DATA, S_CLOCK nP_LOAD, N0:N1, M0:M5, MR REF_CLK0, REF_CLK1 M5 N0, N1, MR, M0:M4, S_CLOCK, S_DATA, S_LOAD, nP_LOAD, REF_SEL, REF_CLK0, REF_CLK1 VIL Input Low Voltage IIH Input High Current IIL Input Low Current M5 N0, N1, MR, M0:M4, S_CLOCK, S_DATA, S_LOAD, nP_LOAD, REF_SEL, REF_CLK0, REF_CLK1 VDD = 3.465, VIN = 0V VDD = 3.465, VIN = 0V -150 -5 A A VOH VOL Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 2.6 0.5 V V Note 1: Outputs terminated with 50 to VCC/2. See parameter Measurement section, 3.3V Output Load Test Circuit. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 6 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company LVPECL DC CHARACTERISTICS Symbol Parameter Signal Min Max M2004-01 Preliminary Specifications Units VOH VOL VSWING Output High Voltage: Note 1 Output Low Voltage: Note 1 Peak-to-Peak Output Voltage Swing FOUT, nFOUT FOUT, nFOUT FOUT, nFOUT VDD - 1.4 VDD - 2.0 0.6 Vcc - 1.0 Vcc - 1.7 0.85 V V V Note 1: Output terminated with 50 to VDD-2.V INPUT FREQUENCY CHARACTERISTICS Symbol Parameter Test Conditions Min Max Units FIN Input Frequency REF_CLK0, REF_CLK1 S_CLOCK 10 166 50 MHz MHz VCC = 3.3V5%, TA = 0C to 70C AC CHARACTERISTICS Symbol Parameter Test Conditions Min Typ Max Units FOUT ONOISE Output Frequency Single Side Band Phase Noise 1kHz offset 10kHz offset 100kHz offset 12kHz to 20 MHz FOUT = 155MHz FOUT = 311MHz FOUT = 622MHz FOUT = 155MHz FOUT = 311MHz FOUT = 622MHz M, N, to nP_LOAD S_DATA to S_CLK S_CLK to S_LOAD 20% to 80%, each output of pair measured is terminated into 50 load biased at Vcc-2V 20% to 80%, each output of pair measured is terminated into 50 load biased at Vcc-2V 38.88 -72 -94 -123 0.69 50 350 325 200 350 325 200 5 5 5 5 5 5 450 425 275 450 425 275 700 MHz dBc/Hz dBc/Hz dBc/Hz ps % J (t) odc tR (Note 1) Jitter (RMS) Output Duty Cycle Output Rise Time for output pairs FOUT0, nFOUT0 & FOUT1, nFOUT1 550 500 350 550 500 350 ps ps ps ps ps ps ns ns ns ns ns ns tF (Note 1) Output Fall Time for output pairs FOUT0, nFOUT0 & FOUT1, nFOUT1 tS Setup Time tH Hold Time M,N, to nP_LOAD S_DATA to S_CLK S_CLK to S_LOAD tLOCK tPW PLL Lock Time Output Pulse Width 1 TBD TBD ms ns ns Note: The output frequencies of 155MHz, 311MHz and 622MHz were chosen for device characterization as these are common optical network clock frequencies. Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 7 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company PARAMETER MEASUREMENT INFORMATION M2004-01 Preliminary Specifications INPUT AND OUTPUT RISE AND FALL TIME 80% 80% V SWING 20% Clock Inputs and Outputs t t 20% R F ODC & tPERIOD Pulse Width t t odc = t PW PERIOD PERIOD SETUP AND HOLD TIME S_DATA S_CLOCK tSET-UP tHOLD S_LOAD tSET-UP M[5:0] N[1:0] nP_LOAD tSET-UP tHOLD Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 8 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company TEST EVALUATION BOARD M2004-01 Preliminary Specifications J3 9-PIN D CONNECTOR Pin Signal SW1 1 3 5 7 9 MR S_CLOCK S_DATA S_LOAD nP_LOAD Position Off On JP1: N0 JP2: N1 1 REF Select 2 M5 3 M4 4 M3 5 M2 6 M1 7 M0 8 N/C REF_CLK0 REF_CLK1 "1" "0" "0" "1" "0" "1" "0" "1" "0" "1" "0" "1" N/C N/C Logic "1" when installed Logic "0" when installed Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 9 fax: 508-852-8456 www.micronetworks.com Micro Networks An Integrated Circuit Systems Company MECHANICAL DIMENSIONS & PIN CONFIGURATION M2004-01 Preliminary Specifications .354 [9.0] #27 #28 #19 #18 .354 [ ] [9.0] #36 #10 .110 [2.8] ORIENTATION TAB Pin #1 .200 [5.1] .025 [0.6] C C L .041 [1.0] R.006 [R0.2] .007 [0.2] Pin# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Designation GND GND GND OP_IN nOP_OUT nVC VC OP_OUT nOP_IN GND VDD NO N1 GND FOUT nFOUT MR Pin# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34, 35, 36 Designation S_CLOCK VDD S_DATA S_LOAD nP_LOAD REF_CLK1 REF_CLK0 REF_SEL GND M0 M1 M2 M3 M4 M5 VDD N/C Dimensions are in inches, (dimensions) are in mm. ORDERING INFORMATION PART NUMBER Series Model VCSO Center Frequency (i.e. 622.0800MHz) M2004-01-622.0800 Available VCSO Frequencies 622.0800 669.1281 625.0000 669.3266 627.3296 672.1600 644.5313 690.5692 666.5143 693.4830 Micro Networks makes no assertion or warranty that the circuitry and the uses thereof disclosed herein are non-infringing on any valid US or foreign patents. Micro Networks assumes no liability as a result of the use of said specifications and reserves the right to make changes to specifications without notice. Contact your nearest Micro Networks sales representative office for the latest specifications. Micro Networks An Integrated Circuit Systems Company 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 European Sales Headquarters Hertogsingel 20 6214 AD Maastricht The Netherlands tel: +31-43-32-70912 fax: +31-43-32-70715 Micro Networks 324 Clark Street Worcester, MA 01606 tel: 508-852-5400 fax: 508-852-8456 www.micronetworks.com www.micronetworks.com 10 Rev. 13.0 |
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