View ICS889872_4116762.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
ICS889872 Features
* * * * * * * * * * * *
Three LVDS outputs Frequency divide select options: /4, /6: >2GHz, /8, /16: >1.6GHz IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML Output frequency: >2GHz Cycle-to-cycle jitter: 1ps (typical) Total jitter: 10ps (typical) Output skew: 7ps (typical), QA/nQA outputs Part-to-part skew: 250ps (typical) Propagation Delay: 750ps (typical), QA/nQA outputs Full 2.5V supply mode -40C to 85C ambient operating temperature Available in both standard (RoHS 5) and lead-free (RoHS 6) packages
General Description
The ICS889872 is a high speed Differential-toLVDS Buffer/Divider w/Internal Termination and is a HiPerClockSTM member of the HiPerClockSTMfamily of high performance clock solutions from IDT. The ICS889872 has a selectable /2, /4, /8, /16 output dividers. The clock input has internal termination resistors, allowing it to interface with several differential signal types while minimizing the number of required external components. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.
ICS
Block Diagram
Pin Assignment
GND
nRESET/ nDISABLE
Enable FF
QB0 1 nQB0 Enable MUX 2
16 15 14 13 12 IN 11 VT 10 VREF_AC 9 nIN 5
QA
QB1 3 QA nQA nQB1 4 6
nQA
VDD
S0
S1
7
VDD
8
nRESET/ nDISABLE
IN
50
QB0 /2, /4, /8, /16 nQB0
VT
50
nIN VREF_AC S1 Decoder S0
ICS889872
QB1 nQB1
16-Lead VFQFN 3mm x 3mm x 0.95mm package body K Package Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
1
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Table 1. Pin Descriptions
Number 1, 2 Name QB0, nQB0 Output Type Description Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be terminated with 100W across the pin (QB0/nQB0). LVDS interface levels. Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be terminated with 100W across the pin (QB1nQB1). LVDS interface levels. Differential undivided output pair. LVDS interface levels. Power supply pins. Output reset and enable/disable pin. When LOW, resets the divider select, and align Bank A and Bank B edges. In addition, when LOW, Bank A and Bank B will be disabled. Input threshold is VDD/2V. Includes a 37k pullup resistor. LVTTL / LVCMOS interface levels. Inverting differential LVPECL clock input. RT = 50 termination to VT. Reference voltage for AC-coupled applications. Equal to VDD - 1.4V (approx.). Maximum sink/source current is 0.5mA. Termination input. Leave pin floating. Non-inverting LVPECL differential clock input. RT = 50 termination to VT. Power supply ground. Pullup Select pins. Logic HIGH if left unconnected (/16 mode). S0 = LSB. Input threshold is VDD/2. 37kW pullup resistor. LVCMOS/LVTTL interface levels.
3, 4 5, 6 7, 14
QB1, nQB1 QA, nQA VDD nRESET/ nDISABLE nIN VREF_AC VT IN GND S1, S0
Output Output Power
8
Input
Pullup
9 10 11 12 13 15, 16
Input Output Input Input Power Input
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol RPULLUP Parameter Input Pullup Resistor Test Conditions Minimum Typical 37 Maximum Units k
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
2
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Function Tables
Table 3A. Control Input Function Table
Input nRESET 0 1 QA, QBx Disabled; LOW Enabled Outputs nQA, nQBx Disabled; HIGH Enabled
NOTE: After nRESET switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1.
Figure 1. nRESET Timing Diagram
VDD/2 tRR
nRESET IN nIN
VIN Swing
tPD
nQBx QBx QA nQA
VOUT Swing
Table 3B. Truth Table
Inputs nRESET/nDISABLE 1 1 1 1 0 S1 0 0 1 1 X S0 0 1 0 1 X Bank A Input Clock Input Clock Input Clock Input Clock QA = LOW, nQA = HIGH; NOTE 1 Outputs Bank B Input Clock /2 Input Clock /4 Input Clock /8 Input Clock /16 QBx = LOW, nQBx = HIGH; NOTE 2
NOTE 1: On the next negative transition of the input signal. NOTE 2: Asynchronous reset/disable function.Absolute Maximum Ratings
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
3
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Item Supply Voltage, VDD Inputs, VI Outputs, IO Continuos Current Surge Current Input Current, IN, nIN VT Current, IVT Input Sink/Source, IREF_AC Operating Temperature Range, TA Package Thermal Impedance, JA, (Junction-to-Ambient) Storage Temperature, TSTG Rating 4.6V -0.5V to VDD + 0.5V 10mA 15mA 50mA 100mA 0.5mA -40C to +85C 51.5C/W (0 lfpm) -65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C
Symbol VDD IDD Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical 2.5 80 Maximum 2.625 Units V mA
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current VDD = VIN = 2.625V VDD = 2.625V, VIN = 0V -150 Test Conditions Minimum 2 0 Typical Maximum VDD + 0.3 0.8 5 Units V V A A
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
4
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Table 4C. Differential DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C
Symbol RIN VIH VIL VIN VDIFF_IN IIN VREF_AC Parameter Differential Input Resistance Input High Voltage Input Low Voltage Input Voltage Swing Differential Input Voltage Swing Input Current Bias Voltage (IN, nIN) VDD - 1.35 (IN, nIN) (IN, nIN) (IN, nIN) 1.2 0 0.15 0.3 45 Test Conditions Minimum Typical 100 VDD VDD - 0.15 2.8 Maximum Units
V V V V mA V
Table 4D. LVDS DC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C
Symbol VOUT VOH VOL VCCM VOCM Parameter Output Voltage Swing Output High Voltage Output Low Voltage Output Common Mode Voltage Change in Common Mode Voltage 0.925 1.35 50 Test Conditions Minimum Typical 350 1.475 Maximum Units mV V V V mV
AC Electrical Characteristics
Table 5. AC Characteristics, VDD = 2.5V 5%, TA = -40C to 85C
Parameter fMAX tPD tsk(o) tsk(pp) tjit(cc) tjit(j) tRR tR / tF Symbol Output Frequency Input Frequency Propagation Delay; NOTE 1, 2 Output Skew; NOTE 2, 3, 4 IN-to-Q QB0-to-QB1 QA-to-QB Test Conditions /2, /4 /8, /16 Input Swing: <400mV Input Swing: 400mV Minimum Typical >2 >1.6 750 750 7 60 250 1 10 600 150 Maximum Units GHz GHz ps ps ps ps ps ps ps ps ps
Part-to-Part Skew; NOTE 2, 4, 5 Cycle-to-Cycle Jitter; NOTE 2, 6 Total Jitter; NOTE 2 Reset Recovery Time; NOTE 2 Output Rise/Fall Time; NOTE 2
All parameters characterized at 1GHz unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Specs are design targets. NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 6: The cycle-to-cycle jitter on the input will equal the jitter on the output. The part does not add jitter.
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
5
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Parameter Measurement Information
VDD
SCOPE
2.5V5% POWER SUPPLY + Float GND -
,
nIN
V Cross Points V
VDD
Qx
LVDS
nQx
IN
IH
IN
V
IL
GND
LVDS Output Load AC Test Circuit
Differential Input Level
Par t 1
nQx
nQx Qx
Qx Qy Par t 1 Qy nQy Qy
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
nQA, nQB[0:1] QA, QB[0:1]
nIN IN
tcycle n
tcycle n+1
nQA, nQB[0:1] QA, QB[0:1]
tjit(cc) = tcycle n - tcycle n+1 1000 Cycles
Cycle-to-Cycle Jitter
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
tPD
Propagation Delay
6
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Parameter Measurement Information, continued
80%
VDIFF_IN, VDIFF_OUT VIN, VOUT 800mV (typical) 1600mV (typical)
80% VOD
Clock Outputs
20% tR tF
20%
Single-Ended & Differential Input Voltage Swing
Output Rise/Fall Time
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input IN
V_REF nIN C1 0.1u
R2 1K
Figure 2. Single-Ended Signal Driving Differential Input
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
7
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Differential Input with Built-in 50 Termination Interface
The IN /nIN with built-in 50 terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL and other differential signals. Both signals must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS IN/nIN input with built-in 50 terminations driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
2.5V 3.3V or 2.5V 2.5V
2.5V
Zo = 50 Zo = 50 IN IN VT nIN Zo = 50 VT nIN
Zo = 50
Receiver With Built-In 50
LVDS
LVPECL R1 18
Receiver With Built-In 50
Figure 3A. HiPerClockS IN/nIN Input with Built-In 50 Driven by an LVDS Driver
Figure 3B. HiPerClockS IN/nIN Input with Built-In 50 Driven by an LVPECL Driver
2.5V
2.5V 3.3V 3.3V LVPECL Zo = 50 IN VT Zo = 50 VT nIN Zo = 50 C2 nIN Zo = 50 C1 IN
2.5V
50 50 REF_AC R5 100 - 200 R5 100 - 200
Receiver With Built-In 50
CML - Built-in 50 Pull-up
Receiver with Built-In 50
Figure 3C. HiPerClockS IN/nIN Input with Built-In 50 Driven by a CML Driver with Built-In 50 Pullup
Figure 3D. HiPerClockS IN/nIN Input with Built-In 50 Driven by an SSTL Driver
2.5V 3.3V 3.3V CML with Built-In Pullup Zo = 50 C1 IN 50 VT Zo = 50 C2 nIN REF_AC 50
Receiver with Built-In 50
Figure 3E. HiPerClockS IN/nIN Input with Built-In 50 Driven by a 3.3V CML Driver with Built-In Pullup
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
8
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Recommendations for Unused Input Pins Inputs:
LVCMOS Select Pins
All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used.
OUTputs:
LVDS Outputs
All unused LVDS output pairs can be either left floating or terminated with 100 across. If they are left floating, we recommend that there is no trace attached.
EPAD Thermal Release Path
The EPAD provides heat transfer from the device to the P.C. board. The exposed metal pad on the PCB is connected to the ground plane through thermal vias. To guarantee the device's electrical and thermal performance, EPAD must be soldered to the exposed metal pad on the PCB, as shown in Figure 4. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor's Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology.
PIN
SOLDER
EPAD
SOLDER
PIN
PIN PAD
GROUND PLANE THERMAL VIA
EXPOSED METAL PAD (GROUND PAD)
PIN PAD
Figure 4. P.C. Board for Exposed Pad Thermal Release Path Example
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
9
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
2.5V LVDS Driver Termination
Figure 5 shows a typical termination for LVDS driver in characteristic impedance of 100 differential (50 single) transmission line environment. For buffer with multiple LDVS driver, it is recommended to terminate the unused outputs.
2.5V 2.5V 50
LVDS Driver R1 100
+
-
50
100 Differential Transmission Line
Figure 5. Typical LVDS Driver Termination
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
10
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS889872. Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS889872 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 2.5V + 5% = 2.625V, which gives worst case results. * Power_MAX = VDD_MAX * IDD_MAX = 2.625V * 80mA = 210mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and a multi-layer board, the appropriate value is 51.5C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.210W * 51.5C/W = 95.8C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance JA for 16 Lead VFQFN, Forced Convection
JA by Velocity Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards 0 51.5C/W
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
11
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Reliability Information
Table 7. JA vs. Air Flow Table for a 16 Lead VFQFN
JA by Velocity Linear Feet per Minute Multi-Layer PCB, JEDEC Standard Test Boards 0 51.5C/W
Transistor Count
The transistor count for ICS889872 is: 323 Pin compatible with SY89872U
Package Outline and Package Dimensions
Package Outline - K Suffix for 16 Lead VFQFN
S eating Plan e Ind ex Area N Anvil Singula tion A1 A3 L N 1 2 E2 (N -1)x e
E2 2
(Re f.) (Ref.)
(N -1)x e
(R ef.)
N &N Even
e (Ty p.) 2 If N & N
are Even
OR
To p View
b A D Chamfer 4x 0.6 x 0.6 max OPTIONAL 0. 08 C C
(Ref.)
e D2 2 D2
N &N Odd
Th er mal Ba se
Table 8. Package Dimensions
JEDEC Variation: VEED-2/-4 All Dimensions in Millimeters Symbol Minimum Maximum N 16 A 0.80 1.00 A1 0 0.05 A3 0.25 Ref. b 0.18 0.30 4 ND & NE D&E 3.00 Basic D2 & E2 1.00 1.80 e 0.50 Basic L 0.30 0.50 Reference Document: JEDEC Publication 95, MO-220
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION 12 ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Ordering Information
Table 9. Ordering Information
Part/Order Number ICS889872AK ICS889872AKT ICS889872AKLF ICS889872AKLFT Marking 872A 872A TBD TBD Package 16 Lead VFQFN 16 Lead VFQFN "Lead-Free" 16 Lead VFQFN "Lead-Free" 16 Lead VFQFN Shipping Packaging Tube 2500 Tape & Reel Tube 2500 Tape & Reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDTTM / ICSTM LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
13
ICS889872AK REV. A AUGUST 22, 2007
ICS889872 DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015 408-284-8200 Fax: 408-284-2775
For Tech Support
netcom@idt.com 480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505
Europe
IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851
www.IDT.com
(c) 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA

▲Up To Search▲

Price & Availability of ICS889872

	To Download ICS889872 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .