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JBT6K48-AS
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
JBT6K48-AS
Gate Driver for TFT LCD Panel
The JBT6K48-AS is a 240-channel output gate driver for TFT-LCD. Combining the source driver JBT6K47-AS for TFT-LCD panel and the power supply IC JBT6K49-AS enables low power consumption operation. Based on high-speed CMOS, the JBT6K48-AS offers both low power consumption and high-speed operation.
Features
* * * * * * * * LCD panel drive output pins: Switching 220 pins /240 pins output LCD panel drive output voltage: 13.0 to 33.0 V Power supply voltage (VDD): 2.5 to 3.6 V Data transfer method: Bidirectional shift registers Operating temperature: -20 to 75C Package: Gold bump chip CMOS process Recommended driver: Source driver JBT6K47-AS for TFT-LCD panel Power supply IC JBT6K49-AS
Block Diagram
DI CPV U/D OCM /OE1 /OE2
Bidirectional shift registers Input circuit block Control circuit block
VDDL/R VSSL/R VGGL/R VEEL/R
Output pin switching circuit
Output circuit block
G1 G2
G3
G238 G240 G239
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PAD Specification
Item Chip size (1) (2) Chip end coordinates (3) (4) Bump pitch Bump height Size 15470 1240 -7735, 620 7735, -620 -7735, -620 7735, 620 60 15 mm mm mm Unit mm
Pin Name Input pin Output pin TEG pin DUMMY pin Alignment mark
Numbers of Pin 96 240 16 46 (Include DUV, DUG, DU) 2
Note 1: The TEG pin is a test pin reserved for electrical characteristics measurements, and must be left open.
Alignment mark specification
Pattern prohibited Al
Coordinates entry point 50 mm
30 mm 30 mm 30 mm
50 mm
50 mm 30 mm 30 mm 50 mm 30 mm
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PAD Layout
VGGL
G240
G239
G2
4
Output PAD 240 60 mm pitch single layout 4
DU
7
G1
VGGR 7
JBT6K48-AS Chip size: 15.47 1.24 mm
DU
12 DI DU U/D DU DU CPV DUV DUG DUG /OE2 VSSL OCM /OE1 DUV TEG VSSR TEST17
8
10
8
4
4
4
4
4
4
4
4
4
4
4
4
4
16
10
8 VDDR
12 VEER Alignment mark_R
VEEL
* Short-side dummy PAD (DU) 40 40 40 40 65 65
Alignment mark_L
VDDL
* Long-side power supply PAD (VGGL/R)
* Long-side input PAD 65 65
100
50 105 80
50
50 20 20 20 20 20 20
50 * Long-side output PAD (G1 to G240) 40 40 40 40
* Long-side power supply PAD (VEEL/R, VDDL/R, VSSL/R) 65 65 65 65
50
50 105 80
[Unit: mm] 20 20 20 20 20 20
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PAD Coordinates (1)
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Name VEEL VEEL VEEL VEEL VEEL VEEL VEEL VEEL VEEL VEEL VEEL VEEL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VDDL VSSL VSSL VSSL VSSL VSSL VSSL VSSL VSSL VSSL VSSL DU DU DU DU DU DU DU DU DUG DUG DUG DUG OCM X POINT Y POINT -7258 -7173 -7088 -7003 -6918 -6833 -6748 -6663 -6578 -6493 -6408 -6323 -5948 -5863 -5778 -5693 -5608 -5523 -5438 -5353 -5108 -5023 -4938 -4853 -4768 -4683 -4598 -4513 -4428 -4343 -4098 -4013 -3928 -3843 -3758 -3673 -3588 -3503 -3261 -3176 -3091 -3006 -2786 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Name OCM OCM OCM DUV DUV DUV DUV U/D U/D U/D U/D DUG DUG DUG DUG CPV CPV CPV CPV DI DI DI DI DU DU DU DU /OE2 /OE2 /OE2 /OE2 /OE1 /OE1 /OE1 /OE1 DUV DUV DUV DUV TEST17 TEST17 TEST17 TEST17 X POINT Y POINT -2701 -2616 -2531 -2311 -2226 -2141 -2056 -1836 -1751 -1666 -1581 -1361 -1276 -1191 -1106 -886 -801 -716 -631 -436 -351 -266 -181 39 124 209 294 514 599 684 769 964 1049 1134 1219 1439 1524 1609 1694 1914 1999 2084 2169 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 No. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 Name DU DU DU DU TEG1 TEG2 TEG3 TEG4 TEG5 TEG6 TEG7 TEG8 TEG9 TEG10 TEG11 TEG12 TEG13 TEG14 TEG15 TEG16 VSSR VSSR VSSR VSSR VSSR VSSR VSSR VSSR VSSR VSSR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VDDR VEER VEER VEER VEER VEER
[Unit: mm]
X POINT Y POINT 2364 2449 2534 2619 2848 2933 3018 3103 3188 3273 3358 3443 3528 3613 3698 3783 3868 3953 4038 4123 4343 4428 4513 4598 4683 4768 4853 4938 5023 5108 5353 5438 5523 5608 5693 5778 5863 5948 6323 6408 6493 6578 6663 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482 -482
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PAD Coordinates (2)
No. 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 Name VEER VEER VEER VEER VEER VEER VEER DU DU DU DU DU DU DU VGGR VGGR VGGR VGGR G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 G23 G24 G25 X POINT Y POINT 6748 6833 6918 7003 7088 7173 7258 7587 7587 7587 7587 7587 7587 7587 7463 7403 7343 7283 7170 7110 7050 6990 6930 6870 6810 6750 6690 6630 6570 6510 6450 6390 6330 6270 6210 6150 6090 6030 5970 5910 5850 5790 5730 -482 -482 -482 -482 -482 -482 -482 -305 -205 -105 -5 95 195 295 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 No. 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 Name G26 G27 G28 G29 G30 G31 G32 G33 G34 G35 G36 G37 G38 G39 G40 G41 G42 G43 G44 G45 G46 G47 G48 G49 G50 G51 G52 G53 G54 G55 G56 G57 G58 G59 G60 G61 G62 G63 G64 G65 G66 G67 G68 X POINT Y POINT 5670 5610 5550 5490 5430 5370 5310 5250 5190 5130 5070 5010 4950 4890 4830 4770 4710 4650 4590 4530 4470 4410 4350 4290 4230 4170 4110 4050 3990 3930 3870 3810 3750 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 No. 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 Name G69 G70 G71 G72 G73 G74 G75 G76 G77 G78 G79 G80 G81 G82 G83 G84 G85 G86 G87 G88 G89 G90 G91 G92 G93 G94 G95 G96 G97 G98 G99 G100 G101 G102 G103 G104 G105 G106 G107 G108 G109 G110 G111
[Unit: mm]
X POINT Y POINT 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411
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PAD Coordinates (3)
No. 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 Name G112 G113 G114 G115 G116 G117 G118 G119 G120 G121 G122 G123 G124 G125 G126 G127 G128 G129 G130 G131 G132 G133 G134 G135 G136 G137 G138 G139 G140 G141 G142 G143 G144 G145 G146 G147 G148 G149 G150 G151 G152 G153 G154 X POINT Y POINT 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 No. 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 Name G155 G156 G157 G158 G159 G160 G161 G162 G163 G164 G165 G166 G167 G168 G169 G170 G171 G172 G173 G174 G175 G176 G177 G178 G179 G180 G181 G182 G183 G184 G185 G186 G187 G188 G189 G190 G191 G192 G193 G194 G195 G196 G197 X POINT Y POINT -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -3990 -4050 -4110 -4170 -4230 -4290 -4350 -4410 -4470 -4530 -4590 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 No. 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 Name G198 G199 G200 G201 G202 G203 G204 G205 G206 G207 G208 G209 G210 G211 G212 G213 G214 G215 G216 G217 G218 G219 G220 G221 G222 G223 G224 G225 G226 G227 G228 G229 G230 G231 G232 G233 G234 G235 G236 G237 G238 G239 G240
[Unit: mm]
X POINT Y POINT -4650 -4710 -4770 -4830 -4890 -4950 -5010 -5070 -5130 -5190 -5250 -5310 -5370 -5430 -5490 -5550 -5610 -5670 -5730 -5790 -5850 -5910 -5970 -6030 -6090 -6150 -6210 -6270 -6330 -6390 -6450 -6510 -6570 -6630 -6690 -6750 -6810 -6870 -6930 -6990 -7050 -7110 -7170 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411 411
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PAD Coordinates (4)
No. 388 389 390 391 392 393 394 395 396 397 398 3/4 3/4 Name VGGL VGGL VGGL VGGL DU DU DU DU DU DU DU Alignment mark_L Alignment mark_R
[Unit: mm]
X POINT Y POINT -7283 -7343 -7403 -7463 -7587 -7587 -7587 -7587 -7587 -7587 -7587 -7548 7548 411 411 411 411 295 195 95 -5 -105 -205 -305 -433 -433
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Pin Description
Pin Name I/O Function Data transfer direction switching pin Specifies the shift direction of the shift registers. U/D I * U/D = H: G1 (R) G2 (R) G3 (R) G4 (R) G5 (R) ... (R) G240 * U/D = L: G240 (R) G239 (R) G238 (R) G237 (R) ... (R) G1 Use the pin at DC level. For High, VDD; for Low, VSS. CPV I Vertical shift clock Shift clock for the shift registers. Data are shifted in sync with the rising edge of CPV. Vertical shift data input pin The data is input in the first stage of the shift register and latched in the shift register at the first rising edge of the CPV. Output switching This pin switches numbers of LCD panel drive pins. OCM I OCM = H: 220 Output mode (G221 to G240 pin output indefinite voltage.) OCM = L: 240 Output mode Output mode switching pin (1) Mode /OE1 I H L Normal mode All output off mode (ASYNC) Output Mode
DI
I
Output mode switching pin (2) Mode /OE2 I H L Normal mode All output off mode (sync with CPV) Output Mode
G1 to G240 VDDL/VDDR VSSL/VSSR VGGL/VGGR VEEL/VEER TEST17 TEG1 to 16
O 3/4 3/4 3/4 3/4 I I
LCD panel drive pins. Power supply pin for internal logic Power supply pin for internal logic LCD panel drive pins LCD panel drive pins Test pin (1) The pull down resistor is connected to this pin, and must be left open. Test pin (2) This is a test pin, and must be left open. Dummy pin These pins are dummies, and each pin has an electric function such as, VDD, VSS or floating. The details are listed below.
DUG DUV DU 3/4
Pin Name DUG DUV DU Note 2: DUG ... A dummy pin for VSS. DUV ... A dummy pin for VDD.
Remarks
DU ... A dummy pin for floating.
The DUG pin and the DUV pin are used to fix the level by the adjacent input pin. Do not use them as the reference power supply.
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Device Function and Operation
* Setting the Data Transferring Direction Setting U/D pin enables JBT6K48-AS shift the shift register in sync with the falling edge of the vertical shift clock input from the CPV pin. When the U/D pin data is fixed before the DI data is input, the function becomes valid. Inputting Data The data is latched at the first falling edge of the CPV. The signal is output from the first falling edge of the CPV recognized the data. Switching Numbers of the Output Pin The valid output pin can be switched either 220 pins or 240 pins using the COM pin. The details about the valid output pins are listed below.
*
*
OCM 0 1
Valid output pin G1 to G240 G1 to G220
Remarks
G221 to G240 output indefinite voltage level
OCM 0 0 1 1
U/D 0 1 0 1
Shifting Direction G240 (R) G239 (R) G238 (R) ...... (R) G3 (R) G2 (R) G1 G1 (R) G2 (R) G3 (R) ...... (R) G238 (R) G239 (R) G240 G220 (R) G219 (R) G218 (R) ...... (R) G3 (R) G2 (R) G1 G1 (R) G2 (R) G3 (R) ...... (R) G218 (R) G219 (R) G220
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* Output mode switching function JBT6K48-AS is capable to control the output signal using /OE1 and /OE2 pins. The /OE2 signal proceeds the /OE1 signal at output-off mode.
/OE2 1
/OE1 1 0 1 Normal mode (Fig. 1)
Functions
Output signals turn off unsynchronizing with CPV (Fig. 3) Output signals turn off synchronizing with CPV (Fig. 2) /OE2 has priority no relation to /OE1 and output signals turn off
0 0
a)
Normal operation mode
DI 1 CPV 2 3 4 5 236 237 238 239 240
G1 (G240)
G2 (G239)
G3 (G238)
G4 (G237)
G237 (G4)
G238 (G3)
G239 (G2)
G240 (G1)
(
) indicates when U/D is Low.
Figure 1
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b) Normal mode + Sync off mode (/OE2)
DI 1 CPV 2 3 4 5
/OE2
G1 (G240)
G2 (G239)
G3 (G238)
G4 (G237)
G5 (G236)
G6 (G235)
G7 (G234)
G8 (G233)
G9 (G232)
G10 (G231)
G11 (G230)
G239 (G2)
G240 (G1)
Figure 2
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c) Normal mode+ ASYNC off mode (/OE1)
DI 1 CPV 2 3 4 5
/OE1
G1 (G240)
G2 (G239)
G3 (G238)
G4 (G237)
G5 (G236)
G6 (G235)
G7 (G234)
G8 (G233)
G239 (G2)
G240 (G1)
Figure 3
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d) Synchronizing off mode + un-synchronizing off mode
DI 1 CPV 2 3 4 5
/OE1
/OE2
G1 (G240)
G2 (G239)
G3 (G238)
G4 (G237)
G5 (G236)
G6 (G235)
G7 (G234)
G8 (G233)
G9 (G232)
Figure 4
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* Recommended Power-on and Power-off Sequence If the logic power supply is applied under the floating condition, the device might be destructed by the large amounts of current because the LCD panel drive voltage is high. For this reason, apply the logic power supply first, then turn the LCD panel drive power supply on, or turn the both power supply on at the same timing. The internal logic condition is instable immediately after the logic power-on. Therefore, initialize the internal logic by transferring the clock for the continuous connecting and setting period using the CPV and DI input. Turn the LCD panel drive power off first, then turn the logic power off, or turn the both power off at the same timing.
VGG VDD
t VEE VEE/VOFF
Figure 1
*
Relations between power supplies
LCD drive output
VGG Logic input Internal logic Level shifter
VDD VSS
VEE
Maximum Ratings (Unless Otherwise Noted, VSS = 0 V, Ta = 25C)
Characteristics Supply voltage (1) Supply voltage (2) Supply voltage (3) Input voltage Operating temperature Storage temperature Symbol VDD VEE VGG - VEE VIN Topr Tstg Rating -0.3 to 6.5 -20.0 to 0.3 -0.3 to 45.0 -0.3 to VDD + 0.3 -20 to 75 -55 to 125 Unit V V V V C C
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JBT6K48-AS
Electrical Characteristics DC Characteristics (1) Unless Otherwise Noted, VGG - VEE = 16.0 to 33.0 V, VDD = 2.5 to 3.6 V, Ta = -20 to 75C
Characteristics Supply voltage 1) Supply voltage (2) Supply voltage (3) Supply voltage (4) Low level Input voltage High level Output resistance Low level High level VIH ROL ROH IIN fCPV1 CL1 3/4 VOUT = VOFF + 0.5 V VOUT = VGG - 0.5 V 3/4 3/4 (Note 3) Symbol VDD VEE VGG iVGG - VEEi VIL 3/4 3/4 Test Circuit 3/4 3/4 3/4 3/4 Test Condition 3/4 3/4 3/4 3/4 Min 2.5 -16.5 8 16.0 VSS 0.8 VDD 3/4 3/4 -1 3/4 3/4 Typ. 3/4 -11.0 12.5 3/4 3/4 3/4 3/4 3/4 3/4 20 36 Max 3.6 -5 16.5 33.0 0.2 VDD VDD 7.5 kW 7.5 1 50 100 mA kHz pF DI, CPV, U/D, /OE1, /OE2, OCM CPV G1~G240 G1 to G240 Unit V V V V Relevant Pin VDDL/R VEEL/R VGGL/R VGGL/R, VEEL/R DI, CPV, U/D, /OE1, /OE2, OCM
V
Input leakage current Operating frequency Output load capacitance
3/4 3/4 3/4
Note 3: Load capacitance per an output pin.
DC Characteristics (2) Unless Otherwise Noted, VGG - VEE = 16.0 to 33.0 V, VDD = 2.5 to 3.6 V, Ta = -20 to 75C Typical value is VDD = 3.0 V, VGG - VEE = 30.0 V, CPV = 20 kHz,
Ta = 25C
Symbol IGG IEE IDD ISS Characteristics Current dissipation (1) Current dissipation (2) Current dissipation (3) Current dissipation (4) Test Circuit 3/4 3/4 3/4 3/4 3/4 Test Condition (Note 4, 5) (Note 4, 5) (Note 4) (Note 4) Min 3/4 3/4 3/4 3/4 -1 Typ. 3.2 3.3 1.8 1.7 3/4 Max 30.0 -30.0 12.5 -13.0 mA Unit Relevant Pin VGGL/R VEEL/R VDDL/R VSSL/R VGGL/R, VEEL/R, VDDL/R, VSSL/R
Current dissipation (5)
STB
(Note 6)
1
Note 4: CPV = 50 kHz Note 5: fFram = 70 Hz Note 6: CPV = "L"
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AC Characteristics Unless Otherwise Noted, VGG - VEE = 30.0 V, VDD = 2.5 to 3.6 V, Ta = -20 to 75C
Characteristics CPV cycle time CPV pulse width Low level CPV pulse width High level CPV rising/falling time /OE enable time Data setup time Symbol tcycCPV tCPVL tCPVH trCPV /tfCPV twOE tsDI tsOE Data hold time Output delay time (1) Output delay time (2) Output rising/falling time thDI thOE tpdG tpdOE trOG /tfOG Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 CL = 100 pF CL = 100 pF CL = 100 pF Test Condition 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1 100 ns 100 300 ns 300 2 2 1.5 ms ms ms 500 5 100 Min Typ. Max 10 Unit ms ns ms ns ms
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tcycCPV tCPVH CPV VIH VIH VIL VIL tsDI tCPVL trCPV VIH VIH VIL thDI tfCPV
DI
VIH VIL
CPV
VIL
tsOE /OE1 VIL
thOE VIL
CPV
VIL tpdG
VIL tpdG
G1 to G240
90% 50% 10% trOG
90% 50% 10% tfOG
twOE /OE1 50% tpdOE 50% tpdOE
G1 to G240
50%
50%
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RESTRICTIONS ON PRODUCT USE
000707EBM
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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