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| 8 Bit Microcontroller TLCS-870/C Series TMP86CH06AUG TMP86CH06AUG The information contained herein is subject to change without notice. 021023 _ D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2006 TOSHIBA CORPORATION All Rights Reserved Page 2 TMP86CH06AUG Differences between the TMP86CH06AUG and the TMP86CH06U The following table shows the function and specification differences between the TMP86CH06AUG and its previous version TMP86CH06U/UG. Please be careful about these differences if you have switched from the TMP86CH06U to the TMP86CH06AUG. Also, there is correction in data sheet of the TMP86CH06AUG. Differences in characteristics Item CGCR register Clock gear TMP86CH06AUG Not disclosed (Reserved) Not to be set Writing is prohibited, and reading yields an undefined value. Do not set. Do not set. High 2.2 V Low Vdd/2 CL = 50 pF 1.5 t -35 ns (min) 58 ns 0.5 t -32 ns (min) 0 ns 1.8 V VDD < 2.0 V : Topr = - 20 to 85 C 2.0 V VDD 5.5 V : Topr = - 40 to 85 C TMP86CH06U CGCR register 0030H To be set CGCR DV1CK DVCK Output level (ALE pin only) AC characteristic (tACH) AC characteristic (tCA) Operating temperature (Topr) Correction in Data sheet Item Guaranteed VDD in external bus mode TMP86CH06AUG Added "VDD = 4.5 V to 5.5 V" to AC Characteristics TMP86CH06U/UG Lack of condition The following name of control registers or bits is different from TMP86CH06U. However, the contents of them are the same as TMP86CH06U. Therefore, the same software can be used for TMP86CH06AUG, if you have switched from the TMP86CH06U to the TMP86CH06AUG. Name of control registers or bits Name of register or control bit Bit 7 in INTSEL Bit 3 in INTSEL Bit 2 in INTSEL Bit 1 in INTSEL Bit 0 in INTSEL UART0 control register 1 UART0 control register 2 UART1 control register 1 UART1 control register 2 SIO data buffer TMP86CH06AUG IL8ER IL12ER IL13ER IL14ER IL15ER UART0CR1 UART0CR2 UART1CR1 UART1CR2 SIOBRx (x=0 to 7) TMP86CH06U INTRX0ER INTOC0ER INTRX1ER INTTXDER INT5ER UART0CRA UART0CRB UART1CRA UART1CRB SIODBR Page 3 TMP86CH06AUG Page 4 Revision History Date 2006/2/23 2006/8/30 Revision 1 2 First Release Contents Revised Table of Contents Differences between the TMP86CH06AUG and the TMP86CH06U TMP86CH06AUG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory Address Map............................................................................................................................... Program Memory (MaskROM).................................................................................................................. Data Memory (RAM) ................................................................................................................................. External Memory Interfaces ...................................................................................................................... Controlling External Bus Controller Wait Controller 2.1.1 2.1.2 2.1.3 2.1.4 7 8 8 8 2.1.5 2.1.4.1 2.1.4.2 2.1.4.3 2.1.5.1 2.1.5.2 2.1.5.3 2.1.5.4 2.1.6.1 2.1.6.2 2.1.6.3 2.1.6.4 System Clock Controller ......................................................................................................................... 12 Clock Generator Timing Generator Operation Mode Control Circuit Operating Mode Control External Reset Input Address trap reset Watchdog timer reset System clock reset 2.1.6 Reset Circuit ........................................................................................................................................... 34 3. Interrupt Control Circuit 3.1 3.2 3.3 3.4 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Interrupt acceptance processing is packaged as follows........................................................................ 41 Saving/restoring general-purpose registers ............................................................................................ 42 Interrupt return ........................................................................................................................................ 44 Using PUSH and POP instructions Using data transfer instructions 3.2.1 3.2.2 Interrupt master enable flag (IMF) .......................................................................................................... 38 Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 38 3.4.1 3.4.2 3.4.3 3.5.1 3.5.2 3.4.2.1 3.4.2.2 3.5 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Address error detection .......................................................................................................................... 45 Debugging .............................................................................................................................................. 45 i 3.6 3.7 3.8 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 4. Special Function Register (SFR) 4.1 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5. I/O Ports 5.1 5.2 5.3 5.4 5.5 Port P0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 53 56 57 58 6. Watchdog Timer (WDT) 6.1 6.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT)...................................................................................................... Watchdog Timer Reset ........................................................................................................................... Selection of Address Trap in Internal RAM (ATAS) ................................................................................ Selection of Operation at Address Trap (ATOUT) .................................................................................. Address Trap Interrupt (INTATRAP)....................................................................................................... Address Trap Reset ................................................................................................................................ 62 63 64 64 65 6.3 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 66 66 66 67 6.3.1 6.3.2 6.3.3 6.3.4 7. Time Base Timer (TBT) 7.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Configuration .......................................................................................................................................... 69 Control .................................................................................................................................................... 69 Function .................................................................................................................................................. 70 Configuration .......................................................................................................................................... 71 Control .................................................................................................................................................... 71 7.1.1 7.1.2 7.1.3 7.2.1 7.2.2 7.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8. Extended Timer-Counter (ETC0) 8.1 8.2 8.3 8.4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Controlling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Source Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Capturing input, Output comparing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Capturing input ....................................................................................................................................... 79 Free Running Timer Mode ...................................................................................................................... 76 Event-counter Mode ............................................................................................................................... 77 8.3.1 8.3.2 8.4.1 ii 8.5 8.4.2 Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Output Comparing .................................................................................................................................. 81 9. 8-Bit TimerCounter (TC0, TC1) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8-Bit Timer Mode (TC0 and 1) ................................................................................................................ 92 8-Bit Event Counter Mode (TC0, 1) ........................................................................................................ 93 8-Bit Programmable Divider Output (PDO) Mode (TC0, 1)..................................................................... 93 8-Bit Pulse Width Modulation (PWM) Output Mode (TC0, 1).................................................................. 96 16-Bit Timer Mode (TC0 and 1) .............................................................................................................. 98 16-Bit Event Counter Mode (TC0 and 1) ................................................................................................ 99 16-Bit Pulse Width Modulation (PWM) Output Mode (TC0 and 1).......................................................... 99 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC0 and 1) ............................................. 102 Warm-Up Counter Mode....................................................................................................................... 104 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 9.3.9.1 9.3.9.2 10. Synchronous Serial Interface (SIO) 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Clock source ....................................................................................................................................... 109 Shift edge............................................................................................................................................ 111 Leading edge Trailing edge Internal clock External clock 10.3.1.1 10.3.1.2 10.3.2.1 10.3.2.2 10.3.1 10.3.2 10.4 10.5 10.6 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 4-bit and 8-bit transfer modes ............................................................................................................. 112 4-bit and 8-bit receive modes ............................................................................................................. 114 8-bit transfer / receive mode ............................................................................................................... 115 10.6.1 10.6.2 10.6.3 11. Asynchronous Serial interface (UART0 ) 11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 122 Data Receive Operation ..................................................................................................................... 122 Parity Error.......................................................................................................................................... 123 Framing Error...................................................................................................................................... 123 117 118 120 121 121 122 122 122 11.8.1 11.8.2 11.9.1 11.9.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 iii 11.9.3 11.9.4 11.9.5 11.9.6 Overrun Error ...................................................................................................................................... Receive Data Buffer Full..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 123 124 124 125 12. Asynchronous Serial interface (UART1 ) 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 132 Data Receive Operation ..................................................................................................................... 132 133 133 133 134 134 135 127 128 130 131 131 132 132 132 12.8.1 12.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Parity Error.......................................................................................................................................... Framing Error...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 12.9.1 12.9.2 12.9.3 12.9.4 12.9.5 12.9.6 13. Input/Output Circuitry 13.1 13.2 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 14. Electrical Characteristics 14.1 14.2 14.3 14.4 14.5 14.6 Absolute Maximum Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLOCK ............................................................................................................................................... 142 External Memory Interface (Multiplexed Bus) ..................................................................................... 142 ........................................................................................................................................................... 144 139 140 141 142 14.4.1 14.4.2 Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Note 3: 15. Package Dimension This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). iv TMP86CH06AUG CMOS 8-Bit Microcontroller TMP86CH06AUG Product No. TMP86CH06AUG ROM (MaskROM) 16384 bytes RAM 512 bytes Package P-LQFP44-1010-0.80B OTP MCU TMP86PH06UG Emulation Chip TMP86C906XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) - 132 types & 731 basic instructions 2. 21interrupt sources (External : 6 Internal : 15) 3. Input / Output ports (35 pins) Large current output: 8pins (Typ. 20mA), LED direct drive 4. Watchdog Timer 5. Prescaler - Time base timer - Divider output function 6. Extended 16bit Timer-Counter - External input Compare output Capture input 7. 8-bit timer counter : 2 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 060116EBP * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86CH06AUG 8. 8-bit SIO/UART0: 1 ch 9. 8-bit UART : 1 ch 10. Clock operation Single clock mode Dual clock mode 11. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz 1.8 V to 5.5 V at 4.2MHz /32.768 kHz Release by Page 2 TMP86CH06AUG 1.2 Pin Assignment (AD4) P04 (AD5) P05 (AD6) P06 (AD7) P07 TEST XIN VSS XOUT VDD (INT5/STOP) P20 Figure 1-1 Pin Assignment Page 3 RESET 1 2 3 4 5 6 7 8 9 10 11 NC (ETC0) P12 (DVO) P13 (TO1) P14 (WR) P15 (RD) P16 (ALE) P17 (AD0) P00 (AD1) P01 (AD2) P02 (AD3) P03 33 32 31 30 29 28 27 26 25 24 23 P11 (INT1/WAIT) P10 (INT0/CLK) P37 (OC0/INT2/A15) P36 (IC0/A14) P35 (TO0/A13) P34 (A12) P33 (A11) P32 (A10) P31 (A9) P30 (A8) P47 (TXD1/INT4) 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 P46(RXD1/INT3) P45 P44(SO/TXD0) P43(SI/RXD0) P42(SCK) P41(TI1) P40 EA P22(XTOUT) P21(XTIN) NC 1.3 Block Diagram TMP86CH06AUG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86CH06AUG 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/2) Pin Name P07 AD7 P06 AD6 P05 AD5 P04 AD4 P03 AD3 P02 AD2 P01 AD1 P00 AD0 P17 ALE Pin Number 4 Input/Output IO IO IO IO IO IO IO I IO IO IO IO IO IO IO IO IO O PORT07 Address/Data bus 7 PORT06 Address/Data bus 6 PORT05 Address/Data bus 5 PORT04 Address/Data bus 4 PORT03 Address/Data bus 3 PORT02 Address/Data bus 2 PORT01 Address/Data bus 1 PORT00 Address/Data bus 0 PORT17 Address Latch Enable(The negative edge of ALE supplies an address latch timing on AD0 to AD7 for External Memory) PORT16 Read(Generates strobe signal to read data from External Memory) PORT15 Write(Generates strobe signal to write data on External Memory) PORT14 TO1 output PORT13 Divider Output PORT12 Extended Timer-Counter PORT11 External interrupt 1 input Wait(Wait request from external Memory) PORT10 External interrupt 0 input Clock(Clock output) PORT22 Resonator connecting pins(32.768kHz) for inputting external clock PORT21 Resonator connecting pins(32.768kHz) for inputting external clock PORT20 STOP mode release signal input External interrupt 5 input Functions 3 2 1 44 43 42 41 40 P16 RD 39 IO O P15 WR 38 IO O IO O IO O IO I IO I I IO I O IO O P14 TO1 37 P13 DVO 36 P12 ETC0 P11 INT1 WAIT 35 33 P10 INT0 CLK 32 P22 XTOUT 14 P21 XTIN P20 STOP INT5 13 IO I IO I I 10 Page 5 1.4 Pin Names and Functions TMP86CH06AUG Table 1-1 Pin Names and Functions(2/2) Pin Name P37 OC0 INT2 A15 P36 IC0 A14 P35 TO0 Pin Number Input/Output IO O I I IO I I IO O I IO I IO I IO I IO I IO I IO O I IO I I IO IO O O IO I I IO IO IO I IO I O IO I IO I I Functions PORT37 Output Compare 0 for Extended Timere External interrupt 2 input Address bus 15 PORT36 Capture Input 0 for Extended Timer Address bus 14 PORT35 TO0 output Address bus 13 PORT34 Address bus 12 PORT33 Address bus 11 PORT32 Address bus 10 PORT31 Address bus 9 PORT30 Address bus 8 PORT47 UART data output 1 External interrupt 4 input PORT46 UART data input 1 External interrupt 3 input PORT45 PORT44 Serial Data Output UART data output 0 PORT43 Serial Data Input UART data input 0 PORT42 Serial Clock I/O PORT41 TI1 input PORT40 Resonator connecting pins for high-frequency clock Resonator connecting pins for high-frequency clock EaEZEbEgieooO Test pin for out-going test (Be fixed to low) +5V 0(GND) Non Connection 31 30 29 A13 P34 A12 P33 A11 P32 A10 P31 A9 P30 A8 P47 TXD1 INT4 P46 RXD1 INT3 P45 P44 SO TXD0 P43 SI RXD0 P42 SCK 28 27 26 25 24 23 22 21 20 19 18 P41 TI1 P40 XIN XOUT RESET 17 16 6 8 11 5 11 7 34 TEST VDD VSS NC Page 6 TMP86CH06AUG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit. 2.1.1 Memory Address Map The TMP86CH06AUG memory consists of 3 blocks: ROM, RAM, and SFR (Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86CH06AUG memory address map. The general-purpose registers are not assigned to the RAM address space. 0000H SFR 003FH 0040H 64 byte RAM 512byte 023FH 0240H ROM: RAM: SFR: External memory includes; Program memory Vector table Random access memory includes: Data memory Stack Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word BFFFH C000H 16K bytes Mask ROM FFC0H 32bytes FFE0H FFFFH Vector table for vector call instructions Vector table for interrupts 32bytes Figure 2-1 Memory Address Map Page 7 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG 2.1.2 Program Memory (MaskROM) The TMP86CH06AUG has a 16 K x 8 bits (Address C000H to FFFFH) of program memory (Mask ROM ). Of the 64-Kbyte memory space, the space excluding the SFR and internal RAM areas can be used as external program memory space. When the EA pin is connected to GND, this space becomes external memory. A program code placed on the internal RAM can be excutable when a certain procedure is executed ( See " 2.1.6.2 Address trap reset "). 2.1.3 Data Memory (RAM) Data memory consists of internal data memory (Internal ROM or RAM). The TMP86CH06AUG has 512 bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to "00H". LD LD LD SRAMCLR: LD INC DEC JRS HL, 0040H A, H BC, 01FFH (HL), A HL BC F, SRAMCLR ; Start address setup ; Initial value (00H) setup ; 2.1.4 External Memory Interfaces The TMP86CH06AUG can be connected with the external memory through address bus, a data bus, and the control bus. It is available up to 64 Kbytes of data memory area except the area where the internal RAM and SFR are located. Data bus and the lower bits of address bus are multiplexed. * The operation mode is selected from the following three by setting EA terminal and control register EXPCR. 1) Single chip mode: (EA = 1, EXPCR TMP86CH06AUG The TMP86CH06AUG can keep CPU from reading the data on internal ROM, while its read instruction is located in external memory. Note:The transfer destination data of the vector table (located from FFC0H to FFFFH) is not protected. 2.1.4.1 Controlling The external memory interfaces are controlled by expansion control register (EXPCR) and wait control register (WAITCR). EXPCR directly manages RD, WR and address bus output. And, assigning terminals to RD or WR subsequently provides AD7 to 0 and ALE. In order to utilize external memory, port directions whether to be input or output is determined regardless of each bit on control register. After reset, EXPCR is a register which can be written only once. Therefore, the second and the following write operation cannot modify the data on EXPCR. External Access Control EXPCR (0031H) 7 6 ABUSEN 5 4 - 3 RDOE 2 WROE 1 - 0 - (Initial value: 111* 11**) EA "0" (Initial value: 000* 00**) EA "1" ABUSEN Upper bits on address bus output enable [A15 to A8] 000: input/output port 001: A9 to A8 output 010: A10 to A8 output 011: A11 to A8 output 100: A12 to A8 output 101: A13 to A8 output 110: A14 to A8 output 111: A15 to A8 output Other terminals on P3 port keep their input output mode. WR 1 time RDOE WROE RD strobe output enable 0: RD strobe output Disable 1: RD strobe output Enable 0: WR strobe output Disable 1: WR strobe output Enable Write only Write only WR strobe output enable Note 1: Once either RDOE or WROE or both are enabled to "1", the following terminals are utilized for external memory interface; therefore they cannot be used for general-purpose input/output ports. * AD7 to 0 (P07 to P00) * ALE (P17) * RD (P16: if RDOE="1") or WR (P15:if WROE = "1") * CLK (P10) Note 2: EXPCR is a write only register and must not be used with any of the read-modify-write instructions. WAITCR manages security for internal ROM, number of waiting cycles and waiting clock output. When control waiting cycles, WAITCR selects waiting mode from three: no-wait, 1-state wait or (1+n)state wait. WAITCR selects output mode from the following: High output by controlling waiting clock output when an external bus is used, CLK output during waiting cycles, CLK output at all times. When the internal ROM is disabled while programs on the external memory and the internal RAM are operating, data in C000H to FFBFH on the ROM cannot be read under software control. WAITCR is a register which can be written only once. Therefore, the second and the following write operation cannot modify this bit. Page 9 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG WAIT Control Register WAITCR (0032H) 7 WAIT 6 5 - 4 "0" 3 CLKV 2 1 - 0 RDMEM (Initial value: 01*0 11*1) EA "0" (Initial value: 00*0 00*1) EA "1" WAIT Control waiting cycles 00: Wait Disable 01: (Fixed) 1-cycle wait Enable 10: (1+n)-cycle wait Enable (WAIT pin) 11: Wait Disable 0* : "H"output (CLK output disable) 10: CLK output enable during waiting cycles 11: always CLK output Enable 0: Read out Disable 1: Read out Enable Write only CLKV CLK output mode R/W WR 1 time RDMEM security for internal ROM reading out Note 1: The timing chart during CLK output enable is described fcgck CLK Note 2: P11 terminal is assigned for WAIT input when WAIT is ; in the condition, it cannot be used for general-purpose input/output port. Note 3: WAITCR include a write only register and must not be used with any of the read-modify-write instructions. Note 4: Make sure to set 0 on bit 4. Note 5: When external memory is used, the P10 pin cannot be used as an external interrupt input (INT0) or an I/O port as CLK is output from this pin. 2.1.4.2 External Bus Controller The TMP86CH06AUG is interfaced to an external memory via following buses. (1) Address/Databus: A15 to 8, AD7 to 0 There are 16-bit output address bus and 8-bit bidirectional databus. The lower 8 bits for address bus and 8 bits for databus are multiplexed. All of the terminals, AD15 to 8 and AD7 to 0, are used also for port. These ports functions as address/databus by setting register EXPCR. Upper bits of address bus can be output either partially or totally. (2) Control signals: RD, WR, ALE RD pulse indicates for reading, WR pulse indicates for writing, and ALE pulse indicates for address latch enable. These terminals are used also for timing for port, and these ports operate as such control signals. RD becomes "L" level on external memory read cycle, and WR becomes "L" level on external memory write cycle. Both RD and WR keep "H" level on both dummy cycle and internal memory read/write cycle. Page 10 TMP86CH06AUG (a) Timing chart on external memory interface A15 to 8 AD7 to 0 ALE WR RD AD7 to 0 Data-out . AD7 to 0 Data-in (b) Example for connecting external ROM/RAM TMP86CH06A A7 to 0 A7 to 0 Address Latch circuit A7 to 0 Address decoder ALE A15 to 8 A15 to 8 External ROM Chip Select Signal R WR External RAM 2.1.4.3 Wait Controller The number of wait cycles is selected from three: no wait, fixed 1-cycle wait and (1+n)-cycle wait. (1) Fixed 1-cycle wait 1-state wait operation is executed regardless of WAIT terminal condition. The following diagram indicates the wait cycle, under WAIT = "01" and /CLK outputs during waiting cycles. Page 11 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG A15 to A8 AD7 to AD0 ALE External memory area A Data - in External memory area A Data - out Internal memory area Internal memory area A A RD WR WAIT CLK Wait Wait (2) (1+n)-cycle wait Continuous wait operation is executed as far as "L" input is detected from WAIT terminal, after 1cycle wait operation is executed. The following diagram indicates the wait cycle, under WAIT="10" and CLK outputs during waiting cycles. A15 to A8 AD7 to AD0 ALE RD WR WAIT CLK A External memory area Data - in External memory area A Data - out 1- cycle wait 1- cycle wait 1 - cycle wait 2.1.5 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register Clock generator XIN fc TBTCR 0036H High-frequency clock oscillator XOUT XTIN Timing generator fs Standby controller 0038H SYSCR1 0039H SYSCR2 Low-frequency clock oscillator XTOUT System clocks Clock generator control System control registers Figure 2-2 System Colck Control Page 12 TMP86CH06AUG 2.1.5.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clocks and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. High-frequency clock Low-frequency clock XOUT (Open) XTIN XTOUT XTIN XTOUT (Open) XIN XOUT XIN (a) Crystal/Ceramic resonator (b) External oscillator (c) Crystal (d) External oscillator Figure 2-3 Examples of Resonator Connection Note: The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. 2.1.5.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output (DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode Table 2-1 Divider Output Capability Divider Output Capability DV1 fc/23 x DV2 fc/24 O DV3 fc/25 O DV4 fc/26 O DV5 fc/27 O Note: When selecting DV1, DV2, DV3, DV4 or DV5 for the operating clock of timer, SIO, etc, check Table 2-1 to see that the divider output is possible (marked with O). If the divider output is impossible (marked with x), do not select them for the operating clock. Page 13 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG Table 2-2 Input Clock to 7th Stage of the Divider Single-clock mode NORMAL1, IDLE1 mode DV7CK=0 fc/28 fc/28 DV7CK=1 fs fs Dual-clock mode NORMAL2, IDLE2 mode (SYSCK=0) SLOW, SLEEP mode (SYSCK=1) Note 1: Do not set DV7CK to "1" when single clock mode is selecte. Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: In SLOW and SLEEP mode, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. Note 4: During the warm-up period after STOP mode is released and in IDLE0 mode, the 6th stage of the divider is output to the 7th stage of the divider regardless of the DV7CK setting. (1) Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, TBTCR fc or fs Main system clock generator SYSCK DV7CK Prescaler Machine cycle counters Divider 123456 High-frequency clock fc Low-frequency clock fs S A Y B Divider 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 12 Multiplexer DV1 DV2 DV3 DV4 DV5 DV6 DV7 DV8 DV9 DV10 DV11 DV12 DV13 DV14 DV15 DV16 DV17 DV18 DV19 DV20 DV21 S B0 B1 A0 Y0 A1 Y1 Multiplexer Warm-up controller Watchdog timer Timer/ counters Time base timer Serial interface Divider output circuit Figure 2-4 Configuration of Timing Generator Page 14 TMP86CH06AUG Table 2-3 Division Ratio of Divider DV7CK=0 DV1 DV2 DV3 DV4 DV5 DV6 DV7 DV8 DV9 DV10 DV11 fc/2 3 DV7CK=1 fc/2 3 DV7CK=0 DV12 DV13 DV14 DV15 DV16 DV17 DV18 DV19 DV20 DV21 fc/2 14 DV7CK=1 fs/26 fs/27 fs/28 fs/29 fs/210 fs/211 fs/212 fs/213 fs/214 fs/215 fc/24 fc/25 fc/26 fc/27 fc/28 fc/29 fc/210 fc/211 fc/212 fc/213 fc/24 fc/25 fc/26 fc/27 fc/28 fs/2 fs/22 fs/23 fs/24 fs/25 fc/215 fc/216 fc/217 fc/218 fc/219 fc/220 fc/221 fc/222 fc/223 TBTCR (0036H) 7 (DVOEN) 6 (DVOCK) 5 4 DV7CK 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0**0 0***) DV7CK Selection of input to the 7th stage of the divider 0: fc/28 [Hz] 1: fs R/W Note 1: In single clock mode, do not set DV7CK to "1". Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. (2) Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock (fm) State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle Page 15 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG Table 2-4 Example of Macheine Cycle Frequency fc = 16.0 MHz fc = 12.5MHz High-frequency clock fc = 4.2 MHz fc = 1 MHz Low-frequency-clock fs = 32.8 kHz Machine cycle 0.25 s 0.32 s 0.95 s 4 s 122 s 2.1.5.3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-frequency clocks, and switches the main system clock. There are two operating modes: Single clock and dual clock. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. (1) Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (a) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86CH06AUG are placed in this mode after reset. (b) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2 Page 16 TMP86CH06AUG When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back again. IDLE0 mode is entered and returned regardless of how TBTCR Note: With the TLCS-870/C Series, no option is provided to select the clock mode after release of reset. When reset is released it becomes the single mode. (a) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (b) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. On-chip peripherals are triggered by the low-frequency clock. As the SYSCK on SYSCR2 becomes "0", the hardware changes into NORMAL2 mode. As SYSCR2 Page 17 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG (e) SLEEP1 mode In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW mode. In SLOW and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (f) SLEEP2 mode The SLEEP2 mode is the idle mode corresponding to the SLOW2 mode. The status under the SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the high-frequency clock. (g) SLEEP0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by setting "1" on SYSCR2 Page 18 TMP86CH06AUG IDLE0 mode Reset release RESET IDLE1 mode (a) Single-clock mode Note 2 SYSCR2 IDLE2 mode Interrupt NORMAL2 mode SYSCR2 SLEEP1 mode (b) Dual-clock mode SYSCR2 Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR Figure 2-6 Operating Mode Transition Diagram Oscillator Operating Mode High Frequency Low Frequency CPU Core TBT Other Peripherals Reset Operate Machine Cycle Time RESET NORMAL1 Single clock IDLE1 IDLE0 STOP NORMAL2 IDLE2 SLOW2 Dual clock SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP Stop Stop Oscillation Stop Oscillation Reset Operate Stop Halt Reset Operate 4/fc [s] Halt Operate with high frequency Halt - 4/fc [s] Oscillation Halt Operate with low frequency Halt Operate with low frequency Operate Operate 4/fs [s] Halt Halt Halt - Page 19 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG System Control Register 1 SYSCR1 (0038H) 7 STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP RELM RETM OUTEN STOP mode start Release method for STOP mode Operating mode after STOP mode Port output during STOP mode 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) 0: Edge-sensitive release 1: Level-sensitive release 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode 0: High impedance 1: Output kept Return to NORMAL mode Return to SLOW mode 3 x 213/fs 213/fs 3 x 26/fs 26/fs R/W WUT Warm-up time at releasing STOP mode 00 01 10 11 3 x 216/fc 216/fc 3 x 214/fc 214/fc Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don't care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, the edge realease can not function according to some conditions. It is recommended to set the level realease (RELM = "1"). Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator. System Control Register 2 SYSCR2 (0039H) 7 XEN 6 XTEN 5 SYSCK 4 IDLE 3 2 TGHAL T 1 0 (Initial value: 1000 *0**) XEN XTEN High-frequency oscillator control Low-frequency oscillator control Main system clock select (Write)/main system clock monitor (Read) CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) TG control (IDLE0 and SLEEP0 modes) 0: Turn off oscillation 1: Turn on oscillation 0: Turn off oscillation 1: Turn on oscillation 0: High-frequency clock 1: Low-frequency clock 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) SYSCK R/W IDLE TGHALT Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "0". Note 2: *: Don't care, TG: Timing generator Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR Page 20 TMP86CH06AUG Note 7: When IDLE0 or SLEEP0 mode is released, SYSCR2< TGHALT> is automatically cleared to "0". Note 8: Before setting SYSCR2< TGHALT> to "1", be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals may be set after IDLE0 or SLEEP0 mode is released. 2.1.5.4 Operating Mode Control (1) STOP mode STOP mode is controlled by the system control register 1 and the STOP pin input. The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1 Note: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (a) Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup. When the STOP pin input is high, executing an instruction which starts STOP mode will not place in STOP mode but instead will immediately start the release sequence (Warm up). Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low. The following two methods can be used for confirmation. 1. Testing a port P20. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: TEST JRS DI SET (SYSCR1). 7 (SYSCR1), 01010000B (P2R). 0 F, SSTOPH ; IMF1 ; Starts STOP mode ; Sets up the level-sensitive release mode ; Wait until the STOP pin input goes low level Page 21 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST JRS LD DI SET SINT5: RETI (SYSCR1). 7 (P2R). 0 F, SINT5 (SYSCR1), 01010000B ; To reject noise, STOP mode does not start if port P20 is at high ; Sets up the level-sensitive release mode. ; IMF1 ; Starts STOP mode STOP pin XOUT pin NORMAL operation STOP operation Confirm by program that the STOP pin input is low and start STOP mode. VIH Warm up NORMAL operation STOP mode is released by the hardware. Always released if the STOP pin input is high. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm up starts, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (b) Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Example :Starting STOP mode from NORMAL mode DI LD (SYSCR1), 10010000B ; IMF1 ; Starts after specified to the edge-sensitive release mode STOP pin XOUT pin NORMAL operation STOP mode started by the program. STOP operation VIH Warm up NORMAL operation STOP operation STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 2-8 Edge-sensitive Release Mode STOP mode is released by the following sequence. Page 22 TMP86CH06AUG 1. In the dual-clock mode, when returning to NORMAL2 or SLOW2, both the high-frequency and low-frequency clock oscillators are turned on; when returning to SLOW1 mode, only the low-frequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with SYSCR1 Warm-up Time [ms] WUT Return to NORMAL Mode 00 01 10 11 12.288 4.096 3.072 1.024 Return to SLOW Mode 750 250 5.85 1.95 Note: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Page 23 2.1 CPU Core Functions Turn off 2. Operational Description Oscillator circuit Turn on Main system clock a+3 SET (SYSCR1). 7 n+1 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) n+2 n+3 n+4 Halt Program counter a+2 Instruction execution Divider n 0 Figure 2-9 STOP Mode Start/Release a+4 Instruction address a + 2 Page 24 0 1 (b) STOP mode release Warm up STOP pin input Oscillator circuit Turn off Turn on Main system clock a+5 Instruction address a + 3 Program counter a+3 a+6 Instruction address a + 4 Instruction execution Halt Divider 0 Count up 2 3 TMP86CH06AUG TMP86CH06AUG (2) IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU and WDT are halted Yes Reset input No No Normal release mode No Interrupt request Yes IMF = 1 Reset Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes (a) Start the IDLE1/2 and SLEEP1/2 modes When IDLE1/2 and SLEEP1/2 modes start, set SYSCR2 Page 25 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG (c) Normal release mode (IMF = "0") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt latches (IL) of the interrupt source used for releasing must be cleared to "0" by load instructions. (d) Interrupt release mode (IMF = "1") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (EF) and the interrupt processing is started. After the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts IDLE1/2 and SLEEP1/2 modes. Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 mode are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 mode will not be started. Page 26 Main system clock Interrupt request a+2 SET (SYSCR2). 4 Operate Halt a+3 Program counter Instruction execution Watchdog timer (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Main system clock Interrupt request a+3 Instruction address a + 2 Operate Normal release mode a+4 Program counter Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 27 a+3 Acceptance of interrupt Operate Operate Interrupt release mode (b) IDLE1/2 and SLEEP1/2 modes release Instruction execution Halt Watchdog timer Halt Main system clock Interrupt request Program counter Instruction execution Halt TMP86CH06AUG Watchdog timer Halt 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG (3) IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Stopping peripherals by instruction Starting IDLE0 and SLEEP0 modes by instruction CPU and WDT are halted Reset input No No TBT source clock falling edge Yes TBTCR Yes Reset No No (Normal release mode) Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0 and SLEEP0 modes start instruction Figure 2-12 IDLE0 and SLEEP0 Modes (a) Start the IDLE0 and SLEEP0 modes Page 28 TMP86CH06AUG Stop (Disable) peripherals such as a timer counter. When IDLE0 and SLEEP0 modes start, set SYSCR2 Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR (c) Normal release mode (IMF * EF6 * ETBTCR (d) Interrupt release mode (IMF * EF6 * ETBTCR Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR Page 29 Main system clock 2.1 CPU Core Functions Interrupt request a+2 a+3 2. Operational Description Program counter Instruction execution SET (SYSCR2). 2 Halt Watchdog timer Operate (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a) Main system clock TBT clock a+3 a+4 Program counter Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 30 Instruction address a + 2 Operate Normal release mode a+3 Instruction execution Halt Watchdog timer Halt Main system clock TBT clock Program counter Instruction execution Halt Acceptance of interrupt Operate Interrupt release mode (b) IDLE0 and SLEEP0 modes release TMP86CH06AUG Watchdog timer Halt TMP86CH06AUG (4) SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter (TC1, TC0). (a) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. When the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before performing the above operations. The timer/counter 1, 0 (TC1, TC0) can conveniently be used to confirm that low-frequency clock oscillation has stabilized. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET LD LD LDW DI SET EI SET : PINTTC1: CLR SET (TC1CR). 3 (SYSCR2). 5 ; Stops TC1, 0 ; SYSCR2 Page 31 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG (b) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 Note: After SYSCR2 High-frequency clock Low-frequency clock Main system clock SYSCK Note: SLOW mode can also be released by inputting low level on the RESET pin, which immediately performs the reset operation. After reset, TMP86CH06AUG are placed in NORMAL1 mode. Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET LD LD LD DI SET EI SET : PINTTC1: CLR CLR (TC1CR). 3 (SYSCR2). 5 ; Stops TC1, 0 ; SYSCR2 Page 32 Highfrequency clock Lowfrequency clock Main system clock Turn off SYSCK XEN CLR (SYSCR2). 7 SLOW2 mode (a) Switching to the SLOW mode Instruction execution SET (SYSCR2). 5 NORMAL2 mode SLOW1 mode Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 33 CLR (SYSCR2). 5 Warm up during SLOW2 mode (b) Switching to the NORMAL2 mode Highfrequency clock Lowfrequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2). 7 TMP86CH06AUG SLOW1 mode NORMAL2 mode 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG 2.1.6 Reset Circuit The TMP86CH06AUG have four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Table 2-6 shows on-chip hardware initialization by reset action. The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. The RESET pin can reset state at the maximum 24/fc [s] (1.5 ms at 16.0 MHz) when power is turned on. Table 2-6 Initializing Internal Status by Reset Action On-chip Hardware Program counter Stack pointer General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (JF) (ZF) (CF) (HF) (SF) (VF) (IMF) (EF) (IL) (PC) (SP) Initial Value (FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Output latches of I/O ports Not initialized Not initialized 0 0 Control registers 0 RAM Refer to each of control register Not initialized Refer to I/O port circuitry Watchdog timer Enable Prescaler and divider of timing generator 0 On-chip Hardware Initial Value 2.1.6.1 External Reset Input The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Sink open drain Figure 2-15 Reset Circuit Page 34 TMP86CH06AUG 2.1.6.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 Instruction execution RESET pin output JP a Address trap is occurred ("L" output) Reset release Instruction at address r 8/fc to 24/fc [s] Note3 4/fc to 12/fc [s] 16/fc [s] Note 1: Address "a" is in the SFR or on-chip RAM (WDTCR1 Figure 2-16 Address Trap Reset Note: The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. 2.1.6.3 Watchdog timer reset Refer to "Watchdog Timer". 2.1.6.4 System clock reset Clearing both SYSCR2 Page 35 2. Operational Description 2.1 CPU Core Functions TMP86CH06AUG Page 36 TMP86CH06AUG 3. Interrupt Control Circuit The TMP86CH06AUG has a total of 21 interrupt sources excluding reset, of which 5 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Latch - - - IL2 IL3 IL5 IL6 IL7 IL8 Vector Address FFFE FFFC FFFC FFFA FFF8 FFF4 FFF2 FFF0 FFEE Interrupt Factors Internal/External Internal Internal Internal Internal External Internal Internal Internal Internal Internal Internal Internal Internal External External Internal External Internal Internal External (Reset) INTSWI (Software interrupt) INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT (Watchdog timer interrupt) INT1 INTTBT INTTC1 INTRXD0 INTSIO INTTXD0 INTET0 INTIC0 INTOC0 INT2 INT3 INTRXD1 INT4 INTTXD1 INTTC0 INT5 Enable Condition Non-maskable Non-maskable Non-maskable Non-maskable Non-maskable IMF* EF5 = 1 IMF* EF6 = 1 IMF* EF7 = 1 IMF* EF8 = 1, IL8ER = 0 IMF* EF8 = 1, IL8ER = 1 IMF* EF9 = 1 IMF* EF10 = 1 IMF* EF11 = 1 IMF* EF12 = 1, IL12ER = 0 IMF* EF12 = 1, IL12ER = 1 IMF* EF13 = 1, IL13ER = 0 IMF* EF13 = 1, IL13ER = 1 IMF* EF14 = 1, IL14ER = 0 IMF* EF14 = 1, IL14ER = 1 IMF* EF15 = 1, IL15ER = 0 IMF* EF15 = 1, IL15ER = 1 Priority 1 2 2 2 2 6 7 8 9 IL9 IL10 IL11 IL12 FFEC FFEA FFE8 FFE6 10 11 12 13 IL13 FFE4 14 IL14 FFE2 15 IL15 FFE0 16 Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Interrupt Source Selector (INTSEL)). Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1 3.1 Interrupt latches (IL15 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Page 37 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CH06AUG Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LDW EI (ILL), 1110100000111111B ; IMF 0 ; IL12, IL10 to IL6 0 ; IMF 1 Example 2 :Reads interrupt latchess LD WA, (ILL) ; W ILH, A ILL Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". 3.2.2 Individual interrupt enable flags (EF15 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor- Page 38 TMP86CH06AUG mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI ; IMF 1 (EIRL), 1110100010100000B ; IMF 0 ; EF15 to EF13, EF11, EF7, EF5 1 Note: IMF should not be set. Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); /* 3AH shows EIRL address */ Page 39 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CH06AUG Interrupt Latches (Initial value: 00000000 000000**) ILH,ILL (003DH, 003CH) 15 IL15 14 IL14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0 ILH (003DH) ILL (003CH) IL15 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 00000000 0000***0) EIRH,EIRL (003BH, 003AH) 15 EF15 14 EF14 13 EF13 12 EF12 11 EF11 10 EF10 9 EF9 8 EF8 7 EF7 6 EF6 5 EF5 4 EF4 EIRL (003AH) 3 2 1 0 IMF EIRH (003BH) EF15 to EF4 IMF Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts R/W Note 1: *: Don't care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 40 TMP86CH06AUG 3.3 Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL register must be set appropriately before interrupt requests are generated. The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL. 1. INTRXD0 and INTSIO share the interrupt source level whose priority is 9. 2. INTOC0 and INT2 share the interrupt source level whose priority is 13. 3. INT3 and INTRXD1 share the interrupt source level whose priority is 14. 4. INT4 and INTTXD1 share the interrupt source level whose priority is 15. 5. INTTC0 and INT5 share the interrupt source level whose priority is 16. Interrupt source selector INTSEL (003EH) 7 IL8ER 6 5 4 3 IL12ER 2 IL13ER 1 IL14ER 0 IL15ER (Initial value: 0*** 0000) IL8ER IL12ER IL13ER IL14ER IL15ER Selects INTRXD0 or INTSIO Selects INTOC0 or INT2 Selects INT3 or INTRXD1 Selects INT4 or INTTXD1 Selects INTTC0 or INT5 0: INTRXD0 1: INTSIO 0: INTOC0 1: INT2 0: INT3 1: INTRXD1 0: INT4 1: INTTXD1 0: INTTC0 1: INT5 R/W R/W R/W R/W R/W 3.4 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 s @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.4.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. Page 41 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86CH06AUG 1-machine cycle Interrupt service task Interrupt request Interrupt latch (IL) IMF Execute instruction a-1 Execute instruction Execute instruction Interrupt acceptance Execute RETI instruction PC a a+1 a b b+1 b+2 b + 3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-2 n-1 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address Interrupt service program FFF2H FFF3H 03H D2H Vector D203H D204H 0FH 06H Figure 3-2 Vector table address,Entry address A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.4.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers. Page 42 TMP86CH06AUG 3.4.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP RETI WA ; Restore WA register ; RETURN Address (Example) SP A SP PCL PCH PSW At acceptance of an interrupt W PCL PCH PSW At execution of PUSH instruction SP PCL PCH PSW At execution of POP instruction SP b-5 b-4 b-3 b-2 b-1 b At execution of RETI instruction Figure 3-3 Save/store register using PUSH and POP instructions 3.4.2.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD RETI A, (GSAVA) ; Restore A register ; RETURN Page 43 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86CH06AUG Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.4.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. 2. Stack pointer (SP) is incremented by 3. As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Example 1 :Returning from address trap interrupt (INTATRAP) service program PINTxx: POP LD PUSH WA WA, Return Address WA ; Recover SP by 2 ; ; Alter stacked data (interrupt processing) RETN ; RETURN Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: INC INC INC SP SP SP ; Recover SP by 3 ; ; (interrupt processing) LD JP EIRL, data Restart Address ; Set IMF to "1" or clear it to "0" ; Jump into restarting address Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Page 44 TMP86CH06AUG Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.5 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the SWI instruction only for detection of the address error or for debugging. 3.5.1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM or SFR areas. 3.5.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3.6 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does. 3.7 Address Trap Interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). 3.8 External Interrupts The TMP86CH06AUG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. The INT0/P10 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/P10 pin function selection are performed by the external interrupt control register (EINTCR). Page 45 3. Interrupt Control Circuit 3.8 External Interrupts TMP86CH06AUG Source Pin Enable Conditions Release Edge (level) Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. INT0 INT0 IMF EF4 INT0EN=1 Falling edge INT1 INT1 IMF EF5 = 1 Falling edge or Rising edge INT2 INT2 IMF EF12 = 1 and IL12ER=1 Falling edge or Rising edge INT3 INT3 IMF and EF13 = 1 IL13ER=0 Falling edge or Rising edge INT4 INT4 IMF EF14 = 1 and IL14ER=0 Falling edge, Rising edge, Falling and Rising edge or H level INT5 INT5 IMF EF15 = 1 and IL15ER=1 Falling edge Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input. Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. Page 46 TMP86CH06AUG External Interrupt Control Register EINTCR (0037H) 7 INT1NC 6 INT0EN 5 INT4ES 4 3 INT3ES 2 INT2ES 1 INT1ES 0 (Initial value: 0000 000*) INT1NC INT0EN Noise reject time select P10/INT0 pin configuration 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P10 input/output port 1: INT0 pin (Port P10 should be set to an input mode) 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: H level 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge R/W R/W INT4 ES INT4 edge select R/W INT3 ES INT2 ES INT1 ES INT3 edge select INT2 edge select INT1 edge select R/W R/W R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc. Note 4: In case RESET pin is released while the state of INT4 pin keeps "H" level, the external interrupt 4 request is not generated even if the INT4 edge select is specified as "H" level. The rising edge is needed after RESET pin is released. Page 47 3. Interrupt Control Circuit 3.8 External Interrupts TMP86CH06AUG Page 48 TMP86CH06AUG 4. Special Function Register (SFR) The TMP86CH06AUG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR). The SFR is mapped on address 0000H to 003FH. This chapter shows the arrangement of the special function register (SFR) for TMP86CH06AUG. 4.1 SFR Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H 0026H 0027H SIOSR UART0SR RD0BUF RD1BUF UART1SR TC0CR TC1CR TTREG0 TTREG1 PWREG0 PWREG1 SIOCR1 SIOCR2 ET0ICAL ET0ICAH ET0ICBL ET0ICBH ET0OCRL ET0OCRH UARTCR1 UART0CR2 TD0BUF TD1BUF UART1CR1 UART1CR2 P2R P4R Reserved ET0CR ET0MIO ET0RL ET0RH PME Read P0DR P1DR P2DR P3DR P4DR Reserved Reserved Reserved P0CR P1CR P3CR P4CR P4OED Write Page 49 4. Special Function Register (SFR) 4.1 SFR TMP86CH06AUG Address 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Read SIOBR0 SIOBR1 SIOBR2 SIOBR3 SIOBR4 SIOBR5 SIOBR6 SIOBR7 Reserved WAITCR Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH INTSEL PSW Write EXPCR WDTCR1 WDTCR2 Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 50 TMP86CH06AUG 5. I/O Ports The TMP86CH06AUG has 5 parallel input/output ports (35 pins) as follows. 1. Port P0; 8-bit I/O port (utilized also for Address/Data bus) 2. Port P1; 8-bit I/O port (utilized also for External interrupt input, Timer input/output and External memory management output) 3. Port P2; 3-bit I/O port (utilized also for Low frequency resonator connections, External interrupt input and STOP mode releasing signal input) 4. Port P3; 8-bit I/O port (utilized also for Address bus output, Timer input/output and External interrupt input) 5. Port P4; 8-bit I/O port (utilized also for Timer input and Serial interface input/output) Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. Figure 5-1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. fetch cycle fetch cycle read cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Ex: LD A, (x) Input strobe Data input (a) Input timing fetch cycle fetch cycle write cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Ex: LD (x), A Output strobe Data output Old (b) Output timing New Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 5-1 Input/Output Timing (Example) Page 51 5. I/O Ports TMP86CH06AUG 5.1 Port P0 Port P0 is the 8-bit I/O port that allows selection of input/output on bit basis. Input/output mode is specified on the P0 port input/output control register (P0CR). During reset, all the bits on P0CR are initialized to "0" and P0 becomes input port. Reset operation also initializes all the bits on P0 port output latch (P0DR) to "0". Besides input/output port, Port P0 functions as multiplexed Address/Data bus (AD7 to 0). Port P0 becomes 8-bit bidirectional Address/Data bus (AD7 to 0) when the CPU accesses to the external memory. When it functions as data bus, the judgment on its input rate is based on TTL level. Note: Input status is read while the port is input mode. Therefore the contents of output latch, that belongs to the terminal for input, may alter if both input and output are mixed in P0 port. Internal Address bus (A0 to 7) Reset Direction control (bit basis) P0CR write P0CR read Selector B A Internal data bus S Y B Output latch P0 write Selector S A S Selector Y Output buffer Port 0 P00 to 07 (AD0 to 7) External Access (Data write) OSC. Enable External Access External Access (Address output) B Y TTL level External Access (Data read) P0 read A Figure 5-2 Port P0 Port P0 P0DR (0000H) 7 P07 6 P06 5 P05 4 P04 3 P03 2 P02 1 P01 0 P00 (Initial value: 0000 0000) P0CR (0008H) 7 P0CR7 6 P0CR6 5 P0CR5 4 P0CR4 3 P0CR3 2 P0CR2 1 P0CR1 0 P0CR0 (Initial value: 0000 0000) P0CR I/O control for port P0 (Set for each bit individually) 0: Input mode 1: Output mode R/W Page 52 TMP86CH06AUG 5.2 Port P1 Port P1 is the 8-bit I/O port that allows selection of input/output on bit basis. Input/output mode is specified on the P1 port input/output control register (P1CR). During reset, all the bits on P1CR are initialized to "0" and P1 becomes input port. Reset operation also initializes all the bits on P1 port output latch (P1DR) to "0". Besides input/output port, the terminals in Port P1 functions as follows. P15, P16 and P17 have WR, RD and ALE function respectively. These terminals output signals for WR, RD and ALE when the CPU accesses to the external memory. In order to utilize WR and RD functions, set WROE and RDOE, located on the EXPCR, respectively. If WROE, RDOE or both are enabled, P17 functions as ALE. If the device is released from reset while EA terminal is low, CLK signal is uttered every machine cycle. P10, P11 and P12 have INT0, INT1, and ETC0 function respectively. In order to utilize these functions, the terminal should be set for input. Furthermore, pll has the function of WAIT while the external memory is begin connected. If the WAIT function is not necessary as external memory is utilized, clear the WAIT bits (bit 7, 6) on WAITCR to "00". P13 and P14 have DVO and TO1 function respectively. In order to utilize these functions, the output latch belongs to each terminal should be set to "1" before the terminal is set for output. Note 1: Input status is read while the port is input mode. Therefore the contents of output latch, that belongs to the terminal for input, may alter if both input and output are mixed in P1 port. Note 2: When the external memory is used, P10 pin cannot be used as external interrupt pin (INT0) or input/output port because CLK is output from P10. Reset CLK CLKV Direction control (bit) P1CR write OSC. Enable Internal data bus P1CR read B Output latch P1 write A S Selector Y Output buffer P10 (INT0, CLK) P1 read INT0 Figure 5-3 P10 Page 53 5. I/O Ports 5.2 Port P1 TMP86CH06AUG Reset Direction control (bit basis) P1CR write OSC. Enable Internal data bus P1CR read Output latch Output buffer P1 write P11, P12 P1 read WAIT, INT1, ETC0 Figure 5-4 P11, P12 Reset Direction control (bit basis) P1CR write OSC. Enable Internal data bus P1CR read Output latch P1 write P13, P14 DVO (P13) TO1 (P14) P1 read Figure 5-5 P13, P14 Page 54 TMP86CH06AUG Reset WR, RD WROE (P15) RDOE (P16) Direction control (bit basis) P1CR write OSC. Enable Internal data bus P1CR read B Output latch P1 write A S Selector Y Output buffer P15, P16 (WR, RD) P1 read Figure 5-6 P15, P16 Reset ALE Direction control (bit basis) P1CR write WROE RDOE OSC. Enable Internal data bus P1CR read B Output latch P1 write A Selector S Y Output buffer P17 (ALE) P1 read Figure 5-7 P17 Page 55 5. I/O Ports 5.3 Port P2 TMP86CH06AUG Port P1DR and P1CR register P1DR (0001H) 7 P17 6 P16 5 P15 4 P14 3 P13 2 P12 1 P11 0 P10 (Initial value: 0000 0000) P1CR (0009H) 7 P1CR7 6 P1CR6 5 P1CR5 4 P1CR4 3 P1CR3 2 P1CR2 1 P1CR1 0 P1CR0 (Initial value: 0000 0000) P1CR I/O control for port P1 (Set for each bit individually) 0: Input mode 1: Output mode R/W 5.3 Port P2 Port P2 is a 3-bit input/output port. It is also used as an external interrupt, a STOP mode release signal input, and low-frequency Xtal connection pins. When they are used as an input port or a secondary function pins, the respective output latch should be set to "1". A low-frequency Xtal (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dual-clock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports. It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse. When a read instruction is executed for port P2, bits 7 to 3 are read as undefined values. P2 port output latch (P2DR) and P2 port terminal input (P2R) are located on their respective addresses. Therefore, if input and output pins are mixed in P2 port, Read Write Modify instructions do not affect the output latch belongs to the terminal for input. STOP, INT5 RESET S D Output latch LE WR P2DR RD Internal data bus Q P2R RD P20 RESET D S Output latch LE Q WR P2DR RD P2R OSC. Enable P21 fs P22 LE D Output latch S RESET Q XTEN Figure 5-8 Port P2 Page 56 TMP86CH06AUG Port P2 P2DR (0002H) 7 * 6 * 5 * 4 * 3 * 2 P22 1 P21 0 P20 (Initial value: 1111 1111) P2R (000DH) 7 * 6 * 5 * 4 * 3 * 2 P22IN 1 P21IN 0 P20IN (Initial value: 1111 1---) Read-only Note 1: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 2: Bit 7 through bit 3 in P2R contain unstable values. Note 3: *: Don't care. 5.4 Port P3 Port P3 is the 8-bit I/O port that allows selection of input/output on bit basis. Input/output mode is specified on the P3 port input/output control register (P3CR). During reset, all the bits on P3CR are initialized to "0" and P3 becomes input port. Reset operation also initializes all the bits on P3 port output latch (P3DR) to "0". Besides input/output port, the terminals in Port P3 functions as follows. P36 and P37 have IC0 and INT2 function respectively. In order to utilize these functions, the terminal should be set for input. P35 and P37 have TO0 and OC0 function respectively. In order to utilize these functions, the output latch belongs to each terminal should be set to "1" before the terminal is set for output. Port P3 also functions as address bus (A15 to 8). Port P3 becomes 8-bit bidirectional address bus (A15 to 8) when the CPU accesses to the external memory. In order to utilize address bus (A15 to 8) function, set ABUSEN, located on the EXPCR. Note: Input status is read while the port is input mode. Therefore the contents of output latch, that belongs to the terminal for input, may alter if both input and output are mixed in P3 port. Page 57 5. I/O Ports 5.5 Port P4 TMP86CH06AUG Internal Address bus (A8 to 15) Reset ABUSEN Direction control (bit basis) P3CR write OSC. Enable Internal data bus P3CR read B Selector Output latch P3 write A OC0 (P37) TO0 (P35) "1" (others) S Y Output buffer Port3 P30 to 37 (A8 to 15) P3 read IC0 (P36) INT2 (P37) Figure 5-9 Port P3 Port P3 P3DR (0003H) 7 P37 6 P36 5 P35 4 P34 3 P33 2 P32 1 P31 0 P30 (Initial value: 0000 0000) P3CR (000AH) 7 P3CR7 6 P3CR6 5 P3CR5 4 P3CR4 3 P3CR3 2 P3CR2 1 P3CR1 0 P3CR0 (Initial value: 0000 0000) P3CR I/O control for port P3 (Set for each bit individually) 0: Input mode 1: Output mode R/W 5.5 Port P4 Port P4 is the 8-bit I/O port that allows selection of input/output on bit basis. Input/output mode is specified on the P4 port input/output control register (P4CR). During reset, all the bits on P4CR are initialized to "0" and P4 becomes input port. Reset operation also initializes all the bits on P4 port output latch (P4DR) to "1". Port P4 has programmable open-drain output function. The data on P4 port open-drain control register (P4ODE) determines whether open-drain output is enabled or disabled on bit basis. During reset, all the bits on P4ODE are initialized to "0", and under the circumstances P4 becomes CMOS output port if P4CR is set to "1". Besides input/output port, the terminals in Port P4 functions as follows. P40 and P41 have TI0 and TI1 function respectively: both TI0 and TI1 are for 8-bit timers. In order to utilize these functions, the terminal should be set for input. P46 and P47 have INT3 and INT4 function respectively: both INT3 and INT4 are for interrupts. In order to utilize these functions, the terminal should be set for input. The bundles, one consists of P42, P43 and P44 and the other consists of P46 and P47, have serial interface function respectively. Page 58 TMP86CH06AUG P4 output latch (P4DR) and P4 port terminal input (P4R) are located on their respective addresses. Therefore, if input and output pins are mixed in P4 port, Read Write Modify instructions do not affect the output latch belongs to the terminal for input. Reset R Open drain enable WR P4ODE RD Reset S Internal data bus D WR P4DR RD Reset R D Direction control Q (bit basis) WR P4CR RD LE OSC. Enable Output latch LE Q Port 4 P47 to P40 LE TxD, SCLK P4R RD RxD, SCLK, INT Figure 5-10 Port P4 Port P4 P4DR (0004H) 7 P47 6 P46 5 P45 4 P44 3 P43 2 P42 1 P41 0 P40 (Initial value: 1111 1111) P4R (000EH) 7 P47IN 6 P46IN 5 P45IN 4 P44IN 3 P43IN 2 P42IN 1 P41IN 0 P40IN (Initial value: ---- ----) Read only P4CR (000BH) 7 P4CR7 6 P4CR6 5 P4CR5 4 P4CR4 3 P4CR3 2 P4CR2 1 P4CR1 0 P4CR0 (Initial value: 0000 0000) P4CR I/O control for port P4 (Set for each bit individually) 0: Input mode 1: Output mode R/W P4ODE (000CH) 7 P4ODE7 6 P4ODE6 5 P4ODE5 4 P4ODE4 3 P4ODE3 2 P4ODE2 1 P4ODE1 0 P4ODE0 (Initial value: 0000 0000) Page 59 5. I/O Ports 5.5 Port P4 TMP86CH06AUG P4ODE I/O control for port P4 (Set for each bit individually) 0: 3-state output mode 1: Nch O.D. output mode R/W Page 60 TMP86CH06AUG 6. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as "reset request" or "interrupt request". Upon the reset release, this signal is initialized to "reset request". When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 6.1 Watchdog Timer Configuration Reset release fc/2 or fs/2 fc/221 or fs/213 fc/219 or fs/211 fc/217 or fs/29 23 15 Selector Binary counters Clock Clear 1 2 Overflow WDT output R S Q Reset request INTWDT interrupt request 2 Interrupt request Internal reset Q SR WDTEN WDTT Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 Watchdog timer control registers Figure 6-1 Watchdog Timer Configuration Page 61 6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control TMP86CH06AUG 6.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 6.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1 Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1 Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD LD LD (WDTCR2), 4EH (WDTCR1), 00001101B (WDTCR2), 4EH : Clears the binary counters. : WDTT 10, WDTOUT 1 : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Page 62 TMP86CH06AUG Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 (ATAS) 4 (ATOUT) 3 WDTEN 2 WDTT 1 0 WDTOUT (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable NORMAL1/2 mode DV7CK = 0 DV7CK = 1 217/fs 215/fs 213/fs 211/fs SLOW1/2 mode 217/fs 215fs 213fs 211/fs Write only WDTT Watchdog timer detection time [s] 00 01 10 11 225/fc 223/fc 221fc 219/fc Write only WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Note 1: After clearing WDTOUT to "0", the program cannot set it to "1". Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don't care is read. Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode. After clearing the counter, clear the counter again immediately after the STOP mode is inactivated. Note 5: To clear WDTEN, set the register in accordance with the procedures shown in "1.2.3 Watchdog Timer Disable". Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Write only Note 1: The disable code is valid only when WDTCR1 6.2.2 Watchdog Timer Enable Setting WDTCR1 Page 63 6. Watchdog Timer (WDT) 6.2 Watchdog Timer Control TMP86CH06AUG 6.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to "0". 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1 Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. Example :Disabling the watchdog timer DI LD LDW (WDTCR2), 04EH (WDTCR1), 0B101H : IMF 0 : Clears the binary coutner : WDTEN 0, WDTCR2 Disable code Table 6-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time[s] WDTT DV7CK = 0 00 01 10 11 2.097 524.288 m 131.072 m 32.768 m NORMAL1/2 mode DV7CK = 1 4 1 250 m 62.5 m SLOW mode 4 1 250 m 62.5 m 6.2.4 Watchdog Timer Interrupt (INTWDT) When WDTCR1 Example :Setting watchdog timer interrupt LD LD SP, 023FH (WDTCR1), 00001000B : Sets the stack pointer : WDTOUT 0 Page 64 TMP86CH06AUG 6.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1 Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. 219/fc [s] 217/fc Clock Binary counter Overflow INTWDT interrupt request (WDTCR1 (WDTT=11) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 A reset occurs (High-Z) Write 4EH to WDTCR2 WDT reset output Figure 6-2 Watchdog Timer Interrupt/Reset Page 65 6. Watchdog Timer (WDT) 6.3 Address Trap TMP86CH06AUG 6.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 ATAS 4 ATOUT 3 (WDTEN) 2 (WDTT) 1 0 (WDTOUT) (Initial value: **11 1001) ATAS Select address trap generation in the internal RAM area Select opertion at address trap 0: Generate no address trap 1: Generate address traps (After setting ATAS to "1", writing the control code D2H to WDTCR2 is reguired) 0: Interrupt request 1: Reset request Write only ATOUT Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code and address trap area control code D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Write only 6.3.1 Selection of Address Trap in Internal RAM (ATAS) WDTCR1 6.3.2 Selection of Operation at Address Trap (ATOUT) When an address trap is generated, either the interrupt request or the reset request can be selected by WDTCR1 6.3.3 Address Trap Interrupt (INTATRAP) While WDTCR1 Page 66 TMP86CH06AUG 6.3.4 Address Trap Reset While WDTCR1 Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Page 67 6. Watchdog Timer (WDT) 6.3 Address Trap TMP86CH06AUG Page 68 TMP86CH06AUG 7. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 7.1 Time Base Timer 7.1.1 Configuration MPX fc/223 or fs/215 fc/221 or fs/213 fc/216 or fs/28 fc/214 or fs/26 fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/29 or fs/2 Source clock Falling edge detector IDLE0, SLEEP0 release request INTTBT interrupt request 3 TBTCK TBTCR Time base timer control register TBTEN Figure 7-1 Time Base Timer configuration 7.1.2 Control Time Base Timer is controled by Time Base Timer control register (TBTCR). Time Base Timer Control Register 7 TBTCR (0036H) (DVOEN) 6 (DVOCK) 5 4 (DV7CK) 3 TBTEN 2 1 TBTCK 0 (Initial Value: 0000 0000) TBTEN Time Base Timer enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 fc/223 fc/221 fc/216 fc/2 14 DV7CK = 1 fs/215 fs/213 fs/28 fs/2 6 SLOW1/2 SLEEP1/2 Mode fs/215 fs/213 - - - - - - R/W TBTCK Time Base Timer interrupt Frequency select : [Hz] 010 011 100 101 110 111 fc/213 fc/2 12 fs/25 fs/2 4 fc/211 fc/2 9 fs/23 fs/2 Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care Page 69 7. Time Base Timer (TBT) 7.1 Time Base Timer TMP86CH06AUG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously. Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD LD DI SET (EIRL) . 6 (TBTCR) , 00000010B (TBTCR) , 00001010B ; TBTCK 010 ; TBTEN 1 ; IMF 0 Table 7-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 010 011 100 101 110 111 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 NORMAL1/2, IDLE1/2 Mode DV7CK = 1 1 4 128 512 1024 2048 4096 16384 1 4 - - - - - - SLOW1/2, SLEEP1/2 Mode 7.1.3 Function An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 7-2 ). Source clock TBTCR INTTBT Interrupt period Enable TBT Figure 7-2 Time Base Timer Interrupt Page 70 TMP86CH06AUG 7.2 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. 7.2.1 Configuration Output latch Data output D Q DVO pin fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/210 or fs/22 MPX A B CY D S 2 DVOCK TBTCR Divider output control register (a) configuration DVOEN Port output latch TBTCR DVO pin output (b) Timing chart Figure 7-3 Divider Output 7.2.2 Control The Divider Output is controlled by the Time Base Timer Control Register. Time Base Timer Control Register 7 TBTCR (0036H) DVOEN 6 DVOCK 5 4 (DV7CK) 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 fs/25 fs/24 fs/23 fs/22 SLOW1/2 SLEEP1/2 Mode fs/25 fs/24 fs/23 fs/22 R/W DVOCK Divider Output (DVO) frequency selection: [Hz] 00 01 10 11 fc/213 fc/212 fc/211 fc/210 R/W Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Page 71 7. Time Base Timer (TBT) 7.2 Divider Output (DVO) TMP86CH06AUG Example :1.95 kHz pulse output (fc = 16.0 MHz) LD LD (TBTCR) , 00000000B (TBTCR) , 10000000B ; DVOCK "00" ; DVOEN "1" Table 7-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k DV7CK = 1 1.024 k 2.048 k 4.096 k 8.192 k SLOW1/2, SLEEP1/2 Mode 1.024 k 2.048 k 4.096 k 8.192 k Page 72 TMP86CH06AUG 8. Extended Timer-Counter (ETC0) The TMP86CH06AUG contains 16-bit extended timer-counter (ETC0), which is accompanied by terminals for capturing input and outputting comparison. The alternative of internal or external input is to be source clock. The ETC0 pin, IC0 pin and OC0 pin can also be used as the port P12, P36 and P37. 8.1 Configuration ICMODE ICEN IC0 2 Setting edge to detect Filter circuit Edge detection circuit Event detected INTIC0 interrupt ET0ICA Full-count INTET0 Source clock (fc or fs) fc/2 3 2 fc/2 or fs/2 4 3 Source fc/2 or fs/2 5 4 clock fc/2 or fs/2 6 5 fc/2 or fs/2 7 6 fc/2 or fs/2 8 7 fc/2 or fs/2 Edge detection circuit 2 ET0ICB ICEN ICM0DE 2 ET0MIO 2 OCID OCEN OCM0DE A B C D E F G H S 3 Y Source clock 16-bit upcounter ET0OCR ENC0 2 Matched Output polarity ETC0 Set J K Q CK R OC0 Filter circuit ET0S RESET OCID write data OCID write timing INTOC0 interrupt ET0ES ET0CKS ET0CR ET0R Figure 8-1 Extended Timer-Counter 0 (ETC0) Page 73 8. Extended Timer-Counter (ETC0) 8.1 Configuration TMP86CH06AUG 8.2 Controlling The extended timer-counter (ETC0) is controlled on the following registers. Extended Timer-Counter Register This 16-bit timer register is to set and record the ETC0 counter value. It is able to read while counting. ET0R (0012, 0013H) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ET0RH (0013H) Read/Write ET0RL (0012H) (Initial value: 0000 0000 0000 0000) Note 1: Data written in the counter, does not reach lower byte of the ETC0 register until data on upper byte of it is set because of buffering. Writing only to lower byte is not allowed. Note 2: On reading the register, the lower byte read operation latches the timer-counter value. Therefore, always read the lower byte first, and the upper byte last. Note 3: Writing FFFFH to the ETC0 register generates an immediate interrupt request signal. Note 4: The lower byte of the ETC0 register and the lower byte of the ETC0 compare register share their buffering register. Therefore, do not execute write instruction against the ETC0 compare register, between writing on lower byte of the ETC0 register and upper byte of it. External Timer-counter Control Register Principal mode register for ETC0 ET0CR (0010H) 7 ET0S ET0S ET0ES ETC0 start/stop Count edge selection for event counter mode 6 5 4 3 ET0ES 0: Stop 1: Start 0: Rising edge 1: Falling edge NORMAL1/2, IDLE1/2 mode 000 001 010 ET0CKS Source clock for ETC0 011 100 101 110 111 fc/22 fc23 fc/24 fc/25 fc/26 fc/2 7 2 1 ET0CKS 0 (Initial value: 0*** 0000) SLOW, SLEEP mode - fs/22 fs/23 fs/24 fs/25 fs/26 fs/27 R/W fc/28 External clock (event counter mode) Note 1: *: Don't care Note 2: Altering source clock(ET0CK) and edge type under event counter mode is allowed only if the extended timer has been stopped. (Do not to change the setting on from enabling status to disabling status.) They can be set concurrently with enabling (start instruction). Pulse Measure Enable Register Mode register for capturing in order to calculate time difference or effective counting PME (0016H) 7 6 5 4 3 2 1 0 PME (Initial value: **** ***0) PME edge which causes interrupt request 0: of earliest detection 1: of second earliest detection Write only Note 1: If the address, PME locates, is read, the lower bits on ET0ICB is extracted. Note 2: As writing on PME by software, only the data "1" is accepted. PME is cleared to "0" by hardware when the edge is detected or the device is totally reset. Note 3: PME is a write only register and must not be used with any of the read-modify-write instructions. Page 74 TMP86CH06AUG ETC0 Capture/Compare Mode Register The register for both capturing and comparing ET0MIO (0011H) 7 OCIDEN 6 ICEN 5 ICMODE 4 3 OCID 2 OCEN 1 OCMODE 0 (Initial value: 1000 1000) OCIDEN ICEN Assignment control for OCID to initialize Capturing channel assignment control 0: Disable 1: Enable 0: Disable (used for port) 1: Enable (used for capturing channel) 00: No detection 01: Detect rising edge 10: Detect falling edge 11: Detect both edges 0: Initialize to "0" 1: Initialize to "1" * Valid when OCIDEN = "1" 0: Disable (used for port) 1: Enable (used for comparing channel) 00: NOP, output unchanged (steady output) 01: "1" output 10: "0" output 11: TOGGLE output (invert output) R/W ICMODE Capturing mode Edge control OCID Initial value for comparator (Set to "1" after RESET) Comparing channel assignment control Comparator output mode polarity control OCEN OCMODE ETC0 Capture Register A/B These 16-bit registers record the time when the capture terminal input changed. At maximum, 2 latest data are recorded; after detection, the capture register A holds the latest. ET0ICA (0014, 0015H) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ET0ICAH (0015H) Read only ET0ICAL (0014H) (Initial value: 0000 0000 0000 0000) 5 4 3 2 1 0 ET0ICB (0016, 0017H) 15 14 13 12 11 10 9 8 7 6 ET0ICBH (0017H) Read only ET0ICBL (0016H) (Initial value: 0000 0000 0000 0000) Note: Since capturing is restored by reading the upper byte of the capture register A, read capture register B before reading capture register A. Read capture register A from lower byte to upper byte. ETC0 Compare Register The 16-bit register is to set the time for changing output on comparator. ET0OCR (0018, 0019H) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ET0OCRH (0019H) Read/Write ET0OCRL (0018H) (Initial value: 0000 0000 0000 0000) Note 1: Data written in the counter, does not reach lower byte of the ETC0 compare register until data on upper byte of it is set because of buffering. Writing only to lower bite is not allowed. Note 2: The lower byte of the ETC0 register and the lower byte of the ETC0 compare register share their buffering register. Therefore, do not execute write instruction against the ETC0 register, between writing on lower byte of the ETC0 compare register and upper byte of it. Page 75 8. Extended Timer-Counter (ETC0) 8.1 Configuration TMP86CH06AUG 8.3 Source Clock The source clock for the extended timer-counter (ETC0) has 2 sorts of operating mode: the free-running mode whose source clock is provided from internal clock, and event-counter mode whose source clock is provided from external clock (through terminal ETC0). Table 8-1 Source Clock and Accuracy for ETC0 (at fc = 8 MHz, fs = 32.768 kHz) Accuracy Operating Mode Free Running Timer Event Counter Source Clock Internal ETCO terminal Edge (fc) Rising Rising or falling 500 ns to 32 s 1 s or more (fs) 122 s to 3.91 ms 244 s or more 8.3.1 Free Running Timer Mode The internal clock increase the extended timer-counter (ETC0). The interrupt INTET0 is requested when the counter reaches FFFFH, meanwhile the counter is still counting up. The source clock is selected on the bit ETC0CR Example 1 :Generate interrupt of ETC0 in 8 s, from source clock of fs/4 (fs = 32.768 kHz) LD LD DI SET EI SET (ET0CR).7 ; ETC0 start (EIRH).2 ; Enable interrupt INTET0 (ET0CR), 00000001B (ET0R), 0000H ; Stop the counter, and assign fs/22 to source clock ; Set timer register (8 s / 122 s = FFFFH) Example 2 :Generate interrupt of ETC0 in 256 s, from source clock of fc/8 (fc = 8 MHz) LD LDW DI SET EI SET (ET0CR).7 ; ETC0 start (EIRH).2 ; Enable interrupt INTET0 (ET0CR), 00000001B (ET0R), 0FEFFH ; Stop the counter, and assign fc/8 to source clock ; Set timer register (FFFFH-100H) Page 76 TMP86CH06AUG ET0S ET0R-WR ET0R INTET0 ET0CR ET0R Counter STOP Set for free running mode Write 0000H write "0" on ETOS count-up start Counter overflow & generates interrupt Note: ET0S is a bit located on ET0CR Figure 8-2 Example for Free-running mode operation Table 8-2 ETC0 Internal clock (fc = 8 MHz, fs = 32.768 kHz) NORMAL 1/2, IDLE 1/2 mode ET0CKS Accuracy 000 001 010 011 100 101 110 500 ns 1 s 2 s 4 s 8 s 16 s 32 s Range 32.77 ms 65.54 ms 131.07 ms 262.14 ms 524.29 ms 1.05 s 2.10 s Accuracy - 122.0 s 244.1 s 488.3 s 976.6 s 1.953 ms 3.906 ms Range - 8s 16 s 32 s 64 s 128 s 256 s SLOW, SLEEP mode Note: ET0CKS is a group of bits, which manages the source clock of ETC0. 8.3.2 Event-counter Mode The edge of ETC0 terminal input increase the extended timer-counter (ETC0). The counter becomes eventcounter mode if ET0CR Example :Generate interrupt of ETC0 after counting 100 (64H) times of rising edge CLR CLR LD LDW DI SET EI SET (ET0CR). 7 (EIRH). 2 ; enables interrupt INTET0 ; ; starts the counter (ET0CR). 7 (P1CR). 2 (ET0CR), 07H (ET0R), 0FF9BH ; stops the counter ; sets P12 (ETC0) for input ; event counter mode, detecting rising edge ; sets timer register (FFFFH to 0064H) Page 77 8. Extended Timer-Counter (ETC0) 8.1 Configuration TMP86CH06AUG Note:Altering source clock and edge type under event counter mode is allowed only if the extended timer has been stopped. Since ETC0 input terminal has digital noise cancellor, only pulse width of 2 machine cycles or longer is accepted. Pulse width of 1 machine cycle or shorter is neglected. It is unstable to acknowledge pulse width of between 1 and 2, as valid input. (input pulse width) < (1 machine cycle) not counted (1 machine cycle) (input pulse width) < (2 machine cycles) counted or not counted (depend on timing) (2 machine cycle) (input pulse width) counted 4/fc = 1 machine cycle (0.5 s at fc = 8 MHz) After detecting a rising (falling) edge, it is required to detect falling (rising) edge before detecting another rising (falling) edge. Machine cycle 1st detection 2nd detection 1st 2nd 1st 1st 1st 2nd 1st 2nd 1st 2nd detection detection detection detection detection detection detection detection detection detection ETC0 Signal sampled from ETC0 ET0R n n+1 n+2 n+3 Figure 8-3 Edge Filtering in Event Counter Mode (Rising Edge Detection) ET0S on ET0CR Signal sampled from ETC0 ET0R 1 2 FFFE FFFF 0 1 FFFE FFFF INTET0 interrupt Set ET0S on ET0CR Ready to count Overflow Continues counting interrupt generated Overflow interrupt generated (a) Interrupt generated after detection of FFFFH event counts ET0S on ET0CR Signal sampled from ETC0 ET0R FFAD FFAE FFAF FFB0 FFFE FFFF INTET0 interrupt Set FFADH on ET0R Ready to count Start count-up Continues counting Overflow interrupt generated (b) Interrupt generated after detection of 52H event counts Figure 8-4 Example of Event Counter Mode Operation (ETC0 Rising Edge Detection) Page 78 TMP86CH06AUG 8.4 Capturing input, Output comparing The extended timer-counter (ETC0) involves terminals for capturing input IC0 (P36) and output comparing OC0 (P37). Both IC0 and OC0 are available for general input/output ports if they are not involved in the extended timercounter (ETC0). Table 8-3 Capturing input and Output comparing Functions Shared function Operation Rising edge Falling edge Both edges "1" output "0" output toggle NOP Depend on timer 1 Accuracy Data register Capture input P36 2 Output compare P37 When capturing input function is to be used, assign input mode to P36 (set "0" on bit6 on P3CR). When output comparing function is to be used, assign output mode to P37 (set "1" on bit7 on P3CR) after P37 output latch (bit7 on P3DR) is set to "1". 8.4.1 Capturing input It is the function to measure matters, such as pulse width, frequency or duty. At the time the capturing acknowledged input changed, the contemporary rate on the extended timer-counter (ETC0) is loaded on the capture register. The capturing contains a digital noise-cancellor circuit in its block. A stable pulse of fc/8 or longer is required in order to inform the hardware of input, otherwise the pulse would not be acknowledged normally. Since the rate on the extended timer-counter (ETC0) is loaded on the capture register after the capturing samples every fc/4 with sampling clock, there is a lag of fc/4 to fc/8 between terminal input and capture register record. After detecting edge, the following capture operation is prohibited, until the data on the capture register ET0ICA. As for reading ET0ICA, read lower byte first then read upper byte. The capturing operates normally regardless of overflow of the counter, since the counter is still counting-up after overflow. fc/4 16-bit up counter source clock ET0R n n+1 n+2 n+3 n+4 n+5 IC0 (Note) Sampling clock fc/8 IC0 shift value IC0 Load signal ET0ICA n+2 Note: Sampling clock for IC0 input is fc/4, regardless of its source clock. Figure 8-5 Example of Event Counter Mode Operation (IC0 rising edge detection, Source clock of fc/4) Page 79 8. Extended Timer-Counter (ETC0) 8.4 Capturing input, Output comparing TMP86CH06AUG Example 1 :Capturing IC0 on rising edge with ETC0 CLR LD (P3CR).6 (ET0MIO), 0101****B ; Assigns input mode to P36 ; Enables capturing on rising edge Example 2 :Capturing positive pulse width IC0, with ETC0 (without using ET0ICB) CLR DI SET EI LD LP: TEST JR DI LD EI LD LD LP2: TEST JR SUB LD SUB DI LD EI (ILH), F7H ; Clears IL11 A, (ET0ICAL) W, (ET0ICAH) (ILH). 3 T, LP2 WA, (ET0ICA) HL, 0000H HL, WA ; Calculates pulse width and loads it on HL register ; Waits until IC0 falls (IL11 rises) ; Reads ET0ICA (ILH), F7H ; Clears IL11 (ET0MIO), 0111****B (ILH). 3 T, LP ; Enables capturing on both edges ; Waits until IC0 rises (IL11 rises) (EIRH). 3 ; Enables individual interrupt enable flag for INTIC0 (P3CR). 6 ; Assigns input mode to P36 If the data "1" is set on register PME located on the address same as ET0ICBL, the interrupt INTIC0 is requested as the second valid edge is detected. As this interrupt is requested, the first detected time (loaded on ET0ICB) and the second (loaded on ET0ICA) can be read consecutively. PME is cleared to "0" by hardware, after the edge is detected. Therefore, after the interrupt INTIC0 is requested, it is required to set "1" on PME again in order to continue extracting the 2-word data on capture register. As the second detected time (loaded on ET0ICA) is read, the capture operation is enabled again. As for extracting the 2-word data on capture register, read the first detected time (loaded on ET0ICB) before reading the second (loaded on ET0ICA). In order to extract the 2-word data normally, the data "1" should be set on PME before the first edge detection, if the capture operation has already been enabled. Page 80 TMP86CH06AUG Example 3 :Calculate (Second risen time) - (First risen time) and then calculate (Fourth risen time) - (Third risen time), as for IC0 input CLR SET DI SET LD EI LP: IC0: JR SET LD LD LP (ET0ICBL).0 HL, (ET0ICBL) BC, (ET0ICAL) ; Raises PME (interrupt after second edge detection) ; Reads the first (third) detected time ; Reads the second (fourth) detected time, ; Enables capturing again SUB RETI BC, HL ; Calculates time (EIRH).3 (ET0MIO), 0101----B ; Enables individual interrupt enable flag for INTIC0 ; Enables capturing on rising edge (P3CR).6 (PME).0 ; Assigns IC0 to P36 ; Rises PME (interrupt after second edge detection) 8.4.2 Output Comparing The output level alters at the time stated. The output mode is selected on the bits ET0MIO Note: ET0MIO Page 81 8. Extended Timer-Counter (ETC0) 8.4 Capturing input, Output comparing TMP86CH06AUG ET0R n-6 n-5 n-4 n-3 n-2 n-1 n n+1 n+2 n+3 n+4 ET0OCR OC0 terminal output INTOC0 interrupt n Data matches, terminal output changes as stated. interrupt requested (a) OC0: "1" (OCMODE = "01") mode ET0R n-6 n-5 n-4 n-3 n-2 n-1 n n+1 n+2 n+3 n+4 ET0OCR OC0 terminal output INTOC0 interrupt n Data matches, terminal output is kept. interrupt requested (b) OC0: NOP (OCMODE = "00") mode Figure 8-6 Examples for comparing operation Example 1 :Change OC0 output from "0" to "1" when ET0R = 0C80H. ("1" output mode) SET SET LDW LD CLR (P3DR).7 (P3CR).7 (ET0OCRL), 0C80H (ET0MIO), 1---0101B (ET0MIO).7 ; assigns OC0 output mode to P37 ; sets time for changing output ; initializes OC0 to "0" and assign "1" output mode to it ; prohibits OCID revising Example 2 : Change OC0 output from "1" to "0" when ET0R = 0C80H. (toggle output mode) SET SET LDW LD CLR (P3DR).7 (P3CR).7 (ET0OCRL), 0C80H (ET0MIO), 1---1111B (ET0MIO).7 ; assigns OC0 output mode to P37 ; sets time for changing output ; initializes OC0 to "1" and assigns toggle output mode to it ; prohibits OCID revising Page 82 TMP86CH06AUG Example 3 :Output the pulse with "0" for 1ms and "1" for 2ms, through OC0 terminal. (at fc = 8 [MHz]) LD LDW LD LD LD SET SET LD LD LD CLR SET OUT0: ADD LP: TEST JR DI LD EI LD LD OUT1: ADD LP1: TEST JR DI LD EI LD LD JR (ET0OCRL), A (ET0OCRH), W OUT0 ; sets time for changing output from "0" to "1" (ILH), 0EFH ; clears IL12 (ILH).4 T, LP1 ; waits for changing output from "1" to "0" (sets IL12) WA, BC ; calculates time to change output from "0" to "1" (ET0OCRL), A (ET0OCRH), W ; sets time for changing output from "1" to "0" (ILH), 0EFH ; clears IL12 (ILH).4 T, LP ; waits for changing output from "0" to "1" (sets IL12) WA, DE ; calculates time to change output from "1" to "0" (ET0CR), 01H (ET0R), 0000H BC, 03E8H DE, 07D0H WA, 03E8H (P3DR).7 (P3CR).7 (ET0OCRL), A (ET0OCRH), W (ET0MIO), 1---0111B (ET0MIO).7 (ET0CR).7 ; sets time for changing output ; initializes OC0 to "0" and assigns toggle output mode to it ; prohibits OCID revising ; ETC0 starts counting ; assigns OC0 output mode to P37 ; selects fc/8 (1 s) for source clock ; clears the counter ; substitutes "0" width (1 ms) for BC ; substitutes "1" width (2 ms) for DE ; substitutes "initial value" width (1 ms) for WA Example 4 :Generate only interrupt request when ET0R = 0C80H: without OC0 terminal output. LDW LD CLR (ET0OCRL), 0C80H (ET0MIO),1---1100B (ET0MIO).7 ; sets time for interrupt request ; initializes OC0 to "1" and assigns NOP output mode to it ; prohibits OCID revising Page 83 8. Extended Timer-Counter (ETC0) 8.4 Capturing input, Output comparing TMP86CH06AUG 8.5 Interrupting There are 3 sorts of interrupt requesting: for extended timer (INTET0), for capture input (INTIC0) and for output compare (INTOC0). 1. INTET0 The interrupt requesting is generated as the counter reaches FFFFH; meanwhile the counter is still counting up. 2. INTIC0 Interrupt requesting is triggered by capture input pin (IC0). The interrupt is requested when the timer value at edge detection is loaded on the capture register. 3. INTOC0 Interrupt requesting is triggered by comparator. The interrupt is requested when the rate of the timercounter and comparator matches. Page 84 TMP86CH06AUG 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration PWM mode Overflow fc/211 or fs/23 INTTC1 interrupt request fc/2 5 fc/2 fc/23 fs 7 fc/2 fc TI1 pin TC1M TC1S TFF1 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC1S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F1 TO1 pin TC1CK TC1CR TTREG1 PWREG1 PWM, PPG mode DecodeEN TFF1 PDO, PWM, PPG mode 16-bit mode TC0S PWM mode fc/211 or fs/23 fc/27 5 fc/2 3 fc/2 fs TI0 pin TC0M TC0S TFF0 fc/2 fc A B C D E F G H S Clear Y 8-bit up-counter Overflow 16-bit mode PDO mode INTTC0 interrupt request 16-bit mode Timer, Event Couter mode Toggle Q Set Clear Timer F/F0 TO0 pin TC0CK TC0CR TTREG0 PWREG0 PWM mode DecodeEN TFF0 PDO, PWM mode 16-bit mode Figure 9-1 8-Bit TimerCouter 0, 1 Page 85 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG 9.2 TimerCounter Control The TimerCounter 0 is controlled by the TimerCounter 0 control register (TC0CR) and two 8-bit timer registers (TTREG0, PWREG0). TimerCounter 0 Timer Register TTREG0 (0022H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG0 (0024H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG0) setting while the timer is running. Note 2: Do not change the timer register (PWREG0) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 0 Control Register TC0CR (0020H) 7 TFF0 6 5 TC0CK 4 3 TC0S 2 1 TC0M 0 (Initial value: 0000 0000) TFF0 Time F/F0 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs(Note 9) fc/2 fc TI0 pin input SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - fc (Note 8) R/W 000 001 TC0CK Operating clock selection [Hz] 010 011 100 101 110 111 TC0S TC0 start control 0: 1: 000: 001: TC0M TC0M operating mode select 010: 011: 1**: fc/211 fc/27 fc/25 fc/23 fs(Note 9) fc/2 fc R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC1M.) Reserved R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC0M, TC0CK and TFF0 settings while the timer is running. Note 3: To stop the timer operation (TC0S= 1 0), do not change the TC0M, TC0CK and TFF0 settings. To start the timer operation (TC0S= 0 1), TC0M, TC0CK and TFF0 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC1CR Page 86 TMP86CH06AUG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Note 9: When used as NORMAL1 and IDLE1 modes (low frequency is disabled), "fs" can not be used as source clock. Page 87 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 8-bit timer registers (TTREG1 and PWREG1). TimerCounter 1 Timer Register TTREG1 (0023H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG1 (0025H) R/ W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG1) setting while the timer is running. Note 2: Do not change the timer register (PWREG1) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 1 Control Register TC1CR (0021H) 7 TFF1 6 5 TC1CK 4 3 TC1S 2 1 TC1M 0 (Initial value: 0000 0000) TFF1 Timer F/F1 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/2 3 R/W SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - - R/W 000 001 TC1CK Operating clock selection [Hz] 010 011 100 101 110 111 TC1S TC1 start control 0: 1: 000: 001: 010: TC1M TC1M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/2 3 fs(Note 10) fc/2 fc fs(Note 10) fc/2 fc TI1 pin input Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC1M, TC1CK and TFF1 settings while the timer is running. Note 3: To stop the timer operation (TC1S= 1 0), do not change the TC1M, TC1CK and TFF1 settings. To start the timer operation (TC1S= 0 1), TC1M, TC1CK and TFF1 can be programmed. Note 4: When TC1M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC1 overflow signal regardless of the TC0CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC1M, where TC0CR Page 88 TMP86CH06AUG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC0CR Page 89 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/2 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - 3 fc/27 fc/25 fc/23 fs fc/2 fc TI0 pin input - - - TI1 pin input - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC0CK). Note 2: : Available source clock Table 9-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/2 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - 3 fc/27 fc/25 fc/23 fs fc/2 fc TI0 pin input - - - TI1 pin input - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC0CK). Note2: : Available source clock Page 90 TMP86CH06AUG Table 9-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 1 (TTREGn) 255 1 (TTREGn) 255 2 (PWREGn) 254 1 (TTREG1, 0) 65535 256 (TTREG1, 0) 65535 2 (PWREG1, 0) 65534 1 (PWREG1, 0) < (TTREG1, 0) 65535 16-bit PPG and (PWREG1, 0) + 1 < (TTREG1, 0) Register Value Note: n = 0 to 1 Page 91 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG 9.3 Function The TimerCounter 0 and 1 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 0 and 1 (TC0, 1) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 9.3.1 8-Bit Timer Mode (TC0 and 1) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR Table 9-4 Source Clock for TimerCounter 0, 1 (Internal Clock) Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 fs DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 fs SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs Resolution Repeated Cycle fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz 128 s 8 s 2 s 500 ns - 244.14 s - - - 30.5 s 32.6 ms 2.0 ms 510 s 127.5 s - 62.3 ms - - - 7.78 ms Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 s later (TimerCounter1, fc = 16.0 MHz) LD DI SET EI LD LD (TC1CR), 00010000B (TC1CR), 00011000B : Sets the operating cock to fc/27, and 8-bit timer mode. : Starts TC1. (EIRL). 7 : Enables INTTC1 interrupt. (TTREG1), 0AH : Sets the timer register (80 s/27/fc = 0AH). Page 92 TMP86CH06AUG TC1CR Internal Source Clock Counter TTREG1 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC1 interrupt request Figure 9-2 8-Bit Timer Mode Timing Chart (TC1) 9.3.2 8-Bit Event Counter Mode (TC0, 1) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TIj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TIj pin. Two machine cycles are required for the low- or high-level pulse input to the TIj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR TC1CR Counter TTREG1 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC1 interrupt request Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC1) 9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC0, 1) This mode is used to generate a pulse with a 50% duty cycle from the TOj pin. In the PDO mode, the up-counter counts up using the internal clock or external clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the TOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the TOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR Page 93 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG When the TIj pin input is selected as source clock (TC0CK="111"), two machine cycles are required for the low- or high-level pulse input to the TIj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Example :Generating 1024 Hz pulse using TC1 (fc = 16.0 MHz) Setting port LD LD LD (TTREG1), 3DH (TC1CR), 00010001B (TC1CR), 00011001B : 1/1024/27/fc/2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC1. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the TOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Page 94 TC1CR TC1CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Counter 0 1 2 Figure 9-4 8-Bit PDO Mode Timing Chart (TC1) Match detect Match detect Match detect Page 95 TTREG1 ? n Match detect Timer F/F1 Set F/F TO1 pin INTTC1 interrupt request Held at the level when the timer is stopped TMP86CH06AUG 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG 9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC0, 1) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock or external clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the TOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Table 9-5 PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 fs fc/2 fc DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 fs fc/2 fc SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 32.8 ms 2.05 ms 512 s 128 s 7.81 ms 32 s 16 s fs = 32.768 kHz 62.5 ms - - - 7.81 ms - - Page 96 TC1CR TC1CR Internal source clock n Write to PWREG4 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p Write to PWREG4 Figure 9-5 8-Bit PWM Mode Timing Chart (TC1) m Shift Shift m Match detect Match detect Page 97 n One cycle period m PWREG1 ? n p Shift p Match detect Shift Shift registar ? n Match detect Timer F/F1 TO1 pin n p INTTC1 interrupt request TMP86CH06AUG 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG 9.3.5 16-Bit Timer Mode (TC0 and 1) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 0 and 1 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG0, TTREG1) value is detected after the timer is started by setting TC1CR Note 1: In the timer mode, fix TCjCR Table 9-6 Source Clock for 16-Bit Timer Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 fs DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs SLOW1/2, SLEEP1/2 mode fs/23 - - - fs Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns - fs = 32.768 kHz 244.14 s - - - 30.5 s Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms - fs = 32.768 kHz 16 s - - - 2s Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW DI SET EI LD (TC0CR), 13H :Sets the operating cock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRL). 7 : Enables INTTC1 interrupt. (TTREG0), 927CH : Sets the timer register (300 ms/27/fc = 927CH). LD LD (TC0CR), 04H (TC0CR), 0CH Page 98 TMP86CH06AUG TC1CR Internal source clock Counter TTREG0 (Lower byte) TTREG1 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC1 interrupt request Figure 9-6 16-Bit Timer Mode Timing Chart (TC0 and TC1) 9.3.6 16-Bit Event Counter Mode (TC0 and 1) In the event counter mode, the up-counter counts up at the falling edge to the TI0 pin. The TimerCounter 0 and 1 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG0, TTREG1) value is detected after the timer is started by setting TC1CR Note 1: In the event counter mode, fix TCjCR 9.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC0 and 1) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 0 and 1 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG0, PWREG1) value is detected, the logic level output from the timer F/F1 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F1 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC1 interrupt is generated at this time. When the TI0 pin input is selected as source clock (TC0CK="111"), two machine cycles are required for the high- or low-level pulse input to the TI0 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F1 by TC1CR 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG (The logic level output from the TO1 pin is the opposite to the timer F/F1 logic level.) Since PWREG1 and 0 in the PWM mode are serially connected to the shift register, the values set to PWREG1 and 0 can be changed while the timer is running. The values set to PWREG1 and 0 during a run of the timer are shifted by the INTTCj interrupt request and loaded into PWREG1 and 0. While the timer is stopped, the values are shifted immediately after the programming of PWREG1 and 0. Set the lower byte (PWREG0) and upper byte (PWREG0) in this order to program PWREG1 and 0. (Programming only the lower or upper byte of the register should not be attempted.) If executing the read instruction to PWREG1 and 0 during PWM output, the values set in the shift register is read, but not the values set in PWREG1 and 0. Therefore, after writing to the PWREG1 and 0, reading data of PWREG1 and 0 is previous value until INTTC1 is generated. For the pin used for PWM output, the output latch of the I/O port must be set to 1. Note 1: In the PWM mode, program the timer register PWREG1 and 0 immediately after the INTTC1 interrupt request is generated (normally in the INTTC1 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC1 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the TO1 pin holds the output status when the timer is stopped. To change the output status, program TC1CR Table 9-7 16-Bit PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/2 fc/2 7 5 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms 2 s fs = 32.768 kHz 16 s - - - 2s - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 7 5 fc/23 fs fc/2 fc fc/23 fs fc/2 fc 8.2 ms 4.1 ms Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW LD (PWREG0), 07D0H (TC0CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Clears TFF1 to the initial value 0, and 16-bit PWM mode (upper byte). : Starts the timer. LD LD (TC1CR), 056H (TC1CR), 05EH Page 100 TC1CR TC1CR Internal source clock an Write to PWREG3 Counter 0 1 an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 Write to PWREG3 FFFF 0 1 cp PWREG1 (Upper byte) ? Write to PWREG4 n m p Write to PWREG4 Figure 9-7 16-Bit PWM Mode Timing Chart (TC0 and TC1) Page 101 b Shift Shift bm Match detect an One cycle period bm PWREG0 (Lower byte) ? a c Shift cp Match detect Match detect Shift 16-bit shift register ? an Match detect Timer F/F1 TO1 pin an cp INTTC1 interrupt request TMP86CH06AUG 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG 9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC0 and 1) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 0 and 1 are cascadable to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG0, PWREG1) value is detected, the logic level output from the timer F/F1 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F1 is switched to the opposite state again when a match between the up-counter and the timer register (TTREG0, TTREG1) value is detected, and the counter is cleared. The INTTC1 interrupt is generated at this time. When the TI0 pin input is selected as source clock (TC0CK="111"), two machine cycles are required for the high- or low-level pulse input to the TI0 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fc/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F1 by TC1CR Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz) Setting ports LDW LDW LD (PWREG0), 07D0H (TTREG0), 8002H (TC0CR), 33H : Sets the pulse width. : Sets the cycle period. : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). : Clears TFF1 to the initial value 0, and 16-bit PPG mode (upper byte). : Starts the timer. LD LD (TC1CR), 057H (TC1CR), 05FH Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the TO1 pin holds the output status when the timer is stopped. To change the output status, program TC1CR Page 102 TC1CR TC1CR Write of "0" Internal source clock 1 mn mn+1 qr-1 qr 0 1 mn mn+1 1 qr-1 qr 0 mn mn+1 0 Counter 0 PWREG1 (Upper byte) ? n Figure 9-8 16-Bit PPG Mode Timing Chart (TC0 and TC10) Page 103 Match detect Match detect Match detect mn mn PWREG0 (Lower byte) ? m Match detect Match detect TTREG1 (Upper byte) ? r TTREG0 (Lower byte) ? q F/F clear Held at the level when the timer stops mn Timer F/F1 TO1 pin INTTC1 interrupt request TMP86CH06AUG 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG 9.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 0 and 1 are cascadable to form a 16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. Note 1: In the warm-up counter mode, fix TCiCR 9.3.9.1 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 9-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz) Maximum Time Setting (TTREG1, 0 = 0100H) 7.81 ms Maximum Time Setting (TTREG1, 0 = FF00H) 1.99 s Example :After checking low-frequency clock oscillation stability with TC1 and 0, switching to the SLOW1 mode SET LD LD LD DI SET EI SET : PINTTC1: CLR SET (TC1CR).3 : (TC1CR).3 (SYSCR2).5 : Stops TC1 and 0. : SYSCR2 CLR RETI : VINTTC1: DW (SYSCR2).7 : PINTTC1 : INTTC1 vector table Page 104 TMP86CH06AUG 9.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 9-9 Setting Time in High-Frequency Warm-Up Counter Mode Minimum time (TTREG1, 0 = 0100H) 16 s Maximum time (TTREG1, 0 = FF00H) 4.08 ms Example :After checking high-frequency clock oscillation stability with TC1 and 0, switching to the NORMAL1 mode SET LD LD LD (SYSCR2).7 (TC0CR), 63H (TC1CR), 05H (TTREG0), 0F800H : SYSCR2 DI SET EI SET : PINTTC1: CLR CLR CLR (SYSCR2).6 RETI : VINTTC1: DW : PINTTC1 : INTTC1 vector table Page 105 9. 8-Bit TimerCounter (TC0, TC1) 9.1 Configuration TMP86CH06AUG Page 106 TMP86CH06AUG 10. Synchronous Serial Interface (SIO) The TMP86CH06AUG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. Serial interface is connected to outside peripherl devices via SO, SI, SCK port. 10.1 Configuration SIO control / status register SIOSR SIOCR1 SIOCR2 CPU Control circuit Buffer control circuit Shift register Shift clock Transmit and receive data buffer (8 bytes in DBR) 7 6 5 4 3 2 1 0 SO Serial data output 8-bit transfer 4-bit transfer SI Serial data input INTSIO interrupt request Serial clock SCK Serial clock I/O Figure 10-1 Serial Interface Page 107 10. Synchronous Serial Interface (SIO) 10.2 Control TMP86CH06AUG 10.2 Control The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be determined by reading SIO status register (SIOSR). The transmit and receive data buffer is controlled by the SIOCR2 SIOCR1 (0026H) 7 SIOS 6 SIOINH 5 4 SIOM 3 2 1 SCK 0 (Initial value: 0000 0000) SIOS Indicate transfer start / stop 0: 1: 0: 1: 000: 010: Stop Start Continuously transfer Abort transfer (Automatically cleared after abort) 8-bit transmit mode 4-bit transmit mode 8-bit transmit / receive mode 8-bit receive mode 4-bit receive mode Write only SIOINH Continue / abort transfer SIOM Transfer mode select 100: 101: 110: Except the above: Reserved NORMAL1/2, IDLE1/2 mode DV7CK = 0 000 001 SCK Serial clock select 010 011 100 101 110 111 fc/213 fc/28 fc/27 fc/26 fc/25 fc/24 DV7CK = 1 fs/25 fc/28 fc/27 fc/26 fc/25 fc/24 Reserved External clock ( Input from SCK pin ) SLOW1/2 SLEEP1/2 mode fs/25 Write only Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz] Note 2: Set SIOS to "0" and SIOINH to "1" when setting the transfer mode or serial clock. Note 3: SIOCR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. SIO Control Register 2 SIOCR2 (0027H) 7 6 5 4 WAIT 3 2 1 BUF 0 (Initial value: ***0 0000) Page 108 TMP86CH06AUG Always sets "00" except 8-bit transmit / receive mode. 00: WAIT Wait control 01: 10: 11: 000: 001: 010: BUF Number of transfer words (Buffer address in use) 011: 100: 101: 110: 111: Tf = TD(Non wait) Tf = 2TD(Wait) Tf = 4TD(Wait) Tf = 8TD (Wait) 1 word transfer 2 words transfer 3 words transfer 4 words transfer 5 words transfer 6 words transfer 7 words transfer 8 words transfer 0028H 0028H ~ 0029H 0028H ~ 002AH 0028H ~ 002BH 0028H ~ 002CH 0028H ~ 002DH 0028H ~ 002EH 0028H ~ 002FH Write only Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving. Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest address. ( The first buffer address transmitted is 0028H ). Note 3: The value to be loaded to BUF is held after transfer is completed. Note 4: SIOCR2 must be set when the serial interface is stopped (SIOF = 0). Note 5: *: Don't care Note 6: SIOCR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. SIO Status Register SIOSR (0027H) 7 SIOF 6 SEF 5 4 3 2 1 0 SIOF SEF Serial transfer operating status monitor Shift operating status monitor 0: 1: 0: 1: Transfer terminated Transfer in process Shift operation terminated Shift operation in process Read only Note 1: Tf; Frame time, TD; Data transfer time Note 2: After SIOS is cleared to "0", SIOF is cleared to "0" at the termination of transfer or the setting of SIOINH to "1". (output) SCK output TD Tf Figure 10-2 Frame time (Tf) and Data transfer time (TD) 10.3 Serial clock 10.3.1 Clock source Internal clock or external clock for the source clock is selected by SIOCR1 Page 109 10. Synchronous Serial Interface (SIO) 10.3 Serial clock TMP86CH06AUG 10.3.1.1 Internal clock Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The SCK pin goes high when transfer starts. When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. Table 10-1 Serial Clock Rate NORMAL1/2, IDLE1/2 mode DV7CK = 0 SCK 000 001 010 011 100 101 110 111 Clock fc/213 fc/28 fc/27 fc/26 fc/25 fc/24 External Baud Rate 1.91 Kbps 61.04 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps 976.56 Kbps External Clock fs/25 fc/28 fc/27 fc/26 fc/25 fc/24 External DV7CK = 1 Baud Rate 1024 bps 61.04 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps 976.56 Kbps External SLOW1/2, SLEEP1/2 mode Clock fs/25 External Baud Rate 1024 bps External Note: 1 Kbit = 1024 bit (fc = 16 MHz, fs = 32.768 kHz) Automatically wait function SCK pin (output) SO pin (output) Written transmit data a a0 a1 a2 a3 b b0 b1 c b2 b3 c0 c1 Figure 10-3 Automatic Wait Function (at 4-bit transmit mode) 10.3.1.2 External clock An external clock connected to the SCK pin is used as the serial clock. In this case, output latch of this port should be set to "1". To ensure shifting, a pulse width of at least 4 machine cycles is required. This pulse is needed for the shift operation to execute certainly. Actually, there is necessary processing time for interrupting, writing, and reading. The minimum pulse is determined by setting the mode and the program. Therfore, maximum transfer frequency will be 488.3K bit/sec (at fc=16MHz). SCK pin (Output) tSCKL tSCKH tcyc = 4/fc (In the NORMAL1/2, IDLE1/2 modes) 4/fs (In the SLOW1/2, SLEEP1/2 modes) tSCKL, tSCKH > 4tcyc Figure 10-4 External clock pulse width Page 110 TMP86CH06AUG 10.3.2 Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. 10.3.2.1 Leading edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/ output). 10.3.2.2 Trailing edge Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output). SCK pin SO pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register 3210 *321 **32 ***3 (a) Leading edge SCK pin SI pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register **** 0*** 10** 210* 3210 *; Don't care (b) Trailing edge Figure 10-5 Shift edge 10.4 Number of bits to transfer Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. The upper 4 bits are cleared to "0" when receiving. The data is transferred in sequence starting at the least significant bit (LSB). 10.5 Number of words to transfer Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred can be selected by SIOCR2 Page 111 10. Synchronous Serial Interface (SIO) 10.6 Transfer Mode TMP86CH06AUG SCK pin SO pin a0 a1 a2 a3 INTSIO interrupt (a) 1 word transmit SCK pin SO pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO interrupt (b) 3 words transmit SCK pin SI pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO interrupt (c) 3 words receive Figure 10-6 Number of words to transfer (Example: 1word = 4bit) 10.6 Transfer Mode SIOCR1 10.6.1 4-bit and 8-bit transfer modes In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data (number of transfer words to be transferred) to the data buffer registers (DBR). After the data are written, the transmission is started by setting SIOCR1 Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do not use the DBR of the remained 5 words. When an external clock is used, the data must be written to the data buffer register before shifting next data. Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. The transmission is ended by clearing SIOCR1 TMP86CH06AUG SIOCR1 Clear SIOS SIOCR1 SIOSR SIOSR SCK pin (Output) SO pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSIO interrupt DBR a Write Write (a) (b) b Figure 10-7 Transfer Mode (Example: 8bit, 1word transfer, Internal clock) Clear SIOS SIOCR1 SIOSR SIOSR SCK pin (Input) SO pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSIO interrupt DBR a Write Write (a) (b) b Figure 10-8 Transfer Mode (Example: 8bit, 1word transfer, External clock) Page 113 10. Synchronous Serial Interface (SIO) 10.6 Transfer Mode TMP86CH06AUG SCK pin SIOSR SO pin MSB of last word tSODH = min 3.5/fc [s] ( In the NORMAL1/2, IDLE1/2 modes) tSODH = min 3.5/fs [s] (In the SLOW1/2, SLEEP1/2 modes) Figure 10-9 Transmiiied Data Hold Time at End of Transfer 10.6.2 4-bit and 8-bit receive modes After setting the control registers to the receive mode, set SIOCR1 Note:Waits are also canceled by reading a DBR not being used as a received data buffer register is read; therefore, during SIO do not use such DBR for other applications. When an external clock is used, the shift operation is synchronized with the external clock; therefore, the previous data are read before the next data are transferred to the data buffer register. If the previous data have not been read, the next data will not be transferred to the data buffer register and the receiving of any more data will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay between the time when the interrupt request is generated and when the data received have been read. The receiving is ended by clearing SIOCR1 Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the transfer mode, end receiving by clearing SIOCR1 Page 114 TMP86CH06AUG Clear SIOS SIOCR1 SIOSR SIOSR SCK pin (Output) SI pin a0 a1 a2 a3 a4 a5 a6 a7 b0 b1 b2 b3 b4 b5 b6 b7 INTSIO Interrupt DBR a Read out b Read out Figure 10-10 Receive Mode (Example: 8bit, 1word transfer, Internal clock) 10.6.3 8-bit transfer / receive mode After setting the SIO control register to the 8-bit transmit/receive mode, write the data to be transmitted first to the data buffer registers (DBR). After that, enable the transmit/receive by setting SIOCR1 Page 115 10. Synchronous Serial Interface (SIO) 10.6 Transfer Mode TMP86CH06AUG Note:The buffer contents are lost when the transfer mode is switched. If it should become necessary to switch the transfer mode, end receiving by clearing SIOCR1 Clear SIOS SIOCR1 SIOSR SIOSR SCK pin (output) SO pin a0 c0 a1 c1 a2 c2 a3 c3 a4 c4 a5 c5 a6 c6 a7 c7 b0 d0 b1 d1 b2 d2 b3 d3 b4 d4 b5 d5 b6 d6 b7 d7 SI pin INTSIO interrupt DBR a Write (a) Read out (c) c b Write (b) d Read out (d) Figure 10-11 Transfer / Receive Mode (Example: 8bit, 1word transfer, Internal clock) SCK pin SIOSR SO pin Bit 6 Bit 7 of last word tSODH = min 4/fc [s] ( In the NORMAL1/2, IDLE1/2 modes) tSODH = min 4/fs [s] (In the SLOW1/2, SLEEP1/2 modes) Figure 10-12 Transmitted Data Hold Time at End of Transfer / Receive Page 116 TMP86CH06AUG 11. Asynchronous Serial interface (UART0 ) 11.1 Configuration UART control register 1 UART0CR1 Transmit data buffer TD0BUF Receive data buffer RD0BUF 3 2 Receive control circuit 2 Transmit control circuit Shift register Shift register Parity bit Stop bit Noise rejection circuit RXD0 INTTXD0 INTRXD0 TXD0 Transmit/receive clock Y M P X S 2 Y Counter UART0SR S fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 INTTC0 A B C fc/2 fc/27 8 fc/2 6 fc/96 A B C D E F G H 4 2 UART0CR2 UART status register Baud rate generator UART control register 2 MPX: Multiplexer Figure 11-1 UART0 (Asynchronous Serial Interface) Page 117 11. Asynchronous Serial interface (UART0 ) 11.2 Control TMP86CH06AUG 11.2 Control UART0 is controlled by the UART0 Control Registers (UART0CR1, UART0CR2). The operating status can be monitored using the UART status register (UART0SR). UART0 Control Register1 UART0CR1 (001AH) 7 TXE 6 RXE 5 STBT 4 EVEN 3 PE 2 1 BRG 0 (Initial value: 0000 0000) TXE RXE STBT EVEN PE Transfer operation Receive operation Transmit stop bit length Even-numbered parity Parity addition 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 000: 001: 010: 011: 100: 101: 110: 111: Disable Enable Disable Enable 1 bit 2 bits Odd-numbered parity Even-numbered parity No parity Parity fc/13 [Hz] fc/26 fc/52 fc/104 fc/208 fc/416 TC0 ( Input INTTC0) fc/96 Write only BRG Transmit clock select Note 1: When operations are disabled by setting TXE and RXE bit to "0", the setting becomes valid when data transmit or receive complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. Note 2: The transmit clock and the parity are common to transmit and receive. Note 3: UART0CR1 UART0 Control Register2 UART0CR2 (001BH) 7 6 5 4 3 2 RXDNC 1 0 STOPBR (Initial value: **** *000) RXDNC Selection of RXD input noise rejectio time 00: 01: 10: 11: 0: 1: No noise rejection (Hysteresis input) Rejects pulses shorter than 31/fc [s] as noise Rejects pulses shorter than 63/fc [s] as noise Rejects pulses shorter than 127/fc [s] as noise 1 bit 2 bits Write only STOPBR Receive stop bit length Note: When UART0CR2 Page 118 TMP86CH06AUG UART0 Status Register UART0SR (001AH) 7 PERR 6 FERR 5 OERR 4 RBFL 3 TEND 2 TBEP 1 0 (Initial value: 0000 11**) PERR FERR OERR RBFL TEND TBEP Parity error flag Framing error flag Overrun error flag Receive data buffer full flag Transmit end flag Transmit data buffer empty flag 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: No parity error Parity error No framing error Framing error No overrun error Overrun error Receive data buffer empty Receive data buffer full On transmitting Transmit end Transmit data buffer full (Transmit data writing is finished) Transmit data buffer empty Read only Note: When an INTTXD is generated, TBEP flag is set to "1" automatically. UART0 Receive Data Buffer RD0BUF (001CH) 7 6 5 4 3 2 1 0 Read only (Initial value: 0000 0000) UART0 Transmit Data Buffer TD0BUF (001CH) 7 6 5 4 3 2 1 0 Write only (Initial value: 0000 0000) Page 119 11. Asynchronous Serial interface (UART0 ) 11.3 Transfer Data Format TMP86CH06AUG 11.3 Transfer Data Format In UART0, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UART0CR1 PE STBT 1 Start 2 Bit 0 3 Bit 1 Frame Length 8 Bit 6 9 Bit 7 10 Stop 1 11 12 0 0 1 1 0 1 0 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Stop 1 Stop 2 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Start Bit 0 Bit 1 Bit 6 Bit 7 Parity Stop 1 Stop 2 Figure 11-2 Transfer Data Format Without parity / 1 STOP bit With parity / 1 STOP bit Without parity / 2 STOP bit With parity / 2 STOP bit Figure 11-3 Caution on Changing Transfer Data Format Note: In order to switch the transfer data format, perform transmit operations in the above Figure 11-3 sequence except for the initial setting. Page 120 TMP86CH06AUG 11.4 Transfer Rate The baud rate of UART0 is set of UART0CR1 Source Clock BRG 16 MHz 000 001 010 011 100 101 76800 [baud] 38400 19200 9600 4800 2400 8 MHz 38400 [baud] 19200 9600 4800 2400 1200 4 MHz 19200 [baud] 9600 4800 2400 1200 600 When TC0 is used as the UART0 transfer rate (when UART0CR1 11.5 Data Sampling Method The UART0 receiver keeps sampling input using the clock selected by UART0CR1 RXD0 pin Start bit RT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Bit 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (a) Without noise rejection circuit Bit 0 RXD0 pin Start bit RT0 1 2 3 4 5 6 7 8 Bit 0 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 RT clock Internal receive data Start bit (b) With noise rejection circuit Bit 0 Figure 11-4 Data Sampling Method Page 121 11. Asynchronous Serial interface (UART0 ) 11.6 STOP Bit Length TMP86CH06AUG 11.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UART0CR1 11.7 Parity Set parity / no parity by UART0CR1 11.8 Transmit/Receive Operation 11.8.1 Data Transmit Operation Set UART0CR1 11.8.2 Data Receive Operation Set UART0CR1 Note:When a receive operation is disabled by setting UART0CR1 Page 122 TMP86CH06AUG 11.9 Status Flag 11.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UART0SR RXD0 pin Parity Stop Shift register UART0SR |