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8 Bit Microcontroller
TLCS-870/C Series
TMP86FM48
The information contained herein is subject to change without notice. 021023_D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
(c) 2007 TOSHIBA CORPORATION All Rights Reserved
TMP86FM48
CMOS 8-Bit Microcontroller
TMP86FM48UG/FG
The TMP86FM48 is the high-speed, high-performance and low power consumption 8-bit microcomputer, including FLASH, RAM, multi-function timer/counter, serial interface (UART, SIO, I2C), a 10-bit AD converter and two clock generators on chip. Product No.
TMP86FM48UG TMP86FM48FG
FLASH
(Program area) 32256 x 8 bits
FLASH
(Data area) 512 x 8 bits
RAM
2.0 K x 8 bits
Package
LQFP64-P-1010-0.50E QFP64-P-1414-0.80C
Emulation Chip
TMP86C948XB
Features
8-bit single chip microcomputer TLCS-870/C series Instruction execution time: 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) 132 types and 731 basic instructions 20 interrupt sources (External: 5, Internal: 15) Input/output ports (54 pins) 16-bit timer counter: 2 ch * Timer, Event counter, Pulse width measurement, External trigger timer, Window, PPG output modes 8-bit timer counter: 2 ch * Timer, Event counter, PWM output, Programmable divider output, Capture modes Time base timer Divider output function Watchdog timer * Interrupt source/internal reset generate (Programmable)
TMP86FM48FG QFP64-P-1414-0.80C TMP86FM48UG LQFP64-P-1010-0.50E
* The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S
86FM48-1
2007-08-24
TMP86FM48
Serial interface * UART/SIO: 1ch * SIO: 1ch * I2C bus: 1ch 10-bit successive approximation type AD converter * Analog input: 16 ch Four Key-on wake-up pins Dual clock operation * Single/dual-clock mode Nine power saving operating modes * STOP mode: Oscillation stops. Battery/capacitor back-up. Port output hold/High-impedance. CPU stops, and peripherals operate using high-frequency clock of Time-Base-Timer. Release by falling edge of TBTCR setting. CPU stops, and peripherals operate using high-frequency clock. Release by interruputs. CPU stops, and peripherals operate using high and low-frequency clock. Release by interruputs. CPU stops, and peripherals operate using low-frequency clock of time-base-timer. Release by falling edge of TBTCR setting. CPU stops, and peripherals operate using low-frequency clock. Release by interrupts. CPU stops, and peripherals operate using high- and low-frequency clock. Release by interrupts.
* SLOW 1, 2 mode: Low-power consumption operation using low-frequency clock (32.768 kHz) * IDLE 0 mode: * IDLE 1 mode: * IDLE 2 mode: * SLEEP 0 mode: * SLEEP 1 mode: * SLEEP 2 mode:
Wide operating voltage: 1.8 to 3.6 V at 8 MHz/32.768 kHz 2.7 to 3.6 V at 16 MHz/32.768 kHz
86FM48-2
2007-08-24
LQFP64-P-1010-0.50E QFP64-P-1414-0.80C
Pin Assignments (Top view)
P80 P81 P82 P83 P84 P85 P86 P87 P30 P31 P32 P33 P34 P35 P36 P37 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22
RESET
86FM48-3
(STOP/INT5) (SO2) (SI2) (SCK2) (PWM5/PDO5/TC5) (INT3/TC3) (TC1) P20 P10 P11 P12 P13 P14 P15 P16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 AVDD VAREF AVSS/VASS BOOT P52 P51 ( DVO /SDA) P50 ( PPG /SCL) P07 ( SCK1 ) P06 (SO1/TXD) P05 (SI1/RXD) P04 P03 (TC2) P02 (INT2) P01 (INT1) P00 ( INT0 ) P17
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P77(AIN17) P76 (AIN16) P75 (AIN15) P74 (AIN14) P73 (AIN13) P72 (AIN12) P71 (AIN11) P70 (AIN10) P67 (AIN07/STOP3) P66 (AIN06/STOP2) P65 (AIN05/STOP1) P64 (AIN04/STOP0) P63 (AIN03) P62 (AIN02) P61 (AIN01) P60 (AIN00)
TMP86FM48
2007-08-24
TMP86FM48
Block Diagram
I/O ports P87 to P80 P37 to P30
P8 Power supply VDD VSS
P3
Address/Data bus
Reset input TEST pin
RESET
TLCS-870/C CPU System control circuit Standby control circuit (Key-on wake-up) Timing generator
Data memory (RAM)
Program memory (FLASH)
Data memory (FLASH)
I2C
TEST
Interrupt controller
Resonator connecting pins
Time base timer XIN XOUT High frequency Clock Low generator frequency
16-bit timer/counter TC1 TC2
8-bit timer/counter TC3 TC5
SIO UART SIO2 SIO1
Watchdog timer
Address/Data bus P2 P7 P6 P1 P0 P5
10-bit AD converter
P22 to P20 P77 (AIN17) to P70 (AIN10) I/O ports
AVDD VAREF AVSS/VASS
P67 (AIN07) P17 to P10 to P60 (AIN00) I/O ports
P07 to P00
P52 to P50
Analog reference pins
86FM48-4
2007-08-24
TMP86FM48
Pin Functions (1/2)
Pin Name
P07 ( SCK1 ) P06 (TXD, SO1) P05 (RXD, SI1) P04 P03 (TC2) P02 (INT2) P01 (INT1) P00 ( INT0 ) P17 P16 P15 (TC1) P14 (TC3,INT3) P13 ( PWM5 , PDO5 , TC5) P12 ( SCK2 ) P11 (SI2) P10 (SO2) P22 (XTOUT) P21 (XTIN) P20 ( INT5 , STOP )
Input/Output
I/O (I/O) I/O (Output) I/O (Input) I/O I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O I/O I/O (Input) I/O (Input) I/O (I/O) I/O (I/O) I/O (Input) I/O (Output) I/O (Output) I/O (Input) I/O (Input)
Functions
8-bit input/output port with latch. When used as a serial interface output or UART output, respective output latch (P0DR) should be set to "1". When used as an input port, an serial interface input, UART input, timer counter input or an external interrupt input, respective output control (P0OUTCR) should be cleared to "0" after setting P0DR to "1". 8-bit input/output port with latch. When used as a timer/counter output or serial interface output, respective output latch (P1DR) should be set to "1". When used as an input port, a timer counter input, an external interrupt input or serial interface input, respective output control (P1OUTCR) should be cleared to "0" after setting P1DR to "1". Serial clock input/output 1 UART data output, Serial data output 1 UART data input, Serial data input 1 Timer counter 2 input External interrupt 2 input External interrupt 1 input External interrupt 0 input
Timer counter 1 input Timer counter 3 input, External interrupt 3 input PWM5 output, PDO5 output, Timer/counter 5 input Serial clock input/output 2 Serial data input 2 Serial data output 2
3-bit input/output port with latch. When used as an input port or an external interrupt input, respective output control (P2OUTCR) should be cleared to "0" after setting output latch (P2DR) to "1". 8-bit input/output port with latch (N-ch high-current output). When used as an input port, respective output control (P3OUTCR) should be cleared to "0" after setting output latch (P3DR) to "1". 3-bit input/output port with latch (N-ch high-current output). When used as an 2 input port or I C bus interface input/output, respective output control (P5OUTCR) should be cleared to "0" after setting output latch (P5DR) to "1". When used as a PPG output or divider output, respective P5DR should be set to "1". 8-bit programmable input/output port (tri-state). Each bit of this port can be individually configured as an input or an output under software control. When used as an input port, respective input/output control (P6CR1) should be cleared to "0" after setting input control (P6CR2) to "1". When used as an analog input or key on wake up input, respective P6CR1 should be cleared to "0" after clearing P6CR2 to "0". When used as a key on wake up input, STOPCR should be set to "1". (i = 0 to 3)
Resonator connecting pins (32.768 kHz) For inputting external clock, XTIN is used and XTOUT is opened. External interrupt input 5 or STOP mode release signal input
P37 to P30
I/O
P52
I/O
P51 ( DVO , SDA)
I/O (Output,I/O)
Divider Output/I C bus serial data input/output PPG Output/I C bus serial clock input/output STOP 3 input STOP 2 input STOP 1 input STOP 0 input AD converter analog inputs
2
2
P50 ( PPG , SCL) P67 (AIN07, STOP3) P66 (AIN06, STOP2) P65 (AIN05, STOP1) P64 (AIN04, STOP0) P63 (AIN03) P62 (AIN02) P61 (AIN01) P60 (AIN00)
I/O (Output,I/O) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input)
86FM48-5
2007-08-24
TMP86FM48
Pin Functions (2/2)
Pin Name
P77 (AIN17) P76 (AIN16) P75 (AIN15) P74 (AIN14) P73 (AIN13) P72 (AIN12) P71 (AIN11) P70 (AIN10)
Input/Output
I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input)
Functions
8-bit programmable input/output port (tri-state). Each bit of this port can be individually configured as an input or an output under software control. When used as an input port, respective input/output control (P7CR1) should be cleared to "0" after setting input control (P7CR2) to "1". When used as an analog input, respective P7CR1 should be cleared to "0" after clearing P7CR2 to "0". 8-bit input/output port with latch (N-ch high-current output). When used as an input port, respective output control (P8OUTCR) should be cleared to "0" after setting output latch (P8DR) to "1".
Pin Name
AD converter analog inputs
P87 to P80
I/O
XIN, XOUT
RESET
Input Output Input Input Input
Resonator connecting pins for high-frequency clock. For inputting external clock, XIN is used and XOUT is opened. Reset signal input Test pin for out-going test. Be fixed to low. Serial prom mode control input. When writing to FLASH memory, BOOT pin should be fixed to high level. Power supply for operation
TEST BOOT VDD, VSS VAREF AVDD AVSS/VASS
Power Supply
Analog reference voltage for AD conversion AD circuit power supply AD circuit power supply/Analog reference GND for AD conversion
86FM48-6
2007-08-24
TMP86FM48
Operational Description 1. CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit.
1.1
Memory Address Map
The TMP86FM48 memory consists of 5 blocks: FLASH memory, BOOT ROM, RAM, DBR (Data buffer register) and SFR (Special function register). They are all mapped in 64-Kbyte address space. Figure 1.1.1 shows the TMP86FM48 memory address map. The general-purpose registers are not assigned to the RAM address space.
0000H SFR 003FH 0040H 64 bytes FLASH memory: FLASH memory includes: Program memory (The area of 8000H to 81FFH can be used as data memory.) Vector table BOOT ROM: FLASH writing program RAM: Random Access Memory includes: Data memory Stack SFR: Special Function Register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Interrupt control registers Program Status Word DBR: Data Buffer Register includes: Peripheral control registers Peripheral Status registers
RAM 083FH 1F80H DBR 1FFFH 3800H BOOT ROM 3FFFH FLASH memory (Data memory) 8000H 81FFH 8200H
2048 bytes
128 bytes
2048 bytes
512 bytes
32176 bytes FLASH memory (Program memory) FFB0H FFBFH FFC0H FFDFH FFE0H FFFFH 16 bytes 32 bytes 32 bytes Vector table for interrupts (8 vectors) Vector table for vector call instructions (16 vectors) Vector table for interrupts/reset (16 vectors)
Figure 1.1.1 Memory Address Maps
1.2
Program Memory (FLASH)
The TMP86FM48 has a 32 K x 8 bits (Address 8000H to FFFFH) of program memory (FLASH). The area of 8000H to 81FFH can be used as a 512 x 8 bits data memory of FLASH.
86FM48-7
2007-08-24
TMP86FM48
1.3
Data Memory (RAM)
The TMP86FM48 has 2048 bytes of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine.
Example: Clears RAM to "00H". LD HL, 0040H LD A, H LD BC, 07FFH SRAMCLR: LD (HL), A INC HL DEC BC JRS F, SRAMCLR
; ; ;
Start address setup Initial value (00H) setup
86FM48-8
2007-08-24
TMP86FM48
1.4
System Clock Controller
The system clock controller consists of a clock generator, a timing generator, and a standby controller.
Timing generator control register TBTCR Clock generator XIN High-frequency clock oscillator XOUT XTIN Low-frequency clock oscillator fs System clocks 0038H 0039H SYSCR2 SYSCR1 Clock generator control fc Timing generator Standby controller 0036H
XTOUT
System control registers
Figure 1.4.1 System Clock Control
1.4.1
Clock Generator
The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: one for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) and low-frequency (fs) clocks can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected.
High-frequency clock Low-frequency clock XOUT (Open) XTIN XTOUT XTIN XTOUT (Open)
XIN
XOUT
XIN
(a) Crystal/Ceramic resonator
(b) External oscillator
(c) Crystal
(d) External oscillator
Figure 1.4.2 Examples of Resonator Connection Note: The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance.
86FM48-9
2007-08-24
TMP86FM48 1.4.2 Timing Generator
The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. a. b. c. d. e. f. Generation of main system clock Generation of divider output ( DVO ) pulses Generation of source clocks for time base timer Generation of source clocks for watchdog timer Generation of internal source clocks for timer/counters and serial interface Generation of warm-up clocks for releasing STOP mode
(1) Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, TBTCR, that is shown in Figure 1.4.4. As reset and STOP mode started/canceled, the prescaler and the divider are cleared to "0".
Main system clock generator
SYSCR2 TBTCR
fc or fs
Machine cycle counters
fc/4
High-frequency clock fc Low-frequency clock fs Timer/counters 1 12 123456
S A Y B
Divider
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Multiplexer
Multiplexer
S B0 B1 A0 Y0 A1 Y1
Warm-up controller
Timer/counters 2
Watchdog timer Timer/counters 3
Time base timer Timer/counters 5
Divider output circuit Serial interface
Figure 1.4.3 Configuration of Timing Generator
86FM48-10
2007-08-24
TMP86FM48
TBTCR (0036H)
7
(DVOEN)
6
5
4
DV7CK
3
(TBTEN)
2
1
(TBTCK)
0 (Initial value: 0000 0000)
(DVOCK)
DV7CK Note 1: Note 2: Note 3: Note 4:
Selection of input to the 7th 0: fc/2 [Hz] 1: fs stage of the divider In single clock mode, do not set DV7CK to "1". Do not set "1" on DV7CK while the low-frequency clock is not operated stably. fc: High-frequency clock [Hz], fc: Low-frequency clock [Hz], *: Don't care
8
R/W
In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider.
Note 5:
When STOP mode is entered from NORMAL 1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period.
Figure 1.4.4 Timing Generator Control Register (2) Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C series: ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock.
1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3
Machine cycle
Figure 1.4.5 Machine Cycle
86FM48-11
2007-08-24
TMP86FM48 1.4.3 Operation Mode Control Circuit
The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and low-frequency clocks, and switches the main system clock. There are two operating modes: single-clock and dual-clock. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 1.4.6 shows the operating mode transition diagram and Figure 1.4.7 shows the system control registers. (1) Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. a. NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86FM48 is placed in this mode after reset. b. IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2, and IDLE1 mode is released to NORMAL1 mode by an interrupt request from the on-chip peripherals or external interrupt inputs. When the IMF (Interrupt master enable flag) is "1" (Interrupt enable), the execution will resume with the acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When the IMF is "0" (Interrupt disable), the execution will resume with the instruction which follows the IDLE1 mode start instruction. c. IDLE0 mode In this mode, all the circuit, except oscillator and the time-base-timer, stops operation. This mode is enabled by setting "1" on bit TGHALT on the system control register 2 (SYSCR2). When IDLE0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR, the timing generator starts feeding the clock to all peripheral circuits. When returned from IDLE0 mode, the CPU restarts operating, entering NORMAL1 mode back again. IDLE0 mode is entered and returned regardless of how TBTCR is set. When IMF = "1", EF7 (TBT interrupt individual enable flag) = "1", and TBTCR = "1", interrupt processing is performed. When IDLE0 mode is entered while TBTCR = "1", the INTTBT interrupt latch is set after returning to NORMAL1 mode.
86FM48-12
2007-08-24
TMP86FM48
(2) Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 s at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C is placed in the single-clock mode during reset. To use the dual-clock mode, the low-frequency oscillator should be turned on at the start of a program. a. NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. b. SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. On-chip peripherals are triggered by the low-frequency clock. As the SYSCK on SYSCR2 becomes "0", the hardware changes into NORMAL2 mode. As the XEN on SYSCR2 becomes "0", the hardware changes into SLOW1 mode. Do not clear XTEN to "0" during SLOW2 mode. c. SLOW1 mode This mode can be used to reduce power-consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock. Switching back and forth between SLOW1 and SLOW2 modes are performed by XEN bit on the system control register 2 (SYSCR2). In SLOW1 and SLEEP mode, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. d. IDLE2 mode In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode. e. SLEEP1 mode In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW mode. In SLOW and SLEEP mode, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped.
86FM48-13
2007-08-24
TMP86FM48
f. SLEEP2 mode The SLEEP2 mode is the IDLE mode corresponding to the SLOW2 mode. The status under the SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the high-frequency clock. g. SLEEP0 mode In this mode, all the circuit, except oscillator and the time-base-timer, stops operation. This mode is enabled by setting "1" on bit TGHALT on the system control register 2 (SYSCR2). When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR, the timing generator starts feeding the clock to all peripheral circuits. When returned from SLEEP0 mode, the CPU restarts operating, entering SLOW1 mode back again. SLEEP0 mode is entered and returned regardless of how TBTCR is set. When IMF = "1", EF7 (TBT interrupt individual enable flag) = "1", and TBTCR = "1", interrupt processing is performed. When SLEEP0 mode is entered while TBTCR = "1", the INTTBT interrupt latch is set after returning to SLOW1 mode. (3) STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin or key on wake up pin input which is enabled by STOPCR. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Note 1: When the IDLE0/1/2 and SLEEP0/1/2 modes are started with the EEPCR = "0", the CPU wait period for stabilizing of the power supply of Flash control circuit is executed after being released from these mode. Note 2: When the STOP mode is started with the EEPCR = "1", the CPU wait period for stablizing of the power supply of Flash control circuit is executed after in the STOP warm-up time.
86FM48-14
2007-08-24
TMP86FM48
IDLE0 mode (Note 2)
Reset release
RESET
SYSCR2 = "1" SYSCR2 = "1" IDLE1 mode Interrupt (a) Single clock mode SYSCR2 = "0" SYSCR2 = "1" IDLE2 mode Interrupt SYSCR2 = "0" SYSCR2 = "1" SLEEP2 mode Interrupt SYSCR2 = "1" SYSCR2 = "1" SLEEP1 mode Interrupt (Note 2) (b) Dual clock mode SLEEP0 mode SLOW1 mode SLOW2 mode NORMAL2 mode NORMAL1 mode
SYSCR1 = "1"
STOP pin input
SYSCR2 = "1" SYSCR1 = "1"
STOP pin input
SYSCR2 = "1" STOP
SYSCR2 = "0" SYSCR1 = "1"
STOP pin input
SYSCR2 = "1"
Note 1:
NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP.
Note 2:
The mode is released by falling edge of TBTCR setting. Oscillator Other Peripherals Reset Operate Halt 4/fc [s] Machine Cycle Time
Operating Mode High Frequency Low Frequency RESET Single Clock NORMAL1 IDLE1 IDLE0 STOP NORMAL2 IDLE2 SLOW2 Dual Clock SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP Stop Stop Oscillation Oscillation Stop Oscillation Stop
CPU Core Reset Operate
TBT Reset Operate
Halt Halt Operate with high frequency Halt Operate with low frequency Halt Operate with low frequency Halt Halt Operate
- 4/fc [s]
Operate 4/fs [s]
Halt
-
Figure 1.4.6 Operating Mode Transition Diagram
86FM48-15
2007-08-24
TMP86FM48
System Control Register 1 SYSCR1 7 6 (0038H) STOP RELM
5 RETM
4 OUTEN
3 WUT
2
1
0 (Initial value: 0000 00**)
STOP RELM RETM OUTEN
WUT
0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) Release method for STOP pin 0: Edge-sensitive release (P20) 1: Level-sensitive release Operating mode after STOP 0: Return to NORMAL1/2 mode mode 1: Return to SLOW1 mode Port output during STOP 0: High impedance mode 1: Output kept Return to NORMAL mode Return to SLOW mode 16 10 13 3 00 3 x 2 /fc + (2 /fc) 3 x 2 /fs + (2 /fs) Warm-up time at releasing 16 10 13 3 01 2 /fc + (2 /fc) 2 /fs + (2 /fs) STOP mode (Note 8) 14 10 6 3 10 3 x 2 /fc + (2 /fc) 3 x 2 /fs + (2 /fs) 14 10 6 3 11 2 /fc + (2 /fc) 2 /fs + (2 /fs) STOP mode start
R/W
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause interrupt request on account of falling edge. When the key-on wake-up input (STOP0 to STOP3) is used, RELM should be set to "1". Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. When the STOP mode is started with the EEPCR = "1", the CPU wait period for stabilizing of the power supply of Flash control circuit is executed after in the STOP warm-up time. (The CPU wait period for FLASH is shown in parentheses)
System Control Register 2 SYSCR2 7 6 (0039H) XEN XTEN
5 SYSCK
4 IDLE
3
2 TGHALT
1
0 (Initial value: 1000 *0**)
XEN XTEN SYSCK
High-frequency oscillator control Low-frequency oscillator control Main system clock select (write)/main system clock monitor (read) CPU and watchdog timer control (IDLE1/2, SLEEP1/2 mode) TG control (IDLE0, SLEEP0 mode)
IDLE
TGHALT
0: Turn off oscillation 1: Turn on oscillation 0: Turn off oscillation 1: Turn on oscillation 0: High-frequency clock 1: Low-frequency clock 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (start IDLE1/2, SLEEP1/2 mode) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0, SLEEP0 mode)
R/W
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: Note 8:
A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". *: Don't care, TG: Timing generator Bits 3, 1and 0 in SYSCR2 are always read as undefined value. Do not set IDLE and TGHALT to "1" simultaneously. Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR. When IDLE1/2 or SLEEP1/2 mode is released, IDLE is automatically cleared to "0". When IDLE0 or SLEEP0 mode is released, TGHALT is automatically cleared to "0". Before setting TGHALT to "1", be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals may be set after IDLE0 or SLEEP0 mode is released.
Figure 1.4.7 System Control Registers
86FM48-16
2007-08-24
TMP86FM48 1.4.4 Operating Mode Control
(1) STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key-on wake-up input (STOP0 to STOP3) which is controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (External interrupt input 5) pin. STOP mode is started by setting SYSCR1 to "1". During STOP mode, the following status is maintained. a. b. c. Oscillations are turned off, and all internal operations are halted. The data memory, registers, the program status word and port output latches are all held in the status in effect before STOP mode was entered. The prescaler and the divider of the timing generator are cleared to "0".
d. The program counter holds the address 2 ahead of the instruction (e.g. [SET (SYSCR1).7]) which started STOP mode. STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the SYSCR1. Do not use any STOPx (x: 0 to 3) pin input for releasing STOP mode in edge-sensitive mode. When the STOP mode is started with the EEPCR = "1", the CPU wait period for stabilizing of the power supply of Flash control circuit is executed after in the STOP warming-up time.
Note 1: The STOP mode can be released by either the STOP or key-on wake-up pin (STOP0 to STOP3). However, because the STOP pin is different from the key-on wake-up and can not inhibit the release input, the STOP pin must be used for releasing STOP mode. Note 2: During stop period (from start of STOP mode to end of warm-up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. a. Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high or setting the STOPx (x: 0 to 3) pin input which is enabled by STOPCR. This mode is used for capacitor back-up when the main power supply is cut off and long term battery back-up. When the STOP pin input is high, executing an instruction which starts STOP mode will not place in STOP mode but instead will immediately start the release sequence (Warm-up). Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low. The following two methods can be used for confirmation. a. b. Testing a port P20. Using an external interrupt input INT5 ( INT5 is a falling edge-sensitive input).
86FM48-17
2007-08-24
TMP86FM48
Example 1: Starting STOP mode from NORMAL mode by testing a port P20. LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode SSTOPH: TEST (P2PRD). 0 ; Wait until the STOP pin input goes low level JRS SET F, SSTOPH (SYSCR1).7 ; Starts STOP mode
Example 2: Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if port P20 is at high JRS F, SINT5 LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode. SET (SYSCR1). 7 ; Starts STOP mode SINT5: RETI Only when EEPCR is "1". (The CPU wait period is added.)
STOP pin
XOUT pin NORMAL operation STOP operation NORMAL CPU wait operation period STOP mode is released by the hardware. Always released if the STOP pin input is high. STOP Warm-up
Note: When the STOP mode is started with the EEPCR = "1", the CPU wait for stabilizing of the power supply of Flash control circuit is executed after in the STOP warming-up time.
Figure 1.4.8 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warming up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. b. Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (For example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOPx (x: 0 to 3) pin input for releasing STOP mode in edge-sensitive release mode.
Example: Starting STOP mode from NORMAL mode LD (SYSCR1), 10010000B
;
Starts after specified to the edge-sensitive release mode
86FM48-18
2007-08-24
TMP86FM48
Only when EEPCR is "1". (The CPU wait period is added.) STOP pin XOUT pin NORMAL operation
STOP mode started by the program. VIH
STOP operation
STOP Warm-up
CPU wait period
NORMAL operation
STOP operation
STOP mode is released by the hardware at the rising edge of STOP pin input.
Note: When the STOP mode is started with the EEPCR = "1", the CPU wait for stabilizing of the power supply of Flash control circuit is executed after in the STOP warm-up time.
Figure 1.4.9 Edge-sensitive Release Mode STOP mode is released by the following sequence. a. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and low-frequency clock oscillators are turned on; when returning to SLOW1 mode, only the low-frequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. A STOP warm-up period is inserted to allow oscillation time to stabilize. During STOP warm-up, all internal operations remain halted. Four different STOP warm-up times can be selected with the SYSCR1 in accordance with the resonator characteristics. When the EEPCR is "1", the CPU wait period is inserted to stabilize the power supply of Flash control circuit. During CPU wait, though CPU operations remain halted, the peripheral function operation is resumed, and the counting of the timing generator is restarted. After the CPU wait is finished, normal operation resumes with the instruction following the STOP mode start instruction. When the EEPCR is "0", normal operation resumes with the instruction following the STOP mode start instruction after the STOP Warm-up.
b.
c.
d.
Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input).
86FM48-19
2007-08-24
TMP86FM48
Table 1.4.1 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz)
Warm-up Time [ms] (Note 2) WUT Return to NORMAL Mode 00 01 10 11 12.288 4.096 3.072 1.024
+ (0.064) + (0.064) + (0.064) + (0.064)
Return to SLOW Mode 750 250 5.85 1.95
+ (0.244) + (0.244) + (0.244) + (0.244)
Note 1: The warm-up time is obtained by dividing the basic clock by the divider: therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered an approximate value. Note 2: The CPU wait period for FLASH is shown in parentheses.
86FM48-20
2007-08-24
Turn off
Oscillator circuit
Turn on
Main system clock a+2 a+3 SET (SYSCR1).7 n+1 n+2 n+3 n+4 Halt
Program counter
Instruction execution
Divider
n
0
(a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
Figure 1.4.10 STOP Mode Start/Release (When EEPCR = "0")
STOP warm up Turn on a+3 a+4 Instruction address a + 2 Count up 0 1 (b) STOP mode release a+5 Instruction address a + 3 2 3
86FM48-21
STOP pin input
Oscillator circuit
Turn off
Main system clock a+6 Instruction address a + 4
Program counter
Halt
Instruction execution
Divider
0
TMP86FM48
2007-08-24
Turn off
Oscillator circuit
Turn on
Main system clock a+2 a+3 SET (SYSCR1).7 n+1 n+3 n+2 n+4 Halt
Program counter
Instruction execution
Divider
n
0
(a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a)
Figure 1.4.11 STOP Mode Start/Release (When EEPCR = "1")
STOP warm up CPU Wait Turn on a+3 a+4 Instruction address a + 2 Count up 0 1 m-1 (b) STOP mode release m a+5 m+1 The counting of divider is restarted.
86FM48-22
STOP pin input
Oscillator circuit
Turn off
Main system clock
Program counter
Halt
Instruction execution
Instruction address a + 3
Divider
0
TMP86FM48
2007-08-24
TMP86FM48
(2) IDLE1/2 mode, SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. a. b. c. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. The program counter holds the address 2 ahead of the instruction which starts these modes.
Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU, WDT are halted
Reset input No No Interrupt request Yes "1" EEPCR "0" CPU wait
Yes
Reset
No (Normal release mode)
IMF = 1 Yes (Interrupt release mode) Interrupt processing
Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction
Note 1: Note 2:
EEPCR is a bit1 in EEPCR, which is a control bit of the power supply circuit for flash. During CPU wait, though CPU operations remain halted, the peripheral function operation is resumed. Therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until the CPU wait is finished.
Figure 1.4.12 IDLE1/2, SLEEP1/2 Modes
86FM48-23
2007-08-24
TMP86FM48
* Start the IDLE1/2 and SLEEP1/2 modes When IDLE1/2 and SLEEP1/2 modes start, set SYSCR2 to "1". * Release the IDLE1/2 and SLEEP1/2 modes IDLE1/2 and SLEEP1/2 modes include a normal release mode and an interrupt release mode. These modes are selected by interrupt master enable flag (IMF). After releasing IDLE1/2 and SLEEP1/2 modes, the SYSCR2 is automatically cleared to "0" and the operation mode is returned to the mode preceding IDLE1/2 and SLEEP1/2 modes. When the IDLE1/2 and SLEEP1/2 modes are started with the EEPCR = "0", the CPU wait period for stabilizing of the power supply of Flash control circuit is added before the operation mode is returned to the preceding modes. The CPU wait time of IDLE1/2 is 210/fc [s] and that of SLEEP1/2 mode is 23/fs [s]. IDLE1/2 and SLEEP1/2 modes can also be released by inputting low level on the
RESET pin. After releasing reset, the operation mode is started from NORMAL1
mode. Note: During CPU wait, though CPU operations remain halted, but the peripheral function operation is resumed. Therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until the CPU wait is finished.
(a) Normal release mode (IMF = "0") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt latches (IL) of the interrupt source used for releasing must be cleared to "0" by load instructions. (b) Interrupt release mode (IMF = "1") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (EF). After the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts IDLE1/2 and SLEEP1/2 modes. Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 mode are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 mode will not be started.
86FM48-24
2007-08-24
Main system clock
Interrupt request a+2 a+3 Halt SET (SYSCR2).4 Operate (a) IDLE1/2, SLEEP1/2 mode start (Example: starting with the SET instruction located at address a)
Program counter
Instruction execution
Watchdog timer
Main system clock
Interrupt request a+3 a+4 Instruction address a + 2 Operate (1) Normal release mode (EEPCR = "1")
Program counter
Instruction execution
Halt
Figure 1.4.13 IDLE1/2, SLEEP1/2 Mode Start/Release
86FM48-25
a+3 Acceptance of interrupt Operate (2) Interrupt release mode
Watchdog timer
Halt
Main system clock
Interrupt request
Program counter
Instruction execution
Halt
Watchdog timer
Halt
TMP86FM48
2007-08-24
(b) IDLE1/2, SLEEP1/2 mode release (EEPCR = "1")
TMP86FM48
(3) IDLE0, SLEEP0 mode (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. a. b. c. Timing generator stops feeding clock to peripherals except TBT. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) periperals.
Note:
Stopping Peripherals by instruction Starting IDLE0, SLEEP0 mode by instruction CPU, WDT are halted
Reset input No No
TBT
Yes
Reset
source clock
falling edge
Yes "1" EEPCR "0" CPU wait Note 1: EEPCR is a bit1 in EEPCR, which is a control bit of the power supply circuit for Flash. Note 2: During CPU wait, though CPU operations remain halted, but the peripheral function operation is resumed. Therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until the CPU wait is finished.
"0"
TBTCR "1"
No (Normal release mode) "0"
TBT interrupt enable Yes IMF
"1" (Interrupt release mode) Interrupt processing
Execution of the instruction which follows the IDLE0, SLEEP0 mode start instruction
Figure 1.4.14 IDLE0, SLEEP0 Mode
86FM48-26
2007-08-24
TMP86FM48
* Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. When IDLE0 and SLEEP0 modes start, set SYSCR2 to "1". * Release the IDLE0 and SLEEP modes IDLE0 and SLEEP0 modes include a normal release mode and an interrupt release mode. These modes are selected by interrupt master flag (IMF), individual interrupt enable-flag (EF7) for INTTBT and TBTCR. After releasing IDLE0 and SLEEP0 modes, the SYSCR2 is automatically cleared to "0" and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 modes. Before starting the IDLE0 or SLEEP0 mode, when the TBTCR is set to "1", INTTBT interrupt latch is set to "1". When the IDLE0 and SLEEP0 modes are started with the EEPCR = "0", the CPU wait period for stabilizing of the power supply of Flash control circuit is added before the operation mode is returned to the preceding modes. The CPU wait time of IDLE0 is 210/fc [s] and that of SLEEP0 mode is 23/fs [s]. IDLE0 and SLEEP0 modes can also be released by inputting low level on the
RESET pin. After releasing reset, the operation mode is started from NORMAL1
mode. Note 1: IDLE0 and SLEEP0 modes TBTCR setting. start/release without reference to
Note 2: During CPU wait, though CPU operations remain halted, but the peripheral function operation is resumed. Therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until the CPU wait is finished. a. Normal release mode (IMF*EF7*TBTCR = "0") IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the TBTCR. After the falling edge is detected, the program operation is resumed from the instruction following the IDLE0 and SLEEP0 modes start instruction. b. Interrupt release mode (IMF*EF7*TBTCR = "1") IDLE0 and SLEEP0 modes are released by the source clock falling edge, which is setting by the TBTCR and INTTBT interrupt processing is started.
Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR. Note 2: When a watchdog timer interrupt is generated immediately before IDLE0/SLEEP0 mode is started, the watchdog timer interrupt will be processed but IDLE0/SLEEP0 mode will not be started.
86FM48-27
2007-08-24
Main system clock
Interrupt request a+2 a+3 Halt SET (SYSCR2).2 Operate (a) IDLE0, SLEEP0 mode start (Example: starting with the SET instruction located at address a)
Program counter
Instruction execution
Watchdog timer
Main system clock
TBT clock a+3 a+4 Instruction address a + 2 Operate (1) Normal release mode (EEPCR = "1")
Program counter
Figure 1.4.15 IDLE0, SLEEP0 Mode Start/Release
86FM48-28
a+3 Acceptance of interrupt Operate (2) Interrupt release mode (b) IDLE0, SLEEP0 mode release (EEPCR = "1")
Instruction execution
Halt
Watchdog timer
Halt
Main system clock
TBT clock
Program counter
Instruction execution
Halt
TMP86FM48
2007-08-24
Watchdog timer
Halt
TMP86FM48
(4) SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter (TC2). a. Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 to switch the main system clock to the low-frequency clock for SLOW2 mode. Next, clear SYSCR2 to turn off high-frequency oscillation. Note: The high-frequency clock oscillation can be continued to return quickly to NORMAL2 mode. But starting STOP mode while SLOW mode, the high-frequency oscillation must be stopped. When the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before performing the above operations. The timer/counter 2 (TC2) can conveniently be used to confirm that low-frequency clock oscillation has stabilized.
Example 1: Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 1 (Switches the main system clock to the low-frequency clock for SLOW2) CLR (SYSCR2). 7 SYSCR2 0 (Turns off high-frequency oscillation) Example2: Switching to the SLOW1 mode after low-frequency clock has stabilized. SET (SYSCR2). 6 ; SYSCR2 1 LD (TC2CR), 14H ; Sets mode for TC2 LDW (TC2DRL), 8000H ; Sets warm-up time (Depend on oscillator accompanied) DI ; IMF 0 SET (EIRE). 4 ; Enables INTTC2 EI ; IMF 1 SET (TC2CR). 5 ; Starts TC2 PINTTC2: CLR SET (TC2CR). 5 (SYSCR2). 5 ; ; Stops TC2 SYSCR2 1 (Switches the main system clock to the low-frequency clock) SYSCR2 0 (Turns off high-frequency oscillation)
CLR RETI VINTTC2: DW
(SYSCR2). 7
;
PINTTC2
;
INTTC2 vector table
86FM48-29
2007-08-24
TMP86FM48
b. Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 to turn on the high-frequency oscillation. When time for stabilization (Warm-up) has been taken by the timer/counter 2 (TC2), clear SYSCR2 to switch the main system clock to the high-frequency clock.
Note 1: After SYSCK is cleared to "0", executing the instructions is continued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks.
High-frequency clock Low-frequency clock Main system clock SYSCK
Note 2: SLOW mode can also be released by inputting low level on the RESET pin, which immediately performs the reset operation. After reset, the TMP86FM48 is placed in NORMAL1 mode.
Example: Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is = 4.0 ms). SET (SYSCR2). 7 ; SYSCR2 1 (Starts high-frequency oscillation) LD (TC2CR), 10H ; Sets mode for TC2 (Timer mode, fc for source) LD (TC2DRH), 0F8H ; Sets warm-up time (Depend on oscillator accompanied) DI ; IMF 0 SET (EIRE). 4 ; Enables INTTC2 EI ; IMF 1 SET (TC2CR). 5 ; Starts TC2 PINTTC2: CLR CLR (TC2CR). 5 (SYSCR2). 5 ; ; Stops TC2 SYSCR2 0 (Switches the main system clock to the high-frequency clock)
RETI VINTTC2: DW PINTTC2 ; INTTC2 vector table
86FM48-30
2007-08-24
High-frequency clock
Turn off
Low-frequency clock
Main system clock
SYSCK
XEN
Instruction execution CLR (SYSCR2).7 SLOW2 mode
SET (SYSCR2).5
NORMAL2 mode (a) Switching to the SLOW mode
SLOW1 mode
Figure 1.4.16 Switching between the NORMAL2 and SLOW Modes
CLR (SYSCR2).5 Warm up during SLOW2 mode (b) Switching to the NORMAL2 mode
86FM48-31
High-frequency clock
Low-frequency clock
Main system clock
SYSCK
XEN
Instruction execution
SET (SYSCR2).7
TMP86FM48
SLOW1 mode
NORMAL2 mode
2007-08-24
TMP86FM48
1.5
Interrupt Control Circuit
The TMP86FM48 has a total (Reset is excluded) of 20 interrupt source: 5 externals and 15 internals. 4 of the internal sources are non-maskable interrupts, and the rest of them are maskable interrupts. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Table 1.5.1 Interrupt Sources Interrupt Factors Enable Interrupt Vector Priority Condition Latch Address
Non-maskable (Software interrupt) Non-maskable Non-maskable Non-maskable Non-maskable IMF*EF4 = 1 IMF*EF5 = 1 IMF*EF6 = 1 IMF*EF7 = 1 IMF*EF8 = 1 IMF*EF9 = 1 IMF*EF10 = 1 IMF*EF11 = 1 IMF*EF12 = 1 IMF*EF13 = 1 IMF*EF14 = 1 IMF*EF15 = 1 IMF*EF16 = 1 (Serial bus interface interrupt) (UART received interrupt) (UART transmitted interrupt) (TC2 interrupt) (External interrupt 5) IMF*EF17 = 1 IMF*EF18 = 1 IMF*EF19 = 1 IMF*EF20 = 1 IMF*EF21 = 1 IMF*EF22 = 1 IMF*EF23 = 1 - - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 FFFEH FFFCH FFFCH FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFBEH FFBCH FFBAH FFB8H FFB6H FFB4H FFB2H FFB0H High 1 2 2 2 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Internal/External (Reset) Internal Internal Internal Internal External Internal External Internal External Internal Internal Internal Internal External Internal INTSWI INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT
INT0
(Watchdog timer interrupt) (External interrupt 0) (TC1 interrupt) (External interrupt 1) (Time base timer interrupt) (External interrupt 2) (TC3 interrupt) (Serial interface 1 interrupt) (Serial interface 2 interrupt) (TC5 interrupt) (External interrupt 3) (AD converter interrupt)
INTTC1 INT1 INTTBT INT2 INTTC3 INTSIO1 INTSIO2 INTTC5 INT3 INTADC Reserved Reserved
Internal Internal Internal Internal External
INTSBI INTRXD INTTXD INTTC2
INT5
Reserved Reserved
Note 1: To use the watchdog timer interrupt (INTWDT), clear WDTCR1 to "0" (It is set for the "Reset request" after reset is released). For details, see 2.4 Watchdog Timer. Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1 to "0" (It is set for the "Reset request" after reset is released). For details, see 2.4.5 Address Trap.
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2007-08-24
INTSWI INTUNDEF INTATRAP S R
IL3 IL2 Q
INTWDT S R
IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 IL4 Q
INT0
Digital noise reject circuit
INT0EN
INTTC1
INT1 Priority encoder & Vector table address generator
Edge selction, Digital noise reject circuit
INTTBT
INT1NC, INT1ES
INT2
Edge selction, Digital noise reject circuit
INTTC3
INT2ES
INTSIO1
Vector table address
INTSIO2
INTTC5
INT3
Edge selction, Digital noise reject circuit
Interrupt request IDLE1/2, SLEEP1/2 mode Releease request
INT3ES
Figure 1.5.1 Interrupt Controller Block Diagram
[DI] instru ction 22 IL23 to IL2 write data
Write strobe for IL
86FM48-33
20 EF23 to EF4 Internal reset
INTADC
INTSBI
INTRXD
Interrupt acceptance
INTTXD
INTTC2
Q IMF RS
INT5
Digital noise reject circuit
[RETI] instruction during maskable interrupt service [RETN] instruction only when IMF was set before interrupt was accepted [EI] Instruction
2
EINTCR
TMP86FM48
2007-08-24
External Interrupt Control register
Individual Interrupt enable flag
Instruction which IMF to "0"
Instruction which sets IMF to "1"
TMP86FM48
(1) Interrupt latches (IL24 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. All interrupt latches are initialized to "0" during reset. The interrupt latches are located on address 002EH, 003CH and 003DH in SFR area. Except for IL3 and IL2, each latch can be cleared to "0" individually by instruction. (However, the read-modify-write instructions such as bit manipulation or operation instructions cannot be used. Interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed.) Thus interrupt request can be canceled/initialized by software. Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: When manipulating IL, clear IMF (to disable interrupts) beforehand.
Example 1: Clears interrupt latches DI LD (ILE), 11110011B LDW (ILL), 1110100000111111B EI Example 2: Reads interrupt latches LD WA, (ILL) Example 3: Tests an interrupt latches TEST (IL).7 JR F, SSET
; ; ; ; ; ;
IMF 0 IL19, IL18 0 IL12, IL10 to IL6 0 IMF 1 W ILH, A ILL IL7 = 1 then jump
(2) Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Non-maskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 002CH, 003AH and 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). a. Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable-interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0", and maskable interrupts are not accepted until it is set to "1".
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b. Individual interrupt enable flags (EF23 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. The individual interrupt enable flags (EF23 to EF4) are located on EIRE, EIRL to EIRH (address: 002CH, 003AH to 003BH in SFR), and can be read and written by an instruction. During reset, all the individual interrupt enable flags (EF23 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note: Before manipulating EF, be sure to clear IMF (Interrupt disabled). Then set IMF newly again after operating on the interrupt enables flag (EF). Normally, IMF is clear to "0" automatically on service routine. When IMF is set to "1" for using a multiple interrupt on service routine, be sure to process as is the case with EF.
Example 1: Enables interrupts individually and sets IMF DI LD (EIRE), 00001100B LDW (EIRL), 0110100010100000B
; ; ; ; ;
IMF 0 EF19, EF18 "1" EF14, EF13, EF11, EF7, EF5 "1" Note: IMF is not set. IMF "1" /* 3AH shows EIRL address */
EI Example 2: C compiler description example unsigned int _io (3AH) EIRL; _DI ( ); EIRL = 10100000B; _EI ( );
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Interrupt Latches ILH, ILL (003CH, 003DH) 15 IL15 14 IL14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0
ILH (003DH) 23 IL23 22 IL22
ILL (003CH) (Initial value: 00000000 000000**) 21 20 19 18 17 16 IL21 IL20 IL19 IL18 IL17 IL16
ILE (002EH)
ILE (002EH) (Initial value: 00000000) at RD 0: No interrupt request 1: Interrupt request at WR Clears the interrupt request (Note 1) (Interrupt Latch is not set.)
IL23 to IL2
Interrupt Latches
R/W
Note 1: IL2 and IL3 are prohibited from clearing. Note 2: When manipulating IL, clear IMF (to disable interrupts) beforehand. Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers 15 14 13 12 11 10 EIRH, EIRL EF15 EF14 EF13 EF12 EF11 EF10 (003AH, 003BH) EIRH (003BH)
9 EF9
8 EF8
7 EF7
6 EF6
5 EF5
4 EF4
3
2
1
0 IMF
EIRL (003AH) 23 22 (Initial value: 00000000 00000***0) 21 20 19 18 17 16
EIRE (002CH)
EF23 EF22 EF21 EF20 EF19 EF18 EF17 EF16 EIRE (002CH) (Initial value: 00000000) Individual-interrupt enable flag (specified for each bit) Interrupt master enable flag
EF23 to EF4
0: Disable the acceptance of each maskable interrupt. 1: Enable the acceptance of each maskable interrupt. 0: Disable the acceptance of all maskable interrupts. 1: Enable the acceptance of all maskable interrupts.
R/W
IMF
Note 1: *: Don't care Note 2: When manipulating EF, clear IMF (to disable interrupts) beforehand. Note 3: Do not set IMF to 1 simultaneously with EF15 to EF4.
Figure 1.5.2 Interrupt Latch (IL), Interrupt Enable Registers (EIR)
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TMP86FM48 1.5.1 Interrupt Sequence
An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8-machine cycles (4 s at 8.0 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 1.5.3 shows the timing chart of interrupt acceptance processing. (1) Interrupt acceptance processing is packaged as follows. 1. 2. 3. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. The instruction stored at the entry address of the interrupt service program is executed. When the contents of PSW are saved on the stack, the contents of IMF are also saved.
4. 5.
Note:
Interrupt service task 1-machine cycle Interrupt request Interrupt latch (IL) IMF Execute Instruction PC SP Note 1: Note 2:
Execute Instruction a-1 a+1
Interrupt acceptance
a b
Execute Instruction b+1 b+2 b+3 c+1
Execute RETI instruction
c+2 a a+1 a+2
a
n
n-1 n-2
n-3
n-2 n-1
n
a: return address entry address, b: entry address, c: address which RETI instructrion is stored On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set.
Figure 1.5.3 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction
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Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program
Vector table address Entry address
FFF0H FFF1H
03H Vector D2H
D203H D204H
0FH 06H
Interrupt service program
A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorter compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. (2) Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the general-purpose registers. a. Using PUSH and POP instructions To save only a specific register, PUSH and POP instructions are available.
Example: Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP WA ; Restore WA register RETI ; RETURN Address (Example)
SP A SP PCL PCH PSW W PCL PCH PSW SP PCL PCH PSW SP
023AH 023B 023C 023D 023E 023F
At Acceptance of an Interrupt
At Execution of PUSH instructin
At Execution of POP instructin
At Execution of an RETI instruction
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b. Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available.
Example: Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD A, (GSAVA) ; Restore A register RETI ; RETURN
Main task
Interrupt acceptance
Interrupt service task Saving registers
Restoring registers Interrupt return Saving/restoring general-purpose registers using PUSH/POP instruction
Figure 1.5.4 Saving/Restoring General-purpose Registers under Interrupt Processing (3) Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return
1. Program Counter (PC) and program status word (PSW, includes IMF) are restored from the stack. Stack pointer (SP) is incremented by 3.
2.
As for Address Trap interrupt (INTARTAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Otherwise returning interrupt causes INTATRAP again. When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Note: If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.
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Example 1: Returning from address trap interrupt (INTATRAP) service program PINTxx: POP WA ; Recover SP by 2 LD WA, Return Address ; PUSH WA ; Alter stacked data (interrupt processing) RETN ; RETURN Example 2: Restarting without returning interrupt (In this case, PSW (includes IMF) before interrupt acceptance is discarded.) PINTxx INC SP ; Recover SP by 3 INC SP ; INC SP ; (interrupt processing) LD EIRL, data ; Set IMF to "1" or clear it to "0" JP Restart Address ; Jump into restarting address
Note:
It is recommended that stack pointer be return to rate before INTATRAP (increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2).
Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task.
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2007-08-24
TMP86FM48 1.5.2 Software Interrupt (INTSW)
Executing the [SWI] instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the [SWI] instruction only for detection of the address error or for debugging. (1) Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM or SFR areas. (2) Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address.
1.5.3
Undefined Instruction Interrupt (INTUNDEF)
Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does.
1.5.4
Address Trap Interrupt (INTATRAP)
Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset-output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset-output or interrupt processing, is selected on watchdog timer control register (WDTCR).
1.5.5
External Interrupts
The TMP86FM48 has five external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT3. INT0 /P00 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0 /P00 pin function selection are performed by the external interrupt control register (EINTCR).
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Table 1.5.2 External Interrupts Source Pin Secondary Enable Conditions Function Pin Edge Digital Noise Reject
Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals.
INT0
INT0
P00
IMF = 1, EF4 = 1, INT0EN = 1
Falling edge
INT1
INT1
P01
IMF*EF6 = 1
INT2
INT2
P02
IMF*EF8 = 1
Falling edge or Rising edge
INT3
INT3
P14/TC3
IMF*EF13 = 1
INT5
INT5
P20/ STOP
IMF*EF21 = 1
Falling edge
Note 1: If a noiseless signal is input to the external interrupt pin in the NORMAL 1/2 or IDLE 1/2 mode, the maximum time from the edge of input signal until the IL is set is as follows: (1) INT1 pin 55/fc [s] (INT1NC = 1), 199/fc [s] (INT1NC = 0) (2) INT2, INT3 pin 31/fc [s] Note 2: Even if the falling edge of INT0 pin input is detected at INT0EN = 0, the interrupt latch IL4 is not set. Note 3: When data changed and did a change of I/O when used external interrupt ports as a normal ports, interrupt request signal occurs incorrectly. Handling of prohibition of interrupt enable register (EIR) is necessary. Note 4: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc.
External interrupt control register EINTCR 7 6 (0037H) INT1NC INT0EN
5
4
3
2
1
0 (Initial value: 00** 000*)
INT3ES INT2ES INT1ES
INT1NC INT0EN INT3ES INT2ES INT1ES Note 1: Note 2:
Noise reject time select P00/ INT0 pin configuration
0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P00 input/output port 1: INT0 pin (Port P00 should be set to an input mode) 0: Rising edge 1: Falling edge R/W
INT3 to INT1 edge select
fc: High-frequency clock [Hz], *: Don't care When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR).
Figure 1.5.5 External Interrupt Control Register
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1.6
Reset Circuit
The TMP86FM48 has four types of reset generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Table 1.6.1 shows on-chip hardware initialization by reset action. Since the reset circuit has an 11-stage counter for generation of flash reset, which is the reset counter for stabilizing of the power supply for Flash, the reset period is 210/fc [s] (64 s at 16.0 MHz). Because the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on, the reset operation occur for the maximum 24/fc [s] (1.5 s at 16.0 MHz). Therefore, the maximum reset period is 24/fc [s] + 210/fc [s] (65.5 s at 16.0 MHz). Table 1.6.1 shows on-chip hardware initialization by reset action.
Table 1.6.1 Initializing Internal Status by Reset Action On-chip Hardware
Program counter Stack pointer (PC) (SP)
Initial Value
(FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized 0 0 0
On-chip Hardware
Prescaler and Divider of timing generator Watchdog timer
Initial Value
0
General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (JF) (ZF) (CF) (HF) (SF) (VF) (IMF) (EF) (IL)
Enable
Output latches of I/O ports
Refer to I/O port circuitry
Control registers RAM
Refer to each of control register Not initialized
1.6.1
External Reset Input
The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When 210/fc (65.5 s at 16 MHz) period passes after the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH.
VDD
Flash reset counter
RESET
Reset input Watchdog timer reset Malfunction reset output circuit Adddress trap reset System clock reset
Figure 1.6.1 Reset Circuit
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TMP86FM48 1.6.2 Address-Trap-Reset
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 is set to "1") or the SFR area, address-trap-reset and the Flash reset will be generated. The reset time is maximum 24/fc [s] + 210/fc [s] (65.5 s at 16.0 MHz).
Instruction execution Internal reset
JP
a Address trap is occurred
Reset release
Instruction at address r
max 24/fc [s]
2 /fc [s] for Flash reset
10
4/fc to 12/fc [s]
16/fc [s]
Note 1: Note 2:
Address "a" is in the SFR or on-chip RAM (WDTCR1 = "1") space. During reset release, reset vector "r" is read out, and an instruction at address "r" is fetched and decoded.
Figure 1.6.2 Address-Trap-Reset Note: The operating mode under address trapped is alternative of reset or interrupt. Address trap or no address trap can be selected by WDTCR1 for the internal RAM.
1.6.3
Watchdog Timer Reset
Refer to Section "2.4 Watchdog Timer".
1.6.4
System-Clock-Reset
If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU. (The oscillation is continued without stopping.) - In case of clearing SYSCR2 and SYSCR2 simultaneously to "0". - In case of clearing SYSCR2 to "0", when the SYSCR2 is "0". - In case of clearing SYSCR2 to "0", when the SYSCR2 is "1". When the system clock reset is generated, the flash reset is also generated. Therefore, the maximum reset period is 24/fc [s] + 210/fc [s] (65.5 s at 16.0 MHz).
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2.
2.1
On-Chip Peripherals Functions
Special Function Register (SFR)
The TMP86FM48 adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 1F80H to 1FFFH. Figure 2.1.1 to Figure 2.1.2 indicate the special function register (SFR) and data buffer register (DBR) for TMP86FM48.
Address
0000H 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
Read
P0DR (P0 Port output latch) P1DR (P1 Port output latch) P2DR (P2 Port output latch) P3DR (P3 Port output latch) Reserved P5DR (P5 Port output latch) P6DR (P6 Port output latch) P7DR (P7 Port output latch) P8DR (P8 Port output latch) Reserved
Write
Address
0020H 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
Read
TC1DRAL (Timer register 1A) TC1DRAH (Timer register 1A) TC1DRBL (Timer register 1B) TC1DRBH (Timer register 1B) TC2DRL (Timer register 2) TC2DRH (Timer register 2) ADCDR2 (AD result register 2) ADCDR1 (AD result register 1) P6CR2 (P6 Port input control) Reserved
Write
- -
P0OUTCR (P0 Port output control) P1OUTCR (P1 Port output control) P6CR1 (P6 Port input/output control) P5OUTCR (P5 Port output control) ADCCR1 (AD control register 1) ADCCR2 (AD control register 2) TC3DRA (Timer register 3A) TC3DRB (Timer register 3B) TC3CR (Timer Counter 3 control) TC2CR (Timer Counter 2 control) TC5CR (Timer Counter 5 control) TC5DR (Timer register 5) Reserved SIO1CR (SIO1 control) SIO1SR (SIO1 status) SIO1BUF (SIO1 data buffer) Reserved SIO2CR (SIO2 control) SIO2SR (SIO2 status) SIO2BUF (SIO2 data buffer) Reserved TC1CR (Timer counter 1 control) - - -
P3OUTCR (P3 Port output control) Reserved EIRE (Interrupt enable register) Reserved ILE (Interrupt latch) Reserved Reserved Reserved Reserved Reserved - - WDTCR1 (Watchdog timer control) WDTCR2 (Watchdog timer control) TBTCR (TBT/TG/DVO control) EINTCR (External interrupt control) SYSCR1 (System control 1) SYSCR2 (System control 2) EIRL (Interrupt enable register) EIRH (Interrupt enable register) ILL (Interrupt latch) ILH (Interrupt latch) Reserved PSW (Program status word)
31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
Note 1: Note 2: Note 3:
Do not access reserved areas by the program. -: Cannot be accessed. Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Figure 2.1.1 The Special Function Register (SFR) for TMP86FM48 (1/2)
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Address Read
1F80H Reserved
Write
D8 D9 DA DB DC DD DE DF - SBISR (SBI status) UARTSR (UART status) - RDBUF -
Reserved SBICRA (SBI control 1) SBIDBR (SBI data buffer) I2CAR (I2C address) SBICRB (SBI control 2) UARTCR1 (UART control 1) UARTCR2 (UART control 2) TDBUF (UART transmit data buffer) -
(UART received data buffer) E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF - P5PRD (P5 Terminal input) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved P0PRD (P0 Terminal input) P1PRD (P1 Terminal input) P2PRD (P2 Terminal input) P3PRD (P3 Terminal input) Reserved
EEPCR (FLASH control) EEPSR (FLASH status)
EEPEVA (FLASH write emulation time control) Reserved P2OUTCR (P2 Port output control) P7CR1 (P7 Port input/output control) P7CR2 (P7 Port input control) P8CR (P8 Port input/output control) Reserved Reserved Reserved Reserved Reserved - - - - -
STOPCR (Key-on wake-up control) Reserved
Note 1: Note 2: Note 3:
Do not access reserved areas by the program. -: Cannot be accessed. Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.).
Figure 2.1.2 The Special Function Register (SFR) for TMP86FM48 (2/2)
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2.2
I/O Ports
The TMP86FM48 has 8 parallel input/output ports (54 pins) as follows. Primary Function Secondary Functions
External interrupt input, serial interface input/output, UART input/output and Timer/Counter input . External interrupt input, serial interface input/output and Timer/Counter input/output. Low-frequency resonator connections, external interrupt input, STOP mode release signal input. Divider output, Timer/Counter output and Serial Bus Interface input/output. Analog input and STOP mode release signal input. Analog input.
Port P0 Port P1 Port P2 Port P3 Port P5 Port P6 Port P7 Port P8
8-bit I/O port 8-bit I/O port 3-bit I/O port 8-bit I/O port 3-bit I/O port 8-bit I/O port 8-bit I/O port 8-bit I/O port
Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing. Figure 2.2.1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port.
Fetch cycle
Fetch cycle
Read cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Ex: LD A, (x)
Input strobe
Data input (a) Input timing
Fetch cycle
Fetch cycle
Read cycle
S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Ex: LD (x), A
Output strobe
Data output
Old (b) Output timing
New
Note: The positions of the read and write cycles may vary, depending on the instruction.
Figure 2.2.1 Input/Output Timing (Example)
86FM48-47
2007-08-24
TMP86FM48 2.2.1 Port P0 (P07 to P00)
Port P0 is an 8-bit input/output port which is also used as an external interrupt input, serial interface input/output, timer/counter input and UART input/output. It can be selected whether output circuit of P0 port is CMOS output or a sink open drain individually, by setting the output circuit control (P0OUTCR). When a corresponding bit of P0OUTCR is cleared to "0", the output circuit is selected to a sink open drain and when a corresponding bit of P0OUTCR is set to "1", the output circuit is selected to a CMOS output. When used as an input port or a secondary function input (External interrupt input, serial interface input, timer/counter input or UART input), the respective output latch (P0DR) should be set to "1" and its corresponding P0OUTCR bit should be cleared to "0". When used as a secondary function output (Serial interface output or UART output), the respective P0DR should be set to "1". During reset, the P0DR is initialized to "1" and P0OUTCR is initialized to "0". P0 port output latch (P0DR) and P0 port terminal input (P0PRD) are located on their respective address. When read the output latch data, the P0DR should be read and when read the terminal input data, the P0PRD register should be read.
STOP OUTEN P0OUTCRi P0OUTCRi input Data input (P0PRD) Data input (P0DR) Data output (P0DR) Control output Control input 7 P0DR (0000H) R/W P0OUTCR (000AH) Port P0 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: CMOS output (Initial value: 0000 0000) P07
SCK1
D
Q
D
Q
P0i Note: i = 7 to 0
Output latch
6 P06 TxD SO1
5 P05 RxD SI1
4 P04
3 P03 TC2
2 P02 INT2
1 P01 INT1
0 P00
INT0
(Initial value: 1111 1111)
P0OUTCR
R/W
P0PRD (1FEDH) Read only P07 P06 P05 P04 P03 P02 P01 P00
Figure 2.2.2 Port 0
86FM48-48
2007-08-24
TMP86FM48 2.2.2 Port P1 (P17 to P10)
Port P1 is a 8-bit input/output port which is also used as an external interrupt input, serial interface input/output and timer/counter input/output. It can be selected whether output circuit of P1 port is CMOS output or a sink open drain individually, by setting the output circuit control (P1OUTCR). When a corresponding bit of P1OUTCR is cleared to "0", the output circuit is selected to a sink open drain and when a corresponding bit of P1OUTCR is set to "1", the output circuit is selected to a CMOS output. When used as an input port or a secondary function input (External interrupt input, serial interface input, timer/counter input), the respective output latch (P1DR) should be set to "1" and its corresponding P1OUTCR bit should be cleared to "0". When used as a secondary function output (Serial interface output or timer/counter output), the respective P1DR should be set to "1". During reset, the P1DR is initialized to "1" and P1OUTCR is initialized to "0". P1 port output latch (P1DR) and P1 port terminal input (P1PRD) are located on their respective address. When read the output latch data, the P1DR should be read and when read the terminal input data, the P1PRD register should be read.
STOP OUTEN P1OUTCRi P1OUTCRi input Data input (P1PRD) Data input (P1DR) Data output (P1DR) Control output Control input D Q P1i Note: i = 7 to 0 D Q
Output latch
7 P1DR (0001H) R/W P17
6 P16
5 P15 TC1
4 P14 TC3 INT3
3 P13 TC5
PWM5 PDO5
2 P12
SCK2
1 P11 SI2
0 P10 SO2 (Initial value: 1111 1111)
P1OUTCR (000BH) Port P1 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: CMOS output
(Initial value: 0000 0000)
P1OUTCR
R/W
P1PRD (1FEEH) Read only
P17
P16
P15
P14
P13
P12
P11
P10
Figure 2.2.3 Port 1
86FM48-49
2007-08-24
TMP86FM48 2.2.3 Port P2 (P22 to P20)
Port P2 is a 3-bit input/output port. It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator connection pins. It can be selected whether output circuit of P2 port is CMOS (P21 and P22 have a pull-up resistor) output or a sink open drain individually, by setting the output circuit control (P2OUTCR). When a corresponding bit of P2OUTCR is cleared to "0", the output circuit is selected to a sink open drain and when a corresponding bit of P2OUTCR is set to "1", the output circuit is selected to a CMOS output. (In case of P21 and P22, the pull-up resistor is connected.) When used as an input port or an external interrupt input, the respective output latch (P2DR) should be set to "1". During reset, the P2DR initialized to "1" and P2OUTCR is initialized to "0". A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dual-clock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports. It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse. P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address. When read the output latch data, the P2DR should be read and when read the terminal input data, the P2PRD register should be read. If a read instruction is executed for port P2DR, P2OUTCR and P2PRD, read data of bits 7 to 3 are unstable.
Data input (P21PRD) Data input (P21) Output latch Data output (P21) P2OUTCR P2OUTCR input Data input (P22PRD) Data input (P22) Data output (P22) D Q D D Q Q Osc.enable
VDD
P21 (XTIN)
VDD
P22 (XTOUT)
Output latch P2OUTCR P2OUTCR input fs STOP OUTEN XTEN D Q
Note: When XTEN is set to "1", P21 and P22 become a high impedance state.
Figure 2.2.4 Port 2 (P21 and P22)
86FM48-50
2007-08-24
TMP86FM48
Data input (P20PRD)
INT5 , STOP input
STOP P2OUTCR P2OUTCR input Data input (P20) Data output (P20) D Q P20 ( INT5 , STOP ) D Q
Output latch Note: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z state.
7 P2DR (0002H) R/W
6
5
4
3
2 P22 XTOUT
1 P21 XTIN
0 P20
INT5 STOP
(Initial value: **** *111) *: Don't care
P2OUTCR (1FE4H) 0: P2OUTCR Port P2 output circuit control (Set for each bit individually) 1: (Initial value: **** *000) *: Don't care Sink open-drain output P20 pin CMOS output P21, P22 ports CMOS output with pull-up resistor R/W
P2PRD (1FEFH) Read only P22 P21 P20
Figure 2.2.5 Port 2 (P20)
86FM48-51
2007-08-24
TMP86FM48 2.2.4 Port P3 (P37 to P30)
Port P3 is an 8-bit input/output port. It can be selected whether output circuit of P3 port is CMOS output or a sink open drain individually, by setting P3OUTCR. (N-ch high current output) When a corresponding bit of P3OUTCR is cleared to "0", the output circuit is selected to a sink open drain and when a corresponding bit of P3OUTCR is set to "1", the output circuit is selected to a CMOS output. When used as an input port, the respective output latch (P3DR) should be set to "1" and its corresponding P3OUTCR bit should be cleared to "0". During reset, the P3DR is initialized to "1", and the P3OUTCR is initialized to "0". P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address. When read the output latch data, the P3DR should be read and when read the terminal input data, the P3PRD register should be read.
STOP OUTEN P3OUTCRi P3OUTCRi input Data input (P3PRD) Data input (P3DR) Data output (P3DR) D Q P3i Note: i = 7 to 0 2 P32 1 P31 0 P30 (Initial value: 1111 1111) D Q
Output latch 7 P3DR (0003H) R/W P3OUTCR (002AH) Port P3 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: CMOS output P37 6 P36 5 P35 4 P34 3 P33
(Initial value: 0000 0000)
P3OUTCR
R/W
P3PRD (1FF0H) Read only P37 P36 P35 P34 P33 P32 P31 P30
Figure 2.2.6 Port 3
86FM48-52
2007-08-24
TMP86FM48 2.2.5 Port P5 (P52 to P50)
Port P5 is an 3-bit input/output port which is also used as a timer/counter output, divider output and serial bus interface input/output. (N-ch high current output) It can be selected whether output circuit of P5 port is CMOS output or a sink open drain individually, by setting the output circuit control (P5OUTCR). When a corresponding bit of P5OUTCR is cleared to "0", the output circuit is selected to a sink open drain and when a corresponding bit of P5OUTCR is set to "1", the output circuit is selected to a CMOS output. When used as an input port or a serial bus interface input/output, the respective output latch (P5DR) should be set to "1" and its corresponding P5OUTCR bit should be cleared to "0". When used as a secondary function output (Timer/counter output or divider output), the respective P5DR should be set to "1". When used as a serial bus interface input/output, P5DR of P50 and P51 should be set to "1" and P5OUTCR of P50 and P51 should be cleared to "0" as a sink open drain output. During reset, the P5DR is initialized to "1" and P5OUTCR is initialized to "0". P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their respective address. When read the output latch data, the P5DR should be read and when read the terminal input data, the P5PRD register should be read. If a read instruction is executed for P5DR, P5OUTCR and P5PRD, read data of bits 7 to 3 are unstable.
STOP OUTEN P5OUTCRi P5OUTCRi input Data input (P5PRD) Data input (P5DR) Data output (P5DR) Control output D Q P5i Note: i = 2 to 0 D Q
Output latch
7 P5DR (0005H) R/W
6
5
4
3
2 P52
1 P51
DVO
0 P50
PPG
SDA
SCL
(Initial value: **** *111) *: Don't care
P5OUTCR (000DH) Port P5 output circuit control P5OUTCR (Set for each bit individually) P5PRD (1FF2H) Read only P52 P51 P50 0: Sink open-drain output 1: CMOS output (Initial value: **** *000) *: Don't care R/W
Figure 2.2.7 Port 5
86FM48-53
2007-08-24
TMP86FM48 2.2.6 Port P6 (P67 to P60)
Port P6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P6 is also used as an analog input and key-on wake-up input. Input/output mode is specified by the P6 control register (P6CR1). P6 port input is controlled by the input control register (P6CR2). When used as an output port, respective P6CR1 should be set to "1". When used as an input port, respective P6CR1 should be cleared to "0" and respective P6CR2 should be set to "1". When used as an analog input, respective P6CR2 should be cleared to "0" after respective P6CR1 is cleared to "0". When used as a key on wake up input, respective STOPkEN should be set to "1". (k = 3 to 0) During reset, the P6CR1 and P6DR are initialized to "0", and the P6CR2 is initialized to "1". Table 2.2.1 and Table 2.2.2 show a P6 state. Table 2.2.1 P63 to P60 State P6CR1
0 0 1 1
P6CR2
0 1 * *
P6DR
* * 0 1
P6DR Read
"0" Terminal input "0" (Output latch) "1" (Output latch)
Output
High-Z High-Z Low High
Remark
- Input mode Output mode Output mode
*: Don't care. Table 2.2.2 P67 to P64 State STOPkEN
0 0 0 0 1
P6CR1
0 0 1 1 *
P6CR2
0 1 * * *
P6DR
* * 0 1 *
P6DR read
"0" Terminal input "0" (Output latch) "1" (Output latch) Terminal input
Output
High-Z High-Z Low High High-Z
Remark
- Input mode Output mode Output mode Key on wake up
*: Don't care. Note: STOPkEN is bit7 to 4 in STOPCR.
Analog input AINDS SAIN STOP OUTEN P6CR2i P6CR2i input P6CR1i P6CR1i input Data input (P6DR) P6i Note 1: i = 3 to 0 Data output (P6DR) D Q Note 2: SAIN is bit0 to 3 in ADCCR1 D Q D Q
Figure 2.2.8 Port 6 (P63 to P60)
86FM48-54
2007-08-24
TMP86FM48
Analog input AINDS SAIN STOPkEN STOP OUTEN P6CR2j P6CR2j input P6CR1j P6CR1j input STOPk input Data input (P6DR) P6j Note 1: j = 7 to 4, k = 3 to 0 Data output (P6DR) D Q Note 2: SAIN is bit0 to 3 in ADCCR1 Note 3: STOPkEN is bit 7 to 4 in STOPCR. 7 6 5 4 P67 P66 P65 P64 AIN07 AIN06 AIN05 AIN04 STOP3 STOP2 STOP1 STOP0 3 P63 AIN03 2 P62 AIN02 1 P61 AIN01 0 P60 AIN00 D Q D Q
P6DR (0006H) R/W
(Initial value: 0000 0000)
P6CR1 (000CH) Port P6 I/O control (Set for each bit individually) 0: Input mode or Analog input 1: Output mode (Initial value: 0000 0000)
P6CR1
R/W
P6CR2 (0028H) Port P6 input control (Set for each bit individually) 0: Input disable 1: Input enable (Initial value: 1111 1111)
P6CR2
R/W
Note 1: Note 2:
Do not set output mode to pin which is used for an analog input. If both P6CR1 and P6CR2 are cleared to "0", the read value of P6DR is always "0".
Figure 2.2.9 Port 6 (P67 to P64)
86FM48-55
2007-08-24
TMP86FM48 2.2.7 Port P7 (P77 to P70)
Port P7 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P7 is also used as an analog input. Input/output mode is specified by the P7 control register (P7CR1). P7 port input is controlled by the input control register (P7CR2). When used as an output port, respective P7CR1 should be set to "1". When used as an input port, respective P7CR1 should be cleared to "0" and respective P7CR2 should be set to "1". When used as an analog input, respective P7CR2 should be cleared to "0" after respective P7CR1 is cleared to "0". During reset, the P7CR1 and P7DR are initialized to "0", and the P7CR2 is initialized to "1". Table 2.2.3 shows a P7 state. Table 2.2.3 P7 Port State P7CR1
0 0 1 1
P7CR2
0 1 * *
P7DR
* * 0 1
P7DR Read
"0" Terminal input "0" (Output latch) "1" (Output latch)
Output
High-Z High-Z Low High
Remark - Input mode Output mode Output mode
*: Don't care.
86FM48-56
2007-08-24
TMP86FM48
Analog input AINDS SAIN STOP OUTEN P7CR2i P7CR2i input P7CR1i P7CR1i input Data input (P7DR) P7i Note 1: i = 7 to 0 Data output (P7DR) 7 P77 AIN17 6 P76 AIN16 5 P75 AIN15 D Q 3 P73 AIN13 2 P72 AIN12 1 P71 AIN11 Note 2: SAIN is bit0 to 3 in ADCCR1 0 P70 AIN10 D Q D Q
P7DR (0007H) R/W
4 P74 AIN14
(Initial value: 0000 0000)
P7CR1 (1FE5H) Port P7 I/O control (set for each bit individually) 0: Input mode 1: Output mode (Initial value: 0000 0000)
P7CR1
R/W
P7CR2 (1FE6H) Port P7 input control (set for each bit individually) 0: Input disable 1: Input enable (Initial value: 1111 1111)
P7CR2
R/W
Note 1: Note 2:
Do not set output mode to pin which is used for an analog input. If both P7CR1 and P7CR2 are cleared to "0", the read value of P7DR is always "0".
Figure 2.2.10 Port 7
86FM48-57
2007-08-24
TMP86FM48 2.2.8 Port P8 (P87 to P80)
Port P8 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Input/output mode is specified by the P8 control register (P8CR). When used as an output port, respective P8CR should be set to "1". When used as an input port, respective P8CR should be cleared to "0". During reset, the P8CR and P8DR are initialized to "0". Table 2.2.4 shows a P8 state. Table 2.2.4 P8 Port State P8CR
0 1 1
P8DR
* 0 1
P8DR read
Terminal input "0" (Output latch) "1" (Output latch)
Output
High-Z Low High
Remark
Input mode Output mode Output mode
*: Don't care.
STOP OUTEN
P8CRi P8CRi input Data input (P8DR)
D
Q
P8i Note: i = 7 to 0
Data output (P8DR)
D
Q
P8DR (0008H) R/W
7 P87
6 P86
5 P85
4 P84
3 P83
2 P82
1 P81
0 P80 (Initial value: 0000 0000)
P8CR (1FE7H) Port P8 I/O control (Set for each bit individually) 0: Input mode or Analog input 1: Output mode (Initial value: 0000 0000)
P8CR
R/W
Figure 2.2.11 Port 8
86FM48-58
2007-08-24
TMP86FM48
2.3
Time Base Timer (TBT)
The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). An INTTBT is generated on the first falling edge of source clock (The divider output of the timing generator) after the time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period (Figure 2.3.1 (b)). The interrupt frequency (TBTCK) must be selected with the time base timer disabled (the interrupt frequency must not be changed with the disable from the enable state). Both frequency selection and enabling can be performed simultaneously.
MPX fc/2 21 fc/2 16 fc/2 14 fc/2 13 fc/2 12 fc/2 11 fc/2 9 fc/2
23
or or or or or or or or
fs/2 13 fs/2 8 fs/2 6 fs/2 5 fs/2 4 fs/2 3 fs/2 fs/2
15
A B C D E F G H 3 TBTCK
Source clock Y
Falling edge detector
IDLE0/SLEEP0 release request INTTBT interrupt request
S TBTEN TBTCR
Time base timer control register (a) Configuration Source clock TBTEN INTTBT Interrupt period Enable TBT (b) Time base timer interrupt MPX: Multiplexer
Figure 2.3.1 Time Base Timer
Example: Sets the time base timer frequency to fc/2 [Hz] and enables an INTTBT interrupt. LD (TBTCR), 00000010B ; TBTCK 010 LD (TBTCR), 00001010B ; TBTEN 1 DI ; IMF 0 SET (EIRL). 6
16
86FM48-59
2007-08-24
TMP86FM48
TBTCR (0036H)
7
(DVOEN)
6
5
4
(DV7CK)
3
TBTEN
2
1
TBTCK
0 (Initial value: 0000 0000)
(DVOCK)
TBTEN
Time base timer enable/disable
0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode 000 001 010 011 100 101 110 111 DV7CK = 0 23 fc/2 21 fc/2 16 fc/2 14 fc/2 13 fc/2 12 fc/2 11 fc/2 9 fc/2 DV7CK = 1 15 fs/2 13 fs/2 8 fs/2 6 fs/2 5 fs/2 4 fs/2 3 fs/2 fs/2 SLOW, SLEEP Mode fs/2 13 fs/2 - - - - - -
15
TBTCK
Time base timer interrupt frequency select [Hz]
R/W
Note: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care
Figure 2.3.2 Time Base Timer Control Register Table 2.3.1 Time Base Timer Interrupt Frequency (Example: fc = 16 MHz, fs = 32.768 kHz)
Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 010 011 100 101 110 111 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 DV7CK = 1 1 4 128 512 1024 2048 4096 16384 SLOW, SLEEP Mode 1 4 - - - - - -
86FM48-60
2007-08-24
TMP86FM48
2.4
Watchdog Timer (WDT)
The watchdog timer is a fail-safe system to rapidly detect the CPU malfunctions such as endless looping caused by noise or the like, or deadlock and resume the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a "reset request" or a non-maskable "interrupt request". However, selection is possible only once after reset. At first the "reset request" is selected. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. Note: Care must be given in system design so as to protect the watchdog timer from disturbing noise. Otherwise the Watchdog Timer may not fully exhibit its functionality.
2.4.1
Watchdog Timer Configuration
Reset release signal from T.G Binary counters Clock 1 2 R Overflow WDT output SQ Interrupt request 2 INTWDT Reset request
fc/2 or fs/2 21 13 fc/2 or fs/2 19 11 fc/2 or fs/2 17 9 fc/2 or fs/2 Clear
23
15
MPX A B Y C DS
Internal reset Q S R
WDTT
WDTEN
Writing disable code
Writing clear code
WDTOUT
Controller 0034H WDTCR1 0035H WDTCR2 MPX: Multiplexer
Watchdog timer control registers
Figure 2.4.1 Watchdog Timer Configuration
86FM48-61
2007-08-24
TMP86FM48 2.4.2 Watchdog Timer Control
Figure 2.4.2 shows the watchdog timer control registers (WDTCR1, WDTCR2). The watchdog timer is automatically enabled after reset. (1) Malfunction detection methods using the watchdog timer The CPU malfunction is detected as follows. 1. 2. Setting the detection time, selecting output, and clearing the binary counter. Repeatedly clearing the binary counter within the setting detection time
If the CPU malfunctions such as endless looping or deadlock occur for any cause, the watchdog timer output will become active at the rising of an overflow from the binary counters unless the binary counters are cleared. At this time, when WDTCR1 = "1", a reset is generated and the internal hardware is reseted. When WDTCR1 = "0", a watchdog timer interrupt (INTWDT) is generated. The watchdog timer temporarily stops counting in STOP mode including warm-up or IDLE mode, and automatically restarts (Continues counting) when the STOP/IDLE mode is released. Note: The watchdog timer consists of an internal divider and a two-stage binary counter. When clear code 4EH is written, only the binary counter is cleared, not the internal divider. Depending on the timing at which clear code 4EH is written on the WDTCR2 register, the overflow time of the binary counter may be at minimum 3/4 of the time set in WDTCR1 . Thus, write the clear code using a shorter cycle than 3/4 of the time set in WDTCR1 .
21
Example: Sets the watchdog timer detection time to 2 /fc [s] and resets the CPU malfunction. SYSCR1 LD (WDTCR2), 4EH ; Clears the binary counters LD (WDTCR1), 00001101B ; WDTT 10, WDTOUT 1 LD (WDTCR2), 4EH ; Clears the binary counters (Always clear Within 3/4 of immediately before and after changing WDT detection WDTT) time LD (WDTCR2), 4EH ; Clears the binary counters Within 3/4 of WDT detection LD (WDTCR2), 4EH ; Clears the binary counters time
86FM48-62
2007-08-24
TMP86FM48
Watchdog Timer Register 1 WDTCR1 7 6 (0034H)
5
4
3
2 WDTT
1
0
WDTOUT
(ATAS) (ATOUT) WDTEN Watchdog timer enable/disable
(Initial value: **11 1001)
WDTEN
0: Disable (It is necessary to write the disable code to WDTCR2) 1: Enable NORMAL1/2 mode DV7CK = 0 DV7CK = 1 2 /fs 15 2 /fs 13 2 /fs 11 2 /fs
17
SLOW mode 2 /fs 15 2 /fs 13 2 /fs 11 2 /fs
17
WDTT
Watchdog timer detection time [s]
00 01 10 11 0: Interrupt request 1: Reset request
2 /fc 23 2 /fc 21 2 /fc 19 2 /fc
25
Write only
WDTOUT Note 1: Note 2: Note 3: Note 4:
Watchdog timer output select
WDTOUT cannot be set to "1" by program after clearing WDTOUT to "0". fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. The watchdog timer must be disabled or the counter must be cleared immediately before entering to the STOP mode. When the counter is cleared, the counter must be cleared again immediately after releasing the STOP mode.
Note 5:
To disable the watchdog timer, always write "4EH" (Clear code) to WDTCR2 for clearing the binary counter before writing "0" to WDTEN, and then write "B1H" (Disable code) to WDTCR2. Also, immediately before these procedure, disable the interrupt mater flag (IMF) by DI instruction.
Watchdog Timer Register 2 WDTCR2 7 6 (0035H)
5
4
3
2
1
0 (Initial value: **** ****)
4EH: Watchdog timer control WDTCR2 code write register B1H: D2H:
Watchdog timer binary counter clear (Clear code) Watchdog timer disable (Disable code) Enable assigning address trap area Write only
Others: Invalid Note 1: Note 2: Note 3: Note 4: The disable code is invalid unless written when WDTCR1 = 0. *: Don't care The binary counter of the watchdog timer must not be cleared by the interrupt task. Write clear code 4EH within 3/4 of the time set in WDTCR1.
Figure 2.4.2 Watchdog Timer Control Registers (2) Watchdog timer enable The watchdog timer is enabled by setting WDTCR1 to "1". WDTCR1 is initialized to "1" during reset, so the watchdog timer operates immediately after reset is released. (3) Watchdog timer disable To disable the watchdog time, write "4EH" (Clear code) to WDTCR2 for clearing the binary counter before writing "0" to WDTCR1, and then write "B1H" (Disable code) to WDTCR2. The watchdog timer is not disabled if this procedure is reversed and the disable code is written to WDTCR2 before WDTCR1 is cleared to "0". Also, immediately before these procedure, disable the interrupt master flag (IMF) by DI instruction. During disabling the watchdog timer, the binary counters are cleared to "0".
86FM48-63
2007-08-24
TMP86FM48
Example: Disables watchdog timer DI LD (WDTCR2), 4EH LDW (WDTCR1), 0B101H
; ; ;
IMF 0 Clear the binary counter WDTEN 0, WDTCR2 Disable code
Table 2.4.1 Watchdog Timer Detection Time (Example: fc = 16 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time [s] WDTT NORMAL1/2 Mode DV7CK = 0
00 01 10 11 2.097 524.288 m 131.072 m 32.768 m
DV7CK = 1
4 1 250 m 62.5 m
SLOW Mode
4 1 250 m 62.5 m
2.4.3
Watchdog Timer Interrupt (INTWDT)
This is a non-maskable interrupt which can be accepted regardless of the contents of the EIR. If a watchdog timer interrupt or a software interrupt is already accepted, however, the new watchdog timer interrupt waits until the previous interrupt processing is completed (The end of the [RETN] instruction execution). The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source with WDTOUT.
Example: Watchdog timer interrupt setting up LD SP, 023FH LD (WDTCR1), 00001000B
; ;
Sets the stack pointer WDTOUT 0
2.4.4
Watchdog Timer Reset
If the watchdog timer reset request occur, a reset is generated and the internal hardware is reseted. When the watchdog timer reset is generated, the flash reset is also generated. Therefore, the maximum reset period is 24/fc [s] + 210/fc [s] (65.5 s at 16.0 MHz). Note: The high-frequency clock oscillator also immediately turns on when a watchdog timer reset is generated in SLOW mode. In this case, the reset time may include a certain amount of error if there is any fluctuation of the oscillation frequency at starting the high-frequency clock oscillation. Therefore, the reset time must be considered an approximated value.
2 /fc [s] 2 /fc
17 19
Clock Binary counter Overflow INTWDT interrupt
(WDTCR1 = "0")
(WDTT = 11B) 1 2 3 0 1 2 3 0
Internal reset
(WDTCR1 = "1")
Reset generate Write 4EH to WDTCR2
Figure 2.4.3 Watchdog Timer Interrupt/Reset
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2007-08-24
TMP86FM48
2.5
Address Trap
The watchdog timer control register 1, 2 shares its addresses with the control registers in case of address trap. These control registers for address trap are shown on Figure 2.5.1.
Watchdog Timer Control Register 1 WDTCR1 7 6 (0034H) - -
5 ATAS
4
3
2 (WDTT)
1
0
(WDTOUT)
ATOUT (WDTEN)
(Initial value: **11 1001)
ATAS
Selection of address trap in internal RAM Selection of operation at address trap
0: No address trap 1: Address trap (After setting ATAS to "1", it is necessary to write the control code D2H to WDTCR2) 0: Interrupt request 1: Reset request
Write only
ATOUT
Watchdog Timer Control Register 2 WDTCR2 7 6 (0035H)
5
4
3
2
1
0 (Initial value: **** ****)
Watchdog timer control code WDTCR2 and Address trapped area control code
D2H: 4EH: B1H:
Address trapped area valid to set (ATRAP control code) Watchdog timer binary counter clear (WDT clear code) Watchdog timer disable (WDT disable code) Write only
Others: Invalid
Figure 2.5.1 Watchdog Timer Control Registers (1) Selection of address trap in internal RAM (ATAS) Using WDTCR1, address trap or no address trap can be selected for the internal RAM area. To execute an instruction in the internal RAM area, set "0" in WDTCR1. Setting in WDTCR1 becomes valid after control code D2H is written in WDTCR2. Executing an instruction in the SFR/DBR area generates an address trap unconditionally regardless of the setting in WDTCR1. (2) Selection of operation at address trap (ATOUT) As the operation at address trap either interrupt request or reset request can be selected by WDTCR1.
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2007-08-24
TMP86FM48
2.6
Divider Output (DVO)
Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from pin P51 ( DVO ). The P51 output latch should be set to "1". Note: Selection of divider output frequency must be made while divider output is disabled. Also, in other words, when changing the state of the divider output frequency from enabled to disable, do not change the setting of the divider output frequency.
7 DVOEN 6 DVOCK 5 4 3 2 1 (TBTCK) 0 (Initial value: 0000 0000)
TBTCR (0036H)
(DV7CK) (TBTEN) 0: Disable 1: Enable
DVOEN
Divider output enable/disable
NORMAL1/2 Mode DV7CK = 0 DVOCK Divider output ( DVO ) frequency selection [Hz] 00 01 10 11 fc/2 12 fc/2 11 fc/2 10 fc/2
13
DV7CK = 1 fs/2 4 fs/2 3 fs/2 2 fs/2
5
SLOW, SLEEP Mode fs/2 fs/2 fs/2 fs/2
5 4 3 2
R/W
Note: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care
Figure 2.6.1 Divider Output Control Register
Example: 1.95 kHz pulse output (at fc = 16.0 MHz) SET (P5DR).1 LD (TBTCR), 00000000B LD (TBTCR), 10000000B
; ; ;
P51 output latch "1" DVOCK "00" DVOEN "1"
Table 2.6.1 Divider Output Frequency (Example: at fc = 16.0 MHz, fs = 32.768 kHz) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0
00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k
DV7CK = 1
1.024 k 2.048 k 4.096 k 8.192 k
SLOW, SLEEP Mode
1.024 k 2.048 k 4.096 k 8.192 k
Output latch Data output
D Q
P51 ( DVO )
MPX: Multiplexer
MPX fc/2 or fs/2 12 4 fc/211 or fs/23 fc/2 or fs/2 10 2 fc/2 or fs/2 DVOCK TBTCR Divider output control register (a) Configuration
DVO pin output
13 5
A B C D 2
Y S
P51 output latch DVOEN DVOEN
(b) Timing Chart
Figure 2.6.2 Divider Output
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2007-08-24
MCAP1
2.7
2.7.1
S TC1S 2 Command start INTTC1 interrupt Start Set Clear MPPG1 TC1S clear PPG output mode METT1
A
Y
B MPX
External trigger start
Decoder
Configuration
Pulse width measurement mode
External trigger
Falling
Rising
16-Bit Timer/Counter 1
Edge detector
TC1 pin MPX B Y A S Window mode Capture Match CMP Clear Source clock Clear
MPX
Port (Note 2) 16-bit up counter
Pulse width measurement mode
D
Figure 2.7.1 Timer/Counter 1 (TC1)
PPG output mode Q Set Toggle Internal reset
86FM48-67
B
ACAP1
fc/2 or fs/2 7 fc/2 3 fc/2
11
3
A BY C S
2
Toggle Q Set Clear
PPG
Y TC1DRA
A
S
Port (Note 2)
pin
TC1CK
TC1CR
TC1DRB
TC1 control register
16-bit timer register 1A, B TC1CR write strobe TFF1
Note 1:
MPX: Multiplexer
CMP: Comparator
Note 2:
When control input /output is used, I/O port setting should be set correctly.
TMP86FM48
2007-08-24
For details, refer to "2.2 I/O ports".
TMP86FM48 2.7.2 Control
The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB).
15 TC1DRA (0021,0020H) R/W TC1DRB (0023,0022H) R/W Note: 7 TC1CR (001FH)
14
13 12 11 10 TC1DRAH (0021H)
9
8
7
6
5
4 3 2 TC1DRAL (0020H)
1
0
(Initial value: 1111 1111 1111 1111) TC1DRBH (0023H) TC1DRB should not be written except PPG mode. 6 5 TC1S TC1CK TC1M (Initial value: 0000 0000) 4 3 2 1 0 TC1DRBL (0022H) (Initial value: 1111 1111 1111 1111)
ACAP1 MCAP1 TFF1 METT1 MPPG1
TC1M
TC1 operating mode select
00: 01: 10: 11:
TC1CK
TC1 source clock select [Hz]
00 01 10 11
Timer/external trigger timer/event counter mode Window mode Pulse width measurement mode PPG (Programmable pulse generate) output mode NORMAL1/2, IDLE1/2 mode SLOW1/2, SLEEP1/2 mode DV7CK = 0 DV7CK = 1 3 11 3 fs/2 fs/2 fc/2 7 7 fc/2 fc/2 - 3 3 fc/2 fc/2 - External clock (TC1 pin input)
Timer Extend Event Window Pulse PPG
00: Stop and counter clear
TC1S
TC1 start control
01: Command start 10: External trigger start at the rising edge 11: External trigger start at the falling edge

x x
x
x

x

x

R/W
ACAP1 MCAP METT1 MPPG1 TFF1
Auto capture control 0: Auto-capture disable Pulse width measurement 0: Double edge capture mode control External trigger timer mode 0: Trigger start control PPG output control Time F/F1 control Note 1: Note 2: 0: Clear
1: Auto-capture enable 1: Single edge capture 1: Trigger start and stop
0: Continuous pulse generation 1: One-shot 1: Set
fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] The timer register consists of two shift registers. A value set in the timer register is put in effect at the rising edge of the first source clock pulse that occurs after the upper data (TC1DRAH and TC1DRBH) are written. Therefore, the lower byte must be written before the upper byte (it is recommended that a 16-bit access instruction be used in writing). Writing only the lower data (TC1DRAL and TC1DRBL) does not put the setting of the timer register in effect. Set the mode, source clock, PPG control and timer F/F control when TC1 stops (TC1S = 00). Auto-capture can be used in only timer, event counter, and window modes. Values to be loaded to timer registers must satisfy the following condition. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (others)
Note 3: Note 4: Note 5:
Note 6: Note 7: Note 8:
Always write "0" to TFF1 except PPG output mode. Writing to the TC1DRB is not possible unless TC1 is set to the PPG output mode. On entering STOP mode, the TC1 start control (TC1S) is cleared to "00" automatically. So, the timer stops. Once the STOP mode has been released, to start using the timer counter, set TC1S again.
Note 9:
Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition.
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2007-08-24
TMP86FM48
Note 10: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time.
Figure 2.7.2 Timer Registers and TC1 Control Register
2.7.3
Function
Timer/counter 1 has six operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output mode. (1) Timer mode In this mode, counting up is performed using the internal clock. The contents of TC1DRA are compared with the contents of up counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to "0". Counting up resumes after the counter is cleared. The current contents of up counter can be transferred to TC1DRB by setting TC1CR to "1" (Auto capture function). Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time.
Table 2.7.1 Source Clock (internal clock) for Timer/Counter 1 (Example: at fc = 16 MHz, fs = 32.768kHz) NORMAL1/2, IDLE1/2 Mode DV7CK = 0 TC1CK Resolution [s]
128 8.0 0.5
SLOW1/2, SLEEP1/2 Mode Maximum Time Setting [s]
16.0 0.524 32.77 m
11
DV7CK = 1 Resolution [s]
244.14 8.0 0.5
Maximum Time Setting [s]
8.39 0.524 32.77 m
Resolution [s]
244.14 - -
Maximum Time Setting [s]
16.0 - -
00 01 10
Example 1: Sets the timer mode with source clock fc/2 [Hz] and generates an interrupt 1 second later (at fc = 16 MHz, DV7CK = 0) LDW DI SET EI LD LD Example 2: Auto-capture LD LD Note : (TC1CR), 01010000B WA, (TC1DRB) ; ; ACAP1 "1" (Capture) Reads the capture value (TC1CR), 00000000B (TC1CR), 00010000B (EIRL). 5 (TC1DRA), 1E84H ; ; ; ; ; ; Sets the timer register (1 s / 2 /fc = 1E84H)
11
IMF = "0" Enable INTTC1 IMF = "1" TFF1 "0", TC1CK "00", TC1M "00" Starts TC1
Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time.
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2007-08-24
TMP86FM48
Command start Source clock Up counter TC1DRA INTTC1 interrupt Source clock Up counter TC1DRB ACAP1 (b) Auto capture ? m - -2 m-1 m-1 m m+1 Capture m m+1 m+2 m+2 n-1 n-1 n n+1 Capture n n+1 ? 0 n Match detect (a) Timer mode Counter clear 1 2 3 4 n-1 n 0 1 2 3 4 5 6 7
Figure 2.7.3 Timer Mode Timing Chart
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2007-08-24
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(2) External trigger timer mode In this mode, counting up is started by an external trigger. This trigger is the edge of the TC1 pin input. Either the rising or falling edge can be selected with TC1S. Source clock is an internal clock. The contents of TC1DRA is compared with the contents of up counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to "0" and halted. The counter is restarted by the selected edge of the TC1 pin input. When TC1CR is "1", inputting the edge to the reverse direction of the trigger edge to start counting clears the counter, and the counter is stopped. Inputting a constant pulse width can generate interrupts. When TC1CR is "0", the reverse directive edge input is ignored. The TC1 pin input edge before a match detection is also ignored. The TC1 pin input has the noise rejection; therefore, pulses of 4/fc [s] or less are rejected as noise. A pulse width of 12/fc [s] or more is required for edge detection in NORMAL1/2 or IDLE1/2 mode. The noise rejection circuit is turned off in SLOW1/2 and SLEEP1/2 modes. But, a pulse width of one machine cycle or more is required.
Example 1: Detects rising edge in TC1 pin input and generates an interrupt 100 s later. (at fc = 16 MHz, DV7CK = 0) DI LDW SET EI LD LD (at fc = 16 MHz) DI LDW SET EI LD LD (TC1CR), 01001000B (TC1CR), 01111000B (TC1DRA), 1F40H (EIRL). 5 ; ; ; ; ; ; IMF = "0" 4 ms / 2 /fc = 1F40H
3
; (TC1DRA), 00C8H (EIRL). 5 (TC1CR), 00001000B (TC1CR), 00101000B ; ; ; ; ;
IMF = "0" 100 s / 2 /fc = C8H
3
INTTC1 interrupt enable IMF = "1" TFF1 = "0", TC1CK = "10", TC1M = "00" TC1 external trigger start, METT1 ="0"
Example 2: Generates an interrupt, inputting "L" level pulse (pulse width: 4 ms or more) to the TC1 pin.
INTTC1 interrupt enable IMF = "1" TFF1 = "0", TC1CK = "10", TC1M = "00" TC1 external trigger start, METT1 = 1
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2007-08-24
TMP86FM48
Count start TC1 pin input Internal clock Up counter TC1DRA INTTC1 interrupt ? n Match detect (a) Trigger start (METT1 = 0) Count start TC1 pin input Internal clock Up counter TC1DRA INTTC1 interrupt n Match detect (b) Trigger start and Stop (METT1 = 1) Counter clear 0 1 2 3 m 0 1 n-2 n-1 n 0 Trigger Count clear Count start Trigger Trigger TC1S = 10 at the rising edge Counter clear 0 1 2 3 n-1 n 0 1 2 3 Trigger Count start Trigger TC1S = 10 at the rising edge
Note: m < n
Figure 2.7.4 External Trigger Timer Mode Timing Chart (3) Event counter mode In this mode, events are counted at the edge of the TC1 pin input (either the rising or falling edge can be selected with the external trigger TC1CR). The contents of TC1DRA are compared with the contents of up counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. After the counter is cleared, the up counter starts counting by TC1 input edge. Match detect is executed on other edge of count-up. A match can not be detected and INTTC1 is not generated when the pulse is still in same state. Two or more machine cycles are required for both the "H" and "L" levels of the pulse width. Setting TC1CR to "1" transfers the current contents of up counter to TC1DRB (Auto-capture function). Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR to "1". Therefore, to read the captured value, wait at least one cycle of the internal source clock before reading TC1DRB for the first time.
Count start TC1 pin input Up counter TC1DRA INTTC1 interrupt ? 0 n Match detect Counter clear 1 2 n-1 n 0 1 2 TC1S = 10 at the rising edge
Figure 2.7.5 Event Counter Mode Timing Chart
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2007-08-24
TMP86FM48
Table 2.7.2 Timer/Counter 1 External Clock Source Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 Mode
"H" width "L" width 2 /fc 2 /fc
3 3
SLOW1/2, SLEEP1/2 Mode
2 /fs 2 /fs
3 3
(4) Window mode In this mode, counting up is performed on the rising edge of the pulse that is the logical AND-ed product of the TC1 pin input (Window pulse) and an internal clock. The contents of TC1DRA are compared with the contents of up counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. It is possible to select either positive logic or negative logic for the TC1 pin input (by using the TC1 start control TC1CR). The maximum frequency that can be applied to the pin must be such that the related count can be analyzed by program. To put another way, the frequency of the applied pulse must be sufficiently low, compared with that of the internally set source clock.
Count start Command start TC1 pin input Internal clock Up counter TC1DRA INTTC1 interrupt Command start TC1 pin input Internal clock Up counter TC1DRA INTTC1 interrupt (b) Negative logic (at TC1S = 11) ? 9 Match detect Counter clear 0 1 2 3 4 5 6 7 8 901 Count start ? 7 Match detect (a) Positive logic (at TC1S = 10) Count stop Counter clear 0 1 2 3 4 5 6 70 1 2 3 Count stop Count start
Count start
Figure 2.7.6 Window Mode Timing Chart
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2007-08-24
TMP86FM48
(5) Pulse width measurement mode In this mode, counting is started by the external trigger (Set to external trigger start by TC1CR). The trigger can be selected either the rising or falling edge of the TC1 pin input. The source clock is used an internal clock. On the next falling (Rising) edge, the counter contents are transferred to TC1DRB and an INTTC1 interrupt is generated. The counter is cleared when the single edge capture mode (TC1CR = "1") is set. When double edge capture (TC1CR = "0") is set, the counter continues and, at the next rising (Falling) edge, the counter contents are again transferred to TC1DRB. If a falling (Rising) edge capture value is required, it is necessary to read out TC1DRB contents until a rising (Falling) edge is detected. Falling or rising edge is selected with the external trigger TC1CR, and single edge or double edge is selected with TC1CR. Note 1: Be sure to read the captured value from TC1DRB before the next trigger edge is detected. If fail to read it, it becomes undefined. It is recommended that a 16-bit access instruction be used to read from TC1DRB. Note 2: If either the falling or rising edge is used in capturing values, the counter stops at "1" after a value has been captured until the next edge is detected. So, the value captured next will become "1" larger than the value captured right after capturing starts. Note 3: The first captured value after the timer starts may be read incorrectively, therefore, ignore the first captured value.
Example: Duty measurement (resolution fc/2 [Hz]) CLR LD DI SET EI LD PINTTC1: CPL JRS LD LD RETI SINTTC1: LD LD RETI VINTTC1: DW PINTTC1 L, (TC1DRBL) H, (TC1DRBH) ; Duty calculation ; Reads TC1DRB (Period) (TC1CR), 00100110B (INTTC1SW). 0 F, SINTTC1 A, (TC1DRBL) W, (TC1DRBH) ; Reads TC1DRB ("H" level pulse width) (EIRL). 5 (INTTC1SW). 0 (TC1CR), 00000110B ; ; ; ; ; ; ; INTTC1 service switch initial setting Sets the TC1 mode and source clock IMF = "0" Enables INTTC1 IMF = "1" Starts TC1 with an external trigger at MCAP1 = 0 Inverts INTTC1 service switch
7
WIDTH HPULSE TC1 pin
INTTC1SW
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2007-08-24
TMP86FM48
Count start Trigger Count start (TC1S = "10")
TC1 pin input Internal clock Up counter TC1DRB INTTC1 interrupt
0
1
2
3
4
n-1 n 0 Capture n
1
2
3
TC1 pin input Internal clock Up counter TC1DRB INTTC1 interrupt
Count start
[Application] "H" or "L" level pulse width measurement (a) Single edge capture (MCAP1 = "1") Count start (TC1S = "10")
0
1
2
3
4
n-1
n
n+1 n+2 n+3 Capture n
m-2 m-1 m 0 1 Capture m
2
[Application] (1) Period/frequency measurement (2) Duty measurement (b) Double edge capture (MCAP1 = "0")
Figure 2.7.7 Pulse Measurement Mode Timing Chart
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2007-08-24
TMP86FM48
(6) Programmable pulse generate (PPG) output mode The PPG output mode is intended to output pulses having an arbitrary duty cycle selected using two timer registers. The timer starts at an edge (Rising or falling edge, that is, the same edge type as selected with the external trigger edge select bits (TC1CR) or on a command. Its source clock is an internal clock. Once the timer starts running, the timer F/F1 is inverted when the counter matches TC1DRB, generating the INTTC1 interrupt. The counter keeps up-counting, and when counter matches TC1DRA, the timer F/F1 is inverted, generating an INTTC1 interrupt. If TC1CR was previously set to "1" (One shot), TC1S is cleared to "00" automatically, causing the timer to stop. If TC1CR was previously cleared to "0" (Continuous pulse generation), the counter is cleared, resulting in the counter keeping to run and the PPG output being continued. If TC1CR is reset to "00" (One-shot-based automatic stop is included) during PPG output, the P50 ( PPG ) pin holds the same level that it does just before the counter stops. In PPG output mode, set the output latch of port P50 to "1". The timer F/F1 is cleared to "0" at a reset. In addition, a positive or negative pulse can be output because the output level can be set up at a start, using TC1CR. The P50 ( PPG ) pin outputs an inversion of the timer F/F1 output level. It is impossible to write to TC1DRB unless the PPG output mode is set. Note 1: To change the content of the timer register when the timer is running, change it to a sufficiently large value, compared with the current count. If the timer register content is changed to a value smaller than the current count when the timer is running, it is likely that unintended pulses may be output. Note 2: Do not change TC1CR when the timer is running. TC1CR can be set correctly only at initialization (after a reset). When the timer is stopped during PPG output, if the PPG output is at a logic state opposite to the PPG that when the timer starts, it will become impossible to set TC1CR correctly (An attempt to program TC1CR will cause a state opposite to the programmed one to be set in the bit). Once the timer has stopped, putting the PPG output securely on an arbitrary level requires initializing the timer F/F1. To initialize it, put TC1CR in the timer mode again (It is unnecessary to start the timer mode), and then put it in the PPG output mode again. At the same time, set TC1CR. Note 3: In the PPG output mode, a value set in the timer register must satisfy: TC1DRA > TC1DRB
Example: Pulse output "H" level 800 s, "L" level 200 s (at fc = 16 MHz, DV7CK = 0) SET LD LDW LDW LD (P5DR). 0 (TC1CR), 10001011B (TC1DRA), 07D0H (TC1DRB), 0190H (TC1CR), 10011011B ; ; ; ; ; P50 output latch 1 Sets the PPG output mode Sets the period (1 ms / 2 /fc = 07D0H)
3
Sets "L" level pulse width (200 s / 2 /fc = 0190H)
3
Starts
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2007-08-24
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P50 output latch Data output D R Q
TFF1 TC1CR write strobe Internal reset Match with TC1DRB Match with TC1DRA INTTC1 interrupt MPPG1
Set Clear Q P50 ( PPG ) pin
Toggle Timer F/F1 TC1S clear MPX: Multiplexer
Figure 2.7.8 PPG Output
Command start Internal clock Up counter TC1DRB TC1DRA
PPG pin output
0 n
1
2
n
n+1
m0
1
2
n
n+1
m0
1
2
Match m
INTTC1 interrupt (a) Continuous pulse generation (with TC1S = 01) Count start TC1 pin input Internal clock Up counter TC1DRB TC1DRA
PPG pin output
Note: m > n
Trigger
0 n
1
n
n+1
m
0
Match m
INTTC1 interrupt [Application] One shot pulse output (b) One-shot (with TC1S = 10)
Note: m > n
Figure 2.7.9 PPG Output Mode Timing Chart
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2007-08-24
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2.8
16-Bit Timer/Counter 2
Configuration
(Note 2) TC2S MPX H
15
2.8.1
TC2 pin
23
Port fc/2 or fs/2 13 5 fc/2 or fs/2 8 fc/2 3 fc/2 fc fs
Window A B C D E F S 3 TC2CK TC2S B Timer/event counter Y TC2M A S Y
Source clock
Clear 16-bit up counter
CMP
Match Enable Match detect control INTTC2 interrupt
TC2CR TC2 control register
TC2DR 16-bit timer register 2
TC2DRH write strobe
TC2DRL write strobe
Note 1:
MPX: Multiplexer CMP: Comparator
Note 2:
When control input/output is used, I/O port setting should be set correctly. For details, refer to "2.2 I/O ports".
Figure 2.8.1 Timer/Counter 2 (TC2A)
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2007-08-24
TMP86FM48 2.8.2 Control
The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TC2DR). Reset does not affect TC2DR.
15 TC2DR (0025, 0024H) R/W TC2CR (0013H) 14 13 12 11 10 TC2DRH (0025H) 9 8 7 6 5 4 3 2 TC2DRL (0024H) 1 0
7
6
5 TC2S
4
3 TC2CK
2
1
0 TC2M (Initial value: **00 00*0)
TC2M
TC2 operating mode select
0: 1:
Timer/event counter mode Window mode NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 15 23 fs/2 fc/2 5 13 fs/2 fc/2 8 8 fc/2 fc/2 3 3 fc/2 fc/2 - - fs fs SLOW1/2 mode fs/2 5 fs/2 - - fc (Note 7) -
15
SLEEP1/2 mode fs/2 5 fs/2 - - - -
15
TC2CK
TC2 source clock select [Hz]
000 001 010 011 100 101 110 111 0: 1:
R/W
Reserved External clock (TC2 pin input) Stop and counter clear Start
TC2S Note 1: Note 2:
TC2 start control
fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care When writing to the Timer Register 2 (TC2DR), always write to the lower side (TC2DRL) and then the upper side (TC2DRH) in that order. Writing to only the lower side (TC2DRL) or the upper side (TC2DRH) has no effect.
Note 3:
The timer register 2 (TC2DR) uses the value previously set in it for coincidence detection until data is written to the upper side (TC2DRH) after writing data to the lower side (TC2DRL). Set the mode and source clock when the TC2 stops (TC2S = 0). Values to be loaded to the timer register must satisfy the following condition. TC2DR > 1 (TC2DR15 to TC2DR11 > 1 at warm up)
Note 4: Note 5:
Note 6: Note 7: Note 8:
If a read instruction is executed for TC2CR, read data of bit 7, 6 and 1 are unstable. The high-frequency clock(fc) can be selected only when the timer mode at SLOW2 mode is selected. On entering STOP mode, the TC2 start control (TC2S) is cleared to "0" automatically. So, the timer stops. Once the STOP mode has been released, to start using the timer counter, set TC2S again.
Figure 2.8.2 Timer Register 2 and TC2 Control Register
86FM48-79
2007-08-24
TMP86FM48 2.8.3 Function
The timer/counter 2 has three operating modes: timer, event counter and window modes. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC2DR are compared with the contents of up counter. If a match is found, a timer/counter 2 interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. When fc is selected for source clock at SLOW2 mode, lower 11-bits of TC2DR are ignored and generated a interrupt by matching upper 5-bits. Though, in this situation, it is necessary to set TC2DRH only. Table 2.8.1 Source Clock (Internal clock) for Timer/Counter 2 (at fc = 16 MHz)
NORMAL1/2, IDLE1/2 Mode DV7CK = 0 TC2CK Resolution Maximum Time Setting 000 001 010 011 100 101 524.29 ms 512.00 s 16.00 s 0.50 s - 30.52 s 9.54 h 33.55 s 1.05 s 32.77 ms - 2.00 s 1.00 s 0.98 ms 16.00 s 0.50 s - 30.52 s Resolution DV7CK = 1 Maximum Maximum Time Setting 18.20 h 1.07 min 1.05 s 32.77 ms - 2.00 s 1.00 s 0.98 ms - - 62.5 ns (Note) - 18.20 h 1.07 min - - - - 1.00 s 0.98 ms - - - - 18.20 h 1.07 min - - - - Resolution Time Setting Resolution Maximum Time Setting SLOW1/2 Mode SLEEP1/2 Mode
Note: When fc is selected as the source clock in timer mode, it is used at warm-up for switching from SLOW2 mode to NORMAL2 mode.
Example: Sets the timer mode with source clock fc/2 [Hz] and generates an interrupt every 25 ms (at fc = 16 MHz). LDW DI SET EI LD LD (TC2CR), 00001100B (TC2CR), 00101100B (EIRE). 4 (TC2DR), 0C350H ; ; ; ; ; ; Sets TC2DR (25 ms / 2 /fc = C350H)
3 3
IMF = "0" Enables INTTC2 interrupt IMF = "1" TC2CK "011", TC2M "0" Starts TC2
86FM48-80
2007-08-24
TMP86FM48
(2) Event counter mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are compared with the contents of the up counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. The minimum input pulse width of TC2 pin is shown in Table 2.8.2. Two or more machine cycles are required for both the "H" and "L" levels of the pulse width. Match detect is executed on the falling edge of the TC2 pin. A match can not be detected and INTTC2 is not generated when the pulse is still in a falling state.
Example: Sets the event counter mode and generates an INTTC2 interrupt 640 counts later. LDW DI SET EI LD LD (TC2CR), 00011100B (TC2CR), 00111100B (EIRE). 4 (TC2DR), 640 ; ; ; ; ; ; Sets TC2DR IMF = "0" Enables INTTC2 interrupt IMF = "1" TC2CK "111", TC2M "0" Starts TC2
Table 2.8.2 Timer/Counter 2 External Clock Source Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 Mode
"H" width "L" width 2 /fc 2 /fc
3 3
SLOW1/2, SLEEP1/2 Mode
2 /fs 2 /fs
3 3
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2007-08-24
TMP86FM48
(3) Window mode In this mode, counting up performed on the rising edge of an internal clock during TC2 external pin input (Window pulse) is "H" level. The contents of TC2DR are compared with the contents of up counter. If a match found, an INTTC2 interrupt is generated, and the up-counter is cleared. The maximum applied frequency (TC2 input) must be considerably slower than the selected internal clock. Note: In the window mode, before the SLOW/SLEEP mode is entered, the timer should be halted by setting TC2CR to "0".
(at fc = 16 MHz, DV7CK = 0) LDW DI SET EI LD LD TC2 pin input Internal clock Up counter TC2DR INTTC2 interrupt n Match detect Counter clear 0 1 2 n-3 n-2 n-1 n 0 1 2 3 (TC2CR), 00000101B (TC2CR), 00100101B (EIRE). 4 (TC2DR), 00EAH ; ; ; ; ; ; Sets TC2DR (120 ms / 2 /fc = 00EAH)
13
Example: Generates an interrupt, inputting "H" level pulse width of 120 ms or more.
IMF = "0" Enables INTTC2 interrupt IMF = "1" TC2CK "001", TC1M "1" Starts TC2
Figure 2.8.3 Window Mode Timing Chart
86FM48-82
2007-08-24
TMP86FM48
2.9
8-Bit Timer/Counter 3
Configuration
2.9.1
TC3S
Edge detector
TC3 pin
Clear
Port
(Note 2) fc/2 or fs/2 12 4 fc/211 or fs/23 fc/210 or fs/22 fc/2 or fs/2 9 fc/28 or fs fc/27 fc/2
13 5
Falling MPX H A B C D E F G S 3 TC3CK TC3S TC3M ACAP Y
Rising
Source clock
8-bit up counter
Overflow
CMP Capture TC3DRB TC3DRA Capture Match
1 0 S
Y INTTC3 interrupt TC3S
8-bit timer register 3A, B
TC3CR
TC3 control register
Note 1:
MPX: Multiplexer CMP: Comparator
Note 2:
When control input/output is used, I/O port setting should be set correctly. For details, refer to "2.2 I/O ports".
Figure 2.9.1 Timer/Counter 3 (TC3)
86FM48-83
2007-08-24
TMP86FM48 2.9.2 Control
The timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two 8-bit timer registers (TC3DRA and TC3DRB).
TC3DRA (0010H) R/W TC3DRB (0011H) Read only TC3CR (0012H)
7
6
5
4
3
2
1
0 (Initial value: 1111 1111)
7
6
5
4
3
2
1
0 (Initial value: 1111 1111)
7
6 ACAP
5
4 TC3S
3
2 TC3CK
1
0 TC3M (Initial value: *0*0 0000)
TC3M
TC3 operation mode set
0: Timer/event counter 1: Capture NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 13 5 fs/2 fc/2 12 4 fc/2 fs/2 11 3 fc/2 fs/2 10 2 fc/2 fs/2 9 fc/2 fs/2 8 8 fc/2 fc/2 7 7 fc/2 fc/2 SLOW1/2, SLEEP1/2 mode 5 fs/2 4 fs/2 3 fs/2 2 fs/2 fs/2 - -
TC3CK
TC3 source clock select [Hz]
000 001 010 011 100 101 110 111
R/W
External clock (TC3 pin input)
TC3S ACAP Note 1: Note 2: Note 3:
TC3 start select Auto-capture control
0: Stop and clear 1: Start 0: - 1: Auto capture enable
fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Set the mode and the source clock when the TC3 stops (TC3S = 0). Values to be loaded into timer register 3A must satisfy the following condition. TC3DRA > 1 (in the timer and event counter mode)
Note 4: Note 5: Note 6: Note 7:
Auto-capture can be used only in the timer and event counter mode. If a read instruction is executed for TC3CR, read data for bits 7 and 5 are unstable. During TC3 operation, do not change TC3DRA. On entering STOP mode, TC3 start control (TC3S) is cleared to "0" automatically, so the timer stops. Once the STOP mode has been released, to start using the timer counter, set TC3S again.
Figure 2.9.2 Timer Register 3 and TC3 Control Register
86FM48-84
2007-08-24
TMP86FM48 2.9.3 Function
The timer/counter 3 has three operating modes: timer, event counter, and capture mode. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC3DRA are compared with the contents of up counter. If a match is found, a timer/counter 3 interrupt (INTTC3) is generated, and the up counter is cleared. The current contents of up counter are loaded into TC3DRB by setting TC3CR to "1" (Auto-capture function). The contents of up counter can be easily confirmed by executing the read instruction (RD instruction) of TC3DRB. Loading the contents of up counter is not synchronized with counting up. The contents of over flow (FFH) and 00H can not be loaded correctly. It is necessary to consider the count cycle.
Clock Counter TC3DRB FE FE FF 00 FF 01 01
Table 2.9.1 Source Clock (Internal clock) for Timer/Counter 3 (Example: at fc = 16 MHz) NORMAL1/2, IDLE1/2 Mode DV7CK = 0 TC3CK DV7CK = 1 SLOW1/2 Mode Maximum Time Setting [ms]
249.0 124.5 62.3 31.1 15.6 - -
Maximum Maximum Resolution Resolution Resolution Time Time [s] Setting Setting [s] [s] [ms] [ms]
512.0 256.0 128.0 64.0 32.0 16.0 8.0 130.6 65.3 32.6 16.3 8.2 4.1 2.0 976.6 488.3 244.1 122.0 61.0 16.0 8.0 249.0 124.5 62.3 31.1 15.6 4.1 2.0 976.6 488.3 244.1 122.0 61.0 - -
000 001 010 011 100 101 110
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2007-08-24
TMP86FM48
(2) Event counter mode In this mode, events are counted on the edge of the TC3 pin input. The counter counts up on the rising edge of the TC3 pin input and when its value matches the TC3DRA set value, it is cleared while at the same time generating an INTTC3 interrupt. The detection of match is executed at the falling edge of the TC3 pin. Therefore, if the TC3 pin keeps high level after the rising, the detection of match is not executed and INTTC3 is not generated until the level of TC3 pin becomes low. The minimum input pulse width of the TC3 pin is shown in Table 2.9.2. One or more machine cycles are required for both the "H" and "L" levels of the pulse width. The current contents of up counter are loaded into TC3DRB by setting TC3CR to "1" (Auto-capture function). The contents of up counter can be easily confirmed by executing the read instruction (RD instruction) of TC3DRB. Loading the contents of up counter is not synchronized with counting up. The contents of over flow (FFH) and 00H can not be loaded correctly. It is necessary to consider the count cycle. Table 2.9.2 Source Clock (External clock) for Timer/Counter Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 Mode
"H" width "L" width 2 /fc 2 /fc
2 2
SLOW1/2, SLEEP1/2 Mode
2 /fs 2 /fs
2 2
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2007-08-24
TMP86FM48
(3) Capture mode In this mode, the pulse width, period and duty of the TC3 pin input are measured in this mode, which can be used in decoding the remote control signals or distinguishing AC 50/60 Hz, etc. Once command operation has started, the counter free-runs on an internal source clock. When the falling edge of the TC3 pin input is detected, the counter value is loaded into TC3DRB. When the rising edge is detected, the counter value is loaded into TC3DRA, and the counter is cleared, generating an INTTC3 interrupt. If the rising edge is detected right after command operation has started, no capture to TC3DRB and an INTTC3 interrupt occurs only on capture to TC3DRA. If a read instruction is executed for TC3DRB, the value that exists at the end of the previous capture (Immediately after a reset, "FF") is read. The minimum acceptable input pulse width is equal to the length of one source clock period selected by TC3CR. Table 2.9.3 Capture Input Edges Capture into TC3DRB
Falling edge
Capture into TC3DRA
INTTC3 Interrupt
Rising edge
When the overflow occurs before detecting the edge, the INTTC3 interrupt is generated, setting "FFH" to TC3DRA and clearing the counter. It is possible to confirm whether the overflow has occurred or not by reading TC3DRA in interrupt routine. After generating of interrupt, the capture function and overflow detection stop until the TC3DRA is read, but the counting is continued. Because the capture function and overflow detection are restarted by reading TC3DRA, read the TC3DRB before the reading TC3DRA.
86FM48-87
2007-08-24
Command start
TC3S
Source clock 1 1 i-1 i 1 i+1 k-1 k 0 n-1 n 0 m-1 m m+1 2 3 FE FF 1 2 3
Up counter
0
TC3 pin input
Figure 2.9.3 Capture Mode Timing Chart
k i Capture m Capture n
86FM48-88
TC3DRA
FF (Overflow) FE Overflow
TC3DRB
INTTC3 interrupt
Reading TC3DRA
TMP86FM48
2007-08-24
TMP86FM48
2.10 8-Bit Timer/Counter 5
2.10.1 Configuration
TC5S MPX fc/2 or fs/2 7 fc/25 fc/23 fc/2 fc/2 fc/2 fc
2 11 3
A B C D Y E F G H
Source clock
Clear
8-bit up counter
Overflow AY B S Match Timer F/F5 Toggle
TC5 pin (Note 2)
Port
S 3 TC5CK TC5M TC5S 2
CMP
Port
A B YS PDO mode TC5S Clear
PWM5 /
(Note 2) PDO5 pin
TC5CR
TC5 control register
TC5DR
8-bit timer register 5
INTTC5 interrupt
PWM output mode
Note 1:
MPX: Multiplexer CMP: Comparator
Note 2:
When control input/output is used, I/O port setting should be set correctly. For details, refer to "2.2 I/O ports".
Figure 2.10.1 Timer/Counter 5 (TC5)
86FM48-89
2007-08-24
TMP86FM48 2.10.2 Control
The timer/counter 5 is controlled by a timer/counter 5 control register (TC5CR) and an 8-bit timer register 5 (TC5DR). Reset does not affect TC5DR.
TC5DR (0015H) R/W TC5CR (0014H) 7 6 5 4 3 2 1 0 (Initial value: 1111 1111)
7
6
5 TC5S
4
3 TC5CK
2
1 0 TC5M
(Initial value: **00 0000)
TC5S
TC5 start control
0: Stop and counter clear 1: Start NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 11 3 fs/2 fc/2 7 7 fc/2 fc/2 5 5 fc/2 fc/2 3 3 fc/2 fc/2 2 2 fc/2 fc/2 fc/2 fc/2 fc fc SLOW1/2, SLEEP1/2 mode 3 fs/2 - - - - - -
TC5CK
TC5 source clock select [Hz]
000 001 010 011 100 101 110 111
R/W
External clock (TC5 pin input)
00: Timer/event counter mode TC5M TC5 operating mode select 01: Reserved 10: Programmable divider output (PDO) mode 11: Pulse width modulation (PWM) output mode Note 1: Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Values to be loaded to the timer register must satisfy the following condition. 1 TC5DR 255 Note 3: When TC5 operation is started (TC5S = "0" "1") or TC5 operation is stopped (TC5S = "1" "0"), do not change TC5CR . Also, during TC5 operation (TC5S = "1" "1"), do not change TC5CR . Note 4: Available source clocks for each operation mode is referred to the following table.
Timer mode 000 001 010 TC5CK 011 100 101 110 111 Note 5: Note 6: Note 7:
Event counter mode
x x x x x x x
PDO mode
PWM mode
x x x

x x x x

x x x x x

x
The TC5S is automatically cleared to "0" after starting STOP mode. If a read instruction is executed for TC5CR, read data of bits 7 and 6 are unstable. During TC5 operation except PWM mode, do not change TC5DR.
Figure 2.10.2 Timer Register 5 and TC5 Control Register
86FM48-90
2007-08-24
TMP86FM48 2.10.3 Function
The timer/counter 5 has four operating modes: timer, event counter, programmable divider output, and PWM output mode. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC5DR is compared with the contents of up counter. If a match is found, an INTTC5 interrupt is generated and the up-counter is cleared to "0". Counting up resumes after the up-counter is cleared. Table 2.10.1 Source Clock (Internal clock) for Timer/Counter 5 (Example: at fc = 16 MHz)
NORMAL1/2, IDLE1/2 Mode DV7CK = 0 TC5CK Resolution [s] Maximum Time Setting [ms] 000 001 010 011 128.0 8.0 2.0 0.5 32.6 2.0 0.510 0.128 244.14 8.0 2.0 0.5 Resolution [s] DV7CK = 1 Maximum Maximum Time Setting [ms] 62.3 2.0 0.510 0.128 244.14 - - - 62.3 - - - Resolution [s] Time Setting [ms] SLOW1/2 Mode
(2) Event counter mode In this mode, events are counted on the rising edge of the TC5 pin input (External clock). The contents of the TC5DR is compared with the contents of the up counter. If a match is found, an INTTC5 interrupt is generated and the counter is cleared. Counting up resumes after the up counter is cleared. The minimum input pulse width of the TC5 pin is shown in Table 2.10.2. Two or more machine cycles are required for both the "H" and "L" levels of the pulse width. Match detect is executed on the falling edge of the TC5 pin. A match can not be detected and INTTC5 interrupt is not generated when the pulse is still in a falling state. Table 2.10.2 Timer/Counter 5 External Clock Source Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 Mode
"H" width "L" width 2 /fc 2 /fc
3 3
SLOW1/2, SLEEP1/2 Mode
2 /fs 2 /fs
3 3
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2007-08-24
TMP86FM48
(3) Programmable divider output (PDO) mode The programmable divider output (PDO) mode is intended to output a pulse having a duty cycle of about 50%. The counter counts up on an internal source clock. If the timer value matches TC5DR, the timer F/F5 is inverted, and the counter is cleared, generating an INTTC5 interrupt. The counter keeps counting up, and the timer F/F5 is inverted each time the timer value matches TC5DR. The P13 ( PDO5 ) pin outputs an inversion of the timer F/F5 output level. At a reset or when the timer stops, the timer F/F5 is cleared to "0". So, stopping the timer when the PDO output is low may cause the duty cycle to become smaller than the set value. To use the programmable divider output mode, set the output latch of the P13 port to "1".
Example: Output a 1024 Hz pulse (at fc = 16 MHz) LD SET LD LD (TC5CR), 00000110B (P1DR). 3 (TC5DR), 3DH (TC5CR), 00100110B ; ; ; ; Sets PDO mode (TC5M = 10, TC5CK = 001) P13 output latch 1 1/1024 / 2 /fc / 2 = 3DH
7
Starts TC5
Internal clock Up counter TC5DR Timer F/F5
PDO5 pin output
0
1 n
2
n0
1
2
n0
1
2
n0
1
2
n0
1
Match detect
INTTC5 interrupt
Figure 2.10.3 PDO Mode Timing Chart
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2007-08-24
TMP86FM48
(4) Pulse width modulation (PWM) output mode The pulse width modulation (PWM) output mode is intended to output pulses at constant intervals with a resolution of 8 bits. The counter counts up on the internal source clock. If the timer value matches TC5DR, the timer F/F5 is inverted, and the counter keeps-up counting. If an overflow is detected, the timer F/F5 is inverted again, generating an INTTC5 interrupt. The P13 ( PWM5 ) pin outputs an inversion of the timer F/F5 output level. At a reset or when the timer stops, the timer F/F5 is cleared to "0". So, stopping the timer when the PWM output is low may cause one cycle to become smaller than the set value. To use the pulse width modulation (PWM) output mode, set the output latch of the P13 port to "1". TC5DR is configured a 2-stage shift register and, during pulse width, will not switch until one output cycle is completed even if TC5DR is overwritten; therefore, pulse width can be altered continuously. Also, the first time, TC5DR is shifted by setting TC5CR to "1" after data are loaded to TC5DR. Note: In PWM mode, writing to the timer register TC5DR should be performed only right after an INTTC5 interrupt occurs (Usually, within the INTTC5 interrupt service routine). If writing to the timer register TC5DR occurs at the same timing as the INTTC5 interrupt, pulses having a value other than the set value may be output before another INTTC5 interrupt occurs, because an unstable value that is being written is shifted.
Internal clock Up counter TC5DR Timer F/F5
PWM pin output
0
1 n/n Match
n
n+1
FF
0
1 n/m Overwrite
n
n+1
FF
0
1 m/m Shift
m-1 m
INTTC5 interrupt 1 cycle
Figure 2.10.4 PWM Output Mode Timing Chart Table 2.10.3 PWM Output Mode (Example: fc = 16 MHz) TC5CK
000 001 010 011 100 101 110
NORMAL1/2, IDLE1/2 Mode Resolution [ns]
- - - 500 250 125 62.5
Repeat Cycle [s]
- - - 128 64 32 16
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2007-08-24
TMP86FM48
2.11 UART (Asynchronous serial interface)
The TMP86FM48 has 1 channel of UART (Asynchronous serial interface). The UART is connected to external devices via RXD and TXD. RXD is also used as P05; TXD, as P06. To use P05 or P06 as the RXD or TXD pin, set P0 port output latches to "1".
2.11.1 Configuration
UART control register 1 Transmit data buffer UARTCR1 TDBUF
Receive data buffer RDBUF
32 2
Shift register Parity bit Stop bit Shift register Receive control circuit Noise rejection circuit RXD
Transmit control circuit
INTTXD
INTRXD Y Transmit/receive clock MPX fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 INTTC5 fc/96 S A B CM DPY EX F G H M P X S 2 Counter UARTSR UART status register Baud rate generator 4 2 UARTCR2 UART control register 2 A B C fc/2 fc/2 fc/2
6 7 8
TXD
Figure 2.11.1 UART
86FM48-94
2007-08-24
TMP86FM48 2.11.2 Control
UART is controlled by the UART control registers (UARTCR1, UARTCR2). The operating status can be monitored using the UART status register (UARTSR).
UART control register UARTCR1 (1FDDH) 7 TXE 6 RXE 5 STBT 4 EVEN 3 PE 2 1 BRG 0: Disable 1: Enable 0: Disable 1: Enable 0: 1 bit 1: 2 bits 0: Odd-numbered parity 1: Even-numbered parity 0: No parity 1: Parity 000: fc/13 [Hz] 001: fc/26 010: fc/52 011: fc/104 100: fc/208 101: fc/416 110: TC5 (INTTC5) 111: fc/96 Write only 0 (Initial value: 0000 0000)
TXE RXE STBT EVEN PE
Transfer operation Receive operation Transmit stop bit length Even-numbered parity Parity addition
BRG
Transmit clock select
Note 1:
When operations are disabled by setting TXE and RXE bit to "0", the setting becomes valid when data transmit or receive complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted.
Note 2: Note 3:
The transmit clock and the parity are common to transmit and receive. UARTCR1 and UARTCR1 should be set to "0" before UARTCR1 is changed
UARTCR2 (1FDEH)
7
6
5
4
3
2
1
0
STOPBR (Initial value: **** *000)
RXDNC
RxDNC
Selection of RXD input noise rejection time
00: No noise rejection (Hysteresis input) 01: Rejects pulses shorter than 31/fc [s] as noise 10: Rejects pulses shorter than 63/fc [s] as noise 11: Rejects pulses shorter than 127/fc [s] as noise 0: 1 bit 1: 2 bits
Write only
STOPBR
Receive stop bit length
Note: When UARTCR2 = "01", pulses longer than 96/fc [s] are always regarded as signals; when UARTCR2 = "10", longer than 192/fc [s]; and when UARTCR2 = "11", longer than 384/fc [s]
Figure 2.11.2 UART Control Register
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2007-08-24
TMP86FM48
UARTSR (1FDDH)
7 PERR
6 FERR
5 OERR
4 RBFL
3 TEND
2 TBEP
1
0 (Initial value: 0000 11**)
PERR FERR OERR RBFL TEND TBEP
Parity error flag Framing error flag Overrun error flag Receive data buffer full flag Transmit end flag Transmit data buffer empty flag
0: No parity error 1: Parity error 0: No framing error 1: Framing error 0: No overrun error 1: Overrun error 0: Receive data buffer empty 1: Receive data buffer full 0: Transmitting 1: Transmit end 0: Transmit data buffer full 1: Transmit data buffer empty Read only
Note: When an INTTXD is generated TBEP is set to "1" automatically. UART receive data buffer 7 6 RDBUF (1FDFH) UART transmit data buffer 7 6 TDBUF (1FDFH)
5
4
3
2
1
0
Read only (Initial value: 0000 0000)
5
4
3
2
1
0
Write only (Initial value: 0000 0000)
Figure 2.11.3 UART Status Register and Data Buffer Registers
86FM48-96
2007-08-24
TMP86FM48 2.11.3 Transfer Data Format
In UART, a one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1), and parity (Select parity in UARTCR1; even- or odd-numbered parity by UARTCR1) are added to the transfer data. The transfer data formats are shown as follow. Table 2.11.1 Transfer Data Format Frame Length PE STBT 1
Start
2
Bit0
3
Bit1
8
Bit6
9
Bit7
10
Stop 1
11
12
0
0
0
1
Start
Bit0
Bit1
Bit6
Bit7
Stop 1
Stop 2
1
0
Start
Bit0
Bit1
Bit6
Bit7
Parity
Stop 1
1
1
Start
Bit0
Bit1
Bit6
Bit7
Parity
Stop 1
Stop 2
Note: In order to switch the transmit data format, perform transmit operations in the following sequence except for the initial setting. Without parity/1 STOP bit
With parity/1 STOP bit
Without parity/2 STOP bit
With parity/2 STOP bit
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2007-08-24
TMP86FM48 2.11.4 Transfer Rate
The baud rate of UART is set of UARTCR1. The example of the baud rate shown as follows. Table 2.11.2 Transfer Rate BRG
000 001 010 011 100 101
Source Clock 16 MHz
76800 [baud] 38400 19200 9600 4800 2400
8 MHz
38400 [baud] 19200 9600 4800 2400 1200
4 MHz
19200 [baud] 9600 4800 2400 1200 600
When TC5 is used as the UART transfer rate (when UARTCR1 = "110"), the transfer clock and transfer rate are determined as follows: Transfer clock = TC5 source clock TTREG5 set value Transfer rate = Transfer clock 16
2.11.5 Data Sampling
The UART receiver keeps sampling input using the clock selected by UARTCR1 until a start bit is detected in RXD pin input. RT clock starts detecting "L" level of the RXD pin. Once a start bit is detected, the start bit, data bits, stop bit (s), and parity bit are sampled at three times of RT7, RT8, and RT9 during one receiver clock interval (RT clock). (RT0 is the position where the bit supposedly starts). Bit is determined according to majority rule (The data are the same twice or more out of three samplings).
RXD pin RT0 RT clock Internal receive data
Start bit
Bit0 2 3 4 5 6 7 8 9 10 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
Start bit
Bit0 a) Without noise rejection circuit
RXD pin RT0 RT clock Internal receive data
Start bit
Bit0 2 3 4 5 6 7 8 9 10 11
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1
Start bit
Bit0 b) With noise rejection circuit
Figure 2.11.4 Data Sampling
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TMP86FM48 2.11.6 STOP Bit Length
Select a transmit stop bit length (1 or 2 bits) by UARTCR1.
2.11.7 Parity
Set parity/no parity by UARTCR1; set parity type (odd- or even-numbered) by UARTCR1.
2.11.8 Transmit/Receive
(1) Data transmit Set UARTCR1 to "1". Read UARTSR to check UARTSR = "1", then write data in TDBUF (Transmit data buffer). Writing data in TDBUF zero-clears UARTSR, transfers the data to the transmit shift register and the data are sequentially output from the TXD pin. The data output include a one-bit start bit, stop bits whose number is specified in UARTCR1 and a parity bit if parity addition is specified. Select the data transfer baud rate using bits 0 to 2 in UARTCR1. When data transmit starts, transmit buffer empty flag UARTSR is set to "1" and an INTTXD interrupt is generated. While UARTCR1 = "0" and from when "1" is written to UARTCR1 to when send data are written to TDBUF, the TXD pin is fixed at high level. When transmitting data, first read UARTSR, then write data in TDBUF. Otherwise, UARTSR is not zero-cleared and transmit does not start. (2) Data receive Set UARTCR1 to "1". When data are received via the RXD pin, the receive data are transferred to RDBUF (Receive data buffer). At this time, the data transmitted include a start bit and stop bit (s) and a parity bit if parity addition is specified. When stop bit (s) are received, data only are extracted and transferred to RDBUF (Receive data buffer). Then the receive buffer full flag UARTSR is set and an INTRXD interrupt is generated. Select the data transfer baud rate using bits 0 to 2 in UARTCR1. If an overrun error (OERR) occurs when data are received, the data are not transferred to RDBUF (Receive data buffer) but discarded; data in the RDBUF are not affected. Note: When a receive operation is disabled by setting UARTCR1 bit to "0", the setting becomes valid when data receive is completed. However, if a framing error occurs in data receive, the receive-disabling setting may not become valid. if a framing error occurs, be sure to perform a re-receive operation.
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TMP86FM48 2.11.9 Status Flag/Interrupt Signal
(1) Parity error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR is set to "1". The UARTSR is cleared to "0" when the RDBUF is read after reading the UARTSR.
RXD pin xxxx0**
Parity
Stop
Shift register
pxxxx0*
1pxxxx0
UARTSR
Reading UARTSR then RDBUF clears PERR.
INTRXD
Figure 2.11.5 Generation of Parity Error (2) Framing error When "0" is sampled as the stop bit in the receive data, framing error flag UARTSR is set to "1". The UARTSR is cleared to "0" when the RDBUF is read after reading the UARTSR.
RXD pin Final bit Stop
Shift register
xxx0**
xxxx0*
1xxxx0
UARTSR
Reading UARTSR then RDBUF clears FERR.
INTRXD
Figure 2.11.6 Generation of Framing Error
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(3) Overrun error When all bits in the next data are received while unread data are still in RDBUF, overrun error flag UARTSR is set to "1". In this case, the receive data is discarded; data in RDBUF are not affected. The UARTSR is cleared to "0" when the RDBUF is read after reading the UARTSR.
RBFL = "H" RXD pin Final bit Stop
Shift register
xxx0**
xxxx0*
1xxxx0
RDBUF
yyyy
UARTSR
Reading UARTSR then RDBUF clears OERR.
INTRXD
Figure 2.11.7 Generation of Overrun Error (4) Receive data buffer full Loading the received data in RDBUF sets receive data buffer full flag UARTSR. The UARTSR is cleared to "0" when the RDBUF is read after reading the UARTSR.
RXD pin Final bit Stop
Shift register
xxx0**
xxxx0*
1xxxx0
RDBUF
yyyy
xxxx
UARTSR
Reading UARTSR then RDBUF clears RBFL.
INTRXD
Figure 2.11.8 Generation of Receive Buffer Full
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(5) Transmit data buffer empty When no data is in the transmit buffer TDBUF, UARTSR is set to "1", that is, when data in TDBUF are transferred to the transmit shift register and data transmit starts, transmit data buffer empty flag UARTSR is set to "1". The UARTSR is cleared to "0" when the TDBUF is written after reading the UARTSR.
Data write TDBUF xxxx yyyy Data write zzzz
Shift register
*****1
1xxxx0
*1xxxx
****1x
*****1
1yyyy0
TXD pin
Start
Bit0
Final bit
Stop
Start
UARTSR After reading UARTSR, writing TDBUF clears TBEP.
INTTXD
Figure 2.11.9 Generation of Transmit Buffer Empty (6) Transmit end flag When data are transmitted and no data is in TDBUF (UARTSR = "1"), transmit end flag UARTSR is set to "1". The UARTSR is cleared to "0" the data transmit is stated after writing the TDBUF.
Transmit clock
Shift register
***1xx
****1x
*****1
1yyyy0
*1yyyy
TXD pin
Stop Data writing to TDBUF
Start
Bit0
UARTSR
UARTSR
INTTXD
Figure 2.11.10 Generation of Transmit Buffer Empty
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2.12 Serial Bus Interface (SBI-ver. D)
The TMP86FM48 has a 1-channel serial bus interface which employs an I2C bus (A bus system by Philips). The serial interface is connected to external devices through P51 (SDA) and P50 (SCL). The serial bus interface pins are also used for the P5 port. When used for serial bus interface pins, set the P5 output latches of these pins to "1". When not used as serial bus interface pins, the P5 port is used as a normal I/O port. Note 1: When P5 is used as serial bus interface pins, P50 and P51 should be set as a sink open drain output by clearing P5OUTCR to "0". Note 2: The serial bus interface can be used only in NORMAL1/2 and IDLE1/2 mode. It can not be used in IDLE0, SLOW1/2 and SLEEP0/1/2 mode. Note 3: The I2C of TMP86FM48 can be used only in the Standard mode of I2C. The fast mode and the high-speed mode can not be used.
2.12.1 Configuration
INTSBI interrupt request SCL fc/4 Divider Transfer control circuit Input/ output control P50 (SCL)
Noise canceller
I C bus clock sync. + control
2
Shift register
I C bus data control
2
Noise canceller
SDA
P51 (SDA)
SBICRB/ SBISR SBI control register B/ SBI status register
2
I2CAR I C bus address register
SBIDBR SBI data buffer register
SBICRA SBI control register A
Figure 2.12.1 Serial Bus Interface (SBI)
2.12.2 Control
The following registers are used for control the serial bus interface and monitor the operation status. * * * * * Serial bus interface control register A (SBICRA) Serial bus interface control register B (SBICRB) Serial bus interface data buffer register (SBIDBR) I2C bus address register (I2CAR) Serial bus interface status register (SBISR)
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TMP86FM48 2.12.3 Software Reset
A serial bus interface circuit has a software reset function, when a serial bus interface circuit is locked by an external noise, etc. To reset the serial bus interface circuit, write "01", "10" into the SWRST (Bit1, 0 in SBICRB).
2.12.4 The Data Format of the I2C Bus
The data format of the I2C bus is shown in as below.
(a) Addressing format 8 bits S Slave address 1 (b) Addressing format (with restart) 8 bits S Slave address 1 (c) Free data format 8 bits S Data 1 S: Start condition R/ W : Direction bit ACK: Acknowledge bit P: Stop condition 1 A C K 1 to 8 bits Data 1 A C K 1 or more 1 to 8 bits Data 1 A CP K 1 RA /C WK 1 to 8 bits Data 1 or more 1 A CS K 8 bits Slave address 1 1 RA /C WK 1 to 8 bits Data 1 or more 1 A CP K 1 RA /C WK 1 to 8 bits Data 1 A C K 1 or more 1 to 8 bits Data 1 A CP K
Figure 2.12.2 Data Format of I2C Bus
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TMP86FM48 2.12.5 I2C Bus Control
The following registers are used to control the serial bus interface (SBI) and monitor the operation status of the I2C bus.
Serial Bus Interface Control Register A 7 6 5 SBICRA (1FD9H) BC 4 ACK 3 2 1 SCK 0 (Initial value: 0000 *000)
BC
ACK
SCK
ACK = 0 ACK = 1 Number of Number of Bits Bits Clock Clock 000 8 8 9 8 001 1 1 2 1 Number of transferred bits 010 2 2 3 2 011 3 3 4 3 100 4 4 5 4 101 5 5 6 5 110 6 6 7 6 111 7 7 8 7 ACK Master mode Slave mode Not generate a clock pulse for Not count a clock pulse for Acknowledgement mode 0: an acknowledgement. an acknowledgement. specification Generate a clock pulse for an Count a clock pulse for an 1: acknowledgement. acknowledgement. n At fc = 8 MHz At fc = 4 MHz SCK At fc = 16 MHz 100.0 kHz Reserved Reserved 4 000: 55.6 kHz Reserved Reserved 5 Serial clock (fscl) selection 001: 29.4 kHz 58.8 kHz Reserved 6 010: (Output on SCL pin) 15.2 kHz 30.3 kHz 60.6 kHz 7 011: 7.7 kHz 15.4 kHz 30.8 kHz 8 100: n+1 [fscl = 1/(2 /fc + 8/fc)] 3.9 kHz 7.8 kHz 15.5 kHz 9 101: 1.9 kHz 3.9 kHz 7.8 kHz 10 110: 111: Reserved BC fc: High-frequency clock [Hz], *: Don't care Set the BC to "000" before switching to 8-bit SIO bus mode. SBICRA cannot be used with any of read-modify-write instructions such as bit manipulation, etc.
Write only
R/W
Write only
Note 1: Note 2: Note 3: Note 4:
This I C bus circuit does not support the Fast mode. It supports the Standard mode only. Although the I C bus circuit itself allows the setting of a baud rate over 100 kbps, the compliance with the I2C specification is not guaranteed in that case.
2
2
Serial Bus Interface Data Buffer Register 7 6 5 SBIDBR (1FDAH) Note 1: Note 2:
4
3
2
1
0 (Initial value: **** ****) R/W
For writing transmitted data, start from the MSB (Bit7). The data which was written into SBIDBR can not be read, since a write data buffer and a read buffer are independent in SBIDBR. Therefore, SBIDBR cannot be used with any of read-modify-write instructions such as bit manipulation, etc.
Note 3:
2
*: Don't care
I C bus Address Register 7 6 I2CAR (1FDBH) SA6 SA5 SA ALS Note 1: Note 2:
4 3 Slave address SA4 SA3 SA2
5
2 SA1
1 SA0
0 ALS (Initial value: 0000 0000)
Slave address selection Address recognition specification manipulation, etc. mode 0: Slave address recognition 1: Non slave address recognition
Write only
I2CAR is write-only register, which cannot be used with any of read-modify-write instruction such as bit Do not set I2CAR to "00H" to avoid the incorrect response of acknowledgment in slave mode. If "00H" is set to I2CAR as the Slave Address and received "01H" in slave mode, the device might transmit the acknowledgment incorrectly.
Figure 2.12.3
Serial Bus Interface Control Register A, Serial Bus Interface Data Buffer Register and I2C Bus Address Register
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Serial Bus Interface Control Register B 7 6 5 SBICRB (1FDCH) MST MST TRX BB PIN TRX BB
4 PIN
3 SBIM
2
1
0
SWRST1SWRST0 (Initial value: 0001 0000)
SBIM
0: 1: 0: Transmitter/receiver selection 1: 0: Start/stop generation 1: 0: Cancel interrupt service request 1: 00: Serial bus interface operating 01: 10: mode selection 11: Master/slave selection
Slave Master Receiver Transmitter Generate a stop condition when MST, TRX and PIN are "1" Generate a start condition when MST, TRX and PIN are "1" - Cancel interrupt service request Port mode (Serial bus interface output disable) Reserved 2 I C bus mode Reserved
Write only
SWRST1 SWRST0 Software reset start bit Note 1: Note 2: Note 3:
2
Software reset starts by first writing "10" and next writing "01"
Switch a mode to port after confirming that the bus is free. Switch a mode to I C bus mode after confiming that the port is high level. SBICRB has write-only register and must not be used with any of read-modify-write instructions such as bit manipulation, etc.
2
Note 4:
When the SWRST (Bit1, 0 in SBICRB) is written to "01", "10" in I C bus mode, software reset is occurred. In this case, the SBICRA, I2CAR and SBISR registers are initialized and the bits of SBICRB except the SBIM (Bit3, 2 in SBICRB) are also initialized.
Serial Bus Interface Status Register 7 6 5 SBISR (1FDCH) MST MST TRX BB PIN AL AAS AD0 LRB TRX BB
4 PIN
3 AL
2 AAS 0: Slave 1: Master 0: Receiver 1: Transmitter 0: Bus free 1: Bus busy
1 AD0
0 LRB (Initial value: 0001 0000)
Master/slave selection status monitor Transmitter/receiver selection status monitor Bus status monitor Interrupt service requests status monitor Arbitration lost detection monitor Slave address match detection monitor "GENERAL CALL" detection monitor Last received bit monitor
0: Requesting interrupt service 1: Releasing interrupt service request 0: - 1: Arbitration lost detected 0: Not detect slave address match or "GENERAL CALL" 1: Detect slave address match or "GENERAL CALL" 0: Not detect "GENERAL CALL" 1: Detect "GENERAL CALL" 0: Last receive bit is "0" 1: Last receiv bit is "1"
Read only
Figure 2.12.4 Serial Bus Interface Control Register B and Serial Bus Interface Status Register
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(1) Acknowledgement mode specification a. Acknowledgment mode (ACK = "1") To set the device as an acknowledgment mode, the ACK (Bit4 in SBICRA) should be set to "1". When a serial bus interface circuit is a master mode, an additional clock pulse is generated for an acknowledge signal. In a slave mode, a clock is counted for the acknowledge signal. In the master transmitter mode, the SDA pin is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle. In the master receiver mode, the SDA pin is set to low level generation an acknowledge signal during additional clock pulse cycle. In a slave mode, when a received slave address matches to a slave address which is set to the I2CAR or when a "GENERAL CALL" is received, the SDA pin is set to low level generating an acknowledge signal. After the matching of slave address or the detection of "GENERAL CALL", in the transmitter, the SDA pin is released in order to receive an acknowledge signal from the receiver during additional clock pulse cycle. In a receiver, the SDA pin is set to low level generation an acknowledge signal during additional clock pulse cycle after the matching of slave address or the detection of "GENERAL CALL" The Table 2.12.1 shows the SCL and SDA pins status in acknowledgment mode. Table 2.12.1 SCL and SDA Pins Status in Acknowledgement Mode Mode
Master
Pin
SCL SDA SCL
Transmitter
Released in order to receive an acknowledge signal.
Receiver
Set to low level generating an acknowledge signal Set to low level generating an acknowledge signal. Set to low level generating an acknowledge signal.
An additional clock pulse is generated.
A clock is counted for the acknowledge signal. - Released in order to receive an acknowledge signal.
Slave
SDA
When slave address matches or a general call is detected After matching of slave address or general call
b.
Non-acknowledgment mode (ACK = "0") To set the device as a non-acknowledgement mode, the ACK should be cleared to "0". In the master mode, a clock pulse for an acknowledge signal is not generated. In the slave mode, a clock for a acknowledge signal is not counted.
(2) Number of transfer bits The BC (Bits7 to 5 in SBICRA) is used to select a number of bits for next transmitting and receiving data. Since the BC is cleared to "000" as a start condition, a slave address and direction bit transmissions are always executed in 8 bits. Other than these, the BC retains a specified value. (3) Serial clock a. Clock source The SCK (Bits2 to 0 in SBICRA) is used to select a maximum transfer frequency output from the SCL pin in the master mode. Set a communication baud rate that meets the I2C bus specification, such as the shortest pulse width of tLOW, based on the equations shown below.
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Four or more machine cycles are required for both high and low levels of pulse width in the external clock which is input from SCL pin. Note: Since the I2C of TMP86FM48 can not be used as the fast mode and the high-speed mode, do not set SCK as the frequency that is over 100 kHz.
tHIGH tLOW 1/fscl
SCK (Bits2 to 0 in the SBICRA) tLOW = 2 /fc
n
n 4 5 6 7 8 9 10
tHIGH = 2 /fc + 8/fc
n
fscl = 1/(tLow + tHIGH) fc: High-frequency clock
000 001 010 011 100 101 110
tSCKL tSCKH tSCKL, tSCKH > 4 tcyc Note: tcyc = 4/fc (in NORMAL mode, IDLE mode)
Figure 2.12.5 Clock Source b. Clock synchronization In the I2C bus, in order to drive a bus with a wired AND, a master device which pulls down a clock pulse to low will, in the first place, invalidate a clock pulse of another master device which generates a high-level clock pulse. The serial bus interface circuit has a clock synchronization function. This function ensures normal transfer even if there are two or more masters on the same bus. The example explains clock synchronization procedures when two masters simultaneously exist on a bus.
SCL pin (Master 1) SCL pin (Master 2) SCL (Bus) a Count restart
Wait
Count start Count reset
b
c
Figure 2.12.6 Clock Synchronization As Master 1 pulls down the SCL pin to the low level at point "a", the SCL line of the bus becomes the low level. After detecting this situation, Master 2 resets counting a clock pulse in the high level and sets the SCL pin to the low level. Master 1 finishes counting a clock pulse in the low level at point "b" and sets the SCL pin to the high level. Since Master 2 holds the SCL line of the bus at the low level, Master 1 waits for counting a clock pulse in the high level. After Master 2 sets a clock pulse to the high level at point "c" and detects the SCL line of the bus at the high level, Master 1 starts counting a clock pulse in the high level. Then, the master, which has finished the counting a clock pulse in the high level, pulls
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down the SCL pin to the low level. The clock pulse on the bus is determined by the master device with the shortest high-level period and the master device with the longest low-level period from among those master devices connected to the bus. (4) Slave address and address recognition mode specification When the serial bus interface circuit is used with an addressing format to recognize the slave address, clear the ALS (Bit0 in I2CAR) to "0", and set the SA (Bits7 to 1 in I2CAR) to the slave address. When the serial bus interface circuit is used with a free data format not to recognize the slave address, set the ALS to "1". With a free data format, the slave address and the direction bit are not recognized, and they are processed as data from immediately after start condition. (5) Master/slave selection To set a master device, the MST (Bit7 in SBICRB) should be set to "1". To set a slave device, the MST should be cleared to "0". When a stop condition on the bus or an arbitration lost is detected, the MST is cleared to "0" by the hardware. (6) Transmitter/receiver selection To set the device as a transmitter, the TRX (Bit6 in SBICRB) should be set to "1". To set the device as a receiver, the TRX should be cleared to "0". When data with an addressing format is transferred in the slave mode, the TRX is set to "1" by a hardware if the direction bit (R/ W ) sent from the master device is "1", and is cleared to "0" by a hardware if the bit is "0". In the master mode, after an acknowledge signal is returned from the slave device, the TRX is cleared to "0" by a hardware if a transmitted direction bit is "1", and is set to "1" by a hardware if it is "0". When an acknowledge signal is not returned, the current condition is maintained. When a stop condition on the bus or an arbitration lost is detected, the TRX is cleared to "0" by the hardware. Table 2.12.2 shows TRX changing conditions in each mode and TRX value after changing. Table 2.12.2 TRX changing conditions in each mode Mode
Slave mode Master mode
Direction Bit
"0" "1" "0" "1"
Conditions
A received slave address is the same value set to I2CAR ACK signal is returned
TRX after Changing
"0" "1" "1" "0"
When a serial bus interface circuit operates in the free data format, a slave address and a direction bit are not recognized. They are handled as data just after generating a start condition. The TRX is not changed by a hardware.
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(7) Start/stop condition generation When the BB (Bit5 in SBISR) is "0", a slave address and a direction bit which are set to the SBIDBR are output on a bus after generating a start condition by writing "1" to the MST, TRX, BB and PIN. It is necessary to set transmitted data to the SBIDBR and set ACK to "1" beforehand.
SCL pin 1 A6 Start condition 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 9
SDA pin
R/ W Acknowledge signal
Slave address and the direction bit
Figure 2.12.7 Start Condition Generation and Slave Address Generation When the BB is "1", sequence of generating a stop condition is started by writing "1" to the MST, TRX and PIN, and "0" to the BB. Do not modify the contents of MST, TRX, BB and PIN until a stop condition is generated on a bus.
SCL pin SDA pin Stop condition
Figure 2.12.8 Stop Condition Generation When a stop condition is generated and the SCL line on a bus is pulled-down to low level by another device, a stop condition is generated after releasing the SCL line. The bus condition can be indicated by reading the contents of the BB (Bit5 in SBISR). The BB is set to "1" when a start condition on a bus is detected and is cleared to "0" when a stop condition is detected. (8) Interrupt service request and cancel When a serial bus interface circuit is in the master mode and transferring a number of clocks set by the BC and the ACK is complete, a serial bus interface interrupt request (INTSBI) is generated. In the slave mode, the conditions of generating INTSBI are follows: * At the end of acknowledge signal when the received slave address matches to the value set by the I2CAR * * At the end of acknowledge signal when a "GENERAL CALL" is received At the end of transferring or receiving after matching of slave address or receiving of "GENERAL CALL"
When a serial bus interface interrupt request occurs, the PIN (Bit4 in SBISR) is cleared to "0". During the time that the PIN is "0", the SCL pin is pulled-down to low level. Either writing data to SBIDBR or reading data from the SBIDBR sets the PIN to "1". The time from the PIN being set to "1" until the SCL pin is released takes tLOW. Although the PIN (Bit4 in SBICRB) can be set to "1" by the program, the PIN can not be cleared to "0" by the program. Note: If the arbitration lost occurs, when the slave address does not match, the PIN is not cleared to "0" even though INTSBI is generated.
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(9) Setting of I2C bus mode The SBIM (Bit3 and 2 in SBICRB) is used to set I2C bus mode. Set the SBIM to "10" in order to set I2C bus mode. Before setting of I2C bus mode, confirm serial bus interface pins in a high level, and then, write "10" to SBIM. And switch a port mode after confirming that a bus is free. (10) Arbitration lost detection monitor Since more than one master device can exist simultaneously on a bus, a bus arbitration procedure is implemented in order to guarantee the contents of transferred data. Data on the SDA line is used for bus arbitration of the I2C bus. The following shows an example of a bus arbitration procedure when two master devices exist simultaneously on a bus. Master 1 and Master 2 output the same data until point "a". After that, when Master 1 outputs "1" and Master 2 outputs "0", since the SDA line of a bus is wired AND, the SDA line is pulled-down to the low level by Master 2. When the SCL line of a bus is pulled-up at point "b", the slave device reads data on the SDA line, that is data in Master 2. Data transmitted from Master 1 becomes invalid. The state in Master 1 is called "arbitration lost". A master device which loses arbitration releases the SDA pin and the SCL pin in order not to effect data transmitted from other masters with arbitration. When more than one master sends the same data at the first word, arbitration occurs continuously after the second word.
SCL (Bus)
SDA pin (Master 1) SDA pin becomes "1" after losing arbitration. SDA pin (Master 2)
SDA (Bus) a b
Figure 2.12.9 Arbitration Lost The serial bus interface circuit compares levels of a SDA line of a bus with its SDA pin at the rising edge of the SCL line. If the levels are unmatched, arbitration is lost and the AL (Bit3 in SBISR) is set to "1". When the AL is set to "1", the MST and TRX are cleared to "0" and the mode is switched to a slave receiver mode. Thus, the serial bus interface circuit stops output of clock pulses during data transfer after the AL is set to "1". The AL is cleared to "0" by writing data to the SBIDBR, reading data from the SBIDBR or writing data to the SBICRB.
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SCL pin Master A SDA pin
1 D7A
2 D6A
3 D5A
4 D4A
5 D3A
6 D2A
7 D1A
8 D0A
9
1 D7A'
2 D6A'
3 D5A'
SCL pin Master B SDA pin
1 D7B
2 D6B
3
4
5
6
7
8
9
Stop clock output Releasing SDA pin and SCL pin to high level as losing arbitration.
AL
MST
TRX Accessed to SBIDBR or SBICRB INTSBI
Figure 2.12.10 Example of when a Serial Bus Interface Circuit is a Master B (11) Slave address match detection monitor In the slave mode, the AAS (Bit2 in SBISR) is set to "1" when the received data is "GENERAL CALL" or the received data matches the slave address setting by I2CAR with an address recognition mode (ALS = 0). When a serial bus interface circuit operates in the free data format (ALS = 1), the AAS is set to "1" after receiving the first 1-word of data. The AAS is cleared to "0" by writing data to the SBIDBR or reading data from the SBIDBR. (12) GENERAL CALL detection monitor The AD0 (Bit1 in SBISR) is set to "1" when all 8-bit received data is "0" immediately after a start condition in a slave mode. The AD0 is cleared to "0" when a start or stop condition is detected on a bus. (13) Last received bit monitor The SDA value stored at the rising edge of the SCL is set to the LRB (Bit0 in SBISR). In the acknowledge mode, immediately after an INTSBI interrupt request is generated, an acknowledge signal is read by reading the contents of the LRB.
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TMP86FM48 2.12.6 Data Transfer of I2C Bus
(1) Device initialization For initialization of device, set the ACK in SBICRA to "1" and the BC to "000". Specify the data length to 8 bits to count clocks for an acknowledge signal. Set a transfer frequency to the SCK in SBICRA. Next, set the slave address to the SA in I2CAR and clear the ALS to "0" to set an addressing format. After confirming that the serial bus interface pin is high level, for specifying the default setting to a slave receiver mode, clear "0" to the MST, TRX and BB in SBICRB, set "1" to the PIN, "10" to the SBIM, and "00" to bits SWRST1 and SWRST0. Note: The initialization of a serial bus interface circuit must be complete within the time from all devices which are connected to a bus have initialized to and device does not generate a start condition. If not, the data can not be received correctly because the other device starts transferring before an end of the initialization of a serial bus interface circuit.
(2) Start condition and slave address generation Confirm a bus free status (BB = 0). Set the ACK to "1" and specify a slave address and a direction bit to be transmitted to the SBIDBR. By writing "1" to the MST, TRX, BB and PIN, the start condition is generated on a bus and then, the slave address and the direction bit which are set to the SBIDBR are output. An INTSBI interrupt request occurs at the 9th falling edge of a SCL clock cycle, and the PIN is cleared to "0". The SCL pin is pulled-down to the low level while the PIN is "0". When an interrupt request occurs, the TRX changes by the hardware according to the direction bit only when an acknowledge signal is returned from the slave device. Note 1: Do not write a slave address to be output to the SBIDBR while data is transferred. If data is written to the SBIDBR, data to been outputting may be destroyed. Note 2: The bus free must be confirmed by software within 98.0 s (The shortest transmitting time according to the I2C bus standard) after setting of the slave address to be output. Only when the bus free is confirmed, set "1" to the MST, TRX, BB, and PIN to generate the start conditions. If the writing of slave address and setting of MST, TRX, BB and PIN doesn't finish within 98.0 s, the other masters may start the transferring and the slave address data written in SBIDBR may be broken.
SCL pin 1 2 3 4 5 6 7 8 9
SDA pin
A6 Start condition
A5
A4
A3
A2
A1
A0
R/ W Acknowledge signal from a slave device
Slave address + Direction bit
PIN INTSBI interrupt request
Figure 2.12.11 Start Condition Generation and Slave Address Transfer
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(3) 1-word data transfer Check the MST by the INTSBI interrupt process after an 1-word data transfer is completed, and determine whether the mode is a master or slave. a. When the MST is "1" (Master mode) Check the TRX and determine whether the mode is a transmitter or receiver. 1. When the TRX is "1" (Transmitter mode) Test the LRB. When the LRB is "1", a receiver does not request data. Implement the process to generate a stop condition (Described later) and terminate data transfer. When the LRB is "0", the receiver requests next data. When the next transmitted data is other than 8 bits, set the BC, set the ACK to "1", and write the transmitted data to the SBIDBR. After writing the data, the PIN becomes "1", a serial clock pulse is generated for transferring a next 1 word of data from the SCL pin, and then the 1 word of data is transmitted. After the data is transmitted, and an INTSBI interrupt request occurs. The PIN become "0" and the SCL pin is set to low level. If the data to be transferred is more than one word in length, repeat the procedure from the LRB test above.
Write to SBIDBR SCL pin 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 Acknowledge signal from a receiver 9
SDA pin
PIN
INTSBI interrupt request
Figure 2.12.12 Example of when BC = "000", ACK = "1" 2. When the TRX is "0" (Receiver mode) When the next transmitted data is other than of 8 bits, set the BC again. Set the ACK to "1" and read the received data from the SBIDBR (Reading data is undefined immediately after a slave address is sent). After the data is read, the PIN becomes "1". A serial bus interface circuit outputs a serial clock pulse to the SCL to transfer next 1-word of data and sets the SDA pin to "0" at the acknowledge signal timing. An INTSBI interrupt request occurs and the PIN becomes "0". Then a serial bus interface circuit outputs a clock pulse for 1-word of data transfer and the acknowledge signal each time that received data is read from the SBIDBR.
Read SBIDBR SCL pin 1 D7 2 3 4 5 6 7 8 9
SDA pin
D6
D5
D4
D3
D2
D1
D0
PIN
New D7 Acknowledge signal to a transmitter
INTSBI interrupt
Figure 2.12.13 Example of when BC = "000", ACK = "1"
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To make the transmitter terminate transmit, clear the ACK to "0" before reading data which is 1-word before the last data to be received. A serial bus interface circuit does not generate a clock pulse for the acknowledge signal by clearing ACK. In the interrupt routine of end of transmission, when the BC is set to "001" and read the data, PIN is set to "1" and generates a clock pulse for a 1-bit data transfer. In this case, since the master device is a receiver, the SDA line on a bus keeps the high-level. The transmitter receives the high-level signal as an ACK signal. The receiver indicates to the transmitter that data transfer is complete. After 1-bit data is received and an interrupt request has occurred, generates the stop condition to terminate transmit, generate the stop condition to terminate data transfer.
SCL pin 1 D7 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 1
SDA pin
Acknowledge signal sent to a transmitter
PIN
INTSBI interrupt request "0" ACK Read SBIDBR
"001" BC Read SBIDBR
Figure 2.12.14 Termination of Data Transfer in Master Receiver Mode b. When the MST is "0" (Slave mode) In the slave mode, a serial bus interface circuit operates either in normal slave mode or in slave mode after losing arbitration. In the slave mode, the conditions of generating INTSBI are follows: * * * When the received slave address matches to the value set by the I2CAR When a "GENERAL CALL" is received At the end of transferring or receiving after matching of slave address or receiving of "GENERAL CALL"
A serial bus interface circuit changes to a slave mode if arbitration is lost in the master mode. And an INTSBI interrupt request occurs when word data transfer terminates after losing arbitration. The behavior of INTSBI and PIN after losing arbitration are shown in Table 2.12.3. Table 2.12.3 The Behavior of INTSBI and PIN after Losing Arbitration
When the Arbitration Lost Occurs during Transmission of Slave Address as a Master INTSBI PIN When the Arbitration Lost Occurs during Transmission of Data as a Master Transmit Mode
INTSBI is generated at the termination of word data. When the slave address matches the value set by PIN keeps "1". I2CAR, the PIN is cleared to "0" by generating of INTSBI. When the slave address doesn't match the value set by I2CAR, the PIN keeps "1".
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Check the AL (Bit3 in the SBISR), the TRX (Bit6 in the SBISR), the AAS (Bit2 in the SBISR), and the AD0 (Bit1 in the SBISR) and implements processes according to conditions listed in Table 2.12.4. Table 2.12.4 Operation in the Slave Mode TRX
1
AL
1
AAS
1
AD0
0
Conditions
A serial bus interface circuit loses arbitration when transmitting a slave address. And receives a slave address of which the value of the direction bit sent from another master is "1". In the slave receiver mode, a serial bus interface circuit receives a slave address of which the value of the direction bit sent from the master is "1". In the slave transmitter mode, 1-word data is transmitted.
Process
Set the number of bits in 1 word to the BC and write transmitted data to the SBIDBR.
0
1
0
0
0
0
1
1
1/0
0
0
0
1
1/0
A serial bus interface circuit loses arbitration when transmitting a slave address. And receives a slave address of which the value of the direction bit sent from another master is "0" or receives a "GENERAL CALL". A serial bus interface circuit loses arbitration when transmitting a slave address or data. And terminates transferring word data. In the slave receiver mode, a serial bus interface circuit receives a slave address of which the value of the direction bit sent from the master is "0" or receives "GENERAL CALL". In the slave receiver mode, a serial bus interface circuit terminates receiving of 1-word data.
Test the LRB. If the LRB is set to "1", set the PIN to "1" since the receiver does not request next data. Then, clear the TRX to "0" to release the bus. If the LRB is set to "0", set the number of bits in 1 word to the BC and write transmitted data to the SBIDBR since the receiver requests next data. Read the SBIDBR for setting the PIN to "1" (Reading dummy data) or write "1" to the PIN.
A serial bus interface circuit is changed to slave mode. To clear AL to "0", read the SBIDBR or write the data to SBIDBR. Read the SBIDBR for setting the PIN to "1" (Reading dummy data) or write "1" to the PIN.
0
1/0
Set the number of bits in 1-word to the BC and read received data from the SBIDBR.
Note: In the slave mode, if the slave address set in I2CAR is "00000000B", the TRX changes to "1" by receiving the start byte data "00000001B". (4) Stop condition generation When the BB is "1", a sequence of generating a stop condition is started by setting "1" to the MST, TRX and PIN, and clear "0" to the BB. Do not modify the contents of the MST, TRX, BB, PIN until a stop condition is generated on a bus. When a SCL line on a bus is pulled-down by other devices, a serial bus interface circuit generates a stop condition after they release a SCL line.
"1" MST "1" TRX "0" BB "1" PIN SCL pin SDA pin
Stop condition
PIN BB (Read)
Figure 2.12.15 Stop Condition Generation
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(5) Restart Restart is used to change the direction of data transfer between a master device and a slave device during transferring data. The following explains how to restart a serial bus interface circuit. Clear "0" to the MST, TRX and BB and set "1" to the PIN. The SDA pin retains the high-level and the SCL pin is released. Since a stop condition is not generated on a bus, a bus is assumed to be in a busy state from other devices. Test the BB until it becomes "0" to check that the SCL pin a serial bus interface circuit is released. Test the LRB until it becomes "1" to check that the SCL line on a bus is not pulled-down to the low level by other devices. After confirming that a bus stays in a free state, generate a start condition with procedure (2). In order to meet setup time when restarting, take at least 4.7 s of waiting time by software from the time of restarting to confirm that a bus is free until the time to generate a start condition. Note: When restarting after receiving in master recever mode, because the device doesn't send an acknowledgment as a last data, the level of SCL line can not be confirmed by reading LRB. Therefore, confirm the status of SCL line by reading P5PRD register.
"0" MST "0" TRX "0" BB "1" PIN "1" MST "1" TRX "1" BB "1" PIN 4.7 s (Min) SCL (Bus) SCL pin SDA (Pin) LRB BB PIN Start condition
Figure 2.12.16 Timing Diagram when Restarting
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2.13 SIO (Synchronous Serial Interface)
The TMP86FM48 contains two channels of SIO (Synchronous serial interface). These serial interfaces connect to an external device via SI1, SI2, SO1, SO2, SCK1 and SCK2 pins. The SI1, SI2, SO1, SO2, SCK1 and SCK2 pins respectively are shared with P05, P11, P06, P10, P07 and P12. When these pins are used as serial interface, the output latches for each port of P0 and P1 must be set to "1". Because SIO1 and SIO2 are the same except that the registers and the function pin for each SIO are assigned as different specification, explanation here is made of only SIO1. The registers for SIO1 and SIO2 are listed in Table below. Table 2.13.1 The Registers for SIO1 and SIO2 SIO1 Register
SIO control register SIO status register SIO receive buffer register SIO transmit buffer register SIO1CR SIO1SR SIO1RDB SIO1TDB
SIO2 Address
0017H 0018H 0019H 0019H
Register
SIO2CR SIO2SR SIO2RDB SIO2TDB
Address
001BH 001CH 001DH 001DH
2.13.1
Configuration
Internal data bus
SIO1CR
SIO1SR SIO1TDB
Shift clock Control circuit MSB/LSB selection
Shift register on transmitter Port (Note) Port (Note) Shift register on receiver SO1 pin (Serial data output) SI1 pin (Serial data input)
SIO1RDB
To BUS INTSIO1 Internal clock interrupt input Note:
Port (Note)
SCK1 pin
Set the register of port correctly for the port assigned as serial interface pins. For details, see the description of the input/output port control register.
Figure 2.13.1 Synchronous Serial Interface
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TMP86FM48 2.13.2 Control
The SIO is controlled using the serial interface control register (SIO1CR). The operating status of the serial interface can be inspected by reading the status register (SIO1SR).
Serial Interface Control Register 1 7 SIO1CR (0017H) 6 5 SIOM 4 3
SIODIR
2
1 SCK
0 (Initial value: 0000 0000)
SIOS SIOINH
SIOS SIOINH
Specify start/stop of transfer Forcibly stops transfer (Note 1)
0: 1: 0: 1:
Stop Start - Forcibly stop (Automatically cleared to "0" after stopping)
00: Transmit mode SIOM Selects transfer mode 01: Receive mode 10: Transmit/receive mode 11: Reserved SIODIR Selects direction of transfer 0: 1: MSB (Transfer beginning with bit7) LSB (Transfer beginning with bit0) NORMAL 1/2 or IDLE 1/2 mode SLOW/SLEEP TBTCR TBTCR mode = "0" = "1" 12 4 4 fc/2 fs/2 fs/2 8 8 fc/2 fc/2 Reserved 7 7 fc/2 fc/2 Reserved 6 6 fc/2 fc/2 Reserved 5 5 fc/2 fc/2 Reserved 4 4 fc/2 fc/2 Reserved 3 3 fc/2 fc/2 Reserved External clock (input from SCK1 pin) R/W
SCK
Selects serial clock
000 001 010 011 100 101 110 111
Note 1:
When SIO1CR is set to "1", SIO1CR, SIO1SR register, SIO1RDB register and STOTDB register are initialized.
Note 2:
Transfer mode, direction of transfer and serial clock must be select during the transfer is stopping (when SIO1SR = "0").
Note 3:
fc: High frequency clock [Hz], fs: Low frequency clock, *: Don't care
Figure 2.13.2 Serial Interface Control Register
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Serial Interface Status Register 7 6 5 SIO1SR SIOF SEF TXF (0018H)
4 RXF
3
2
1
0 (Initial value: 0010 00**)
TXERR RXERR
SIOF SEF TXF RXF
Serial transfer operation status monitor Number of clocks monitor Transmit buffer empty flag Receive buffer full flag
0: 1: 0: 1: 0: 1: 0: 1: 0:
Transfer finished Transfer in progress 8 clocks 1 to 7 clocks Data exists in transmit buffer No data exists in transmit buffer No data exists in receive buffer Data exists in receive buffer - (No error exist) Read only
Read 1: Transmit buffer under run occurs in an external clock mode. Write 0: 1: 0: RXERR Receive operation error flag Clear the flag - (A write of "1" to this bit is ignored) - (No error exist) R/W
TXERR
Transfer operation error flag
Read 1: Receive buffer over run occurs in an external clock mode. Write 0: 1: Note 1: Clear the flag - (A write of "1" to this bit is ignored)
The operation error flag (TXERR and RXERR) are not automatically cleared by stopping transfer with SIO1CR = "0". Therefore, set these bits to "0" for clearing these error flag. Or set SIO1CR to "1".
Note 2:
*: Don't care
Figure 2.13.3 Serial Interface Status Register
Receive buffer register 7 6 SIO1RDB (0019H) Transmit buffer register 7 6 SIO1TDB (0019H)
5
4
3
2
1
0
Read only (Initial value: 0000 0000)
5
4
3
2
1
0
Write only (Initial value: **** ****)
Note 1:
SIO1TDB is write only register. A bit manipulation should not be performed on the transmit buffer register using a read-modify-write instruction. The SIO1TDB should be written after checking SIO1SR = "1". When SIO1SR is "0", the writing data can't be transferred to SIO1TDB even if write instruction is executed to SIO1TDB.
Note 2:
Note 3:
*: Don't care
Figure 2.13.4 Receive Buffer Register and Transmit Buffer Register
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TMP86FM48 2.13.3 Functional Description
(1) Serial clock a. Clock source The serial clock can be selected by using SIO1CR. When the serial clock is changed, the writing instruction to SIO1CR should be executed while the transfer is stopped (when SIO1SR = "0"). 1. Internal clock Setting the SIO1CR to other than "111" outputs the clock (Shown in Table 2.8.2) as serial clock outputs from SCK1 pin. At the before beginning or finishing of a transfer, SCK1 pin is kept in high level. When writing (in the transmit mode) or reading (in the receive mode) data can not follow the serial clock rate, an automatic-wait function is executed to stop the serial clock automatically and hold the next shift operation until reading or writing is completed. The maximum time from releasing the automatic-wait function by reading or writing a data is 1 cycle of the selected serial clock until the serial clock comes out from SCK1 pin.
SIO1CR
SCK1 pin output
Automatic wait
SO1 pin SIO1TDB A
A7 A6 A5 A4 A3 A2 A1
A0
B7 B6 B5 B4 B3 B2 B1 B0 B
Automatic wait is released by writing SIO1TDB.
Figure 2.13.5 Automatic-wait Function (Example of transmit mode) Table 2.13.2 Serial Clock Rate (fc = 16 MHz, fs = 32.768kHz) NORMAL1/2, IDLE1/2 Mode TBTCR = "0" Serial Clock
000 001 010 011 100 101 110 fc/2
12 8 7 6 5 4 3
TBTCR = "1" Serial Clock
fs/2 fc/2 fc/2 fc/2 fc/2 fc/2 fc/2
4 8 7 6 5 4 3
SLOW1/2, SLEEP1/2 Mode Serial Clock
fs/2
4
Baud Rate
3.906 kbps 62.5 125 250 500 kbps kbps kbps kbps
Baud Rate
2048 125 250 500 bps kbps kbps kbps
Baud Rate
2048 bps - - - - - -
fc/2 fc/2 fc/2 fc/2 fc/2 fc/2
62.5 kbps
Reserved Reserved Reserved Reserved Reserved Reserved
1.00 Mbps 2.00 Mbps
1.00 Mbps 2.00 Mbps
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2. External clock When an external clock is selected by setting SIO1CR to "111", the clock via the SCK1 pin from an external source is used as the serial clock. To ensure shift operation, the serial clock pulse width must be 4/fc or more for both "H" and "L" levels.
SCK1 pin
VIL TSCKL
VIH TSCKH TSCKL, TSCKH 4/fc
Figure 2.13.6 External Clock b. Shift edges The leading edge is used to transmit data, and the trailing edge is used to receive data. 1. Leading edge shift Data is shifted on leading edges of the serial clock (Falling edges of the SCK1 pin input/output). 2. Trailing edge shift Data is shifted on trailing edges of the serial clock (Rising edges of the SCK1 pin input/output).
SIO1CR
SCK1 pin
Shift register SO1 pin
01234567 *0123456 **012345 ***01234 ****0123 *****012 ******01 *******0 ********* Shift out Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
(a) Leading edge shift (Example of MSB transfer) SIO1CR
SCK1 pin
SI1 pin Shift register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
********* 7******* 67****** 567***** 4567**** 34567*** 234567** 1234567* 01234567 (b) Trailing edge shift (Example of MSB transfer)
Figure 2.13.7 Shift Edge
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(2) Transfer bit direction Transfer data direction can be selected by using SIO1CR. The transfer data direction can't be set individually for transmit and receive operations. When the data direction is changed, the writing instruction to SIO1CR should be executed while the transfer is stopped (when SIO1SR = "0").
SIO1CR
SCK1 pin
SIO1TDB SO1 pin
A Shift out A7 A6 A5 A4 A3 A2 A1 A0
(a) MSB transfer SIO1CR
SCK1 pin
SIO1TDB SO1 pin
A Shift out A0 A1 A2 A3 A4 A5 A6 A7
(b) LSB transfer
Figure 2.13.8 Transfer Bit Direction (Example of transmit mode) a. Transmit mode 1. MSB transmit mode MSB transmit mode is selected by setting SIO1CR to "0", in which case the data is transferred sequentially beginning with the most significant bit (Bit7). 2. LSB transmit mode LSB transmit mode is selected by setting SIO1CR to "1", in which case the data is transferred sequentially beginning with the least significant bit (Bit0). b. Receive mode 1. MSB receive mode MSB receive mode is selected by setting SIO1CR to "0", in which case the data is received sequentially beginning with the most significant bit (Bit7). 2. LSB receive mode LSB receive mode is selected by setting SIO1CR to "1", in which case the data is received sequentially beginning with the least significant bit (Bit0). c. Transmit/receive mode 1. MSB transmit/receive mode MSB transmit/receive mode are selected by setting SIO1CR to "0" in which case the data is transferred sequentially beginning with the most significant bit (Bit7) and the data is received sequentially beginning with the most significant (Bit7).
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2. LSB transmit/receive mode LSB transmit/receive mode are selected by setting SIO1CR to "1", in which case the data is transferred sequentially beginning with the least significant bit (Bit0) and the data is received sequentially beginning with the least significant (Bit0).
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(3) Transfer modes Transmit, receive and transmit/receive mode are selected by using SIO1CR. a. Transmit mode Transmit mode is selected by writing "00" to SIO1CR. 1. Starting the transmit operation Transmit mode is selected by setting "00" to SIO1CR. Serial clock is selected by using SIO1CR. Transfer direction is selected by using SIO1CR. When a transmit data is written to the transmit buffer register (SIO1TDB), SIO1SR is cleared to "0". After SIO1CR is set to "1", SIO1SR is set synchronously to "1" the falling edge of SCK1 pin. The data is transferred sequentially starting from SO1 pin with the direction of the bit specified by SBIDIR, synchronizing with the SCK1 pin's falling edge. SIO1SR is kept in high level, between the first clock falling edge of SCK1 pin and eighth clock falling edge. SIO1SR is set to "1" at the rising edge of SCK1 pin after the data written to the SIO1TDB is transferred to shift register, then the INTSIO1 interrupt request is generated, synchronizing with the next falling edge on SCK1 pin. Note 1: In internal clock operation, when SIO1CR is set to "1", transfer mode does not start without writing a transmit data to the transmit buffer register (SIO1TDB). Note 2: In internal clock operation, when the SIO1CR is set to "1", SIO1TDB is transferred to shift register after maximum 1-cycle of serial clock frequency, then a serial clock is output from SCK1 pin. Note 3: In external clock operation, when the falling edge is input from SCK1 pin after SIO1CR is set to "1", SIO1TDB is transferred to shift register immediately. 2. During the transmit operation When data is written to SIO1TDB, SIO1SR is cleared to "0". In internal clock operation, in case a next transmit data is not written to SIO1TDB, the serial clock stops to "H" level by an automatic-wait function when all of the bit set in the SIO1TDB has been transmitted. Automatic-wait function is released by writing a transmit data to SIO1TDB. Then, transmit operation is restarted after maximum 1-cycle of serial clock. When the next data is written to the SIO1TDB before termination of previous 8-bit data with SIO1SR = "1", the next data is continuously transferred after transmission of previous data. In external clock operation, after SIO1SR is set to "1", the transmit data must be written to SIO1TDB before the shift operation of the next data begins. If the transmit data is not written to SIO1TDB, transmit error occurs immediately after shift operation is started. Then, INTSIO1 interrupt request is generated after SIO1SR is set to "1".
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3. Stopping the transmit operation There are two ways for stopping transmits operation. * The way of clearing SIO1CR. When SIO1CR is cleared to "0", transmit operation is stopped after all transfer of the data is finished. When transmit operation is finished, SIO1SR is cleared to "0" and SO1 pin is kept in high level. In external clock operation, SIO1CR must be cleared to "0" before SIO1SR is set to "1" by beginning next transfer. * The way of setting SIO1CR. Transmit operation is stopped immediately after SIO1CR is set to "1". In this case, SIO1CR, SIO1SR register, SIO1RDB register and SIO1TDB register are initialized.
Clearing SIOS SIO1CR SIO1SR SIO1SR
SCK1 pin
Start shift operation
Start shift operation
Start shift operation
Automatic wait
output SO1 pin SIO1SR INTSIO1 interrupt request SIO1TDB A B C
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Writing transmit data A
Writing transmit data B
Writing transmit data C
Figure 2.13.9 Example of Internal Clock and MSB Transmit Mode
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Writing transmit data SIO1CR SIO1SR SIO1SR
SCK1 pin
Clearing SIOS
Start shift operation
Start shift operation
Start shift operation
input SO1 pin SIO1SR INTSIO1 interrupt request SIO1TDB A B C
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Writing transmit data A
Writing transmit data B
Writing transmit data C
Figure 2.13.10 Example of External Clock and MSB Transmit Mode
SCK1 pin
SIO1SR SO1 pin TSODH 4/fc TSODH 8/fc
Figure 2.13.11 Hold Time of the End of Transmit Mode
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4. Transmit error processing Transmit errors occur on the following situation. * Shift operation starts before writing next transmit data to SIO1TDB in external clock operation. If transmit errors occur during transmit operation, SIO1SR is set to "1" immediately after starting shift operation. Synchronizing with the next serial clock falling edge, INTSIO1 interrupt request is generated. If shift operation starts before writing data to SIO1TDB after SIO1CR is set to "1", SIO1SR is set to "1" immediately after shift operation is started and then INTSIO1 interrupt request is generated. SO1 pin is kept in high level when SIO1SR is set to "1". When transmit error occurs, transmit operation must be forcibly stop by writing SIO1CR to "1". In this case, SIO1CR, SIO1SR register, SIO1RDB register and SIO1TDB register are initialized.
SIO1CR SIO1SR SIO1SR
SCK1 pin
Start shift operation
Start shift operation
Start shift operation
Input SO1 pin TXF SIO1SR INTSIO1 interrupt request SIO1TDB A Writing transmit data A B Writing transmit data B Unknown
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
SIO1CR
Figure 2.13.12 Example of Transmit Error Processing
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b.
Receive mode The receive mode is selected by writing "01" to SIO1CR. 1. Starting the receive operation Receive mode is selected by setting "01" to SIO1CR. Serial clock is selected by using SIO1CR. Transfer direction is selected by using SIO1CR. After SIO1CR is set to "1", SIO1SR is set synchronously to "1" the falling edge of SCK1 pin. Synchronizing with the SCK1 pin's rising edge, the data is received sequentially from SI1 pin with the direction of the bit specified by SBIDIR. SIO1SR is kept in high level, between the first clock falling edge of SCK1 pin and eighth clock falling edge. When 8-bit data is received, the data is transferred to SIO1RDB from shift register. INTSIO1 interrupt request is generated and SIO1SR is set to "1". Note: In internal clock operation, when the SIO1CR is set to "1", the serial clock is generated from SCK1 pin after maximum 1-cycle of serial clock frequency. 2. During the receive operation The SIO1SR is cleared to "0" by reading a data from SIO1RDB. In the internal clock operation, the serial clock stops to "H" level by an automatic-wait function when the all of the 8-bit data has been received. Automatic-wait function is released by reading a received data from SIO1RDB. Then, receive operation is restarted after maximum 1-cycle of serial clock. In external clock operation, after SIO1SR is set to "1", the received data must be read from SIO1RDB before the next data shift-in operation is finished. If received data is not read out from SIO1RDB, receive error occurs immediately after shift operation is finished. Then INTSIO interrupt request is generated after SIO1SR is set to "1". 3. Stopping the receive operation There are two ways for stopping the receive operation. * The way of clearing SIO1CR. When SIO1CR is cleared to "0", receive operation is stopped after all of the data is finished to receive. When receive operation is finished, SIO1SR is cleared to "0". In external clock operation, SIO1CR must be cleared to "0" before SIO1SR is set to "1" by starting the next shift operation. * The way of setting SIO1CR. Receive operation is stopped immediately after SIO1CR is set to "1". In this case, SIO1CR, SIO1SR register, SIO1RDB register and SIO1TDB register are initialized.
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Clearing SIOS SIO1CR SIO1SR SIO1SR
SCK1 pin Automatic wait A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Start shift operation
Start shift operation
Start shift operation
output SI1 pin SIO1SR INTSIO1 interrupt request SIO1RDB
A Reading received data A
B Reading received data B
C Reading received data C
Figure 2.13.13 Example of Internal Clock and MSB Receive Mode
Reading received data SIO1CR SIO1SR SIO1SR
SCK1 pin
Clearing SIOS
Start shift operation
Start shift operation
Start shift operation
input SI1 pin SIO1SR INTSIO1 interrupt request SIO1RDB A Reading received data A B Reading received data B C Reading received data C
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Figure 2.13.14 Example of External Clock and MSB Receive Mode
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4. Receive error processing Receive errors occur on the following situation. To protect SIO1RDB and the shift register contents, the received data is ignored while the SIO1SR is "1". * Shift operation is finished before reading out received data from SIO1RDB at SIO1SR is "1" in an external clock operation. If receive error occurs, set the SIOCR1 to "0" for reading the data that received immediately before error occurence. And read the data from SIO1RDB. Data in shift register (at errors occur) can be read by reading the SIO1RDB again. When SIO1SR is cleared to "0" after reading the received data, SIO1SR is cleared to "0". After clearing SIO1CR to "0", when 8-bit serial clock is input to SCK1 pin, receive operation is stopped. To restart the receive operation, confirm that SIO1SR is cleared to "0". If the receive error occurs, set the SIOCR1 to "1" for stopping the receive operation immediately. In this case, SIO1CR, SIO1SR register, SIO1RDB register and SIO1TDB register are initialized.
SIO1CR SIO1SR SIO1SR
SCK1 pin
Start shift operation
Start shift operation
Start shift operation
input SI1 pin SIO1SR SIO1SR INTSIO1 interrupt request SIO1RDB A B Reading received data A Reading received data B Write a "0" after reading the received data when a receive error occurs.
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
Figure 2.13.15 Example of Receive Error Processing Note: If receive error is not corrected, an interrupt request does not generate after the error occurs.
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c. Transmit/receive mode The transmit/receive mode are selected by writing "10" to SIO1CR. 1. Starting the transmit/receive operation Transmit/receive mode is selected by writing "10" to SIO1CR. Serial clock is selected by using SIO1CR. Transfer direction is selected by using SIO1CR. When a transmit data is written to the transmit buffer register (SIO1TDB), SIO1SR is cleared to "0". After SIO1CR is set to "1", SIO1SR is set synchronously to the falling edge of SCK1 pin. The data is transferred sequentially starting from SO1 pin with the direction of the bit specified by SIO1CR, synchronizing with the SCK1 pin's falling edge. And receiving operation also starts with the direction of the bit specified by SIO1CR, synchronizing with the SCK1 pin's rising edge. SIO1SR is kept in high level between the first clock falling edge of SCK1 pin and eighth clock falling edge. SIO1SR is set to "1" at the rising edge of SCK1 pin after the data written to the SIO1TDB is transferred to shift register. When 8-bit data has been received, the received data is transferred to SIO1RDB from shift register, then the INTSIO1 interrupt request occurs, synchronizing with setting SIO1SR to "1". Note 1: In internal clock operation, when the SIO1CR is set to "1", SIO1TDB is transferred to shift register after maximum 1-cycle of serial clock frequency, then a serial clock is output from SCK1 pin. In external clock operation, when the falling edge is input from SCK1 pin after SIO1CR is set to "1", SIO1TDB is transferred to shift register immediately. When the rising edge is input from SCK1 pin, receive operation also starts.
Note 2:
2. During the transmit/receive operation When data is written to SIO1TDB, SIO1SR is cleared to "0" and when a data is read from SIO1RDB, SIO1SR is cleared to "0". In internal clock operation, in case of the condition described below, the serial clock stops to "H" level by an automatic-wait function when all of the bit set in the data has been transmitted. * * * Next transmit data is not written to SIO1TDB after reading a received data from SIO1RDB Received data is not read from SIO1RDB after writing a next transmit data to SIO1TDB Neither SIO1TDB nor SIO1RDB is accessed after transmission. The automatic wait function is released by writing the next transmit data to SIO1TDB after reading the received data from SIO1RDB, or reading the received data from SIO1RDB after writing the next data to SIO1TDB. Then, transmit/receive operation is restarted after maximum 1 cycle of serial clock.
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In external clock operation, reading the received data from SIO1RDB and writing the next data to SIO1TDB must be finished before the shift operation of the next data begins. If the transmit data is not written to SIO1TDB after SIO1SR is set to "1", transmit error occurs immediately after shift operation is started. When the transmit error occurred, SIO1SR is set to "1". If received data is not read out from SIO1RDB before next shift operation starts after setting SIO1SR to "1", receive error occurs immediately after shift operation is finished. When the receive error has occurred, SIO1SR is set to "1".
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3. Stopping the transmit/receive operation There are two ways for stopping the transmit/receive operation. * The way of clearing SIO1CR. When SIO1CR is cleared to "0", transmit/receive operation is stopped after all transfer of the data is finished. When transmit/receive operation is finished, SIO1SR is cleared to "0" and SO1 pin is kept in high level. In external clock operation, SIO1CR must be cleared to "0" before SIO1SR is set to "1" by beginning next transfer. * The way of setting SIO1CR. Transmit/receive operation is stopped immediately after SIO1CR is set to "1". In this case, SIO1CR, SIO1SR register, SIO1RDB register and SIO1TDB register are initialized.
Clearing SIOS SIO1CR SIO1SR SIO1SR
SCK1 pin
Start shift operation
Start shift operation
Start shift operation
output SO1 pin SI1 pin INTSIO1 interrupt request TXF SIO1TDB A Writing transmit data A SIO1SR SIO1RDB
A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1
Automatic wait A0 D0 B7 B6 B5 B4 B3 B2 B1 E7 E6 E5 E4 E3 E2 E1
Automatic wait B0 E0 C7 C6 C5 C4 C3 C2 C1 C0 F7 F6 F5 F4 F3 F2 F1 F0
B Writing transmit data B Writing transmit data C
C
D Reading received data D Reading received data E
E
F Reading received data F
Figure 2.13.16 Example of Internal Clock and MSB Transmit/Receive Mode
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Reading received data Writing transmit data SIO1CR SIO1SR SIO1SR
SCK1 pin
Clearing SIOS
Start shift operation
Start shift operation
Start shift operation
input SO1 pin SI1 pin INTSIO1 interrupt request SIO1SR SIO1TDB A Writing transmit data A SIO1SR SIO1RDB D Reading received data D E Reading received data E F Reading received data F B Writing transmit data B C Writing transmit data C
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0
Figure 2.13.17 Example of External Clock and MSB Transmit/Receive Mode
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4. Transmit/receive error processing Transmit/receive errors occur on the following situation. Corrective action is different, which errors occur transmits or receives. Transmit errors Transmit errors occur on the following situation. * Shift operation starts before writing next transmit data to SIO1TDB in external clock operation. If transmit errors occur during transmit operation, SIO1SR is set to "1" immediately after starting shift operation. And INTSIO1 interrupt request is generated after all of the 8-bit data has been received. If shift operation starts before writing data to SIO1TDB after SIO1CR is set to "1", SIO1SR is set immediately after starting shift operation. And INTSIO1 interrupt request is generated after all of the 8-bit data has been received. SO1 pin is kept in high level when SIO1SR is set to "1". When transmit error occurs, transmit operation must be forcibly stop by writing SIO1CR to "1" after the received data is read from SIO1RDB. In this case, SIO1CR, SIO1SR register, SIO1RDB register and SIO1TDB register are initialized.
SIO1CR SIO1SR SIO1SR
SCK1 pin
Start shift operation
Start shift operation
Start shift operation
input SO1 pin SI1 pin INTSIO1 interrupt request SIO1SR SIO1SR SIO1TDB A B Writing transmit data B Unknown
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0
Writing transmit data A SIO1SR SIO1RDB
D Reading received data D
E Reading received data E
F Reading received data F
SIO1CR
Figure 2.13.18 Example of Transmit/Receive (Transmit) Error Processing
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Receive errors Receive errors occur on the following situation. To protect SIO1RDB and the shift register contents, the received data is ignored while the SIO1SR is "1". * Shift operation is finished before reading out received data from SIO1RDB at SIO1SR is "1" in an external clock operation. If receive error occurs, set the SIO1CR to "0" for reading the data that received immediately before error occurence. And read the data from SIO1RDB. Data in shift register (at errors occur) can be read by reading the SIO1RDB again. When SIO1SR is cleared to "0" after reading the received data, SIO1SR is cleared to "0". After clearing SIO1CR to "0", when 8-bit serial clock is input to SCK1 pin, receive operation is stopped. To restart the receive operation, confirm that SIO1SR is cleared to "0". If the received error occurs, set the SIO1CR to "1" for stopping the receive operation immediately. In this case, SIO1CR, SIO1SR register, SIO1RDB register and SIO1TDB register are initialized.
SIO1CR SIO1SR SIO1SR
SCK1 pin
Start shift operation
Start shift operation
Start shift operation
input SO1 pin SI1 pin INTSIO1 interrupt request SIO1SR SIO1TDB A Writing transmit data A SIO1SR SIO1SR Write a "0" after reading the received data when a receive mode error occurs. SIO1RDB D E Reading received data D SIO1CR FFH Reading received data E B Writing transmit data B C Writing transmit data C Unknown
A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 D7 D6 D5 D4 D3 D2 D1 D0 E7 E6 E5 E4 E3 E2 E1 E0 F7 F6 F5 F4 F3 F2 F1 F0
Figure 2.13.19 Example of Transmit/Receive (Receive) Error Processing Note: If receive error is not corrected, an interrupt request does not generate after the error occurs.
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SCK1 pin
SIO1SR SO1 pin TSODH 4/fc TSODH 8/fc
Figure 2.13.20 Hold Time of the End of Transmit/Receive Mode
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2.14 Key-On Wake-Up (KWU)
In the TMP86FM48, the STOP mode must be released by not only P20 ( INT5 / STOP ) pin but also P64 to P67 pins. When the STOP mode is released by P64 to P67 pins, the P20 ( INT5 / STOP ) pin needs to be used.
2.14.1 Configuration
Stop mode control INT5 Stop mode release signal (1: Release) P20 ( INT5 / STOP )
P67 (AIN07/STOP3) P66 (AIN06/STOP2) P65 (AIN05/STOP1) P64 (AIN04/STOP0)
STOP0EN
STOP1EN
STOP2EN
STOPCR (1FFEH)
Figure 2.14.1 Key-On Wake-Up Circuit Note1: STOP pin doesn't have the control register such as STOPCR, so when STOP mode is relesed by STOPx (x: 0 to 3), STOP pin should be used as STOP function.
STOP3EN
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TMP86FM48 2.14.2 Control
P64 to P67 (STOP0 to STOP3) pin can controlled by key-on wake-up control register (STOPCR). It can be configured as enable/disable in 1-bit unit. STOP mode can be entered by setting up the system control register1 (SYSCR1), and can be exited by detecting low level of STOP0 to STOP3 pins, which are enabled by STOPCR, for releasing STOP mode (Note 1). Also, because each level of the STOP0 to STOP3 can be confirmed by reading P6DR, check all STOP0 to STOP3 pins that is enabled by STOPCR before the STOP mode is started (Note 2, 3). Note 1: When the STOP mode is used by edge-sensitive mode (SYSCR1 = "0"), all bit of STOPCR (STOP3EN to STOP0EN) should be cleared to "0". Note 2: When the STOP pin input is high or STOP0 to STOP3 pin input which is enabled by STOPCR is low, executing an instruction which starts STOP mode will not place in STOP mode but instead will immediately start the release sequence (Warm-up). Note 3: When confirms the level of STOP0 to STOP3 pin which is enabled by STOPCR, the corresponding bit of P6CR1 should be cleared to "0" before reading P6DR. Table 2.14.1 Input Edge (Level) of Stop Mode Release Terminal name
STOP STOP0 STOP1 STOP2 STOP3
As both terminal
P20/ INT5 P64/AIN04 P65/AIN05 P66/AIN06 P67/AIN07
SYSCR1 = "1"
"H" level (Note2) "L" level (Note 2)
SYSCR1 = "0"
Rising edge Do not use key on wake up function (Note 1)
Release edge (Level)
Key-On Wake-Up Control Register STOPCR (1FFEH) 7 6 5 4 3 - 2 - 1 - 0 - (Initial value: 0000 ****)
STOP0EN STOP1EN STOP2EN STOP3EN
STOP0EN STOP1EN STOP2EN STOP3EN
Stop mode released by P64 port Stop mode released by P65 port Stop mode released by P66 port Stop mode released by P67 port
0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable Write only
Figure 2.14.2 Key-On Wake-Up Control Register
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2.15 10-Bit AD Converter (ADC)
The TMP86FM48 has a 10-bit successive approximation type AD converter.
2.15.1 Configuration
The circuit configuration of the 10-bit AD converter is shown in Figure 2.15.1. It consists of control registers ADCCR1 and ADCCR2, registers ADCDR1 and ADCDR2, a DA converter, a sample-and-hold circuit, a comparator, and a successive comparison circuit.
DA converter VAREF AVDD R/2 R Reference voltage R/2 VSS
Analog input multiplexer AIN00 AIN01 ~ A B ~ Y
Sample hold circuit
10 G H I J ~ ~ 4 SAIN AINDS ADRS ADCCR1 IREFON 2 AMD ADCCR2 ACK 3 ADCDR1 ADCDR2 8 2 EOCF ADBF Analog comparator Shift clock Control circuit INTADC Successive approximate circuit
AIN06 AIN07 AIN10 AIN11
AIN16 AIN17
OS P EN
AD converter control register1, 2
AD conversion result register
Figure 2.15.1 AD Converter (ADC)
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TMP86FM48 2.15.2 Register Configuration
The AD converter consists of the following four registers: * * * AD converter control register 1 (ADCCR1) AD converter control register 2 (ADCCR2) AD conversion result register 1/2 (ADCDR1/ADCDR2)
(1) AD converter control register 1 (ADCCR1) This register selects the analog channels and operation mode (Software start or repeat) in which to perform AD conversion and controls the AD converter as it starts operating. (2) AD converter control register 2 (ADCCR2) This register selects the AD conversion time and controls the connection of the DA converter (Ladder resistor network). (3) AD conversion result register (ADCDR1) This register is used to store the digital value (Bit9 to bit2) after being converted by the AD converter. (4) AD conversion result register (ADCDR2) This register is used to store the digital value (Bit1 and bit0) after being converted by the AD converter, and then this register is also used to monitor the operating status of the AD converter. The AD converter control register configurations are shown in Figure 2.15.2 and Figure 2.15.3.
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AD Converter Control Register 1 ADCCR1 7 6 (000EH) ADRS AMD
5
4 AINDS
3
2 SAIN 0: 1: 00: 01: 10: 11: 0: 1: 0000: 0001: 0010: 0011: 0100: 0101: 0110: 0111:
1
0 (Initial value: 0001 0000)
ADRS
AD conversion start
AMD
AD operating mode
AINDS
Analog input control
SAIN
Analog input channel select
- Start AD operation disable Software start mode Reserved Repeat mode Analog input enable Analog input disable Selects AIN00 Selects AIN01 Selects AIN02 Selects AIN03 Selects AIN04 Selects AIN05 Selects AIN06 Selects AIN07
1000: Selects AIN10 1001: Selects AIN11 1010: Selects AIN12 1011: Selects AIN13 1100: Selects AIN14 1101: Selects AIN15 1110: Selects AIN16 1111: Selects AIN17
R/W
Note 1: Note 2: Note 3: Note 4: Note 5:
Select analog input when AD converter stops (ADCDR2 = "0"). When the analog input is all use disabling, the AINDS should be set to "1". During conversion, do not perform output instruction to maintain a precision for all of the pins. And port near to analog input, do not input intense signaling of change. The ADRS is automatically cleared to "0" after starting conversion. Do not set ADRS newly again during AD conversion. Before setting ADRS newly again, check ADCDR2 to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling routine).
Note 6:
After STOP or SLOW mode are started, AD converter control register 1 (ADCCR1) is all initialized. Therefore, set the ADCCR1 newly again after exiting these modes.
AD Converter Control Register 2 ADCCR2 7 6 (000FH)
5 IREFON
4 "1"
3
2 ACK
1
0 "0" (Initial value: **00 0000)
IREFON
DA converter (Ladder resistor) connection control
ACK
AD conversion time select
Inputting current to the ladder resistor 0: Connected only during AD conversion 1: Always connected Conversion fc = fc = fc = fc = ACK time 16 MHz 8 MHz 4 MHz 1 MHz 000 39/fc 39.0 s - - - 001 Reserved 010 78/fc 78.0 s - - - 011 156/fc 39.0 s 156.0 s - - 100 312/fc 39.0 s 78.0 s - - 101 624/fc 39.0 s 78.0 s 156.0 s - 110 1248/fc 78.0 s 156.0 s - - 111 Reserved
R/W
Note 1: Note 2:
Settings for "-" in the above table are inhibited. Set conversion time by analog reference voltage (VAREF) as follows. VAREF = 2.7 to 3.6 V (31.2 or more) VAREF = 1.8 to 3.6 V (124.8 or more)
Note 3: Note 4: Note 5: Note 6:
Always set bit0 in ADCCR2 to "0" and set bit4 in ADCCR2 to "1". When a read instruction for ADCCR2, bit6 to 7 in ADCCR2 read in as undefined data. fc: High-frequency clock [Hz] After STOP or SLOW mode are started, AD converter control register 2 (ADCCR2) is all initialized. Therefore, set the ADCCR2 newly again after exiting these modes.
Figure 2.15.2 AD Converter Control Register
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AD Conversion Result Register ADCDR1 7 6 (0027H) ADCDR2 (0026H) AD09 7 AD01 AD08 6 AD00
5 AD07 5 EOCF
4 AD06 4 ADBF
3 AD05 3
2 AD04 2
1 AD03 1
0 AD02 0 (Initial value: 0000 ****) (Initial value: 0000 0000)
EOCF ADBF Note 1:
AD conversion end flag AD conversion busy flag
0: 1: 0: 1:
Before or during conversion Conversion completed During stop of AD conversion During AD conversion
Read only
The EOCF is cleared to "0" when reading the ADCDR1. Therefore, the AD conversion result should be read to ADCDR2 more first than ADCDR1.
Note 2:
ADBF is set to "1" when AD conversion starts and cleared to "0" when the AD conversion is finished. It also is cleared upon entering STOP or SLOW mode.
Note 3:
If a read instruction is executed for ADCDR2, read data of bit 3 to 0 are unstable.
Figure 2.15.3 AD Converter Result Register
2.15.3 AD Converter Operation
(1) Set up the AD converter control register 1 (ADCCR1) as follows: * * * Choose the channel to AD convert using AD input channel select (SAIN). Specify analog input enable for analog input control (AINDS). Specify AMD for the AD converter control operation mode (Software or repeat mode).
(2) Set up the AD converter control register 2 (ADCCR2) as follows: * * Set the AD conversion time using AD conversion time (ACK). For details on how to set the conversion time, refer to Note 2 for AD converter control register 2. Choose IREFON for DA converter control.
(3) After setting up (1) and (2) above, set AD conversion start (ADRS) of AD converter control register 1 (ADCCR1) to "1". (4) After an elapse of the specified AD conversion time, the AD converted value is stored in AD conversion result register 1 (ADCDR1), AD conversion result register (ADCDR2) and then the AD conversion end flag (EOCF) of AD conversion result register 2 (ADCDR2) is set to "1", upon which time AD conversion interrupt INTADC is generated. (5) EOCF is cleared to "0" by a read of the conversion result. However, if reconverted before a register read, although EOCF is cleared the previous conversion result is retained until the next conversion is completed.
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TMP86FM48 2.15.4 AD Converter Operation Modes
There are following two AD converter operation modes: * * Software start: AD conversion is performed once by setting AMD to "01B" and ADRS to "1". Repeat mode: AD conversion is performed repeatedly by setting AMD to "11B" and ADRS to "1".
(1) Software start mode After setting ADCCR1 to "01" (Software start mode), set ADCCR1 to "1". AD conversion of the voltage at the analog input pin specified by ADCCR1 is thereby started. After completion of the AD conversion, the conversion result is stored in AD conversion result registers (ADCDR1, ADCDR2) and at the same time ADCDR2 is set to "1", the AD conversion finished interrupt (INTADC) is generated. ADCCR1 is automatically cleared to "0" after AD conversion has started. Do not set ADCCR1 newly again (Restart) during AD conversion. Before setting ADCCR1 newly again, check ADCDR2 to see that the conversion is completed or wait until the interrupt signal (INTADC) is generated (e.g., interrupt handling routine).
ADCCR1 ADCDR2 ADCDR1, ADCDR2 Indeterminate First conversion result Second conversion result AD conversion start AD conversion start
ADCDR2 INTADC request Reading ADCDR1 Reading ADCDR2 Conversion result read Conversion result read
Figure 2.15.4 Operation in Software Start Mode
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Example: After selecting the conversion time of 39.0 s at 16 MHz and the analog input channel AIN3 pin, perform AD conversion once. After checking EOCF, read the converted value, store the lower 2 bits in address 009EH and store the upper 8 bits in address 009FH on RAM. The operation mode is software start mode. ; AIN SELECT LD (P6CR1), 00000000B LD (P6CR2), 00000000B LD (ADCCR1), 00100011B LD (ADCCR2), 11011010B ; AD CONVERT START SET (ADCCR1). 7 TEST (ADCDR2). 5 JRS T, SLOOP ; RESULT DATA READ LD A, (ADCDR2) LD (9EH), A LD A, (ADCDR1) LD (9FH), A
; ; ; ;
P6CR1 bit 3 = 0 P6CR2 bit 3 = 0 Select AIN3 Select conversion time (624/fc) and operation mode ADRS = 1 EOCF = 1 ?
SLOOP:
; ;
(2) Repeat mode AD conversion of the voltage at the analog input pin specified by ADCCR1 is performed repeatedly. In this mode, AD conversion is started by setting ADCCR1 to "1" after setting ADCCR1 to "11". After completion of the AD conversion, the conversion result is stored in AD conversion result registers (ADCDR1, ADCDR2) and at the same time ADCDR2

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