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| DF6811CPU 8-bit FAST Microcontrollers Family ver 2.17 OVERVIEW Document contains brief description of DF6811CPU core functionality. The DF6811CPU is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. DF6811CPU soft core is binarycompatible with the industry standard 68HC11 8-bit microcontroller and can achieve a performance 45-100 million instructions per second. There are two configurations of DF6811CPU: Harvard where data and program buses are separated, and von Neumann with common program and data bus DF6811CPU has FAST architecture that is 4.4 times faster compared to original implementation. Self-monitoring circuitry is included on-chip to protect against system errors. An illegal opcode detection circuit provides a nonmaskable interrupt when illegal opcode detected. Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6811CPU IP Core especially attractive for automotive and battery-driven applications. The DF6811CPU have built in the development support features designed into DF6811. The LIR signal is intended as a debugging aid. This signal is driven to active low for the first bus cycle of each new instruction, making it easy to reverse assemble (disassemble) instructions from the display of a logic analyzer. All trademarks mentioned in this document are trademarks of their respective owners. DF6811CPU is fully customizable, which means it is delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow. CPU FEATURES FEATURES FAST architecture, 4,4 times faster than the original implementation Software compatible with industry standard 68HC11 Configurable Harvard or Von Neumann architectures 10 times faster multiplication 16 times faster division 256 bytes of remapped System Function Registers space (SFRs) Up to 16M bytes of Data Memory De-multiplexed Address/Data Bus to allow easy connection to memory Two power saving modes: STOP, WAI Ready pin allows Core to operate with slow program and data memories Fully synthesizable, static synchronous design with no internal tri-states http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. No internal reset generator or gated clock Scan test ready Technology independent HDL source code Core can be fully customized 1 GHz virtual clock frequency compared to original implementation DoCDTM on Chip Debugger Processor execution control Read, write all processor contents Hardware execution breakpoints Three wire communication interface DELIVERABLES Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment Active-HDL automatic simulation macros ModelSim automatic simulation macros Tests with reference responses Technical documentation Installation notes HDL core specification Datasheet Synthesis scripts Example application Technical support IP Core implementation support 3 months maintenance DESIGN FEATURES ONE GLOBAL SYSTEM CLOCK SYNCHRONOUS RESET The DF6811 has 3 reset vectors sources, which easy identify a cause of system reset. ALL ASYNCHRONOUS INPUT SIGNALS ARE SYNCHRONIZED BEFORE INTERNAL USE Delivery the IP Core updates, minor and major versions changes Delivery the documentation updates Phone & email support CONFIGURATION The following parameters of the DF6811CPU core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code. TM * DoCD Hardware Debugger DATA MEMORY: The DF6811 can address up to 16M bytes of Data Memory via the function interconnect signals. The 256 bytes of Data Memory in every 64k page is reserved for the Function Registers. Extra DPP (Data Page Pointer) register is used for segments swapping. Data Memory can be implemented as synchronous or asynchronous RAM. SYSTEM FUNCTION REGISTERS: - used unused Harvard Von Neumann Synchronous Asynchronou 64 kB 16 MB used unused used unused used unused used unused * Architecture type * Memories type * Data Memory size * Data Memory wait-states * Power saving STOP mode * Support for DIV Instructions * Support for MUL Instruction Up to 256 System Function Registers(SFRs) may be implemented to the DF6811 design. SFRs are memory mapped into Data Memory within any 64k bytes address space. PROGRAM MEMORY: Up to 64kB of Program Memory may be implemented to the DF6811 design. Program Memory can be implemented as synchronous or asynchronous ROM. All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. LICENSING Comprehensible and clearly defined licensing methods without royalty fees make using of IP Core easy and simply. Single Design license allows use IP Core in single FPGA bitstream and ASIC implementation. Unlimited Designs, One Year licenses allow use IP Core in unlimited number of FPGA bitstreams and ASIC implementations. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction except One Year license where time of use is limited to 12 months. Single Design license for VHDL, Verilog source code called HDL Sour- SYMBOL clk por cmf prgdata(7:0) ready datai(7:0) prgaddr(15:0) prgoe datao(7:0) addr(23:0) ramwe ramoe ufraddr(7:0) ufrwe ufroe lir halt docddatao docdclk prgwe ufrdatai(7:0) irq xirq clkdocd docddatai DoCD TM ce Encrypted, or plain text EDIF called Netlist Interface One Year license for Encrypted Netlist only PINS DESCRIPTION PIN clk por cmf prgdata[7:0] ready datai[7:0] ufrdatai[7:0] irq xirq prgaddr[15:0] prgoe datao[7:0] addr[23:0] ramwe ramoe ufraddr[7:0] ufrwe ufroe lir halt clkdocd docddatai docddatao docdclk prgwe ACTIVE Low Low Low Low Low Low Low Low Low Low High TYPE input input input input input input input input input output output output output output output output output output output output input input output output output DESCRIPTION Global system clock Power on Reset indicator Clock Monitor Fail Reset ID Program memory bus input Non-maskable interrupt input External memory bus input UFRs data bus input Ready pin for CODE & DATA Non-maskable interrupt input Program memory address bus Program memory output enable Data memory & UFR bus output Data memory address bus Data memory write enable Data memory output enable FR address bus UFRs write enable UFRs output enable Load instruction register Halt clock system (STOP inst.) Separate DoCD DoCD DoCD DoCD DoCD TM TM TM TM TM Unlimited Designs license for HDL Source Netlist Upgrade from HDL Source to Netlist Single Design to Unlimited Designs Clock input serial Data input Serial Data Output Serial Clock Output Program Memory Write * Kind of activity is configurable All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. BLOCK DIAGRAM Control Unit - Performs the core synchronization and data flow control. This module manages execution of all instructions. The Control Unit also manages execution of STOP instruction and waking-up the processor from the STOP mode. Opcode Decoder - Performs an instruction opcode decoding and the control functions for all other blocks. ALU - Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG), and related logic like arithmetic unit, logic unit, multiplier and divider. Bus Controller - Program Memory, Data Memory & SFR's (Special Function Register) interface controls access into the program and data memories and special registers. It contains Program Counter (PC), Stack Pointer (SP) register, INIT register (INIT), Data Page Pointer (DPP), Stretch register (ST) and related logic. clk por cmf Opcode Decoder intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used. OPTIONAL MODULES There are also available an optional peripherals, not included in presented DF6811CPU Microcontroller Core. The optional peripherals, can be implemented in microcontroller core upon customer request. Four 8-bit I/O Ports Interrupt Controller 20 interrupt sources 17 priority levels Dedicated Interrupt vector for each interrupt prgdata(7:0) prgaddr(15:0) prgoe datao(7:0) BUS Controller halt lir Control Unit irq xirq Interrupt Controller datai(7:0) addr(23:0) ramwe ramoe ufrdatai(7:0) ufraddr(7:0) ufrwe ufroe ready source Main16-bit timer/counter system 16 bit free running counter Four stage programmable prescaller Timer clocked by internal source Real Time Interrupt clkdocd docddatai docddatao docdclk prgwe DoCD Debugger TM ALU Interrupt Controller - DF6811CPU has implemented only an external interrupts from pins IRQ and XIRQ. The interrupts are activated at low level (XIRQ,IRQ pins) or falling edge (IRQ pin) and are sampled each 1 system clock at the rising edge of CLK. DoCD - Debug Unit - it's a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCDTM provides nonAll trademarks mentioned in this document are trademarks of their respective owners. TM 16-bit Compare/Capture Unit Three independent input-capture functions Five output-compare channels Events capturing Pulses generation Digital signals generation Gated timers Sophisticated comparator http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. Pulse width modulation Pulse width measuring NORMAL speed 100 kbs FAST speed 400 kbs HIGH speed 3400 kbs Wide range of system clock frequencies User defined data setup time on I2C lines Interrupt generation 8-bit Pulse accumulator Two major modes of operation Simple event counter Gated time accumulation Clocked by internal source or external pin Programmable Watchdog Timer Fixed-Point arithmetic coprocessor Multiplication - 16bit * 16bit Division - 32bit / 16bit Division - 16bit / 16bit Left and right shifting - 1 to 31 bits Normalization Full-duplex UART - SCI Standard Nonreturn to Zero format (NRZ) 8 or 9 bit data transfer Integrated baud rate generator Enhanced receiver data sampling technique Noise, Overrun and Framing error detection IDLE and BREAK characters generation Wake-up block to recognize UART wake-up from IDLE condition Three SCI related interrupts Floating-Point arithmetic coprocessor IEEE-754 standard single precision FADD, FSUB - addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM - compare FCHS - change sign FABS - absolute value SPI - Master and Slave Serial Peripheral Interface Supports speeds up 1/4 of system clock Software selectable polarity and phase of se- rial clock SCK System errors detection Allows operation from a wide range of system clock frequencies (build-in 5-bit timer) Interrupt generation Floating-Point math coprocessor - IEEE754 standard single precision real, word and short integers FADD, FSUB- addition, subtraction FMUL, FDIV- multiplication, division FSQRT- square root FUCOM- compare FCHS - change sign FABS - absolute value FSIN, FCOS- sine, cosine FTAN, FATAN - tangent arcs tangent PWM - Pulse Width Modulation Timer 4 independent 8-bit PWM channels, concate- nated on two 16-bit PWM channel Software-selectable duty from 0% to 100% and pulse period Software-selectable polarity of output wave- form I2C bus controller - Master 7-bit and 10-bit addressing modes NORMAL, FAST, HIGH speeds Multi-master systems supported Clock arbitration and synchronization User defined timings on I2C lines Wide range of system clock frequencies Interrupt generation I2C bus controller - Slave All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. PERFORMANCE The following table gives a survey about the Core area and performance in the ALTERA(R) devices after Place & Route: Speed Logic Cells Fmax grade CYCLONE -6 1834 58 MHz STRATIX -5 1834 60 MHz MERCURY -5 1808 61 MHz APEX II -7 1849 50 MHz APEX20KC -7 1809 46 MHz APEX20KE -1 1809 42 MHz ACEX1K -1 1785 34 MHz FLEX10KE -1 1785 32 MHz Core performance in ALTERA(R) devices Device IMPROVEMENT For user the most important is application speed improvement. The most commonly used arithmetic functions and theirs improvement are shown in table below. Improvement was computed as {M68HC11 clock periods} divided by {DF6811CPU clock periods} required to execute an identical function. More details are available in core documentation. Function 8-bit addition (immediate data) 8-bit addition (direct addressing) 8-bit addition (indirect addressing) 8-bit subtraction (immediate data) 8-bit subtraction (direct addressing) 8-bit subtraction (indirect addressing) 16-bit addition (immediate data) 16-bit addition (direct addressing) 16-bit addition (indirect addressing 16-bit subtraction (immediate data) 16-bit subtraction (direct addressing) 16-bit subtraction (indirect addressing Multiplication Fractional division Integer division Improvement 4 4 4 4 4 4 5,3 5 4,8 5,3 5 4,8 10 14,9 16.4 DF68XX FAMILY OVERVIEW The main features of each DF68XX family member have been summarized in table below. It gives a briefly member characterization helping user to select the most suitable IP Core for its application. User can specify its own peripheral set (including listed below and the others) and requests the core modifications. Paged Data Memory space READY for Prg. and Data memories Main Timer System Real Time Interrupt Speed acceleration Pulse accumulator Design DF6805 DF6808 DF6811 DF6811CPU 4.1 3.2 4.4 4.4 64k 64k 64k 64k 64k 64k 16M 16M - 7 7 20 3 7 7 17 3 + 1* 1* * * * * 2/2* 2/2* 5/3* + 1* 1* 1* + * * * + 4 4 4 + + * + + * * * * + 6 700 8 900 12 000 6 500 DF68XX family of High Performance Microcontroller Cores + optional * configurable All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. Size - ASIC gates Compare\Capture SPI M/S Interface Motorola Memory Expansion Logic Interrupt sources DoCD Debugger Watchdog Timer Interface for additional SFRs Physical Linear memory space Interrupt levels Data Pointers SCI (UART) I\O Ports CONTACTS For any modification or special request please contact to Digital Core Design or local distributors. Headquarters: Wroclawska 94 41-902 Bytom, POLAND n fo @ d c d .p l e-mail: iinfo@dcd.pl tel. fax : +48 32 282 82 66 : +48 32 282 74 37 Distributors: http://www.dcd.pl/apartn.php Please check http://www.dcd.pl/apartn.php All trademarks mentioned in this document are trademarks of their respective owners. http://www.DigitalCoreDesign.com http://www.dcd.pl Copyright 1999-2007 DCD - Digital Core Design. All Rights Reserved. |
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