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16 Bit Microcontroller
TLCS-900/L1 Series
TMP91FW60FG TMP91FW60DFG
Revision 1.9
TOSHIBA CORPORATION
The information contained herein is subject to change without notice. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.
(c) 2007 TOSHIBA CORPORATION All Rights Reserved
Revision History Date
2006/2/28 2006/3/06 2006/3/13 2006/8/04
Revision
0.1 0.2 0.3 1.4 TENTATIVE Flash section is corrected. Correction of a clerical error. P99 Figure 5-3 is corrected. P99 Figure 5-4 is deleted. P272 The value is added to T.B.D of Specification section. P126 Figure 7-1 P132-133 TMRB Mode register TA1OUT of TB3MOD and TB4MOD is corrected. TA1OUT -> TA3OUT, TA5OUT P226 Table 14-6 is corrected P178 9.3.3.14 The description is corrected.
2006/10/31
1.5
SCOUT: System clock output fFPH -> fSYS DC SPEC VIH/VIL is corrected. Table 2-8 Sample Warm-up Times after Clearance of STOP Mode is corrected. Table 4-2 I/O Port Setting List is corrected. PORT 3, 4, 7 control register/function register contrast table is corrected. 1.1 Features Interrupts is corrected 9.3.2 I2CBus Mode control Register Note1:Set the to "000" before switching to a clockedsynchronous 8-bit SIO mode is deleted. 9.3.4.1 Device initialization SBI0CR1 is deleted. 9.3.4.2 Start condition and slave address generation (1) Master mode register settings is corrected. 6.4.1.2 Generating a 50% duty radio square wave pulse register settings example is corrected. 6.4.3 8-bit PPG output mode. Register settings is corrected. 6.4.4 8-bit PWM output mode Register settings example is corrected. Table 14-6 Correspondence between Operating Frequency and Baund Rate in Single Boot Mode is corrected. 15.2 DC Electrical Characteristics Peak current for intermittent operation T.B.D -> 20mA
Date
2007/2/16
Revision
1.6 1.1 Features Program patch logic 2.3.4 Prescaler Clock Controller is corrected. 16.Table of SFR's 2.1 RESET 10 system clocks 16us -> 1us 18. Points to Note and Restriction
2007/4/16
1.7
15.2 DC Electrical Characteristics Power down voltage Min 4.5V -> 2.0V 14.6.10 Addresses of Program example are corrected
2007/8/27
1.8
DMAR register (89H) is corrected by RWM prohibition. 18.2 Points of note j. Releasing the HALT mode by requesting an interruption is deleted. 2.3.2 Note3 is added 8.2.1 SIO Plescaler is corrected, and Table 8-2 is corrected 8.3 Note2 and Note3 are added 18.2 Points of note j.Clocks for serial channels (SIO) is added 7.3 SFR 16. Table of SFR's TB0FFCR, TB1FFCR, TB2FFCR, TB3FFCR and TB4FFCR register is corrected.
2007/10/15
1.9
TMP91FW60
CMOS 16 Bit Microcontroller
TMP91FW60FG/DFG
Product No. TMP91FW60FG 128K bytes TMP91FW60DFG 8K bytes QFP100-P-1420-0.65A ROM (Flash ROM) RAM Package LQFP100-P-1414-0.50F
1.1 Features
* High-speed 16-bit CPU (900/L1 CPU) - Instruction mnemonics are upward-compatible with TLCS-900,900/H,900/L - 16 Mbytes of linear address space - General-purpose registers and register banks - 16-bit multiplication and division instructions; bit transfer and arithmetic instructions - Micro DMA: 4 channels (800ns/2 bytes at 20MHz) * Minimum instruction execution time:200ns (at 20MHz) * Built-in memory - ROM:128K bytes (Flash ROM) - RAM:8K bytes * External memory expansion - Expandable up to 16 Mbytes (shared program/data area) - Can simultaneously support 8/16-bit width external data bus Dynamic data bus syzing * 8-bit timers: 6 channels * 16-bit timers: 5 channels * General-purpose serial interface: 5 channels - UART/Synchronous mode: 3 channels - I2C bus mode: 2 channels * 10-bit AD converter (Built-in Sample hold circuit): 16 channels * Special timer for CLOCK
This product uses the Super Flash(R) technology under the licence of Silicon Storage Technology, Inc. Super Flash(R) is registered trademark of Silicon Storage Technology, Inc.
20070701-EN
* The information contained herein is subject to change without notice. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. * Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations.
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2007-10-15
TMP91FW60
* Watchdog timer * Program patch logic: 6 banks * Chip select/wait controller: 4 channels * Interrupts: 57 interrupts - 9 CPU interrupts: Software interrupt instruction and illegal instruction - 36 internal interrupts: 7 priority levels are selectable - 12 external interrupts: 7 priority levels are selectable (among 1 interrupts are selectable edge mode) * Input/output ports: 83 pins * Standby function: Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP * Clock controller - Clock gear function: Select a High-frequency clock fc/1 to fc/16 - Oscillator for CLOCK (fs = 32.768 kHz) * Operating voltage Flash read operation > Vcc=4.5 V - 5.5 V (fc max = 20MHz) Flash write/erase operation > Vcc=4.75 V - 5.25 V (fc max = 20MHz) * Package - LQFP100-P-1414-0.50F (TMP91FW60FG) - QFP100-P-1420-0.65A (TMP91FW60DFG)
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TMP91FW60
1.2 Pin Assignment Diagram
100
95
90
VREFH AVSS AVCC P70/TA0IN P71/TA1OUT P72/TA3OUT P73/TA4IN P74/TA5OUT P75/INT0 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0 P91/RXD0 P92/SCLK0/CTS0 P93/TXD1 P94/RXD1 P95/SCLK1/CTS1 AM0 DVCC
1
85
80
P67/AN15 P66/AN14 P65/AN13 P64/AN12 P63/AN11 P62/AN10 P61/AN9 P60/AN8 P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0 DVSS DVCC PB3/TB4OUT1 PB2/TB4OUT0 PB1/TB4IN1/INT10/SCL1 PB0/TB4IN0/INT9/SDA1 P33/TB3OUT1 P32/WAIT/TB3OUT0 P31/TB3IN1/INT4/SCL0
75
5 70
10
TMP91FW60FG
LQFP100
65
15
TOPVIEW
60
20 55
25
P30/TB3IN0/INT3/SDA0 PZ3/R/W PZ2/HWR PZ1/WR PZ0/RD P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 DVCC NMI DVSS P21/A1/A17 P20/A0/A16 P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 P10/AD8/A8 P07/AD7
30
35
X2 DVSS X1 AM1 RESET P96/XT1 P97/XT2 BOOT/EMU0 EMU1 PA0/TB2IN0/INT1 PA1/TB2IN1/INT2 PA2/TB2OUT0 PA3/TB2OUT1 P40/CS0/SCOUT P41/CS1/TXD2 P42/CS2/RXD2 P43/CS3/SCLK2/CTS2 P44/ALE P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6
Figure 1-1 Pin Assignment(TMP91FW60FG)
40
45
50
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2007-10-15
10 70
15
100
80 5 75 65
1
PB0/TB4IN0/INT9/SDA1 PB1/TB4IN1/INT10/SCL1 PB2/TB4OUT0 PB3/TB4OUT1 DVCC DVSS P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P60/AN8 P61/AN9 P62/AN10 P63/AN11 P64/AN12 P65/AN13
95 90 85
TOPVIEW
TMP91FW60DFG
Figure 1-2 Pin Assignment(TMP91FW60DFG)
Page 4
QFP100
20 25 30
60
P66/AN14 P67/AN15 VREFH AVSS AVCC P70/TA0IN P71/TA1OUT P72/TA3OUT P73/TA4IN P74/TA5OUT P75/INT0 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0 P91/RXD0 P92/SCLK0/CTS0 P93/TXD1 P94/RXD1 P95/SCLK1/CTS1 AM0 DVCC X2 DVSS X1
55
45
50
40
35
P33/TB3OUT1 P32/WAIT/TB3OUT0 P31/TB3IN1/INT4/SCL0 P30/TB3IN0/INT3/SDA0 PZ3/R/W PZ2/HWR PZ1/WR PZ0/RD P27/A7/A23 P26/A6/A22 P25/A5/A21 P24/A4/A20 P23/A3/A19 P22/A2/A18 DVCC NMI DVSS P21/A1/A17 P20/A0/A16 P17/AD15/A15 P16/AD14/A14 P15/AD13/A13 P14/AD12/A12 P13/AD11/A11 P12/AD10/A10 P11/AD9/A9 P10/AD8/A8 P07/AD7 P06/AD6 P05/AD5
TMP91FW60
P04/AD4 P03/AD3 P02/AD2 P01/AD1 P00/AD0 P44/ALE P43/CS3/SCLK2/CTS2 P42/CS2/RXD2 P41/CS1/TXD2 P40/CS0/SCOUT PA3/TB2OUT1 PA2/TB2OUT0 PA1/TB2IN1/INT2 PA0/TB2IN0/INT1 EMU1 EMU0/BOOT P97/XT2 P96/XT1 RESET AM1
2007-10-15
TMP91FW60
1.3 Block Diagram
Figure 1-3 Block Diagram
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TMP91FW60
1.4 Pin Names and Functions
Table 1-1 Pin Names and Functions(1/3)
Input / Output IO IO IO IO O IO O O O O O O IO O IO O IO I I IO IO I I IO IO I O IO O IO O O IO O O IO O I IO O IO I IO O IO I
Pin Name
Pin Number
Functions
P00-P07 AD0-AD7 P10-P17 AD8-AD15 A8-A15 P20-P27 A0-A7 A16-A23 PZ0 RD PZ1 WR PZ2 HWR PZ3 R/W P30 TB3IN0 INT3 SDA0 P31 TB3IN1 INT4 SCL0 P32 WAIT TB3OUT0 P33 TB3OUT1 P40 CS0 SCOUT P41 CS1 TXD2 P42 CS2 RXD2 P43 CS3 SCLK2 CTS2 P44 ALE P50-57 AN0-AN7
8
Port 0: I/O port that allows I/O to be selected at the bit level Address data (Lower): 0 to 7 address/data bus Port1: I/O port that allows I/O to be selected at the bit level Address data (Upper): 8 to 15 of address/data bus Address: 8 to 15 of address bus Port 2: I/O port that allows I/O to be selected at the bit level Address: 0 to 7 of address bus Address: 16 to 23 of address bus Port Z0: Output port Read:Strobe signal for reading external memory Port Z1: Output port Write: Strobe signal for writing data to pins AD0 to AD7 Port Z2: I/O port (with pull-up resistor) High write: Strobe signal for writing data to pins AD8 to AD15 Port Z3: I/O port (with pull-up resistor) Read/Write: 1 represents Read or Dummy cycle; 0 represents Write cycle. Port 30: I/O port 16-bit timer 3 input 0:Timer B3 count/capture trigger Input 0 Interrupt Request Pin 3: Interrupt request pin with programmable rising edge / falling edge. Serial bus interface data 0 in I2C bus Mode. Port 31: I/O port 16-bit timer 3 input 1:Timer B3 count/capture trigger Input 1 Interrupt Request Pin 4: Interrupt request on rising edge Serial bus interface clock 0 in I2C bus Mode. Port 32: I/O port Wait: Pin used to request CPU bus wait ((1 N) wait mode) 16-bit timer 3 output 0: Timer B3 Output 0 Port 33: I/O port 16-bit timer 3 output 1: Timer B3 Output 1 Port 40: I/O port (with pull-up resistor) Chip Select 0: Outputs 0 when address is within specified address area System Clock Output: Outputs fSYS or fs clock. Port 41: I/O port (with pull-up resistor) Chip Select 1: Outputs 0 when address is within specified address area Serial Send Data 2 Port 42: I/O port (with pull-up resistor) Chip Select 2: Outputs 0 when address is within specified address area Serial Receive Data 2 Port 43: I/O port (with pull-up resistor) Chip Select 3: Outputs 0 when address is within specified address area Serial Clock I/O 2 Serial Data Send Enable 2 (Clear to Send) Port 44: I/O port (with pull-up resistor) Address Latch Enable Port 5: I/O port Analog input: Pin used to input to AD converter
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
8
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TMP91FW60
Table 1-1 Pin Names and Functions(2/3)
Input / Output IO I IO I IO O IO O IO I IO O IO I IO I I IO I I IO O IO O IO I I IO I I IO O IO O IO O IO I IO IO I IO O IO I
Pin Name
Pin Number
Functions
P60-67 AN8-AN15 P70 TA0IN P71 TA1OUT P72 TA3OUT P73 TA4IN P74 TA5OUT P75 INT0 P80 TB0IN0 INT5 P81 TB0IN1 INT6 P82 TB0OUT0 P83 TB0OUT1 P84 TB1IN0 INT7 P85 TB1IN1 INT8 P86 TB1OUT0 P87 TB1OUT1 P90 TXD0 P91 RXD0 P92 SCLK0 CTS0 P93 TXD1 P94 RXD1
8
Port 6: I/O port Analog input: Pin used to input to AD converter Port 70: I/O port 8-bit timer 0 input: Timer A0 Input Port 71: I/O port 8-bit timer 1 output:Timer A1 Output Port 72: I/O port 8-bit timer 3 output:Timer A3 Output Port 73: I/O port 8-bit timer 4 input: Timer A4 Input Port 74: I/O port 8-bit timer 5 output:Timer A5 Output Port 75: I/O port Interrupt Request Pin 0: Interrupt request pin with programmable level / rising edge / falling edge. Port 80: I/O port 16-bit timer 0 input 0:Timer B0 count/capture trigger Input 0 Interrupt Request Pin 5: Interrupt request pin with programmable rising edge / falling edge. Port 81: I/O port 16-bit timer 0 input 1:Timer B0 count/capture trigger Input 1 Interrupt Request Pin 6: Interrupt request on rising edge Port 82: I/O port 16-bit timer 0 output 0: Timer B0 Output 0 Port 83: I/O port 16-bit timer 0 output 1: Timer B0 Output 1 Port 84: I/O port 16-bit timer 1 input 0:Timer B1 count/capture trigger Input 0 Interrupt Request Pin 7: Interrupt request pin with programmable rising edge / falling edge. Port 85: I/O port 16-bit timer 1 input 1:Timer B1 count/capture trigger Input 1 Interrupt Request Pin 8: Interrupt request on rising edge Port 86: I/O port 16-bit timer 1 output 0: Timer B1 Output 0 Port 87: I/O port 16-bit timer 1 output 1: Timer B1 Output 1 Port 90: I/O port Serial Send Data 0 Port 91: I/O port Serial Receive Data 0 Port 92: I/O port Serial Clock I/O 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 Port 94: I/O port Serial Receive Data 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
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TMP91FW60
Table 1-1 Pin Names and Functions(3/3)
Input / Output IO IO I IO I IO O IO I I IO I I IO O IO O IO I I IO IO I I IO IO O IO O Port 95: I/O port Serial Clock I/O 1 Serial Data Send Enable 1 (Clear to Send) Port 96: I/O port Low-frequency oscillator connection pin Port 97: I/O port Low-frequency oscillator connection pin Port A0: I/O port 16-bit timer 2 input 0:Timer B2 count/capture trigger Input 0 Interrupt Request Pin 1: Interrupt request pin with programmable rising edge / falling edge. Port A1: I/O port 16-bit timer 2 input 1:Timer B2 count/capture trigger Input 1 Interrupt Request Pin 2: Interrupt request on rising edge Port A2: I/O port 16-bit timer 2 output 0: Timer B2 Output 0 Port A3: I/O port 16-bit timer 2 output 1: Timer B2 Output 1 Port B0: I/O port 16-bit timer 4 input 0:Timer B4 count/capture trigger Input 0 Interrupt Request Pin 9: Interrupt request pin with programmable rising edge / falling edge. Serial bus interface data 1 in I2C bus Mode. Port B1: I/O port 16-bit timer 4 input 1:Timer B4 count/capture trigger Input 1 Interrupt Request Pin 10: Interrupt request on rising edge Serial bus interface clock 1 in I2C bus Mode. Port B2: I/O port 16-bit timer 4 output 0: Timer B4 Output 0 Port B3: I/O port 16-bit timer 4 output 1: Timer B4 Output 1 Non-Maskable Interrupt Request Pin: Interrupt request pin with programmable falling edge or both edge. Operation mode:Fixed to AM1 "1", AM0 "1". Set to Open pins Reset: initializes TMP91FW60. (with pull-up resistor) Pin for reference voltage input to AD converter Power supply pin for AD converter GND pin for AD converter (0 V) IO High frequency oscillator connection pins Power supply pins (All DVCC pins should be connected with the power supply pin.) GND pins (0 V) (All DVSS pins should be connected with the GND (0V) pin.)
Pin Name
Pin Number
Functions
P95 SCLK1 CTS1 P96 XT1 P97 XT2 PA0 TB2IN0 INT1 PA1 TB2IN1 INT2 PA2 TB2OUT0 PA3 TB2OUT1 PB0 TB4IN0 INT9 SDA1 PB1 TB4IN1 INT10 SCL1 PB2 TB4OUT0 PB3 TB4OUT1
1
1
1
1
1
1
1
1
1
1
1
NMI
1
I
AM0-1 EMU0-1 RESET VREFH AVCC AVSS X1/X2 DVCC DVSS
2 2 1 1 1 1 2 3 3
I O I I
Note: All pins that have built-in pull-up resistors (other than the RESET pin) can be disconnected from the built-in pull-up resistor by software.
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TMP91FW60
2. CPU
The TMP91FW60 incorporates a high-performance 16-bit CPU (The 900/L1-CPU). For CPU operation, see the "TLCS-900/L1 CPU". The following describe the unique function of the CPU used in the TMP91FW60; these functions are not covered in the TLCS-900/L1 CPU section.
2.1 RESET
When resetting the TMP91FW60 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks (1us at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to Low level at least for 10 system clocks. It means that the system clock mode fSYS is set to fc/2. When the reset is accept, the CPU: 1. Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: - PC (7:0) - PC (15:8) <- Value at FFFF00H address <- Value at FFFF01H address
- PC (23:16) <- Value at FFFF02H address 2. Sets the stack pointer (XSP) to 100H. 3. Sets bits of the status register (SR) to 111 (Sets the interrupt level mask register to level 7). 4. Sets the bit of the status register (SR) to 1 (MAX mode). 5. Clears bits of the status register (SR) to 000 (Sets the register bank to 0). When reset is released, the CPU starts executing instructions in accordance with the program counter settings. CPU internal registers not mentioned above do not change when the reset is released. When the reset is accepted, the CPU sets internal I/O, ports, and other pins as follows. 1. Initializes the internal I/O registers. 2. Sets the port pins, including the pins that also act as internal I/O, to general-purpose input or output port mode. 3. Sets ALE pin to high impedance.
Note 1: The CPU internal register (except to PC, SR, XSP in CPU) and internal RAM data do not change by resetting. Note 2: It is necessary to re-set up a stack pointer XSP by the user program.
Figure 2-1 is a reset timing chart of the TMP91FW60.
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fFPH Sampling Sampling
RESET
A16~A23 (P40 to P43 input mode)
(P20 to P27 input mode)
CS0CS3
R/W
(PZ3 input mode)
ALE (P44 input mode) Address (P00 to P07, P10 to P17 input mode) (P30 output mode)
AD0~AD15
Address
RD
Figure 2-1 TMP91FW60 Reset Timing Chart
Address (P00 to P07, P10 to P17 input mode) (P31 output mode)
Page 10
(P32 input mode) (output mode) (input mode) (input mode)
AD0~AD15
Address
Data-out
WR
HWR
PZ0PZ1
PZ2,PZ3, P40~P43
P00~P07, P10~P17, P20~P27, P60~P67, P70~P75, P80~P87, P90~P97, PA0~PA3 PB0~PB3
TMP91FW60
2007-10-15
TMP91FW60
2.2 Memory Map
Figure 2-2 is a memory map of the TMP91FW60.
000000H
Internal I/O (4 Kbytes)
(n)
000100H 001000H Internal RAM (8 Kbytes)
64 Kbyte area (nn)
003000H 010000H
FE0000H
128 Kbyte
16-Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn)
FFFF00H FFFFFFH
Figure 2-2 TMP91FW60 Memory Map
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TMP91FW60
2.3 System Clock Function and Standby Control
TMP91FW60 contains a clock gear, stand-by controller and noise-reduction circuit. It is used for low-noise systems. The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1,X2,XT1 and XT2 pins). Figure 2-3 shows a transition figure.
(fOSCH/2) IDLE2 mode (I/O operate) IDLE1 mode
(Operate only oscillator)
NORMAL mode (fOSCH /gear value/2)
STOP mode
(Stops All circuits)
(a) Single clock mode transition figure
(fOSCH/2) IDLE2 mode (I/O operate) IDLE1 mode
(Operate only oscillator)
NORMAL mode (fOSCH /gear value/2)
STOP mode
(Stops All circuits)
IDLE2 mode (I/O operate) IDLE1 mode
(Operate only oscillator)
SLOW mode (fs/2) (b) Dual clock mode transition figure
Figure 2-3 TMP91FW60 Clock Operating Mode
Note: The clock frequency input from the X1 and X2 pins is called fOSCH and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 is called fFPH. The system clock fSYSis defined as the divided clock of fFPH, and one cycle of fSYS is regret to as one state.
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TMP91FW60 2.3.1 Block Diagram of System Clock
SYSCR0 SYSCR2 Warm-up timer (for high/low frequency oscillator) SYSCR0 T0 fc/16 fFPH
/4
SYSCR0 XT1 XT2
Lowfrequency oscillator
fs fFPH fs fc fc/2 2 fc/4 fc/8
fc/16 / / / /
fSYS
SYSCR0 X1 X2
Highfrequency oscillator
SYSCR1
SYSCR1
fOSCH
fSYS TMRA01 to TMRA45 T0 Prescaler
CPU ROM RAM TMRB0 toTMRB4 Prescaler WDT I/O port SIO0 to SIO2 Prescaler ADC
SBI0 to SBI1 Prescaler
fs
Binary counter
SYSCR2 P40
f
Figure 2-4 Block Diagram of System Clock
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TMP91FW60
2.3.2
Table 2-1
SFR
SFR for System Clock
7 Bit Symbol Read/Write After reset 1 0 1 XEN 6 XTEN 5 RXEN 4 RXTEN R/W 0 0 0 Warm-up timer control 0 Write: Don't care 1 Write: Start warmup 0 Read: End warmup 1 Read: Do not end warm-up GEAR2 R/W 0 0 0 0 0 3 RSYSCK 2 WUEF 1 PRCK1 0
- - -
SYSCR0 (00E0H) Function
Highfrequency oscillator 0:Stop 1:Oscillation
Lowfrequency oscillator 0:Stop 1:Oscillation
Highfrequency oscillator (fc) after release of STOP mode 0:Stop 1:Oscillation
Lowfrequency oscillator (fs) after release of STOP mode 0:Stop 1:Oscillation
Selects clock after release of STOP mode 0:fc 1:fs
Select prescaler clock 0:fFPH 1:fc/16
Bit Symbol Read/Write After reset
- - -
- - -
- - -
- - -
SYSCK
GEAR1
GEAR0
SYSCR1 (00E1H) Function
-
-
-
-
Select system clock 0: fc 1: fs
Select gear value of high frequency (fc) 000:fc 001:fc/2 010:fc/4 011:fc/8 100:fc/16 101:reserved 110:reserved 111:reserved HALTM0
Bit Symbol Read/Write After reset SYSCR2 (00E2H) Function
- - -
SCOSEL
WUPTM1
WUPTM0 R/W
HALTM1
- -
DRVE R/W 0 Pin state control in STOP mode 0: I/O off 1: Remains the state before HALT
0
1
0
1
1
-
-
Select SCOUT 0:fs 1:fSYS
Select warm-up time for oscillator 00:218/inputted frequency 01:28/inputted frequency 10:214/inputted frequency 11:216/inputted frequency
HALT mode 00:reserved 01:STOP mode 10:IDLE1 mode 11:IDLE2 mode
-
Note 1: "-" = Don't care Note 2: SYSCR0,SYSCR1,SYSCR2 are read as undefined value. Note 3: As for the serial channels SIO0, SIO1 and SIO2, a baud rate generator is unavailable as an input clock of an I/O interface and a clock for a serial transfer if a prescaler clock is set to fc/16 when SYSCR0 is "1".
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2.3.3
System Clock Controller
The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O.It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 changes the system clock to either fc or fs, SYSCR0 and SYSCR0 control enabling and disabling of each oscillator, and SYSCR1 sets the high-frequency clock gear to either 1, 2, 4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). These functions can reduce the power consumption of the equipment in which the device is installed. The combination of settings = "1", = "0", = "0" and = "000" will cause the system clock (fSYS) to be set to fc/2 (=fc x 1/2) after a Reset. For example, fSYS is set to 8 MHz when the 16 MHz oscillator connected to the X1 and X2 pins. (1) Switching from NORMAL mode to SLOW mode When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins, the warm-up timer can be used to change the operation frequency after stable oscillation has been attained. The warm-up time can be selected using SYSCR2. This warm-up timer can be programmed to start and stop as shown in the following examples 1 and 2. Table 2-2 shows the warm-up time.
Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Note 3: Note of using low-frequency oscillator When connect low-frequency oscillator to ports 96 and 97, need below setting for cut consumption power. (Case of resonators) Set P9CR = "11", P9 = "00" (Case of oscillator) Set P9CR = "11", P9 = "10"
Table 2-2 Warm-up Times (when changing clock)
Select Warm-up Time SYSCR2 01(28/frequency) 10(214/frequency) 11(216/frequency) 00(218/frequency) Change to NORMAL (fc) 12.8[us] 0.819[ms] 3.277[ms] 13.107[ms] Change to SLOW (fs) 7.8[ms] 500[ms] 2000[ms] 8000[ms]
Note: At fOSCH=20MHzfs=32.768kHz
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Example 1: Changing from high frequency (fc) to low frequency (fs). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR SET RES 00E0H 00E1H 00E2H (SYSCR2),X-11--X-B 6,(SYSCR0) 2,(SYSCR0) 2,(SYSCR0) NZ,WUP 3,(SYSCR1) 7,(SYSCR0) ; ; ; ;
Detects stopping of warm-up timer. Sets warm-up time to 216/fs. Enables low-frequency oscillation. Clears and starts warm-up timer.
; ; ;
Changes fSYS from fc to fs. Disables high-frequency oscillation.
Note: X: Don't care, -:No change
X1 and X2 pins XT1 and XT2 pins
Counts up by fSYS
Counts up by fs
fSYS
Figure 2-5 Changing from high frequency (fc) to low frequency (fs)
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Example 2: Changing from low frequency (fs) to high frequency (fc).
SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR RES RES 00E0H 00E1H 00E2H (SYSCR2),X-10--X-B 7,(SYSCR0) 2,(SYSCR0) 2,(SYSCR0) NZ,WUP 3,(SYSCR1) 6,(SYSCR0) ; ; ; ; Detects stopping of warm-up timer. ; ; ; Changes fSYS from fs to fc Disables low-frequency oscillation. Sets warm-up time to 214/fc. Enables high-frequency oscillation. Clears and starts warm-up timer.
Note: X: Don't care, -:No change
X1 and X2 pins XT1 and XT2 pin2 Counts up by fSYS
Counts up by fc
fSYS
Figure 2-6 Changing from low frequency (fs) to high frequency (fc)
(2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1 = "0", fFPH is set according to the contents of the clock gear select register SYSCR1 to either fc, fc/2, fc/4, fc/8 or fc/16. Using the clock gear to select a lower value of fFPH reduces power consumption. Below show example of changing clock gear.
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Example 3: Changing to a clock gear SYSCR1 EQU LD X:Don't care (Clock gear changing) To change the clock gear, write the register value to the SYSCR1 register. It is necessary the warm-up time until changing after writing the register value. There is the possibility that the instruction next to the clock gear changing instruction is executed by the clock gear before changing. To execute the instruction next to the clock gear switching instruction by the clock gear after changing, input the dummy instruction as follows (instruction to execute the write cycle). 00E1H (SYSCR1),XXXX0000B
;
Changes fSYS to fc/2.
SYSCR1
EQU LD LD
00E1H (SYSCR1),XXXX0000B (DUMMY),00H ; ; Changes fSYS to fc/2. Dummy instruction
Instruction to be executed after clock gear has changed.
(3)Internal clock output The fSYS or fs internal clock can be driven out from the P40/SCOUT pin. The P40/SCOUT pin is configured as SCOUT (System clock output) by programming the port 4 registers as follows: P4CR = "1" and P4FC = "1". The output clock is selected through the SYSCR2 bit. Table 2-3 shows the pin states in each clocking mode when the P40/SCOUT pin is configured as SCOUT. Table 2-3 SCOUT Output States
HALT mode NORMAL SLOW IDLE2 ="0" ="1" The fs clock is driven out. The fSYS clock is driven out. IDLE1 STOP HOLD at either "1" or "0"
2.3.4
Prescaler Clock Controller
For the internal I/O (TMRA01 to TMRA45, TMRB0 to TMRB4, SIO0 to SIO2, SBI0, SBI1) there is a prescaler which can divide the clock. The T0 clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 4. The setting of the SYSCR0 register determines which clock signal is input.
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2.3.5
Runaway provision with SFR protection register
(Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (CS/WAIT controller) is changed.
Specified SFR list
1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. Clock gear (write enable only EMCCR1) SYSCR0, SYSCR1, SYSCR2
(Block diagram)
EMCCR0
S R
Q
Write signal to SFR
(Setting method) If writing except "1FH" code to EMCCR1 register, it become protect ON. By this operation, write operation to specified SFR is disabling. If writing "1FH" to EMCCR1 register, it become protect OFF. State of protect can to confirm by reading EMCCR0. Table 2-4 SFR for EMCCR
7 Bit Symbol Read/Write EMCCR0 (00E3H) After reset PROTECT R 0 Protect flag 0: OFF 1: ON 0 1 0 6 5 4 3 2 1 0
-
-
-
-
R/W 0
-
-
-
0
1
1
Function
Write "0".
Write "1".
Write "0".
Write "0".
Write "0".
Write "1".
Write "1".
Bit Symbol EMCCR1 (00E4H) Read/Write After reset Function Protect OFF by writing "1FH". Protect ON by writing except "1FH".
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2.3.6
Standby Controller
(1)HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 register. The subsequent actions performed in each mode are as follows: 1. IDLE2: Only the CPU halts. The internal I/O is available to select operation during IDLE2 mode by setting the following register. Shows the registers of setting operation during IDLE2 mode. Table 2-5 SFR Setting Operation during IDLE2 Mode
Internal I/O TMRA01 TMRA23 TMRA45 TMRB0 TMRB1 TMRB2 TMRB3 TMRB4 SFR TA01RUN TA23RUN TA45RUN TB0RUN TB1RUN TB2RUN TB3RUN TB4RUN Internal I/O SIO0 SIO1 SIO2 SBI0 SBI1 AD WDT SFR SC0MOD1 SC1MOD1 SC2MOD1 SBI0BR SBI1BR ADCCR2 WDMOD
2. IDLE1: Only the oscillator and the RTC (Real time clock) continue to operate. 3. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 2-6. Table 2-6 I/O Operation during HALT Modes
HALT mode SYSCR2 CPU I/O port TMRA,TMRB Block RTC SIO,SBI AD Available to select operation block Operate enable IDLE2 IDLE1 STOP
11
10 Stop
01
Keep the state when the HALT instruction was executed.
See Table 2-9
Stop
WDT Interrupt controller Operate
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(2)How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register and the HALT modes. The details for releasing the halt status are shown in Table 2-7. Released by requesting an interrupt The operating released from the HALT mode depends on the interrupt enabled status. When the interrupt request level set before executing the HALT instruction exceeds the value of interrupt mask register, the interrupt due to the source is processed after releasing the HALT mode, and CPU status executing an instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is not executed. (In non-maskable interrupts, interrupt processing is processed after releasing the HALT mode regardless of the value of the mask register.) However only for INT0 and RTC interrupts, even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is executed. In this case, interrupt processing, and CPU starts executing the instruction next to the HALT instruction, but the interrupt request flag is held at "1".
Note:Usually, interrupts can release all halts status. However, the interrupts (NMI, INT0, INTRTC) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
Releasing by resetting Releasing all halt status is executed by resetting. When the STOP mode is released by RESET, it is necessary enough resetting time (See Table 2-6)to set the operation of the oscillator to be stable. When releasing the HALT mode by resetting, the internal RAM data keeps the state before the "HALT" instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the "HALT" instruction is executed.)
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Table 2-7 Source of Halt State Clearance and Halt Clearance Operation
Status of Received Interrupt
Interrupt Enable (Interrupt level) IDLE2
(Interrupt mask)
STOP
Interrupt Disable (Interrupt level) < (Interrupt mask) IDLE2 IDLE1 STOP -
HALT mode
NMI INTWDT INT0(Note 1) INTRTC
IDLE1
(Note 2)
RESET
x x x x x x x x
*1 x *1 x x x x x x x x
Source of Halt state clearance
x x x x x x x
x x x x x x x
*1 x x x x x x x x
Interrupt
INT1-INT10 INTTA0-INTTA5 INTTB00-40,INTTB01-41 INTTB0F0-4 INTRX0-INTRX2,TX0-TX2 INTSBI0-1 INTAD
Initialize LSI
:After clearing the HALT mode, CPU starts interrupt processing. :After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. (Interrupt routine don't execute.) x:It can not be used to release the HALT mode. - :The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1:Releasing the HALT mode is executed after passing the warm-up time.
Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold high level until starting interrupt process. If low level was set before interrupt process is stared, interrupt process is not started correctly. Note 2: If using external interrupt INT1 to INT10 in IDLE2 mode, set 16-bit timer RUN register TB0RUN, TB1RUN, TB2RUN, TB3RUN, TB4RUN to "1".
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Example:Clearing halt state An INT0 interrupt clears the halt state when the device is in IDLE1 mode.
8203H 8206H 8209H 820BH 820EH INT0
LD LD EI LD HALT
(IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H
; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets CPU interrupt level to 5. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine RETI
820FH
LD
XX, XX
(3)Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 2-7 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt.
X1 A0~A23 ALE AD0~AD15
RD WR
Address Data Address Address Data
IDLE2
Figure 2-7 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt
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2. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC continue to operate. The system clock in the MCU stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the Halt state (e.g., restart of operation) is synchronous with it. Figure 2-8 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt.
X1 A0A23 ALE AD0AD15
RD WR
Address Data Address Data
IDLE1 mode
Figure 2-8 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt
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3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. Pin status in STOP mode depends on the settings in the SYSCR2 register. Table 2-9 summarizes the state of these pins in STOP mode. After STOP mode has been cleared, system clock output starts when the warm-up time has elapsed, in order to allow oscillation to stabilize. After STOP mode has been cleared, either NORMAL mode or SLOW mode can be selected using the SYSCR0 register. Therefore, , and must be set. See the sample warm-up times in Table 2-8. Figure 2-9 illustrates the timing for clearance of the STOP mode halt state by an interrupt.
X1 A0A23 ALE AD0AD15
RD WR
Address Data Address Data
STOP
Figure 2-9 Timing Chart for STOP Mode Halt State Cleared by Interrupt
Table 2-8 Sample Warm-up Times after Clearance of STOP Mode SYSCR0 0(fc) 1(fs) SYSCR2 01(28) 12.8us 7.8ms 10(214) 0.819ms 500ms 11(216) 3.277ms 2000ms 00(218) 13.107ms 8000ms
Note: fOSCH=20MHz, fs=32.768kHz
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Example: "The STOP mode is entered when the low-frequency operates, and high-frequency operates after releasing due to NMI.
SYSCR0 SYSCR1 SYSCR2 8FFDH 9000H 9002H 9005H
NMI
EQU EQU EQU LD LD LD HALT
00E0H 00E1H 00E2H (SYSCR1), 08H (SYSCR2), X-1001X1B (SYSCR0), 011000 - -B
; ; ;
fSYS = fs/2 214/fOSCH
NMI
9006H
LD -: No change
XX, XX
RETI
Note:When different modes are used before and after STOP mode as the above mentioned, there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of "HALT" instruction (during 6 state). In the system which accepts the interrupts during execution "HALT" instruction, set the same operation mode before and after the STOP mode.
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Table 2-9 Input/output Buffer State Table Port Name
P00-07
Input / Output
input mode output mode AD0-AD7 input mode output mode AD8-AD15 input mode output mode,A0-A7/A16-A23 output input mode output mode input mode output mode input mode output mode input mode output mode analog input input mode output mode analog input input mode output mode input mode output mode input mode output mode input mode output mode input mode output mode input mode output mode input input input input output
=0
PU* PU* PU* PU* input input input input "H" level output
=1
output output output output PU* output output PU* output output output input output input output output output output output input input input "H" level output
P10-17
P20-27 PZ0(RD),PZ1(WR) PZ2(HWR),PZ3(R/W)
P30-33
P40-44
P50-57
P60-67
P70-74
P75
P80-87
P90-97
PA0-A3
PB0-B3 NMI RESET AM0,AM1 X1 X2
-:
Input for input mode / input pins is invalid; output mode / output pin is at high impedance.
input: Input gate in operation. Fix input voltage to "L" or "H" so that input pin stays constant. output: Output state PU*: Programmable pull-up pin. Input gate disable state. No through current even if the pin is set high impedance.
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3. Interrupts
Interrupts are controlled by the CPU interrupt mask register SR and by the built-in interrupt controller. The TMP91FW60 has a total of 57 interrupts divided into the following three types:
* Interrupts generated by CPU: 9 sources (Software interrupts, illegal instruction interrupt) * Interrupts on external pins (NMI, INT0 to INT10): 12 sources * Internal interrupts: 36 sources
A (fixed) individual interrupt vector number is assigned to each interrupt. One of six (Variable) priority level can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at 7 as the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register . If the priority level of the interrupt is higher than the value of the interrupt mask register, the CPU accepts the interrupt. The interrupt mask register value can be updated using the value of the EI instruction ("EI num" sets data to num). For example, specifying "EI3" enables the maskable interrupts which priority level set in the interrupt controller is 3 or higher, and also non-maskable interrupts. Operationally, the DI instruction ( "7") is identical to the "EI7" instruction. DI instruction is used to disable maskable interrupts because of the priority level of maskable interrupts is 0 to 6. The EI instruction is valid immediately after execution. In addition to the above general-purpose interrupt processing mode, TLCS-900/L1 has a micro DMA interrupt processing mode as well. The CPU can transfer the data (1/2/4 bytes) automatically in micro DMA mode, therefore this mode is used for speed-up interrupt processing, such as transferring data to the internal or external peripheral I/ O. Moreover, TMP91FW60 has software start function for micro DMA processing request by the software not by the hardware interrupt. Figure 3-1 shows the overall interrupt processing flow.
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Interrupt processing
Interrupt specified by micro DMA start vector?
Yes Micro DMA soft start request
Clear interrupt request flag
No Interrupt vector value "V" read Interrupt request F/F clear
General-purpose interrupt processing
Data transfer by micro DMA
PUSH PUSH SR INTNEST
PC SR Level of accepted interrupt + 1 INTNEST + 1
Count
Count - 1
Micro DMA processing
PC
(FFFF00H + V)
Yes
Count = 0
No
Clear vector register generating micro DMA transfer and interrupt (INTTC0 to INTTC3)
Interrupt processing program
RETI instruction POP SR POP PC INTNEST - 1 INTNEST
End
Figure 3-1 Overall Interrupt Processing Flow
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3.1 General-purpose Interrupt Processing
When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. 1. The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt. The smaller vector value has the higher priority level.) 2. The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (Indicated by XSP). 3. The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask register . However, if the priority level of the accepted interrupt is 7, the register's value is set to 7. 4. The CPU increases the interrupt nesting counter INTNEST by 1 (+1). 5. The CPU jumps to the address indicated by the data at address "FFFF00H + Interrupt vector" and starts the interrupt processing routine. The above processing time is 18 states (1.8 s at 20 MHz) as the best case (16-bit data bus width and 0 waits). When the CPU completed the interrupt processing, use the RETI instruction to return to the main routine. RETI restores the contents of program counter (PC) and status register (SR) from the stack and decreases the interrupt nesting counter INTNEST by 1 (-1). Non-maskable interrupts cannot be disabled by a user program. Maskable interrupts, however, can be enabled or disabled by a user program. A program can set the priority level for each interrupt source. (A priority level setting of 0 or 7 will disable an interrupt request.) If an interrupt request which has a priority level equal to or greater than the value of the CPU interrupt mask register comes out, the CPU accepts its interrupt. Then, the CPU interrupt mask register is set to the value of the priority level for the accepted interrupt plus 1 (+1). Therefore, if an interrupt is generated with a higher level than the current interrupt during its processing, the CPU accepts the later interrupt and goes to the nesting status of interrupt processing. Moreover, if the CPU receives another interrupt request while performing the said 1. to 5. processing steps of the current interrupt, the latest interrupt request is sampled immediately after execution of the first instruction of the current interrupt processing routine. Specifying DI as the start instruction disables maskable interrupt nesting. A reset initializes the interrupt mask register to "111", disabling all maskable interrupts. Table 3-1 shows the TMP91FW60 interrupt vectors and micro DMA start vectors. The address FFFF00H to FFFFFFH (256 bytes) is assigned for the interrupt vector area.
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Table 3-1 TMP91FW60 Interrupt Vectors Table(1/2)
Default Priority 1 2 3 4 5 6 7 8 9 10 - 11 12 13 14 15 16 17 18 19 20 21 22 23 Maskable 24 25 26 27 28 29 30 31 32 33 34 35 36 37 INTTA2: 8-bit timer 2 INTTA3: 8-bit timer 3 INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 INTTB00: 16-bit timer 0 (TB0RG0) INTTB01: 16-bit timer 0 (TB0RG1) INTTB10: 16-bit timer 1 (TB1RG0) INTTB11: 16-bit timer 1 (TB1RG1) INTTB20: 16-bit timer 2 (TB2RG0) INTTB21: 16-bit timer 2 (TB2RG1) INTTB30: 16-bit timer 3 (TB3RG0) INTTB31: 16-bit timer 3 (TB3RG1) INTTB40: 16-bit timer 4 (TB4RG0) INTTB41: 16-bit timer 4 (TB4RG1) 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Nonmaskable Type Interrupt Source and Source of Micro DMA Request "Reset" or "SWI 0" instruction "SWI 1" instruction INTUNDEF: Illegal instruction or "SWI 2" instruction "SWI 3" instruction "SWI 4" instruction "SWI 5" instruction "SWI 6" instruction "SWI 7" instruction NMI:NMI pin INTWD: Watchdog timer Micro DMA (MDMA) INT0: INT0 pin INT1: INT1 pin INT2: INT2 pin INT3: INT3 pin INT4: INT4 pin INT5: INT5 pin INT6: INT6 pin INT7: INT7 pin INT8: INT8 pin INT9: INT9 pin INT10: INT10 pin INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 Vector Value (V) 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H Vector Reference Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H Micro DMA Start Vector - - - - - - - - - - - 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H
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Table 3-1 TMP91FW60 Interrupt Vectors Table(2/2)
Default Priority 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Maskable Type Interrupt Source and Source of Micro DMA Request INTTBOF0: 16-bit timer 0 (Over flow) INTTBOF1: 16-bit timer 1 (Over flow) INTTBOF2: 16-bit timer 2 (Over flow) INTTBOF3: 16-bit timer 3 (Over flow) INTTBOF4: 16-bit timer 4 (Over flow) INTRX0:Serial reception (Channel 0) INTTX0:Serial transmission (Channel 0) INTRX1:Serial reception (Channel 1) INTTX1:Serial transmission (Channel 1) INTRX2:Serial reception (Channel 2) INTTX2:Serial transmission (Channel 2) INTSBI0:Serial bus interface interrupt (Channel 0) INTSBI1:Serial bus interface interrupt (Channel 1) INTRTC: Interrupt for special timer for CLOCK INTAD: AD conversion end INTTC0 Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) (Reserved) : (Reserved) Vector Value (V) 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H 00C8H 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H : 00FCH Vector Reference Address FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H FFFFB8H FFFFBCH FFFFC0H FFFFC4H FFFFC8H FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H : FFFFFCH Micro DMA Start Vector 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H - - - - - : -
Note: Micro DMA default priority: Micro DMA stands up prior to other maskable interrupt.
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TMP91FW60
3.2 Micro DMA Processing
In addition to general-purpose interrupt processing, the TMP91FW60 supports a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (Level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. The micro DMA has 4 channels and is possible continuous transmission by specifying the described later burst mode. The micro DMA has 4 channels and is possible continuous transmission by specifying the described later burst mode. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes to a standby mode (STOP, IDLE1 and IDLE2) by HALT instruction, the requirement of micro DMA will be ignored (Pending) and DMA transfer is started after release HALT.
3.2.1
Micro DMA Operation
When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite of any interrupt source's level. The micro DMA is ignored on = "7". The 4 micro DMA channels allow micro DMA processing to be set for up to 4 types of interrupts at any one time. When micro DMA is accepted, the interrupt request flip-flop assigned to that channel is cleared. The data are automatically transferred once (1/2/4 bytes) from the transfer source address to the transfer destination address set in the control register, and the transfer counter is decreased by 1 (-1). If the decreased result is "0", the micro DMA transfer end interrupt (INTTC0 to INTTC3) passes from the CPU to the interrupt controller. In addition, the micro DMA start vector register DMAnV is cleared to 0, the next micro DMA is disabled and micro DMA processing completes. If the decreased result is other than "0", the micro DMA processing completes if it does not specify the described later burst mode. In this case, the micro DMA transfer end interrupt (INTTC0 to INTTC3) aren't generated. If an interrupt request is triggered for the interrupt source in use during the interval between the clearing of the micro DMA start vector and the next setting, general-purpose interrupt processing executes at the interrupt level set. Therefore, if only using the interrupt for starting the micro DMA (Not using the interrupts as a general-purpose interrupt: Level 1 to 6), first set the interrupts level to 0 (Interrupt requests disabled). If using micro DMA and general-purpose interrupts together, first set the level of the interrupt used to start micro DMA processing lower than all the other interrupt levels. (Note) In this case, the cause of general interrupt is limited to the edge interrupt. The priority of the micro DMA transfer end interrupt (INTTC0 to INTTC3) is defined by the interrupt level and the default priority as the same as the other maskable interrupt. If a micro DMA request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel 0 (High) > Channel 3 (Low)). While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (The upper eight bits of the 32 bits are not valid).
Note:If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in the Figure 3-1) and reading interrupt vector with setting below, the vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because checking of micro DMA has been finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA
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TMP91FW60
Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One-word) transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/destination addresses are increased, decreased, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the transfer modes, see" 3.2.4 Detailed Description of the Transfer Mode Register ". As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 42 interrupts shown in the micro DMA start vectors of Table 31 and by the micro DMA soft start, making a total of 43 interrupts. Figure 3-2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer source/transfer destination addresses both even-numberd values).
1 state DM1 DM2 DM3 DM4 (Note 1) DM5 DM6 (Note 2) DM7 DM8
X1
Transfer destination address
A0 to A23
Transfer source address
RD
WR, HWR
D0 to D15
Input
Output
Figure 3-2 Timing for Micro DMA Cycle
States 1 to 3: Instruction fetch cycle (Gets next address code). If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycle State 6: Dummy cycle (The address bus remains unchanged from state 5.)
States 7 to 8: Micro DMA write cycle
Note 1: If the source address area is an 8-bit bus, it is increased by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. Note 2: If the destination address area is an 8-bit bus, it is increased by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by two states.
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TMP91FW60
3.2.2
Soft Start Function
In addition to starting the micro DMA function by interrupts, TMP91FW60 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing "1" to each bit of DMAR register causes micro DMA once (If write "0" to each bit, micro DMA doesn't operate) At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to "0". Only one-channel can be set once for micro DMA. (Do not write "1" to plural bits.) When writing again "1" to the DMAR register, check whether the bit is "0" before writing "1". If read "1", micro DMA transfer isn't started yet. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is "0" after start up of the micro DMA. If execute soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn't change. Don't use Read-modify-write instruction to avoid writing to other bits by mistake.
Symbol
Name
Address 89H
7 - - -
6 - - -
5 - - -
4 - - -
3 DMAR3
2 DMAR2 R/W
1 DMAR1
0 DMAR0
DMAR
DMA Request Register
RMW instructions are prohibited.
0
0
0
0
DMA request
3.2.3
Transfer Control Registers
The transfer source address and the transfer destination address are set in the following registers in CPU. Data setting for these registers is done by an "LDC cr, r" instruction.
Channel 0
DMAS0 DMAD0 DMAC0 DMAM0
DMA source address register 0: Only use LSB 24 bits DMA destination address register 0: Only use LSB 24 bits DMA counter register 0: 1 to 65536 DMA mode register 0
Channel 3
DMAS3 DMAD3 DMAC3 DMAM3
DMA source address register 3 DMA destination address register 3 DMA counter register 3 DMA mode register 3
8 bits 16 bits 32 bits
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TMP91FW60 3.2.4 Detailed Description of the Transfer Mode Register
(DMAM0 to DMAM3) 0 0 0
Mode
Note: The upper three bit of data programmed to these registers must always be 0. Execution time
ZZ: 0 = Byte transfer, 1 = Word transfer, 2 = 4-byte transfer, 3 = Reserved Transfer destination address INC modeI/O to memory (DMADn+) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Transfer destination address DEC mode I/O to memory (DMADn-) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Transfer source address INT modememory to I/O (DMADn) (DMASn+) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Transfer source address DEC mode memory to I/O (DMADn) (DMASn-) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Address fixed modeI/O to I/O (DMADn) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Counter mode for counting number of times interrupt is generated DMASn DMASn + 1 DMACn DMACn - 1 if DMACn = 0 then INTTC is generated 8 states (800 ns) @ byte/word transfer 12 states (1200 ns) @ 4-byte/word transfer 8 states (800 ns) @ byte/word transfer 12 states (1200 ns) @ 4-byte/word transfer 8 states (800 ns) @ byte/word transfer 12 states (1200 ns) @ 4-byte/word transfer 8 states (800 ns) @ byte/word transfer 12 states (1200 ns) @ 4-byte/word transfer 8 states (800 ns) @ byte/word transfer 12 states (1200 ns) @ 4-byte/word transfer 5 states (500 ns)
0
0
0
Z
Z
0
0
1
Z
Z
0
1
0
Z
Z
0
1
1
Z
Z
1
0
0
Z
Z
1
0
1
0
0
Note 1: "n" is the corresponding micro DMA channels 0 to 3. DMADn+/DMASn+: Post-increment (Increment register value after transfer) DMADn-/DMASn-: Post-decrement (Decrement register value after transfer) The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC) addresses. Note 2: Execution time is under the condition of: 16-bit bus width (Both transfer and destination address area)/0 waits/ fc = 20 MHz/selected high-frequency mode (fc x 1) Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the above table.
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3.3 Interrupt Controller Operation
The block diagram in Figure 3-3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For interrupt controller there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to 0 in the following cases: * When reset occurs * When the CPU reads the channel vector after accepted its interrupt * When executing an instruction that clears the interrupt (Write DMA start vector to INTCLR register) * When the CPU receives a micro DMA request (when micro DMA is set) * When the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE56). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are generated at the same time, the default priority is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request and its vector address to the CPU. The CPU compares the priority value in the status register by the interrupt request signal with the priority value set; if the latter is higher, the interrupt is accepted. Then the CPU sets a value higher than the priority value by 1 (+1) in the CPU SR. Interrupt request where the priority value equals or is higher than the set value are accepted simultaneously during the previous interrupt routine. When interrupt processing is completed (after execution of the RETI instruction), the CPU restores the priority value saved in the stack before the interrupt was generated to the CPU SR. The interrupt controller also has registers (4 channels) used to store the micro DMA start vector. Writing the start vector of the interrupt source for the micro DMA processing beforehand (see Table 3-1), enables the corresponding interrupt to be processed by micro DMA processing. The values must be set in the micro DMA parameter register (e.g., DMAS and DMAD) prior to the micro DMA processing.
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Interrupt controller
CPU
Interrupt request F/F
NMI Q
V = 20H V = 24H
RESET Interrupt vector read
S R IFF2:0
Interrupt request signal to CPU 3 3 INTRQ2 to INTRQ0 3 Priority encoder 1 7 6 6 RESET EI 1 to 7 DI
1
Interrupt mask F/F
INTWD
Decoder
Priority setting register
Dn Dn+1 Dn+2 A B C Interrupt level detect D0 D1 D2
V = 28H V = 2CH V = 30H If INTRQ2 to 0 then 1. IFF2 to 0
DQ CLR
Interrupt request F/F
Y1 Y2 Y3 Y4 Y5 Y6 Dn+3
48
Interrupt request signal
INT0
RESET
S R D3 D4 D5 D6 D7
Interrupt vector read
Q
1 2 Highest A priority 3 interrupt B 4 level C select 5 6 7
Interrupt request F/F Interrupt vector read Micro DMA acknowledge
INT1 INT2 INT3 Interrupt vector generator
Figure 3-3 Block Diagram of Interrupt Controller
V = CCH V = D0H V = D4H V = D8H V = DCH
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Software start 4 4 input OR
During IDLE1 During STOP
Halt release RESET INT0, INTRTC NMI
Micro DMA counter zero interrupt
INTAD INTTC0 INTTC1 INTTC2 INTTC3
Micro DMA request If IFF = 7 then 0
S
Selector
Micro DMA start vector setting register D5 D4 D3 42 DQ D2 D1 6 CLR D0
A B
Micro DMA channel priority encoder
2
2
Micro DMA channel specification
TMP91FW60
2007-10-15
INTTC0
DMA0V DMA1V DMA2V DMA3V
RESET
0 1 2 3
TMP91FW60 3.3.1 Interrupt Level Setting Registers
Interrupt Level Setting Registers
Symbol Name Address 7 6 INTAD INTE0AD INT0 & INTAD enable IADC 90H R 0 0 INT2 INTE12 INT1 & INT2 enable I2C 91H R 0 0 INT4 INTE34 INT3 & INT4 enable I4C 92H R 0 0 INT6 INTE56 INT5 & INT6 enable I6C 93H R 0 0 INT8 INTE78 INT7 & INT8 enable I8C 94H R 0 0 INT10 INTE910 INT9 & INT10 enable I10C 95H R 0 0 R/W 0 0 R 0 0 R/W 0 0 I10M2 I10M1 I10M0 I9C I9M2 R/W 0 0 R 0 0 INT9 I9M1 I9M0 R/W 0 0 I8M2 I8M1 I8M0 I7C I7M2 R/W 0 0 R 0 0 INT7 I7M1 I7M0 R/W 0 0 I6M2 I6M1 I6M0 I5C I5M2 R/W 0 0 R 0 0 INT5 I5M1 I5M0 R/W 0 0 I4M2 I4M1 I4M0 I3C I3M2 R/W 0 0 R 0 0 INT3 I3M1 I3M0 R/W 0 0 I2M2 I2M1 I2M0 I1C I1M2 R/W 0 0 R 0 0 INT1 I1M1 I1M0 R/W 0 0 IADM2 IADM1 IADM0 I0C I0M2 5 4 3 2 INT0 I0M1 I0M0 1 0
INTTA1(TMRA1) INTETA01 INTTA0 & INTTA1 enable ITA1C 96H R 0 0 R/W 0 0 R 0 ITA1M2 ITA1M1 ITA1M0 ITA0C
INTTA0 (TMRA0) ITA0M2 ITA0M1 R/W 0 0 0 ITA0M0
IxxxC Interrupt request flag
IxxM2 0 0 0 0 1 1 1 1
IxxM1 0 0 1 1 0 0 1 1
IxxM0 0 1 0 1 0 1 0 1
Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests
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Interrupt Level Setting Registers
Symbol Name Address 7 6 5 4 3 2 1 0
INTTA3 (TMRA3) INTETA23 INTTA2 & INTTA3 enable ITA3C 97H R 0 0 R/W 0 0 R 0 ITA3M2 ITA3M1 ITA3M0 ITA2C
INTTA2 (TMRA2) ITA2M2 ITA2M1 R/W 0 0 0 ITA2M0
INTTA5 (TMRA5) INTETA45 INTTA4 & INTTA5 enable ITA5C 98H R 0 0 R/W 0 0 R 0 ITA5M2 ITA5M1 ITA5M0 ITA4C
INTTA4 (TMRA4) ITA4M2 ITA4M1 R/W 0 0 0 ITA4M0
INTTB01(TMRB0) INTETB0 Interrupt enable TMRB0 ITB01C 99H R 0 0 R/W 0 0 R 0 ITB01M2 ITB01M1 ITB01M0 ITB00C
INTTB00(TMRB0) ITB00M2 ITB00M1 R/W 0 0 0 ITB00M0
INTTB11(TMRB1) INTETB1 Interrupt enable TMRB1 ITB11C 9AH R 0 0 R/W 0 0 R 0 ITB11M2 ITB11M1 ITB11M0 ITB10C
INTTB10(TMRB1) ITB10M2 ITB10M1 R/W 0 0 0 ITB10M0
INTTB21(TMRB2) INTETB2 Interrupt enable TMRB2 ITB21C 9BH R 0 0 R/W 0 0 R 0 ITB21M2 ITB21M1 ITB21M0 ITB20C
INTTB20(TMRB2) ITB20M2 ITB20M1 R/W 0 0 0 ITB20M0
INTTB31(TMRB3) INTETB3 Interrupt enable TMRB3 ITB31C 9CH R 0 0 R/W 0 0 R 0 ITB31M2 ITB31M1 ITB31M0 ITB30C
INTTB30(TMRB3) ITB30M2 ITB30M1 R/W 0 0 0 ITB30M0
INTTB41(TMRB4) INTETB4 Interrupt enable TMRB4 ITB41C 9DH R 0 Interrupt enable TMRB0/1 (Over flow) 0 R/W 0 0 R 0 ITB41M2 ITB41M1 ITB41M0 ITB40C
INTTB40(TMRB4) ITB40M2 ITB40M1 R/W 0 0 0 ITB40M0
INTTBOF1(TMRB1 Over flow) ITF1C 9EH R 0 0 R/W 0 0 R 0 ITF1M2 ITF1M1 ITF1M0 ITF0C INTETB01V
INTTBOF0(TMRB0 Over flow) ITF0M2 ITF0M1 R/W 0 0 0 ITF0M0
IxxxC Interrupt request flag
IxxM2 0 0 0 0 1 1 1 1
IxxM1 0 0 1 1 0 0 1 1
IxxM0 0 1 0 1 0 1 0 1
Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests
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Interrupt Level Setting Registers
Symbol Name Interrupt enable TMRB2/3 (Over flow) Address 7 6 5 4 3 2 1 0
INTTBOF3(TMRB3 Over flow) ITF3C 9FH R 0 Interrupt enable TMRB4/ INTRTC 0 INTRTC IRTCC A0H R 0 0 INTTX0 INTES0 INTRX0 & INTTX0 enable ITX0C A1H R 0 0 INTTX1 INTES1 INTRX1 & INTTX1 enable ITX1C A2H R 0 0 INTTX2 INTES2 INTRX2 & INTTX2 enable ITX2C A3H R 0 0 INTSBI1 INTESBI01 INTSBI0 & INTSBI1 enable ISBI1C A4H R 0 0 INTTC1 INTETC01 INTTC0 & INTTC1 enable ITC1C A5H R 0 0 INTTC3 INTETC23 INTTC2 & INTTC3 enable ITC3C A6H R 0 0 R/W 0 0 R 0 ITC3M2 ITC3M1 ITC3M0 ITC2C R/W 0 0 R 0 ITC1M2 ITC1M1 ITC1M0 ITC0C R/W 0 0 R 0 ISBI1M2 ISBI1M1 ISBI1M0 ISBI0C R/W 0 0 R 0 ITX2M2 ITX2M1 ITX2M0 IRX2C R/W 0 0 R 0 ITX1M2 ITX1M1 ITX1M0 IRX1C R/W 0 0 R 0 ITX0M2 ITX0M1 ITX0M0 IRX0C R/W 0 0 R 0 IRTCM2 IRTCM1 IRTCM0 ITF4C INTETB4VRTC R/W 0 0 R 0 ITF3M2 ITF3M1 ITF3M0 ITF2C INTETB23V
INTTBOF2(TMRB2 Over flow) ITF2M2 ITF2M1 R/W 0 0 0 ITF2M0
INTTBOF4(TMRB4 Over flow) ITF4M2 ITF4M1 R/W 0 INTRX0 IRX0M2 IRX0M1 R/W 0 INTRX1 IRX1M2 IRX1M1 R/W 0 INTRX2 IRX2M2 IRX2M1 R/W 0 INTSBI0 ISBI0M2 ISBI0M1 R/W 0 INTTC0 ITC0M2 ITC0M1 R/W 0 INTTC2 ITC2M2 ITC2M1 R/W 0 0 0 ITC2M0 0 0 ITC0M0 0 0 ISBI0M0 0 0 IRX2M0 0 0 IRX1M0 0 0 IRX0M0 0 0 ITF4M0
IxxxC Interrupt request flag
IxxM2 0 0 0 0 1 1 1 1
IxxM1 0 0 1 1 0 0 1 1
IxxM0 0 1 0 1 0 1 0 1
Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests
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TMP91FW60 3.3.2 External Interrupt Control
External Interrupt Control Register (IIMC)
Symbol Name Address 7 - 6 - 5 - 4 - W Interrupt input mode control 8CH RMW instructions are prohibited. 0 0 0 0 0 0 0 0 1:Operates even on rising/ falling edge of NMI 3 - 2 I0EDGE 1 I0LE 0 NMIREE
IIMC
Always write "0".
-
-
-
-
INT0 EDGE 0: Rising 1: Falling
INT0 mode 0: Edge 1: Level
INT0 setting
P7FC 1 1 1 1 0 0 1 1 0 1 0 1 INT0 Rising edge interruption Falling edge interruption "H" level INT "L" level INT
NMI rising edge enable 0 1 INT request generation at falling edge INT request generation at rising/falling edge
3.3.3
Interrupt Request Flag Clear Register
The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 31, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH: Clears interrupt request flag INT0.
Interrupt Request Flag Clear Register (INTCLR)
Symbol Name Address 88H Interrupt Clear Control RMW instructions are prohibited. 7 - - - 6 - - - 0 0 0 5 CLRV5 4 CLRV4 3 CLRV3 W 0 0 0 2 CLRV2 1 CLRV1 0 CLRV0
INTCLR
Interrupt vector
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3.3.4
Micro DMA Start Vector Registers
This register assigns micro DMA processing to which interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. When the micro DMA transfer counter value reaches 0, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the higher number. (Micro DMA chaining)
Micro DMA Start Vector Registers (DMAnV)
Symbol Name Address 7 - DMA0 Start Vector - 80H - - 0 0 0 0 0 0 6 - - 5 DMA0V5 4 DMA0V4 3 DMA0V3 R/W 2 DMA0V2 1 DMA0V1 0 DMA0V0
DMA0V
DMA0 start vector - DMA1 Start Vector - 81H - - 0 0 0 0 0 0 - - DMA1V5 DMA1V4 DMA1V3 R/W DMA1V2 DMA1V1 DMA1V0
DMA1V
DMA1 start vector - DMA2 Start Vector - 82H - - 0 0 0 0 0 0 - - DMA2V5 DMA2V4 DMA2V3 R/W DMA2V2 DMA2V1 DMA2V0
DMA2V
DMA2 start vector - DMA3 Start Vector - 83H - - 0 0 0 0 0 0 - - DMA3V5 DMA3V4 DMA3V3 R/W DMA3V2 DMA3V1 DMA3V0
DMA3V
DMA3 start vector
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3.3.5
Micro DMA Burst Specification
Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches 0 after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to "1" specifies a burst. If other interrupts (maskable/nonmaskable is not concerned) are generated during burst transfer, interrupt is executed after completed burst transfer.
Micro DMA Burst Request Registers (DMAR)
Symbol Name Address 89H DMA Software Request Register RMW instructions are prohibited. 7 - - - 6 - - - 5 - - - 4 - - - 0 0 3 DMAR3 2 DMAR2 R/W 0 0 1 DMAR1 0 DMAR0
DMAR
1: DMA software request - - - - - - - - - - 0 0 DMAB3 DMAB2 R/W 0 0 DMAB1 DMAB0
DMAB
DMA Burst Register
- 8AH -
1: DMA burst request
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3.3.6
Attention Point
The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag (Note) between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0008H and reads the interrupt vector address FFFF08H. To avoid the above problem, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1-instructions (ex. "NOP" * 1 times). If executed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register by execution of POP SR instruction, disable an interrupt by DI instruction before execution of POP SR instruction. In addition, take care as the following 2 circuits are exceptional and demand special attention.
In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H ; Switches interrupt input mode from level mode to edge mode. LD (INTCLR), 0AH ; Clears interrupt request flag. NOP ; Wait EI instruction EI The interrupt request flip-flop can only be cleared by reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register.
INT0 level mode
INTRXn
Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag. INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input change from high to low after interrupt request has been generated in level mode. (H L) INTRXn: Instruction which reads the receive buffer.
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4. Port Function
The TMP91FW60 features 83 bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 4-1 lists the functions of each port pin. Table 4-1 lists the functions of each port pin. Table 4-2 lists I/O registers and their specifications. Table 4-1 Port Functions (R: PU = with programmable pull-up resistor) (1/2)
Port Names Port0 Port1 Port2 Pin Names P00 to P07 P10 to P17 P20P27 P30 P31 Port3 P32 P33 P40 P41 Port4 P42 P43 P44 P50 P51 P52 P53 Port5 P54 P55 P56 P57 P60 P61 P62 P63 Port6 P64 P65 P66 P67 1 1 1 1 I/O I/O I/O I/O 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O 1 1 1 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Number of Pins 8 8 8 1 1 Direction I/O I/O I/O I/O I/O R Direction Setting Unit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Names for Built-in Functions AD0 to AD7 AD8 to AD15/A8 to A15 A16 to A23/A0 to A7 TB3IN0, INT3, SDA0 TB3IN1, INT4, SCL0 WAIT, TB3OUT0 TB3OUT1 CS0, SCOUT CS1, TXD2 CS2 RXD2 CS3, SCLK2, CTS2 ALE AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15
- - - - - - -
PU PU PU PU PU
- - - - - - - - - - - - - - - -
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Table 4-1 Port Functions (R: PU = with programmable pull-up resistor) (2/2)
Port Names Pin Names P70 P71 P72 Port7 P73 P74 P75 P80 P81 P82 P83 Port8 P84 P85 P86 P87 P90 P91 P92 P93 Port9 P94 P95 P96 P97 PA0 PA1 PortA PA2 PA3 PB0 PB1 PortB PB2 PB3 PZ0 PZ1 PortZ PZ2 PZ3 1 1 I/O I/O PU PU Bit Bit HWR R/W 1 1 1 1 I/O I/O Output Output 1 1 1 1 I/O I/O I/O I/O 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O Number of Pins 1 1 1 Direction I/O I/O I/O R Direction Setting Unit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Names for Built-in Functions TA0IN TA1OUT TA3OUT TA4IN TA5OUT INT0 TB0IN0, INT5 TB0IN1, INT6 TB0OUT0 TB0OUT1 TB1IN0, INT7 TB1IN1, INT8 TB1OUT0 TB1OUT1 TXD0 RXD0 SCLK0, CTS0 TXD1 RXD1 SCLK1, CTS1 XT1 XT2 TB2IN0, INT1 TB2IN1, INT2 TB2OUT0 TB2OUT1 TB4IN0, INT9, SDA1 TB4IN1, INT10, SCL1 TB4OUT0 TB4OUT1 RD WR
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
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Table 4-2
Ports
I/O Port Setting List(1/4)
I/O Register Setting Values Pin Names Specifications Pn Input port PnCR 0 1 None None None PnFC PnFC2 ODE
x x x x x x x x x x x x x x x x x x x x x x x x x
Port0
P00 to P07
Output port AD0 to AD7 bus#1 Input port Output port
x
0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 None 1 1 0 0 None 1 1 0 0 0 0 None 0 1 0 0 1 0 0 1 1 1 None None 0 1 1 0 1 1 None 0 0 0 None None
Port1
P10 to P17 AD8 to AD15 bus A8 to A15 output Input port Output port
Port2
P20 to P27 A0 to A7 output A16 to A23 output Input port P30 to P31 Output port (CMOS output) Output port (open drain output) Input port P32 to P33 Output port TB3IN0 Input, INT3 Input P30 SDA0 input/output (CMOS output) SDA0 input/output (open drain output)#2 TB3IN1 Input, INT4 Input P31 SCL0 input/output (CMOS output) SCL0 input/output (open drain output)#2 WAIT output P32 TB3OUT0 output P33 TB3OUT1 output
-
0 1
-
0 1
Port3
-
0 1
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Table 4-2
Ports
I/O Port Setting List(2/4)
I/O Register Setting Values Pin Names Specifications Pn Input port (without pull up) P40, P43 Input port (with pull up) Output port Input port (without pull up) P42, P44 Input port (with pull up) Output port Input port (without pull up) Input port (with pull up) P41 Output port (CMOS output) Output port (open drain output) CS0 output P40 0 1 PnCR 0 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 PnFC 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 None 0 1 0 0 0 1 1 0 0 1 0 0 0 0 None 1 None 1 None 1 1 None None None None None 0 0 None 1 0 None None None 0 0 0 0 0 None 1 0 0 1 1 0 1 0 1 None None PnFC2 0 0 0 None ODE
x
0 1
x
0 1
- -
0 1
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Port4
SCOUT output CS1 output (CMOS output) CS1 output (open drain output) P41 TXD2 output (CMOS output) TXD2 output (open drain output)#2 CS2 output P42 RXD2 Input CS3 output SCLK2 Input P43 SCLK2 output CTS2 Input P44 ALE output Input port
Port5
P50 to P57
Output port AN0 to AN7 Input #3 Input port
Port6
P60 to P67
Output port AN8 to AN15 Input #3 Input port
P70 to P75 Output port P70 P71 Port7 P72 P73 P74 P75 TA3OUT output TA4IN Input TA5OUT output INT0 Input TA0IN Input TA1OUT output
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Table 4-2
Ports
I/O Port Setting List(3/4)
I/O Register Setting Values Pin Names Specifications Pn Input port P80 to P87 Output port P80 P81 P82 TB0IN0, INT5 Input TB0IN1, INT6 Input TB0OUT0 output TB0OUT1 output TB1IN0, INT7 Input TB1IN1, INT8 Input TB1OUT0 output TB1OUT1 output Input port Output port Input port P90, P93 Output port (CMOS output) Output port (open drain output) TXD0 output (CMOS output) P90 TXD0 output (open drain output)#2 P91 RXD0 Input SCLK0 Input P92 SCLK0 output CTS0 Input TXD1 output (CMOS output) P93 TXD1 output (open drain output)#2 P94 RXD1 Input SCLK1 Input P95 SCLK1 output CTS1 Input Input port P96 to P97 Output port XT1 to XT2 #4 Input port PA0 to PA3 Output port PA0 TB2IN0 Input, INT1 Input TB2IN1 Input, INT2 Input TB2OUT0 TB2OUT1 PnCR 0 1 0 0 1 1 0 0 1 1 0 1 0 1 1 1 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 1 PnFC 0 0 1 1 1 None 1 1 1 1 1 0 None 0 0 0 0 1 1 None 0 1 None 0 1 1 None 0 1 0 1 1 0 0 0 1 None 1 1 1 None None None 0 1 None None None PnFC2 ODE
x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Port8 P83 P84 P85 P86 P87 P91 to P92, P94 to P95
-
0 1 0 1 None
Port9
PortA PA1 PA2 PA3
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Table 4-2
Ports
I/O Port Setting List(4/4)
I/O Register Setting Values Pin Names Specifications Pn Input port PB0 to PB1 Output port (CMOS output) Output port (open drain output) Input port PB2 to PB3 Output port TB4IN0 Input, INT9 Input PnCR 0 1 1 0 1 0 1 1 0 1 1 1 1 PnFC 0 0 0 0 None 0 1 0 0 1 0 0 1 None 1 0 None 1 1 0 None 1 None Input port (without pull up) PZ2 to PZ3 Input port (with pull up) Output port PZ2 PZ3 HWR output R/W output 0 1 0 0 1 1 0 0 0 0 1 1 None None 0 1 1 0 1 1 None PnFC2 0 0 0 ODE
x x x x x x x
#2
-
0 1
-
0 1
PortB
PB0
SDA1 input/output (CMOS output) SDA1 input/output (open drain output) TB4IN1 Input, INT10 Input
x x x x x x x
1 0
-
0 1
PB1
SCL1 input/output (CMOS output) SCL1 input/output (open drain output)#2
PB2 PB3
TB4OUT0 output TB4OUT1 output Output port
PZ0
RD output only when accessing an external Always RD output Output port
PZ1 WR output only when accessing an external PortZ
x x
x x x
#1 #2 #3 #4
There is not port setting for changing AD0 to AD7. When accessing external area, it changes automatically. If using P30/P31/P41/P90/P93/PB0/PB1 as open-drain output in SDA0/SCL0/TXD2/TXD0/TXD1/SDA1/SCL1 output, please set ODE. If using P50 to P57,P60 to P67 as an analog input, please set ADCCR1. If using P96 to P97 as XT1-XT2, please set SYSCR0.
Note:
x:Don't care
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4.1 Port 0 (P00 to P07)
Port 0 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P0CR. Reset operation initializes all bits of the control register P0CR to "0" and sets port 0 to input port. In addition to functioning as a general-purpose I/O port, port 0 can also function as address data bus (AD0 to AD7). When accessing external area, port 0 functions as address data bus (AD0 to AD7) automatically, and P0CR is cleared to "0".
Reset
Direction control (on bit basis)
Internal data bus
P0CR write Port 0 P00 to P07 (AD0 to AD7) Output buffer P0 write S B A P0 read
Figure 4-1 Port 0
Port 0 Register
7 Bit symbol P0 (0000H) Read/Write After reset P07 6 P06 5 P05 4 P04 R/W Data from external port (Output latch register is undefined.) 3 P03 2 P02 1 P01 0 P00
Port 0 Control Register
(Read-modify-write instructions are prohibited.) 7 6 P06C 5 P05C 4 P04C W 0 0 0 0 0 0 0 0 3 P03C 2 P02C 1 P01C 0 P00C
Bit symbol P0CR (0002H) Read/Write After reset Function
P07C
0: Input 1: Output (When access to external, become AD7 to AD0 and this register is cleared to "0".)
access
P0xC 0
P07 function input port output port AD7
P06 function input port output port AD6
P05 function input port output port AD5
P04 function input port output port AD4
P03 function input port output port AD3
P02 function input port output port AD2
P01 function input port output port AD1
P00 function input port output port AD0
internal 1 external cleared to "0"
Note: is bit X of each register P0CR.
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4.2 Port 1 (P10 to P17)
Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR and function register P1FC. Reset operation initializes all bits of output latch P1, the control register P1CR and function register P1FC to "0" and sets port 1 to input port. In addition to functioning as a general-purpose I/O port, port 1 can also function as address data bus (AD8 to AD15) and address bus (A8 to A15).
Reset
Direction control (on bit basis)
P1CR write
Function control (on bit basis)
Internal data bus
P1FC write
P10 to P17 (AD8 to AD15/A8 to A15 P1 write S B A P1 read
Figure 4-2 Port 1
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Port 1 Register
7 P1 (0001H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W Data from external port (Output latch register is cleared to "0".) 3 P13 2 P12 1 P11 0 P10
Port 1 Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P1CR (0004H) Read/Write After reset Function 0 0 0 0 P17C 6 P16C 5 P15C 4 P14C W 0 0 0 0 3 P13C 2 P12C 1 P11C 0 P10C
<>
Port 1 Function Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P1FC (0005H) Read/Write After reset Function 0 0 0 0 P17F 6 P16F 5 P15F 4 P14F W 0 0 0 0 3 P13F 2 P12F 1 P11F 0 P10F
P1FC/P1CR = 00: Input, 01: Output, 10: AD15 to AD8, 11: A15 to A8
P1xF 0 0 1 1
P1xC 0 1 0 1
P17 function input port output port AD15 A15
P16 function input port output port AD14 A14
P15 function input port output port AD13 A13
P14 function input port output port AD12 A12
P13 function input port output port AD11 A11
P12 function input port output port AD10 A10
P11 function input port output port AD9 A9
P10 function input port output port AD8 A8
Note:/ is bit X of each register P1FC/P1CR.
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4.3 Port 2 (P20 to P27)
Port 2 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P2CR and function register P2FC. Reset operation initializes all bits of output latch P2 to "1", and the control register P2CR and function register P2FC to "0", and sets port 2 to input port. In addition to functioning as a general-purpose I/O port, port 2 can also function as address bus (A0 to A5) and address bus (A16 to A23).
A0 to A7
A
S
Direction control (on bit basis) P2CR Function control (on bit basis) P2FC B A S Selector P20~P27 (A0~A7/A16~A23)
Internal data bus
P2 S B A P2
Selector
A16 to A23
B
Figure 4-3 Port 2
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Port 2 Register
7 P2 (0006H) Bit symbol Read/Write After reset P27 6 P26 5 P25 4 P24 R/W Data from external port (Output latch register is set to "1".) 3 P23 2 P22 1 P21 0 P20
Port 2 Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P2CR (0008H) Read/Write After reset Function 0 0 0 0 P27C 6 P26C 5 P25C 4 P24C W 0 0 0 0 3 P23C 2 P22C 1 P21C 0 P20C
<>
Port 2 Function Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P2FC (0009H) Read/Write After reset Function 0 0 0 0 P27F 6 P26F 5 P25F 4 P24F W 0 0 0 0 3 P23F 2 P22F 1 P21F 0 P20F
P2FC/P2CR = 00: Input, 01: Output, 10: A7 to A0, 11: A23 to A16
P2xF 0 0 1 1
P2xC 0 1 0 1
P27 function input port output port A7 A23
P26 function input port output port A6 A22
P25 function input port output port A5 A21
P24 function input port output port A4 A20
P23 function input port output port A3 A19
P22 function input port output port A2 A18
P21 function input port output port A1 A17
P20 function input port output port A0 A16
Note: / is bit X of each register P2FC/P2CR. When setting to address bus A23 to A16, set P2FC after setting P2CR. If P2CR is set after setting P2FC, A7 to A0 are outputted between setting P2FC and setting P2CR when P2CR is "0".
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4.4 Port3 (P30 to P33)
Port 3 is an 4-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register P3 are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port 3 function register P3FC. *The input function of wait control (WAIT) *The input function of external interrupt (INT3, INT4) *The input function of 16-bit timer 3 (TB3IN0, TB3IN1) *The output function of 16-bit timer 3 (TB3OUT0, TB3OUT1) *The I/O function of serial bus interface 0 (SDA0, SCL0) Reset operation initializes, P3CR,P3FC and P3FC2 to "0", all bits are set to input port. And Port 30 and 31 have a programmable open-drain function which can be controlled by the ODE register.
Direction control (on bit basis)
P3CR write
Function control 2 (on bit basis) Internal data bus P3FC2 write
S
A
S
Open-drain possible: ODE
P3 write
B
P30(TB3IN0,INT3,SDA0) P31(TB3IN1,INT4,SCL0)
SDA0 SCL0
Function control (on bit basis) P3FC write
SB
P3 TB3IN0,INT3 TB3IN1,INT4 SDA0 SCL0
A
Figure 4-4 Port 30 and 31
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Direction control (on bit basis)
P3CR
Function control (on bit basis)
Internal data bus
P3FC S
A
S P32( WAIT ,TB3OUT0)
P3 TB3OUT0
B
SB
P3
WAIT
A
Direction control (on bit basis)
P3CR
(
) P3FC write S
Internal data bus
A
S P33(TB3OUT1)
P3 TB3OUT1
B
SB
P3
A
Figure 4-5 Port 32 and 33
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Port 3 Register
7 P3 (000CH) Bit symbol Read/Write After reset Function 6 5 4 3 P33 2 P32 R/W Data from external port (Output latch register is set to "1".) output mode 1 P31 0 P30
- - -
- - -
-
- - -
- - -
Port 3 Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P3CR (000EH) Read/Write After reset Function 6 5 4 3 P33C 2 P32C W 0 0 0 0 1 P31C 0 P30C
- - -
- - -
-
- - -
- - -
0:Input 1:Output
Port 3 Function Register (Read-modify-write instructions are prohibited.)
7 P3FC (000FH) Bit symbol Read/Write After reset 6 5 4 3 P33F 2 P32F W 0 0 0 0 1 P31F 0 P30F
- - -
- - -
- - -
- - -
Port 3 Function Register 2 (Read-modify-write instructions are prohibited.)
7 P3FC2 (000DH) Bit symbol Read/Write After reset 6 5 4 3 2 1 P31F2 W 0 0 0 P30F2
- - -
- - -
- - -
- - -
- - -
- - -
P3xF2 0 0 0 0 1 1 1 1
P3xF 0 0 1 1 0 0 1 1
P3xC 0 1 0 1 0 1 0 1
P33 function input port output port reserved TB3OUT1 reserved reserved reserved reserved
P32 function input port output port WAIT TB3OUT0 reserved reserved reserved reserved
P31 function input port output port TB3IN1/INT4 reserved reserved SCL0 reserved reserved
P30 function input port output port TB3IN0/INT3 reserved reserved SDA0 reserved reserved
Note 1: // is bit X of each register P3FC2/P3FC/P3CR. Note 2: Wen P32/WAIT pin is used as a WAIT pin, set P3CR to "0" and Chip Select/WAIT control register to "010".
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4.5 Port 4 (P40 to P44)
Port 4 is an 5-bit general-purpose I/O port. Reset operation initializes to input port, and connects a pull-up resistor. All bits of output latch register P4 are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port 4 function register P4FC. *The output function of a chip select signal (CS0 to CS3) *The I/O function of the serial channel 2 (RXD2, TXD2, SCLK2/CTS2) *The output function of an Address latch enable signal (ALE) *The output function of a system clock signal (SCOUT) Reset operation initializes, P4CR,P4FC and P4FC2 to "0", all bits are set to input port. And Port 41 have a programmable open-drain function which can be controlled by the ODE register.
Reset
Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write Internal data bus
Function control 2 (on bit basis) P-ch P4FC2 write
(Programmable pull up)
Selector
Output buffer
P4 write
P4 read
Figure 4-6 Port 40
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Reset
Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write Internal data bus Function control 2 (on bit basis) P4FC2 write Open-drain possible: ODE P-ch
(Programmable pull up)
P4 write
P4 read
Figure 4-7 Port 41
Selector
=0 Output buffer L Level output H Level output pull-up OFF ON
Input (internal signal) =0,CS1=0, TXD2=0 =1, CS1=1, TXD2=1
=1 Output buffer L Level output Hi-z pull-up OFF ON
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Reset
Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write P-ch
(Programmable pull up)
Internal data bus
Selector
Output buffer
P4 write
P4 read
Figure 4-8 Port 42
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Reset
Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write Internal data bus
Function control 2 (on bit basis) P-ch P4FC2 write
(Programmable pull up)
Selector
Output buffer
P4 write
P4 read
Figure 4-9 Port 43
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Reset
Direction control (on bit basis) P4CR write Function control (on bit basis) P4FC write P-ch
(Programmable pull up)
Internal data bus
Selector
Output buffer
P4 write
P4 read
Figure 4-10 Port 44
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Port 4 Register
7 P4 (0010H) Bit symbol Read/Write After reset 6 5 4 P44 3 P43 2 P42 R/W Data from external port (Output latch register is set to "1".) 0 (Output latch register): Pull-up resistor OFF 1 (Output latch register): Pull-up resistor ON 1 P41 0 P40
- - -
- - -
- - -
Function
Port 4 Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P4CR (0012H) Read/Write After reset Function 6 5 4 P44C 3 P43C 2 P42C W 0 0 0 0: Input 1: Output 0 0 1 P41C 0 P40C
- - -
- - -
- - -
Port 4 Function Register (Read-modify-write instructions are prohibited.)
7 P4FC (0013H) Bit symbol Read/Write After reset 6 5 4 P44F 3 P43F 2 P42F W 0 0 0 0 0 1 P41F 0 P40F
- - -
- - -
- - -
Port 4 Function Register 2 (Read-modify-write instructions are prohibited.)
7 P4FC2 (0011H) Bit symbol Read/Write After reset 6 5 4 3 P43F2 W 0 2 1 P41F2 W 0 0 0 P40F2
- - -
- - -
- - -
- - -
- - -
P4xF2
P4xF
P4xC
P44 function input port output port reserved ALE output input port output port reserved ALE output
P43 function input port (SCLK2/CTS2) output port reserved CS3 reserved SCLK2 reserved reserved
P42 function input port (RXD2) output port reserved CS2 input port (RXD2) output port reserved CS2
P41 function input port output port reserved CS1 reserved TXD2 reserved reserved
P40 function input port output port reserved CS0 reserved SCOUT reserved reserved
0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Note 1: // is bit X of each register P4FC2/P4FC/P4CR. Note 2: When port 4 is used as input mode, P4 register controls internal pull-up resistor. Read-modify-write instruction is prohibited in input mode or I/O mode. Setting the internal pull-up resistor may be depended on the states of the input pin. Note 3: When outputting chip select signal (CS0 to CS3), set bit of control register (P4CR) to "1" after setting bit of function register (P4FC) to "1". If P4FC is set after setting P4CR, value of P4 register is outputted between setting P4CR and setting P4FC. Note 4: When setting TXD2 pin to open-drain output, write "1" to bit2 of ODE register. P42/RXD2 pin does not have a register which changes Port/Function. For example, when it is also used as an input port, the input signal is inputted to SIO as serial receiving data.
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4.6 Port 5 (P50 to P57)
Port 5 is an 8-bit general-purpose I/O port. By the reset action, it becomes Hi-Z and becomes analog input permission.All bits of output latch register P5 are set to "1". There are the following functions in addition to an I/O port. *The input function of the Analog/Digital Converter (AN0 to AN7) Reset operation initializes, P5CR,P5FC to "0", all bits are set to input port.
Reset Direction control (on bit basis) P5CR write Function control (on bit basis) P5FC write
Internal data bus
S
P5 write P5 read
S
Port 5 P50 to P57 (AN0 to AN7)
B
A
AD
AD read
Figure 4-11 Port 5
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Port 5 Register
7 P5 (0014H) Bit symbol Read/Write After reset P57 6 P56 5 P55 4 P54 R/W Data from external port (Output latch register is set to "1".) 3 P53 2 P52 1 P51 0 P50
Port 5 Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P5CR (0016H) Read/Write After reset Function 0 0 0 0 P57C 6 P56C 5 P55C 4 P54C W 0 0 0 0 3 P53C 2 P52C 1 P51C 0 P50C
0: Input 1: Output
Port 5 Function Register (Read-modify-write instructions are prohibited.)
7 Bit symbol Read/Write P5FC (0017H) After reset 0 P57 input 0:disable 1:enable 0 P56 input 0:disable 1:enable 0 P55 input 0:disable 1:enable 0 P54 input 0:disable 1:enable P57F 6 P56F 5 P55F 4 P54F W 0 P53 input 0:disable 1:enable 0 P52 input 0:disable 1:enable 0 P51 input 0:disable 1:enable 0 P50 input 0:disable 1:enable 3 P53F 2 P52F 1 P51F 0 P50F
Function
P5xF 0 0 1 1
P5xC 0 1 0 1
P57 function input disable output port input enable output port
P56 function input disable output port input enable output port
P55 function input disable output port input enable output port
P54 function input disable output port input enable output port
P53 function input disable output port input enable output port
P52 function input disable output port input enable output port
P51 function input disable output port input enable output port
P50 function input disable output port input enable output port
Note 1: / is bit X of each register P5FC/P5CR. Note 2: The input channel selection of AD converter are set by AD converter mode register ADCCR1.
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4.7 Port 6 (P60 to P67)
Port 6 is an 8-bit general-purpose I/O port. By the reset action, it becomes Hi-Z and becomes analog input permission.All bits of output latch register P6 are set to "1". There are the following functions in addition to an I/O port. *The input function of the Analog/Digital Converter (AN8 to AN15) Reset operation initializes, P6CR,P6FC to "0", all bits are set to input port.
Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P6FC write
Internal data bus
S
S
P6 write P6 read
B
Port 6 P60 to P67 (AN8 to AN15)
A
AD
AD read
Figure 4-12 Port 6
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Port 6 Register
7 P6 (0018H) Bit symbol Read/Write After reset P67 6 P66 5 P65 4 P64 R/W Data from external port (Output latch register is set to "1".) 3 P63 2 P62 1 P61 0 P60
Port 6 Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P6CR (001AH) Read/Write After reset Function 0 0 0 0 P67C 6 P66C 5 P65C 4 P64C W 0 0 0 0 3 P63C 2 P62C 1 P61C 0 P60C
0: Input 1: Output
Port 6 Function Register (Read-modify-write instructions are prohibited.)
7 Bit symbol Read/Write P6FC (001BH) After reset 0 P67 input 0:disable 1:enable 0 P66 input 0:disable 1:enable 0 P65 input 0:disable 1:enable 0 P64 input 0:disable 1:enable P67F 6 P66F 5 P65F 4 P64F W 0 P63 input 0:disable 1:enable 0 P62 input 0:disable 1:enable 0 P61 input 0:disable 1:enable 0 P60 input 0:disable 1:enable 3 P63F 2 P62F 1 P61F 0 P60F
Function
P6xF 0 0 1 1
P6xC 0 1 0 1
P67 function input disable output port input enable output port
P66 function input disable output port input enable output port
P65 function input disable output port input enable output port
P64 function input disable output port input enable output port
P63 function input disable output port input enable output port
P62 function input disable output port input enable output port
P61 function input disable output port input enable output port
P60 function input disable output port input enable output port
Note 1: / is bit X of each register P6FC/P6CR. Note 2: The input channel selection of AD converter are set by AD converter mode register ADCCR1.
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4.8 Port 7 (P70 to P75)
Port 7 is an 6-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register P7 are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port 7 function register P7FC. *The I/O function of 8-bit timer 01 (TA0IN,TA1OUT) *The output function of 8-bit timer 23 (TA3OUT) *The I/O function of 8-bit timer 45 (TA4IN,TA5OUT) *The input function of external interrupt (INT0) Reset operation initializes, P7CR and P7FC to "0", all bits are set to input port.
Direction control (on bit basis) P7CR S P70 (TA0IN) P73 (TA4IN)
P7
SB A
TA0IN TA4IN
P7
Internal data bus
Direction control (on bit basis) P7CR Function control (on bit basis) P7FC S AS B P7 F/F OUT
TA1OUT: TMRA1 TA3OUT: TMRA3 TA5OUT: TMRA5
P71 (TA1OUT) P72 (TA3OUT) P74 (TA5OUT)
B S P7
Figure 4-13 Port 70 to 74
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Direction control (on bit basis) Internal data bus P7CR Function control (on bit basis) P7FC
S Output latch
P7
P75(INT0)
S
B
Selector P7
A
&
IIMC
Figure 4-14 Port 75
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Port 7 Register
7 P7 (001CH) Bit symbol Read/Write After reset 6 5 P75 4 P74 3 P73 R/W Data from external port (Output latch register is set to "1".) 2 P72 1 P71 0 P70
- - -
- - -
Port 7 Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P7CR (001EH) Read/Write After reset Function 6 5 P75C 4 P74C 3 P73C W 0 0 0 0 0 0 2 P72C 1 P71C 0 P70C
- - -
- - -
0: Input 1: Output
Port 7 Function Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P7FC (001FH) Read/Write After reset Function 6 5 P75F W 0 0: port 1: INT0 0 0: port 1: TA5OUT 4 P74F 3 2 P72F W 0 0: port 1: TA3OUT 0 0: port 1: TA1OUT 1 P71F 0
- - -
- - -
- - -
- - -
P75 INT0 setting
1 1 1 1 0 0 1 1 0 1 0 1 INT0 Rising edge detect INT falling edge detect INT H level INT L level INT
P7xF
P7xC
P75 function input port output port INT0 reserved
P74 function input port output port reserved TA5OUT
P73 function input port (TA4IN) output port reserved reserved
P72 function input port output port reserved TA3OUT
P71 function input port output port reserved TA1OUT
P70 function input port (TA0IN) output port reserved reserved
0 0 1 1
0 1 0 1
Note 1: / is bit X of each register P7FC/P7CR. Note 2: P70/TA0IN, P73/TA4IN pin dose not have a register changing PORT/FUNCTION. For example, when it is used as an input port, the input signal is inputted to 8bit Timer.
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4.9 Port 8 (P80 to P87)
Port 8 is an 8-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register P8 are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port 8 function register P8FC. *The I/O function of 16-bit timer 0 (TB0IN0,TB0IN1,TB0OUT0,TB0OUT1) *The I/O function of 16-bit timer 1 (TB1IN0,TB1IN1,TB1OUT0,TB1OUT1) *The input function of external interrupt (INT5 to INT8) Reset operation initializes, P8CR and P8FC to "0", all bits are set to input port.
Direction control (on bit basis) P8CR Function control (on bit basis) P8FC S P80 (TB0IN0/INT5) P81 (TB0IN1/INT6) P84 (TB1IN0/INT7) P85 (TB1IN1/INT8) SB A
P8
Internal data bus
P8 TB0IN0, INT5 TB0IN1, INT6 TB1IN0, INT7 TB1IN1, INT8
Direction control (on bit basis) P8CR Function control (on bit basis) P8FC S AS B P8 F/F OUT
TB0OUT0: TMRB0 TB0OUT1: TMRB0 TB1OUT0: TMRB1 TB1OUT1: TMRB1
P82 (TB0OUT0) P83 (TB0OUT1) P86 (TB1OUT0) P87 (TB1OUT1)
B S
P8
Figure 4-15 Port 8
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Port 8 Register
7 P8 (0020H) Bit symbol Read/Write After reset P87 6 P86 5 P85 4 P84 R/W Data from external port (Output latch register is set to "1".) 3 P83 2 P82 1 P81 0 P80
Port 8 Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P8CR (0022H) Read/Write After reset Function 0 0 0 0 P87C 6 P86C 5 P85C 4 P84C W 0 0 0 0 3 P83C 2 P82C 1 P81C 0 P80C
0: Input 1: Output
Port 8 Function Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P8FC (0023H) Read/Write After reset 0 0: port 1: TB1OUT1 0 0: port 1: TB1OUT0 0 0: port 1: TB1IN1, INT8 0 0: port 1: TB1IN0, INT7 P87F 6 P86F 5 P85F 4 P84F W 0 0: port 1: TB0OUT1 0 0: port 1: TB0OUT0 0 0: port 1: TB0IN1, INT6 0 0: port 1: TB0IN0, INT5 3 P83F 2 P82F 1 P81F 0 P80F
Function
P8xF 0 0 1 1
P8xC 0 1 0 1
P87 function input port output port reserved TB1OUT1
P86 function input port output port reserved TB1OUT0
P85 function input port output port TB1IN1/ INT8 reserved
P84 function input port output port TB1IN0/ INT7 reserved
P83 function input port output port reserved TB0OUT1
P82 function input port output port reserved TB0OUT0
P81 function input port output port TB0IN1/ INT6 reserved
P80 function input port output port TB0IN0/ INT5 reserved
Note: / is bit X of each register P8FC/P8CR.
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4.10 Port 9 (P90 to P97)
* Port 90 to 95 Port 90 to 95 are a 6-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register are set to "1". In addition to functioning as a I/O port, port 90 to 95 can also function as I/O of SIO0, SIO1. This function enable each function by writing "1" to applicable bit of port 9 function register P9FC. Reset operation initializes P9CR and P9FC to "0", all bits are set to input port. * Port 96 to 97 Port 96 to 97 are a 2-bit general-purpose I/O port. In case of output port, this is open drain output. Reset operation initializes output latch register and control register to "1", and it is set to "High-Z" (High impedance). In addition to functioning as a I/O port, port 96 to 97 can also function as low-frequency oscillator connection pin (XT1 and XT2) during using low speed clock function. Therefore, dual clock function can use by setting of system clock control registers SYSCR0 and SYSCR1.
4.10.1 Port 90 and 93 (TXD0 and TXD1)
In addition to functioning as a I/O port, Port 90 and 93 can also function as TXD output pin of serial channel. And Port 90 and 93 have a programmable open-drain function which can be controlled by the ODE register.
Direction control (on bit basis) P9CR Internal data bus Function control (on bit basis) P9FC S AS B P9 TXD0, TXD1 SB A P9 Open-drain possible: ODE P90 (TXD0) P93 (TXD1)
Figure 4-16 Port 90 and 93
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4.10.2 Port91(RXD0), 94 (RXD1)
In addition to functioning as a I/O port, port 91 and 94 can also function as RXD input pin of serial channel.
Direction control (on bit basis) P9CR Internal data bus S
P91 (RXD0) P94 (RXD1)
P9 SB A
P9 RXD0, RXD1
Figure 4-17 Port 91 and 94
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4.10.3 Port 92(CTS0/SCLK0), 95 (CTS1/SCLK1)
In addition to functioning as a I/O port, port 92 and 95 can also function as CTS input pin or SCLK I/O pin of serial channel.
Direction control (on bit basis) P9CR Internal data bus Function control (on bit basis) P9FC S AS B P9 SCLK0, SCLK1 SB P9 CTS0, CTS1 SCLK0, SCLK1 A P92 (SCLK0/CTS0) P95 (SCLK1/CTS1)
Figure 4-18 Port 92 and 95
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4.10.4 Port 96 (XT1), 97 (XT2)
In addition to functioning as a I/O port, port 96 and 97 can also function as low frequency oscillator connection pins.
Function control (on bit basis)
Direction control (on bit basis)
Internal data bus
Function control (on bit basis)
Direction control (on bit basis)
Figure 4-19 Port 96 and 97
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Port 9 Register
7 P9 (0024H) Bit symbol Read/Write After reset P97 6 P96 5 P95 4 P94 R/W Data from external port (Output latch register is set to "1".) 3 P93 2 P92 1 P91 0 P90
Port 9 Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol P9CR (0026H) Read/Write After reset Function 1 1 0 0 P97C 6 P96C 5 P95C 4 P94C W 0 0 0 0 3 P93C 2 P92C 1 P91C 0 P90C
0: Input 1: Output
Port 9 Function Register (Read-modify-write instructions are prohibited.)
7 Bit Symbol P9FC (0027H) Read/Write After reset 0 Port 0: disable 1: enable P97F 6 P96F W 0 Port 0: disable 1: enable 0 0: port 1: SCLK1 output 5 P95F 4 - - - 0 0: port 1: TXD1 output 3 P93F W 0 0: port 1: SCLK0 output 2 P92F 1 - - - 0 P90F W 0 0: port 1: TXD0 output
Function
P9xF 0 0 1 1
P9xC 0 1 0 1
P97 function XT2 reserved input port output port
P96 function XT1 reserved input port output port
P95 function input port output port reserved SCLK1
P94 function input port output port reserved reserved
P93 function input port output port reserved TXD1
P92 function input port output port reserved SCLK0
P91 function input port output port reserved reserved
P90 function input port output port reserved TXD0
Note 1: / is bit X of each register P9FC/P9CR. Note 2: When setting TXD pin to open-drain output, write "1" to bit3 of ODE register (for TXD0 pin), or bit4 (for TXD1 pin). P91/ RXD0 and P94/RXD1 pin does not have a register which changes Port/Function. For example, when it is also used as an input port, the input signal is inputted to SIO as serial receiving data. Note 3: Low frequency oscillation circuit To connect a low frequency resonator to port 96 and 97, it is necessary to set a following procedure to reduce the consumption power supply. (Case of resonator connection) P9CR = "11", P9 = "00" (Case of external clock input) P9CR = "11", P9 = "10"
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4.11 Port A (PA0 to PA3)
Port A is an 4-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register PA are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port A function register PAFC. *The I/O function of 16-bit timer 2 (TB2IN0,TB2IN1,TB2OUT0,TB2OUT1) *The input function of external interrupt (INT1, INT2) Reset operation initializes, PACR and PAFC to "0", all bits are set to input port.
Direction control (on bit basis) PACR Function control (on bit basis) PAFC S PA0 (TB2IN0/INT1) PA1 (TB2IN1/INT2)
PA
SB A
Internal data bus
PA TB2IN0, INT1 TB2IN1, INT2
Direction control (on bit basis) PACR Function control (on bit basis) PAFC S AS B PA F/F OUT
TB02UT0: TMRB2 TB02UT1: TMRB2
PA2 (TB2OUT0) PA3 (TB2OUT1)
B S
PA
Figure 4-20 Port A
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Port A Register
7 PA (0028H) Bit symbol Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 3 PA3 2 PA2 R/W Data from external port (Output latch register is set to "1".) 1 PA1 0 PA0
Port A Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol PACR (002AH) Read/Write After reset Function - - - - 6 - - - - 5 - - - - 4 - - - - 0 0 3 PA3C 2 PA2C W 0 0 1 PA1C 0 PA0C
0: Input 1: Output
Port A Function Register (Read-modify-write instructions are prohibited.)
7 Bit symbol PAFC (002BH) Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 0 0: port 1: TB2OUT1 0 0:port 1: TB2OUT0 3 PA3F 2 PA2F W 0 0: port 1: TB2IN1, INT2 0 0: port 1: TB2IN0, INT1 1 PA1F 0 PA0F
Function
-
-
-
-
PAxC 0 0 1 1
PAxF 0 1 0 1
PA3 function input port output port reserved TB2OUT1
PA2 function input port output port reserved TB2OUT0
PA1 function input port output port TB2IN1/ INT2 reserved
PA0 function input port output port TB2IN0/INT1 reserved
Note: / is bit X of each register PAFC/PACR.
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4.12 Port B (PB0 to PB3)
Port B is an 4-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register PB are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port B function register PBFC. *The I/O function of 16-bit timer 4 (TB4IN0,TB4IN1,TB4OUT0,TB4OUT1) *The input function of external interrupt (INT9, INT10) *The I/O function of serial bus interface 1 (SDA1, SCL1) Reset operation initializes, PBCR and PBFC to "0", all bits are set to input port.
Direction control (on bit basis)
PBCR write
Function control 2 (on bit basis) Internal data bus PBFC2 write
S
A
S
Open-drain possible: ODE
PB write
B
PB0(TB4IN0,INT9,SDA1) PB1(TB4IN1,INT10,SCL1)
SDA1 SCL1
Function control (on bit basis) PBFC write
SB
PB TB4IN0,INT9 TB4IN1,INT10 SDA1 SCL1
A
Figure 4-21 Port B0 and B1
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Direction control (on bit basis)
PBCR write
Function control (on bit basis)
Internal data bus
PBFC write S
A
S PB2(TB4OUT0) PB3(TB4OUT1)
PB write TB4OUT0 TB4OUT1
B
SB
PB
A
Figure 4-22 Port B2 and B3
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Port B Register
7 PB (002CH) Bit symbol Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 3 PB3 2 PB2 R/W Data from external port (Output latch register is set to "1".) 1 PB1 0 PB0
Port B Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol PBCR (002EH) Read/Write After reset Function - - - - 6 - - - - 5 - - - - 4 - - - - 0 0 3 PB3C 2 PB2C W 0 0 1 PB1C 0 PB0C
0: Input 1: Output
Port B Function Register (Read-modify-write instructions are prohibited.)
7 Bit symbol PBFC (002FH) Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 0 0 3 PB3F 2 PB2F W 0 0 1 PB2F 0 PB0F
Port B Function Register 2 (Read-modify-write instructions are prohibited.)
7 Bit symbol PBFC2 (002DH) Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 3 - - - 2 - - - 0 1 PB1F2 W 0 0 PB0F2
PBxC 0 1 0 1 0 1 0 1
PBxF 0 0 1 1 0 0 1 1
PBxF2 0 0 0 0 1 1 1 1
PB3 function input port output port reserved TB4OUT1 reserved reserved reserved reserved
PB2 function input port output port reserved TB4OUT0 reserved reserved reserved reserved
PB1 function input port output port TB4IN1/INT10 reserved reserved SCL1 reserved reserved
PB0 function input port output port TB4IN0/INT9 reserved reserved SDA1 reserved reserved
Note: / is bit X of each register PBFC/PBCR.
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4.13 Port Z (PZ0 to PZ3)
Port Z is a 4-bit general-purpose I/O port (however PZ0 and PZ1 are only output port). Each bit can be set individually for input or output using the control register PZCR and function register PZFC. Reset operation initializes all bits of output latch PZ to "1", and the control register PZCR and function register PZFC to "0". And PZ0 and PZ1 output "High", and sets PZ2 and PZ3 to input port with pull-up resister. In addition to functioning as a general-purpose I/O port, port Z can also function as the output for the CPU's control/status signal. If PZ0 is defined as RD signal output mode ( = "1") and the output latch register is cleared to "0", RD strobe of PZ0 is outputted (for pseudo static RAM) even when accessing internal address. If remains "1", RD strobe signal is output only when external address area is accessed.
Direction control (on bit basis) PZFC S S Selector A B PZ Output buffer
PZ0 (RD) PZ1 (WR)
RD, WR PZ
Figure 4-23 Port Z0 and Z1
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Reset Direction control (on bit basis)
PZCR write
Internal data bus Function control (on bit basis)
PZFC write S
Selector
P-ch
(Programmable pull up)
S
A B
PZ2( HWR )
Output buffer
PZ write
HWR
PZ read
Reset
Direction control (on bit basis)
PZCR write
Internal data bus Function control (on bit basis)
PZFC write S
Selector
P-ch
(Programmable pull up)
S
A B
PZ3(R/ W )
Output buffer
PZ write R/ W
PZ read
Figure 4-24 Port Z2 and Z3
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Port Z Register
7 PZ (007DH) Bit symbol Read/Write - - 6 - - 5 - - 4 - - 3 PZ3 2 PZ2 R/W Data from external port (Output latch register is set to "1".) 0 (Output latch register): Pull-up resistor OFF 1 (Output latch register): Pull-up resistor ON 1 PZ1 0 PZ0
After reset
-
-
-
-
1
1
Function
-
output mode
Port Z Control Register (Read-modify-write instructions are prohibited.)
7 Bit symbol PZCR (007EH) Read/Write After reset Function - - - 6 - - - - 5 - - - 4 - - - 0 3 PZ3C W 0 2 PZ2C 1 - - - 0 - - -
0:Input 1:Output
Port Z Function Register (Read-modify-write instructions are prohibited.)
7 Bit symbol PZFC (007FH) Read/Write After reset Function - - - - 6 - - - - 5 - - - - 4 - - - - 0 0: port 1:R/ W 0 0: port 1: HWR 3 PZ3F 2 PZ2F W 0 0: port 1: WR 0 0: port 1: RD 1 PZ1F 0 PZ0F
PZxF 0 0 0 0 1
PZxC 0 0 1 1 0
PZx 0 1 0 1 0
PZ3 function input port input port output port output port R/W
PZ2 function input port input port output port output port reserved
PZ1 function Output "0". Output "1". Output "0". Output "1". WR is output only during external accesses. WR is output only during external accesses. WR is output only during external accesses. WR is output only during external accesses.
PZ0 function Output "0". Output "1". Output "0". Output "1". Always output RD.(Correspond to pseudo SRAM) RD is output only during external accesses. Always output RD.(Correspond to pseudo SRAM) RD is output only during external accesses.
1
0
1
R/W
reserved
1
1
0
reserved
HWR
1
1
1
reserved
HWR
Note 1: / is bit X of each register PZFC/PZCR. Note 2: When port Z is used as input mode, PZ register controls internal pull-up resistor. Read-modify-write instruction is prohibited in input mode or I/O mode. Setting the internal pull-up resistor may be depended on the states of the input pin.
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4.14 Open-drain Control
P30,P31,P41,P90,P93,PB0,PB1 can perform selection of an open-drain output per bit. Reset operation initializes all bits of the control register ODE to "0" and sets to CMOS output. Open-drain Control Register
7 ODE (003FH) Bit symbol Read/Write After reset Function 6 ODEB1 5 ODEB0 4 ODE93 3 ODE90 R/W 0 0 0 0 0: CMOS output 1:Open drain output 0 0 0 2 ODE41 1 ODE31 0 ODE30
- - -
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5. Chip Select/Wait Controller
On the TMP91FW60, four user specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 and others). The pins CS0 to CS3 (which can also function as port pins P40 to P43) are the respective output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to be output, the port 6 function register P4FC,P4FC2 must be set. The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3. The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin controlling these states is the bus wait request pin (WAIT).
5.1 Specifying an Address Area
The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to MSAR3) and memory address mask registers (MAMR0 to MAMR3). At each bus cycle, a compare operation is performed to determine if the address on the specified a location in the CS0 to CS3 area. If the result of the comparison is a match, this indicates an access to the corresponding CS area. In this case, the CS0 to CS3 pin outputs the chip select signal and the bus cycle operates in accordance with the settings in chip select/wait control registers B0CS to B3CS. (See" 5.2 Chip Select/Wait Control Registers ".)
5.1.1
Memory start address registers
The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper 8 bits (A23 to A16) of the start address in . The lower 16 bits of the start address (A15 to A0) are permanently set to 0. Accordingly, the start address can only be set in 64-Kbyte increments, starting from 000000H. Figure 5-1 shows the relationship between the start address and the start address register value.
Memory Start Address Registers (for areas CS0 to CS3)
7 MSAR0 (00C8H) MSAR1 (00CAH) MSAR2 (00CCH) MSAR3 (00CEH) Bit symbol Read/Write After reset 1 1 1 1 S23 6 S22 5 S21 4 S20 R/W 1 1 1 1 3 S19 2 S18 1 S17 0 S16
Function
Determine A23 to A16 of start address (Set start addresses for areas CS0 to CS3.)
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Start address Address 000000H 000000H 64 Kbytes 010000H 020000H 030000H 040000H 050000H 060000H to FF0000H FFFFFFH
Value in start address register (MSAR0 to MSAR3) 00H 01H 02H 03H 04H 05H 06H to FFH
Figure 5-1 Relationship between Start Address and Start Address Register Value
5.1.2
Memory address mask registers
Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set in memory start address registers MAMR0 to MAMR3. The compare operation used to determine if an address is in the CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to "0" in these registers. Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0 to CS3 areas. Accordingly, the size that can be each area is different.
Memory Address Mask Register (for CS0 area)
7 Bit symbol MAMR0 (00C9H) Read/Write After reset Function 1 1 1 1 V20 6 V19 5 V18 4 V17 R/W 1 1 1 1 3 V16 2 V15 1 V14 to V9 0 V8
Set size of CS0 area
0: Used for address compare
Note: Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes.
Memory Address Mask Register (CS1)
7 Bit symbol MAMR1 (00CBH) Read/Write After reset Function 1 1 1 1 V21 6 V20 5 V19 4 V18 R/W 1 1 1 1 3 V17 2 V16 1 V15 to V9 0 V8
Set size of CS1 area
0: Used for address compare
Note: Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes.
Memory Address Mask Register (CS2, CS3)
7 MAMR2 (00CDH) MAMR3 (00CFH) Bit symbol Read/Write After reset Function 1 1 1 1 V22 6 V21 5 V20 4 V19 R/W 1 1 1 1 3 V18 2 V17 1 V16 0 V15
Set size of CS1 area
0: Used for address compare
Note: Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes.
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TMP91FW60 5.1.3 Setting memory start addresses and address areas
Figure 5-2 shows an example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas. Set "01H" in memory start address register MSAR0 (Corresponding to the upper 8 bits of the start address). Next, calculate the difference between the start address and the anticipated end address (01FFFFH). Bits 20 to 8 of the result correspond to the mask value to be set for the CS0 area. Setting this value in memory address mask register MAMR0 sets the area size. This example sets "07H" in MAMR0 to specify a 64-Kbyte area.
0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H CS0 (64 K H
V14 ~ V9 V8
S23 S22 S21 S20 S19 S18 S17 S16
MSAR0
0
0 0
0
0
0
0 1
0
1
)
V20 V19 V18 V17 V16 V15
MSMR0
0
0
0
0
0 0
0
0
0
1
1
1 7
1
1
1
1
1
1 H
1
1
1
1
1
1
1
"07H"
64 K
Figure 5-2 Example Showing How to Set the CS0 Area
After a reset, MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to "FFH". B0CS, B1CS and B3CS are reset to "0". This disables the CS0, CS1 and CS3 areas. However, as B2CS to "0" and B2CS to "1", CS2 is enabled "002000 to FDFFFF" in TMP91FW60. Also, the bus width and number of waits specified in BEXCS are used for accessing addresses outside the specified CS0 to CS3 area.
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5.1.4
Address area size specification
Table 5-1 shows the relationship between CS area and area size. "" indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using a combination indicated by "", set the start address mask register in the desired steps starting from 000000H. If the CS2 area is set to 16 Mbytes or if two or more areas overlap, the smaller CS area number has the higher priority.
5.1.4.1
To set the area size for CS0 to 128 Kbytes:
Example: Valid
start addresses (128 Kbytes)
000000H
020000H
(128 Kbytes)
040000H
Any of these addresses may be set as the start address.
:
(128 Kbytes)
060000H
Example: Invalid
start addresses
(64 Kbytes)
000000H
010000H
(128 Kbytes)
030000H
This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address.
(128 Kbytes)
050000H :
Table 5-1
Valid Area Sizes for Each CS Area
Size (Bytes) 256 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M
CS0 CS area CS1 CS2 CS3

Note: "" indicates areas that cannot be set by memory start address register and address mask register combinations.
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5.2 Chip Select/Wait Control Registers
The master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 and others) are set in their respective chip select/wait control registers, B0CS to B3CS and BEXCS. Chip Select/Wait Control Registers
7 Bit symbol Read/Write B0CS (00C0H) RMW instructions are prohibited. After reset B0E W 0 6 0 0 0 5 B0OM1 4 B0OM0 3 B0BUS W 0 Number of waits Data bus width 0: 16 bits 1: 8 bits 000: 2 WAIT 001: 1 WAIT 010: 1 WAIT+N 011: 0 WAIT B1W2 W 0 0 0 0 Number of waits Data bus width 0: 16 bits 1: 8 bits 000: 2 WAIT 001: 1 WAIT 010: 1 WAIT+N 011: 0 WAIT B2W2 100: 101: 110: 111: Reserved 3 WAIT 4 WAIT 8 WAIT B2W0 0 0 100: 101: 110: 111: Reserved 3 WAIT 4 WAIT 8 WAIT B1W0 0 0 2 B0W2 1 B0W1 0 B0W0
Function
0: Disable 1: Enable
Chip select output waveform selection 00: For ROM/SRAM 01: Don't care 10: Don't care 11: Don't care B1OM1 B1OM0
Bit symbol Read/Write B1CS (00C1H) RMW instructions are prohibited. After reset
B1E W 0
B1BUS
B1W1
Function
0: Disable 1: Enable
Chip select output waveform selection 00: For ROM/SRAM 01: Don't care 10: Don't care 11: Don't care B2M B2OM1 B2OM0
Bit symbol Read/Write B2CS (00C2H) RMW instructions are prohibited. After reset
B2E W 1
B2BUS W
B2W1
0 CS2 area selection 0: 16-Mbyte area 1: CS area -
0
0
0
0 Number of waits
0
0
Function
0: Disable 1: Enable
Chip select output waveform selection 00: For ROM/SRAM 01: Don't care 10: Don't care 11: Don't care B3OM1 B3OM0
Data bus width 0: 16 bits 1: 8 bits
000: 2 WAIT 001: 1 WAIT 010: 1 WAIT+N 011: 0 WAIT B3W2 W
100: 101: 110: 111:
Reserved 3 WAIT 4 WAIT 8 WAIT B3W0
Bit symbol Read/Write B3CS (00C3H) RMW instructions are prohibited. After reset
B3E W 0
B3BUS
B3W1
0
0
0
0 Number of waits
0
0
Function
0: Disable 1: Enable
Chip select output waveform selection 00: For ROM/SRAM 01: Don't care 10: Don't care 11: Don't care
Data bus width 0: 16 bits 1: 8 bits
000: 2 WAIT 001: 1 WAIT 010: 1 WAIT+N 011: 0 WAIT
100: 101: 110: 111:
Reserved 3 WAIT 4 WAIT 8 WAIT
Master enable bit
BnE (n = 0 to 3) 0 1 Disable
CS2 area selection
0 B2M Enable 1 Specified address area 16-Mbyte area
Chip select output waveform selection
00 BnOM1:0 (n = 0 to 3) 01 10 11 Don't care for ROM/SRAM
Data bus width selection
BnBUS (n = 0 to EX) 0 1 16-bit data bus 8-bit data bus
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7 Bit symbol Read/Write BEXCS (00C7H) RMW instructions are prohibited. After reset - - -
6 - - -
5 - - -
4 - - -
3 BEXBUS
2 BEXW2 W
1 BEXW1
0 BEXW0
0
0 Number of waits
0
0
Function
Data bus width 0: 16 bits 1: 8 bits
000: 2 WAIT 001: 1 WAIT 010: 1 WAIT+N 011: 0 WAIT
100: 101: 110: 111:
Reserved 3 WAIT 4 WAIT 8 WAIT
Number of address area waits
BnW2:0 (n = 0 to EX) See" 5.2.3 Wait control "
5.2.1
Master enable bits
Bit7 (, , or ) of a chip select/wait control register is the master bit which is used to enable or disable settings for the corresponding address area. Writing "1" to this bit enables the settings. Reset disables (Sets to "0") , and , and enabled (Sets to "1") . This enables area CS2 only.
5.2.2
Data bus width selection
Bit3 (, , , or ) of a chip select/wait control register specifies the width of the data bus. This bit should be set to "0" when memory is to be accessed using a 16-bit data bus and to "1" when an 8-bit data bus is to be used. This process of changing the data bus width according to the address being accessed is known as "Dynamic bus sizing". For details of this bus operation see Table 5-2.
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Table 5-2 Dynamic Bus Sizing
Operand Data Bus Width Operand Start Address 2n + 0 (Even number) 8 bits 2n + 1 (Odd number) 8 bits 16 bits 8 bits 16 bits 16 bits 8 bits 2n + 1 (Odd number) 16 bits 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 2n + 1 2n + 2 2n + 4 xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 Memory Data Bus Width 8 bits 16 bits CPU Data CPU Address D15 to D8 2n + 0 2n + 0 xxxxx xxxxx D7 to D0 b7 to b0 b7 to b0
2n + 0 (Even number)
8 bits 2n + 0 (Even number) 16 bits 32 bits 8 bits 2n + 1 (Odd number) 16 bits
Note:"xxxxx" indicates that the input data from these bits are ignored during a read. During a write, indicates that the bus for these bits goes too high impedance; also, that the write strobe signal for the bus remains inactive.
5.2.3
Wait control
Bits 0 to 2 (, , , , ) of a chip select/wait control register specify the number of waits that are to be inserted when the corresponding memory area is accessed. The following types of wait operation can be specified using these bits. Bit settings other than those listed in the table should not be made. A reset sets these bit to "000" (2 waits).
Table 5-3
Wait Operation Settings
Number of Waits 2 waits 1 wait (1 + N) waits 0 waits Reserved 3 waits 4 waits 8 waits Wait Operation Inserts a wait of 2 states, irrespective of the WAIT pin state. Inserts a wait of 1 state, irrespective of the WAIT pin state. Samples the state of the WAIT pin after inserting a wait of one state. If the WAIT pin is low, the waits continue and the bus cycle is extended until the pin goes high. Ends the bus cycle without a wait, regardless of the WAIT pin state. Invalid setting Inserts a wait of 3 state, irrespective of the WAIT pin state. Inserts a wait of 4 state, irrespective of the WAIT pin state. Inserts a wait of 8 state, irrespective of the WAIT pin state.
000 001 010 011 100 101 110 111
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5.2.4
Bus width and wait control for an area other than CS0 to CS3
The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3.
5.2.5
Selecting 16-Mbyte area/specified address area
Setting B2CS (Bit6 of the chip select/wait control register for CS2) to "0" designates the 16-Mbyte area "002000 to FDFFFF" as the CS2 area. Setting B2CS to "1" designates the address area specified by the start address register MSAR2 and the address mask register MAMR2 as CS2 (e.g., if B2CS = 1, CS2 is specified in the same manner as CS0, CS1 and CS3 are). A reset clears this bit to "0", specifying CS2 as a 16-Mbyte address area.
5.2.6
Procedure for setting chip select/wait control
When using the chip select/wait control function, set the registers in the following order: 1. Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. 2. Set the memory address mask registers MAMR0 to MAMR3. Set the sizes of CS0 to CS3. 3. Set the chip select/wait control registers B0CS to B3CS. Set the chip select output waveform, data bus width, number of waits and master enable/disable status for
CS0 to CS3.
The CS0 to CS3 pins can also function as pins P40 to P43. To output a chip select signal using one of these pins, set the corresponding bit in the port 6 function register P4FC/P4FC2 to "1". If a CS0 to CS3 address is specified which is actually an internal I/O and RAM area address, the CPU accesses the internal address area and no chip select signal is output on any of the CS0 to CS3 pins.
Example :In this example CS0 is set to the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is set to 0.
LD LD LD (MSAR0), 01H (MAMR0), 07H (B0CS), 83H ; Start address: 010000H ; Address area: 64 Kbytes ; ROM/SRAM, 16-bit data bus, 0 waits, CS0 area settings enabled
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5.3 Connecting External Memory
Figure 5-3 shows an example of how to connect external memory to TMP91FW60. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus.
TMP91FW60
74AC573 DQ LE CS DQ LE
Upper byte ROM
Address bus CS CS CS
CS0 CS1 CS2 ALE
Lower byte ROM
8-bit bus RAM
8-bit bus I/O
OE
OE
OE WE
OE WE
AD8~AD15 AD0~AD7 RD WR
Figure 5-3 Example of External Memory Connection (ROM uses 16-bit bus, RAM and I/O use 8-bit bus.
A reset clears all bits of the port 4 control register P4CR and the port 4 function register P4FC/P4FC2 to "0" and disables output of the CS signal. To output the CS signal, the appropriate bit must be set to "1".
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6. 8-Bit Timers (TMRA)
The TMP91FW60 features 6 channels (TMRA0 to TMRA5) built-in 8-bit timers. These timers are paired into 3 modules: TMRA01, TMRA23 and TMRA45. Each module consists of 2 channels and can operate in any of the following 4 operating modes. * 8-bit interval timer mode * 16-bit interval timer mode * 8-bit programmable square wave pulse generation output mode (PPG - Variable duty cycle with variable period) * 8-bit pulse width modulation output mode (PWM - Variable duty cycle with constant period) Figure 6-1 to Figure 6-3 show block diagrams for TMRA01, TMRA23 and TMRA45. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by 5-byte registers SFRs (Special function registers). Each of the three modules (TMRA01, TMRA23 and TMRA45) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. Table 6-1
Specification Input pin for external clock External pin Output pin for timer flip-flop TA1OUT (Shared with P71) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TA3OUT (Shared with P72) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) TA5OUT (Shared with P74) TA45RUN (0110H) TA4REG (0112H) TA5REG (0113H) TA45MOD (0114H) TA5FFCR (0115H)
Registers and Pins for Each Module
Module TMRA01 TA0IN (Shared with P70) TMRA23 TMRA45 TA4IN (Shared with P73)
None
Timer run register
Timer register SFR (Address) Timer mode register
Timer flip-flop control register
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Prescaler 2 T1 T4 T16 T256 4 8 16 32 64 128 256 512 Run/clear TA01RUN
6.1 Block Diagrams
Prescaler clock: T0
Selector TA01RUN Selector T1 T4 T16 8-bit up counter (UC1)
n
External input clock: TA0IN 8-bit up counter (UC0) T1 T16 T256
TA01MOD
TA01RUN
Timer flip-flop TA1FF
Timer flip-flop output: TA1OUT TA1FFCR
Figure 6-1 TMRA01 Block Diagram
TA01MOD 2 overflow TA01MOD Match detect TA0TRG
TA01MOD
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8-bit comparator (CP0) 8-bit timer register TA0REG TA01RUN Register buffer 0 Internal data bus TMRA0 interrupt output: INTTA0 TMRA0 match output: TA0TRG
Match detect 8-bit comparator (CP1)
8-bit timer register TA1REG
Internal data bus
TMRA1 interrupt output: INTTA1
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Prescaler 2 T1 T4 T16 T256 4 8 16 32 64 128 256 512 Run/clear TA23RUN
Prescaler clock: T0
Selector TA23RUN Selector 8-bit up counter (UC2) 2n TA23MOD overflow TA23MOD
TA23MOD
TA23RUN 8-bit up counter (UC3)
Timer flip-flop TA3FF
Timer flip-flop output: TA3OUT TA3FFCR
T1 T4 T16 T1 T16 T256
Figure 6-2 TMRA23 Block Diagram
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8-bit comparator (CP2) 8-bit timer register TA2REG TA23RUN Register buffer 2
TA23MOD
Match detect TA2TRG
Match detect 8-bit comparator (CP3)
8-bit timer register TA3REG
Internal data bus
TMRA2 interrupt output: INTTA2
TMRA2 match output: TA2TRG
Internal data bus
TMRA3 interrupt output: INTTA3
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Prescaler 2 T1 T4 T16 T256 4 8 16 32 64 128 256 512 Run/clear TA45RUN
Prescaler clock: T0
Selector TA45RUN Selector T1 T4 T16
n
External input clock: TA4IN 8-bit up counter (UC4) T1 T16 T256
TA45MOD
TA45RUN 8-bit up counter (UC5)
Timer flip-flop TA5FF
Timer flip-flop output: TA5OUT TA5FFCR
Figure 6-3 TMRA45 Block Diagram
TA45MOD 2 overflow TA45MOD Match detect TA4TRG
TA45MOD
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8-bit comparator (CP4) 8-bit timer register TA4REG TA45RUN Register buffer 4 Internal data bus TMRA4 interrupt output: INTTA4 TMRA4 match output: TA4TRG
Match detect 8-bit comparator (CP5)
8-bit timer register TA5REG
Internal data bus
TMRA5 interrupt output: INTTA5
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6.2 Operation of Each Circuit
6.2.1 Prescalers
A 9-bit prescaler generates the input clock to TMRA01. The "T0" as the input clock to prescaler is a clock divided by 4 which is selected using the prescaler clock selection register SYSCR0. The prescaler's operation can be controlled using TA01RUN in the timer control register. Setting to "1" starts the count; setting to "0" clears the prescaler to "0" and stops operation. Table 6-2 shows the various prescaler output clock resolutions. Table 6-2 Prescaler Output Clock Resolution
@ fc = 20 MHz, fs = 32.768 kHz System Clock Selection SYSCR1 1 (fs) Prescaler Clock Selection SYSCR0 Prescaler Output Clock Resolution T1 (1/2) 23/fs (244 s) 23/fc (0.4 s) 0 (1/1) fFPH 24/fc (0.8 s) 25/fc (1.6 s) 26/fc (3.2 s) 27/fc (6.4 s) 1 (1/16) fc/16 CLOCK 27/fc (6.4 s) T4 (1/8) 25/fs (977 s) 25/fc (1.6 s) 26/fc (3.2 s) 27/fc (6.4 s) 28/fc (12.8 s) 29/fc (25.6 s) 29/fc (25.6 s) T16 (1/32) 27/fs (3.9 ms) 27/fc(6.4 s) 28/fc (12.8 s) 29/fc (25.6 s) 210/fc (51.2 s) 211/fc (102.4 s) 211/fc (102.4 s) T256 (1/512) 211/fs (62.5 ms) 211/fc (102.4 s) 212/fc (204.8 s) 213/fc (409.6 s) 214/fc (819.2 s) 215/fc (1638.4 s) 215/fc (1638.4 s)
Gear Value SYSCR1
XXX 000 (fc) 001 (fc/2) 010 (fc/4)
0 (fc)
011 (fc/8) 100 (fc/16) XXX
Note: xxx: Don't care
6.2.2
Up counters (UC0 and UC1)
These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks T1, T4, or T16. The clock setting is specified by the value set in TA01MOD. The input clock for UC1 depends on the operation mode. In 16-bit timer mode, the overflow output from UC0 is used as the input clock. In any mode other than 16-bit timer mode, the input clock is selectable and can either be one of the internal clocks T1, T16 or T256, or the comparator output (The match detection signal) from TMRA0. For each interval timer the timer operation control register bits TA01RUN and TA01RUN can be used to stop and clear the up counters and to control their count. A reset clears both up counters, stopping the timers.
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6.2.3
Timer registers (TA0REG and TA1REG)
These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN determines whether TA0REG's double buffer structure is enabled or disabled. It is disabled if = "0" and enabled if = "1". When the double buffer is enabled, data is transferred from the register buffer to the timer register when a 2n overflow occurs in PWM mode, or at the start of the PPG cycle in PPG mode. Hence the double buffer cannot be used in timer mode. A reset initializes to "0", disabling the double buffer. To use the double buffer, write data to the timer register, set to "1", and write the following data to the register buffer. Figure 6-4 shows the configuration of TA0REG.
Timer registers 0 (TA0REG)
B Y
Selector A
Shift trigger Register buffers 0 Write Internal data bus
Matching detection in PPG cycle 2n overflow PWM Write to TA0REG
S
TA01RUN
Figure 6-4 Configuration of TA0REG
Note:The same memory address is allocated to the timer register TA0REG and the register buffer 0. When = 0, the same value is written to the register buffer 0 and the timer register TA0REG; when = 1, only the register buffer 0 is written to.
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6.2.4
Comparator (CP0 and CP1)
The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time.
Note:If a value smaller than the up-counter value is written to the timer register while the timer is counting up, this will cause the timer to overflow and an interrupt cannot be generated at the expected time. (The value in the timer register can be changed without any problem if the new value is larger than the up-counter value.) In 16bit interval timer mode, be sure to write to both TA0REG and TA1REG in this order (16 bits in total), The compare circuit will not function if only the lower 8 bits are set.
6.2.5
Timer flip-flop (TA1FF)
The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR in the timer flip-flop control register. A reset clears the value of TA1FF1 to "0". Writing "01" or "10" to TA1FFCR sets TA1FF to 0 or 1. Writing "00" to these bits inverts the value of TA1FF (This is known as software inversion). The TA1FF signal is output via the TA1OUT pin (Concurrent with P71). When this pin is used as the timer output, the timer flip-flop should be set beforehand using the port 7 function registers P7CR, P7FC.
The condition for TA1FF inversion varies with mode as shown below
8-bit interval timer mode 16-bit interval timer mode 8 bit PWM mode 8 bit PPG mode : UC0 matches TA0REG or UC1 matches TA1REG (Select either one of the two) : UC0 matches TA0REG or UC1 matches TA1REG : UC0 matches TA0REG or a 2n overflow occurs : UC0 matches TA0REG or UC0 matches TA1REG
Note: If an inversion by the match-detect signal and a setting change via the TMRA1 flip-flop control register occur simultaneously, the resultant operation varies depending on the situation, as shown below.
* If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the flip-flop will be
inverted only once.
* If an inversion by the match-detect signal and an attempt to set the flip-flop to 1 via the register occur simultaneously, the timer flip-flop will be set to 1. * If an inversion by the match-detect signal and an attempt to clear the flip-flop to 0 via the register occur simultaneously the flip-flop will be cleared to 1.
Be sure to stop the timer before changing the flip-flop insertion setting. If the setting is changed while the timer is counting, proper operation cannot be obtained.
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6.3 SFR
TMRA01 Run Register
7 Bit symbol TA01RUN (0100H) Read/Write After Reset TA0RDE R/W 0 Double buffer 0: Disable 1: Enable 6 - - - 5 - - - 4 - - - 0 0 TMRA01 prescaler 3 I2TA01 2 TA01PRUN R/W 0 Up counter (UC1) 0 Up counter (UC0) 1 TA1RUN 0 TA0RUN
Function
IDLE2 0: Stop 1: Operate
0: Stop and clear 1: Run (count up)
Count operation
TA01PRUN TA1RUN / TA0RUN 0 1 Stop and clear
TA0REG double buffer control
0 TA0RDE Run (Count up) 1 Enable Disable
Note: The values of bits 4 to 6 of TA01RUN are "1" when read.
TMRA23 Run Register
7 Bit symbol TA23RUN (0108H) Read/Write After Reset TA2RDE R/W 0 Double buffer 0: Disable 1: Enable 6 - - - 5 - - - 4 - - - 0 0 TMRA23 prescaler 3 I2TA23 2 TA23PRUN R/W 0 Up counter (UC3) 0 Up counter (UC2) 1 TA3RUN 0 TA2RUN
Function
IDLE2 0: Stop 1: Operate
0: Stop and clear 1: Run (count up) TA2REG double buffer control
Count operation
TA23PRUN TA3RUN / TA2RUN 0 1 Stop and clear
0 TA2RDE 1
Disable Enable
Run (Count up)
Note: The values of bits 4 to 6 of TA23RUN are "1" when read.
TMRA45 Run Register
7 Bit symbol TA45RUN (0110H) Read/Write After Reset TA4RDE R/W 0 Double buffer 0: Disable 1: Enable 6 - - - 5 - - - 4 - - - 0 0 TMRA45 prescaler 3 I2TA45 2 TA45PRUN R/W 0 Up counter (UC5) 0 Up counter (UC4) 1 TA5RUN 0 TA4RUN
Function
IDLE2 0: Stop 1: Operate
0: Stop and clear 1: Run (count up) TA4REG double buffer control
Count operation
TA45PRUN TA5RUN / TA4RUN 0 1 Stop and clear
0 TA4RDE 1
Disable Enable
Run (Count up)
Note: The values of bits 4 to 6 of TA45RUN are "1" when read.
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TMRA01 Mode Register
7 Bit symbol TA01MOD (0104H) Read/Write After reset 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 26 10: 27 11: 28 0 TA01M1 6 TA01M0 5 PWM01 4 PWM00 R/W 0 0 0 0 3 TA1CLK1 2 TA1CLK0 1 TA0CLK1 0 TA0CLK0
Function
Input clock for TMRA1 00: TA0TRG 01: T1 10: T16 11: T256
Input clock for TMRA0 00: TA0IN pin 01: T1 10: T4 11: T16
TMRA0 input clock selection
00 01 10 11 TA0INioO T1 T4 T16
TMRA1 input clock selection
TA01MOD 01 00 01 10 11 Comparator output from TMRA0 T1 T16 T256 Overflow output from TMRA0 (16-bit timer mode) TA01MOD = 01
PWM cycle selection
00 01 10 11 Reserved 26 x Clock source 27 x Clock source 28 x Clock source
TMRA01 operation mode selection
00 01 10 11 8-bit PPG 8-bit PWM (TMRA0) + 8-bit timer (TMRA1) 8-bit timers 2ch 16-bit timer
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TMRA23 Mode Register
7 Bit symbol TA23MOD (010CH) Read/Write After reset 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 26 10: 27 11: 28 0 TA23M1 6 TA23M0 5 PWM21 4 PWM20 R/W 0 0 0 0 3 TA3CLK1 2 TA3CLK0 1 TA2CLK1 0 TA2CLK0
Function
Input clock for TMRA3 00: TA2TRG 01: T1 10: T16 11: T256
Input clock for TMRA2 00: Reserved 01: T1 10: T4 11: T16
TMRA2 input clock selection
00 01 10 11 Reserved T1 T4 T16
TMRA3 input clock selection
TA23MOD 01 00 01 10 11 Comparator output from TMRA2 T1 T16 T256 Overflow output from TMRA2 (16-bit timer mode) TA23MOD = 01
PWM cycle selection
00 01 10 11 Reserved 26 x Clock source 27 x Clock source 28 x Clock source
TMRA23 operation mode selection
00 01 10 11 8-bit PPG 8-bit PWM (TMRA2) + 8-bit timer (TMRA3) 8-bit timers 2ch 16-bit timer
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TMRA45 Mode Register
7 Bit symbol TA45MOD (0114H) Read/Write After reset 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 26 10: 27 11: 28 0 TA45M1 6 TA45M0 5 PWM41 4 PWM40 R/W 0 0 0 0 3 TA5CLK1 2 TA5CLK0 1 TA4CLK1 0 TA4CLK0
Function
Input clock for TMRA5 00: TA4TRG 01: T1 10: T16 11: T256
Input clock for TMRA4 00: TA4IN pin 01: T1 10: T4 11: T16
TMRA4 input clock selection
00 01 10 11 TA4IN T1 T4 T16
TMRA5 input clock selection
TA45MOD 01 00 01 10 11 Comparator output from TMRA4 T1 T16 T256 Overflow output from TMRA4 (16-bit timer mode) TA45MOD = 01
PWM cycle selection
00 01 10 11 Reserved 26 x Clock source 27 x Clock source 28 x Clock source
TMRA45 operation mode selection
00 01 10 11 8-bit PPG 8-bit PWM (TMRA4) + 8-bit timer (TMRA5) 8-bit timers 2ch 16-bit timer
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TMRA1 Flip-Flop Control Register
7 Bit symbol TA1FFCR (0105H) Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don't care 3 TA1FFC1 R/W 1 0 TA1FF control for inversion 0: Disable 1: Enable 2 TA1FFC0 1 TA1FFIE R/W 0 TA1FF inversion select 0: TMRA0 1:TMRA1 0 TA1FFIS
Function
Inverse signal for timer flip-flop 1 (TA1FF) (Don't care except in 8-bit timer mode)
0 TA1FFIS 1 Inversion by TMRA1 Inversion by TMRA0
Inversion of TA1FF
0 TA1FFIE 1 Enabled Disabled
Control of TA1FF
00 01 10 11 Clears TA1FF to "0" Don't care Inverts the value of TA1FF (Software inversion) Sets TA1FF to "1"
Note: The values of bits 4 to 7 of TA1FFCR are "1" when read.
TMRA3 Flip-Flop Control Register
7 Bit symbol TA3FFCR (010DH) Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 1 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don't care 3 TA3FFC1 R/W 1 0 TA3FF control for inversion 0: Disable 1: Enable 2 TA3FFC0 1 TA3FFIE R/W 0 TA3FF inversion select 0: TMRA2 1:TMRA3 0 TA3FFIS
Function
Inverse signal for timer flip-flop 3 (TA3FF) (Don't care except in 8-bit timer mode)
0 TA3FFIS 1 Inversion by TMRA3 Inversion by TMRA2
Inversion of TA3FF
0 TA3FFIE 1 Enabled Disabled
Control of TA3FF
00 01 10 11 Clears TA3FF to "0" Don't care Inverts the value of TA3FF (Software inversion) Sets TA3FF to "1"
Note: The values of bits 4 to 7 of TA3FFCR are "1" when read.
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TMRA5 Flip-Flop Control Register
7 Bit symbol TA5FFCR (0115H) Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 1 00: Invert TA5FF 01: Set TA5FF 10: Clear TA5FF 11: Don't care 3 TA5FFC1 R/W 1 0 TA5FF control for inversion 0: Disable 1: Enable 2 TA5FFC0 1 TA5FFIE R/W 0 TA5FF inversion select 0: TMRA4 1:TMRA5 0 TA5FFIS
Function
Inverse signal for timer flip-flop 5 (TA5FF) (Don't care except in 8-bit timer mode)
0 TA5FFIS 1 Inversion by TMRA5 Inversion by TMRA4
Inversion of TA5FF
0 TA5FFIE 1 Enabled Disabled
Control of TA5FF
00 01 10 11 Clears TA5FF to "0" Don't care Inverts the value of TA5FF (Software inversion) Sets TA5FF to "1"
Note: The values of bits 4 to 7 of TA5FFCR are "1" when read.
Timer Register
7 Bit symbol TA0REG (0102H) Read/Write After Reset Bit symbol TA1REG (0103H) Read/Write After Reset Bit symbol TA2REG (010AH) Read/Write After Reset Bit symbol TA3REG (010BH) Read/Write After Reset Bit symbol TA4REG (0112H) Read/Write After Reset Bit symbol TA5REG (0113H) Read/Write After Reset 6 5 4 - W 0 - W 0 - W 0 - W 0 - W 0 - W 0 3 2 1 0
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6.4 Operation in Each Mode
6.4.1 8-bit timer mode
Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Set its function or counter data for TMRA0 and TMRA1 after stop these registers.
6.4.1.1
Generating interrupts at a fixed interval (Using TMRA1)
To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 12 s at fc = 20 MHz, set each register as follows:
* Clock state System clock Prescaler clock Clock gear : High frequency (fc) : fFPH : 1 (fc)
MSB 7 TA01RUN TA01MOD TA1REG INTETA01 TA01RUN - 0 0 X - 6 X 0 0 1 X 5 X X 0 0 X 4 X X 1 1 X 3 - 0 1 X - 2 - 1 1 - 1 1 0 X 1 - 1
LSB 0 - X 0 - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (0.4 s at fc = 20 MHz) as the input clock. Set TA1REG to 12 s / T1 = 30 = 1EH Enable INTTA1 and set it to level 5. Start TMRA1 counting.
Note: X: Don't care, -: No change
Select the input clock using Table 6-2.
Note: The input clocks for TMRA0 and TMRA1 are different from as follows. TMRA0: TA0IN input, T1, T4 or T16 TMRA1: Match output of TMRA0, T1, T16, T256
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6.4.1.2
Generating a 50% duty ratio square wave pulse
The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4 s square wave pulse from the TA1OUT pin at fc = 20 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used.
* Clock state System clock Prescaler clock Clock gear : High frequency (fc) : fFPH : 1 (fc)
MSB 7 TA01RUN TA01MOD TA1REG TA1FFCR P7CR P7FC TA01RUN - 0 0 X X X - 6 X 0 0 X X X X 5 X X 0 X X X X 4 X X 0 X - - X 3 - 0 0 1 - - - 2 - 1 0 0 - - 1 1 0 - 1 1 1 1 1
LSB 0 - - 1 1 - Set P71 to function as the TA1OUT pin. - - Start TMRA1 counting. Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (0.4 s at fc = 20 MHz) as the input clock. Set the timer register to 2.4 s / T1 / 2 = 03H Clear TA1FF to "0" and set it to invert on the match detects signal from TMRA1.
Note: X: Don't care, -: No change
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T1 TA01RUN Bits 7 to 2
Up counter Bit1 0 1 2 3 0 1 2 3 0 1 2 3 0
Bit0 Comparator timig Comparator output (Match detect) INTTA1 UC1 clear
TA1FF
TA1OUT 0.9 s at fc = 20 MHz
Figure 6-5 Square Wave Output Timing Chart (50% duty)
6.4.1.3
Making TMRA1 count up on the match signal from the TMRA0 comparator
Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1.
Comparator output (TMRA0 match)
TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2)
1
2
3
4
5
1
2
3
4
5
1
2
3
1
2
1
TMRA1 match output
Figure 6-6 TMRA1 Count Up on Signal from TMRA0
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6.4.2
16-bit timer mode
A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD to 01. In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for TMRA1, regardless of the value set in TA01MOD. Table 6-2 shows the cycle of the input clock for TMRA0. LSB 8-bit set to TA0REG and MSB 8-bit is for TA1REG. Please keep setting TA0REG first because setting data for TA0REG inhibit its compare function and setting data for TA1REG permit it. Example: To generate an INTTA1 interrupt every 0.4 [s] at fc = 20 MHz, set the timer registers TA0REG and TA1REG as follows:
* Clock state System clock Prescaler clock Clock gear : High frequency (fc) : fFPH : 1 (fc)
If T16 (27/fc s at fc = 20 MHz) is used as the input clock for counting, set the following value in the registers: 0.4 s/(27/fc) s 62500 = F424H (e.g., set TA1REG to F4H and TA0REG to 24H). As a result, INTTA1 interrupt can be generated every 0.4 [s]. The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not cleared and also INTTA0 is not generated. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparators TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. Example: When TA1REG = 04H and TA0REG = 80H
Value of up counter (UC1, UC0) TMRA0 comparator match detect signal TMRA1 comparator match detect signal Interrupt INTTA0 Interrupt INTTA1
0080H
0180H
0280H
0380H
0480H
0080H
Timer output TA1OUT
Inversion
Figure 6-7 Timer Output by 16-Bit Timer Mode
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6.4.3
8-bit PPG (Programmable pulse generation) output mode
Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active low or active high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin.
tH = "10" t tL = "01" t tH tL
Example: = "01"
TA0REG and UC0 match (Interrupt INTTA0) TA1REG and UC0 match (Interrupt INTTA1)
TA1OUT TA0REG TA1REG
Figure 6-8 8-Bit PPG Output Waveforms
In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN should be set to "1", so that UC1 is set for counting. Figure 6-9 shows a block diagram representing this mode.
TA1OUT TA01RUN
Selector
TA0IN T1 T4 T16 TA01MOD
TA1FF 8-bit up counter (UC0)
TA1FFCR
Inversion
INTTA0
Comparator
Comparator
INTTA1
Selector TA0REG-WR
TA0REG
Shift trigger
Register buffer TA01RUN
TA1REG
Internal data bus
Figure 6-9 Block Diagram of 8-Bit PPG Output Mode
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If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low-duty waves (when duty is varied).
Match with TA0REG and up counter
(Up counter = Q1) Match wiht TA1REG Shift from register buffer 0 TA0REG (Value to be compared) Register buffer (Up counter = Q2)
Q1 Q2
Q2 Q3
TA0REG (Register buffer 0) write
Figure 6-10 Operation of Register Buffer 0
Note:The values that can be set in TAxREG range from 01h to 00h (equivalent to 100h). If the maximum value 00h is set, the match-detect signal goes active when the up-counter overfolws.
Example: To generate 1/4-duty 50-kHz pulses (at fc = 20 MHz):
20
s
* Clock state
System clock Prescaler clock Clock gear
: High frequency (fc) : fFPH : 1 (fc)
Calculate the value which should be set in the timer register. To obtain a frequency of 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 s T1 = 23/fc s (at fc = 20 MHz); 20 s/(23/fc) s = 50 Therefore set TA1REG to 50 (32H), and 50-kHz pulses can be obtained. The duty is to be set to 1/4: t x 1/4 = 20 s x 1/4 = 5 s 5 s/(23/fc) s 13 Therefore, set TA0REG = 13 = 0DH.
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7 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR 0 1 0 0 X
6 X 0 0 0 X
5 X X 0 1 X
4 X X 0 1 X
3 - X 1 0 0
2 - X 1 0 1
1 0 0 0 1 1
0 0 1 1 0 X Stop TMRA0 and TMRA01 and clear it to "0".(Double buffer disable) Set the 8-bit PPG mode, and select T1 as input clock. Write 0DH. Write 32H. Set TA1FF, enabling both inversion and the double buffer. Writing "10" provides negative logic pulse.
P7CR P7FC TA01RUN
X X 1
X X X
X X X
- - X
- - -
- - 1
1 1 1
- Set P71 as the TA1OUT pin. - 1 Start TMRA0 and TMRA01 counting.(Double buffer enable)
Note:X : Don't Care - : No change
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6.4.4
8-bit PWM output mode
This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin. TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7 or 8 as specified by TA01MOD). The up counter UC0 is cleared when 2n counter overflow occurs. The following conditions must be satisfied before this PWM mode can be used. Value set in TA0REG < Value set for 2n counter overflow Value set in TA0REG 0
TA0REG and UC0 match 2n overflow (INTTA0 interrupt) TA1OUT tPWM (PWM cycle)
Figure 6-11 8-Bit PWM Waveforms
Figure 6-12 shows a block diagram representing this mode.
Selector
TA0IN T1 T4 T16 8-bit up counter (UC0)
TA01RUN
TA1OUT
Clear 2n overflow control Overflow
TA1FF
Invert TA01MOD
TA1FFCR
TA01MOD
Comparator
INTTA0
Selector TA0REG-WR
TA0REG
Shift trigger
Register buffer0 TA01RUN Internal data bus
Figure 6-12 Block Diagram of 8-Bit PWM Mode
In this mode, the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Page 118
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Use of the double buffer facilitates the handling of low duty ratio waves.
Match with TA0REG
(Up counter = Q1) 2n overflow (Up counter = Q2)
Shift into TA0REG
TA0REG (Value to be compared) Register buffer 0
Q1 Q2
Q2 Q3
TA0REG (Register buffer 0) write
Figure 6-13 Operation of Register Buffer 0
Example: To output the following PWM waves on the TA1OUT pin at fc = 20 MHz:
* Clock state
System clock Prescaler clock Clock gear
: High frequency (fc) : fFPH : 1 (fc)
To achieve a 51.2 s PWM cycle by setting T1 to 23/fc s (at fc = 20 MHz): 51.2 s/(23/fc) s 128 = 2n Therefore n should be set to 7. Since the low-level period is 29.6 s when T1 = 23/fc s (at fc = 20 MHz), set the following value for TA0REG: 29.6 s/(23/fc) s 74 = 4AH
MSB 7 TA01RUN TA01MOD TA0REG TA1FFCR P7CR P7FC TA01RUN - 1 0 X X X 1 6 X 1 1 X X X X 5 X 1 0 X X X X 4 X 0 0 X - - X 3 - - 1 1 - - - 2 - - 0 0 - - 1 1 - 0 1 1 1 1 -
LSB 0 0 1 0 X - Set P71 and the TA1OUT pin. - 1 Start TMRA0 counting. Stop TMRA0 and clear it to 0. Select 8-bit PWM mode (Cycle: 27) and select T1 as the input clock. Write 4AH. Clear TA1FF to 0, enable the inversion and double buffer.
Note:X : Don't Care - : No change
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Table 6-3 PWM Cycle
Select System Clock SYSCR1 1 (fs) Gear Value SYSCR1 XXX 000 (fc) 001 (fc/2) 010 (fc/4) 0 (fc) 011 (fc/8) 100 (fc/16) XXX 1 (1/16) fc/16 clock 0 (1/1) fFPH Select Prescaler Clock SYSCR0 PWM cycle 26 T1 15.6 ms 25.6 s 51.2 s 102.4 s 204.8 s 409.6 s 409.6 s T4 62.5 ms 102.4 s 204.8 s 409.6 s 819.2 s 1638 s 1638 s T16 250 ms 409.6 s 819.2 s 1638 s 3277 s 6554 s 6554 s T1 31.3 ms 51.2 s 102.4 s 204.8 s 409.6 s 819.2 s 819.2 s 27 T4 125 ms 204.8 s 409.6 s 810.2 s 1638 s 3277 s 3277 s
@ fc = 20 MHz, fs = 32.768 kHz
28 T16 500 ms 819.2 s 1638 s 3277 s 6554 s 13107 s 13107 s T1 62.5 ms 102.4 s 204.8 s 409.6 s 819.2 s 1638 s 1638 s T4 250 ms 409.6 s 819.2 s 1638 s 3277 s 6554 s 6554 s T16 1000 ms 1638 s 3277 s 6554 s 13107 s 26214 s 26214 s
Note: xxx: Don't care
6.4.5
Settings for each mode
Table 6-4 shows the SFR settings for each mode.
Table 6-4 Timer Mode Setting Registers
Register Name Function Timer Mode PWM Cycle TA01MOD Upper Timer Input Clock Lower timer match T1, T16, T256 (00, 01, 10, 11) Lower Timer Input Clock External clock T1 T4, T16 (00, 01, 10, 11) External clock T1, T4, T16 (00, 01, 10, 11) External clock T1, T4, T16 (00, 01, 10, 11) External clock T1, T4, T16 (00, 01, 10, 11) - TA1FFCR TA1FFIS Timer F/F Invert Signal Select 0: Lower timer output 1: Upper timer output
8-bit timer x 2 channels
00
-
16-bit timer mode
01
-
-
-
8-bit PPG x 1 channel
10
-
-
-
8-bit PWM x 1 channel
11
26, 27, 28 (01, 10, 11)
-
-
8-bit timer x 1 channel
11
-
T1, T16, T256 (01, 10, 11)
Output disabled
Note: - : Don't care
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7. 16-Bit Timer/Event Counters (TMRB)
The TMP91FW60 incorporates five multifunctional 16-bit timer/event counters (TMRB0, TMRB1, TMRB2, TMRB3, TMRB4) which have the following operation modes: * 16-bit interval timer mode * 16-bit event counter mode * 16-bit programmable pulse generation (PPG) output mode The capture function enables selection of the following modes: * Frequency measurement mode * Pulse width measurement mode * Time differential measurement Figure 7-1 show block diagrams for TMRB0, TMRB1, TMRB2, TMRB3 and TMRB4. Each timer/event counter channel consists of a 16-bit up-counter, two 16-bit timer registers (one of them with a double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, two timer flipflops and a timer flip-flop controller. Each timer/event counter is controlled by an 11-byte SFR (special-function register). Each of the five channels (TMRB0, TMRB1, TMRB2, TMRB3, TMRB4) can be used independently. Each channel features the same operations except for those described in Table 7-1. Hence, only the operation of TMRB0 is explained below. Table 7-1 Registers and Pins for TMRB
Channel TMRB0 Specification TB0IN0 (also used as P80) TB0IN1 (also used as P81) TB0OUT0 (also used as P82) TB0OUT1 (also used as P83) TB0RUN (0180H) TB0MOD (0182H) TB0FFCR (0183H) TB0RG0L (0188H) SFR (address) TB0RG0H (0189H) Timer registers TB0RG1L (018AH) TB0RG1H (018BH) TB0CP0L (018CH) TB0CP0H (018DH) Capture registers TB0CP1L (018EH) TB0CP1H (018FH) TB1CP1L (019EH) TB1CP1H (019FH) TB2CP1L (01AEH) TB2CP1H (01AFH) TB3CP1L (01BEH) TB3CP1H (01BFH) TB4CP1L (01CEH) TB4CP1H (01CFH) TB1RG1L (019AH) TB1RG1H (019BH) TB1CP0L (019CH) TB1CP0H (019DH) TB2RG1L (01AAH) TB2RG1H (01ABH) TB2CP0L (01ACH) TB2CP0H (01ADH) TB3RG1L (01BAH) TB3RG1H (01BBH) TB3CP0L (01BCH) TB3CP0H (01BDH) TB4RG1L (01CAH) TB4RG1H (01CBH) TB4CP0L (01CCH) TB4CP0H (01CDH) TB1IN0 (also used as P84) TB1IN1 (also used as P85) TB1OUT0 (also used as P86) TB1OUT1 (also used as P87) TB1RUN (0190H) TB1MOD (0192H) TB1FFCR (0193H) TB1RG0L (0198H) TB1RG0H (0199H) TB2IN0 (also used as PA0) TB2IN1 (also used as PA1) TB2OUT0 (also used as PA2) TB2OUT1 (also used as PA3) TB2RUN (01A0H) TB2MOD (01A2H) TB2FFCR (01A3H) TB2RG0L (01A8H) TB2RG0H (01A9H) TB3IN0 (also used as P30) TB3IN1 (also used as P31) TB3OUT0 (also used as P32) TB3OUT1 (also used as P33) TB3RUN (01B0H) TB3MOD (01B2H) TB3FFCR (01B3H) TB3RG0L (01B8H) TB3RG0H (01B9H) TB4IN0 (also used as PB0) TB4IN1 (also used as PB1) TB4OUT0 (also used as PB2) TB4OUT1 (also used as PB3) TB4RUN (01C0H) TB4MOD (01C2H) TB4FFCR (01C3H) TB4RG0L (01C8H) TB4RG0H (01C9H) TMRB1 TMRB2 TMRB3 TMRB4
External clock/capture trigger input pins External pins Timer flip-flop output pins
Timer run register Timer mode register Timer flip-flop control register
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Internal data bus Internal data bus
Run/ clear TBnRUN
INT output INTTBn0 INTTBn1
7.1 Block Diagrams
Prescaler clock: T0 2 T1
TBnMOD Capture, external INT input control Timer flip-flop control TBnRUN TBnMOD Selector Count clock 16-bit up-counter (UCn) TBnMOD
4 T4 T16
Capture register 0 TBnCP0H/L Capture register 1 TBnCP1H/L
8 16 32
External INT input INTx INTy
Timer flip-flop TBnFF0 TBnFF1
TAzOUT (From TMRA) TBnIN0 TBnIN1
Timer flip-flop output TBnOUT0 TBnOUT1
Figure 7-1 Block Diagrams of TMRB0 to TMRB4
T1 T4 T16
TBnMOD
Match detection
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16-bit comparator (CPn0) 16-bit timer register TBnRG0H/L 16-bit comparator (CPn1) 16-bit timer register TBnRG1H/L TBnRUN Register buffer
Overflow interrupt INTTBOFn
Timer TMRB0 TMRB1 TMRB2 TMRB3 TMRB4
Match detection
n 0 1 2 3 4
INTx INT5 INT7 INT1 INT3 INT9
INTy INT6 INT8 INT2 INT4 INT10
TAzOUT TA1OUT TA1OUT TA1OUT TA3OUT TA5OUT
TMP91FW60
Internal data bus
Internal data bus
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7.2 Operation of Each Block
7.2.1 Prescaler
The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (T0) is divided clock (divided by 4) from selected clock by the register SYSCR0 of clock gear. This prescaler can be started or stopped using TB0RUN. Counting starts when is set to 1; the prescaler is cleared to 0 and stops operation when is cleared to 0. Table 7-2 show prescaler output clock resolution. Table 7-2 Prescaler Output Clock Resolution
Clock Gear Value SYSCR1 Prescaler Clock Selection
@fc = 20 MHz, fs = 32.768 kHz
Prescaler Output Clock Resolution T1 (1/2) 23/fs (244 s) 23/fc (0.4 s) T4 (1/8) 25/fs (977 s) 25/fc (1.6 s) 26/fc (3.2 s) 27/fc (6.4 s) 28/fc (12.8 s) 29/fc (25.6 s) 29/fc (25.6 s) T16 (1/32) 27/fs (3.9 ms) 27/fc(6.4 s) 28/fc (12.8 s) 29/fc (25.6 s) 210/fc (51.2 s) 211/fc (102.4 s) 211/fc (102.4 s)
System Clock SelectionSYSC1< SYSCK> 1 (fs)
XXX 000 (fc) 001 (fc/2) 010 (fc/4) 0 (1/1) fFPH
24/fc (0.8 s) 25/fc (1.6 s) 26/fc (3.2 s) 27/fc (6.4 s)
0 (fc)
011 (fc/8) 100 (fc/16) XXX 1 (1/16) fc/16 clock
27/fc (6.4 s)
Note: xxx: Don't care
7.2.2
Up counter (UC0)
UC0 is a 16-bit binary counter which counts up according to input from the clock specified by TB0MOD register. As the input clock, one of the prescaler internal clocks T1, T4 and T16 or an external clock from TB0IN0 pin can be selected. Counting or stopping and clearing of the counter is controlled by timer operation control register TB0RUN. When clearing is enabled, the up counter UC0 will be cleared to 0 each time its value matches the value in the timer register TB0RG1H/L. If clearing is disabled, the counter operates as a free-running counter. Clearing can be enabled or disabled by using TB0MOD. A timer overflow interrupt (INTTBOF0) is generated when UC0 overflow occurs.
7.2.3
Timer registers (TB0RG0H/L, TB0RG1H/L)
These two 16-bit registers are used to set the interval time. When the value in the up counter UC0 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower timer registers is needed. For example, using 2-byte data transfer instruction or using 1-byte data transfer instruction twice for lower 8 bits and upper 8 bits in order. (The compare circuit will not operate if only the lower 8 bits are written. Be sure to write to both timer registers (16 bits) from the lower 8 bits followed by the upper 8 bits.) The TB0RG0H/L timer register has a double-buffer structure, which is paired with register buffer 0. The value set in TB0RUN determines whether the double-buffer structure is enabled or disabled: it is disabled when = "0", and enabled when = "1".
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When the double buffer is enabled, data is transferred from the register buffer 0 to the timer register when the values in the up counter (UC0) and the timer register TB0RG1H/L match. The double buffer circuit incorporates two flags to indicate whether or not data is written to the lower 8 bits and the upper 8 bits of the register buffer, respectively. Only when both flags are set can data be transferred from the register buffer to the timer register by a match between the up-counter UC0 and the timer register TB0RG1. This data transfer is performed so long as 16-bit data is written in the register buffer regardless of the register buffer to the timer register unexpectedly as explained below. For example, let us assume that an interrupt occurs when only the lower 8 bits (L1) of the register buffer data (H1L1) have been written and the interrupt routine includes writes to all 16 bits in the register buffer and a transfer of the data to the timer register. In this case, if the higher 8 bits (H1) are written after the interrupt routine is completed, only the flag for the higher 8 bits will be set, the flag for the lower 8 bits having been cleared in the interrupt routine. Therefore, even if a match occurs between UC0 and TB0RG1, no data transfer will be performed. Then, in an attempt to set the next set of data (H2L2) in the register buffer, when the lower 8 bits (L2) are written, this will cause the flag for the lower 8 bits to be set as well as the flag for the higher 8 bits which has been set by writing the previous data (H1). If a match between UC0 and TB0RG1 occurs before the higher 8 bits (H2) are written, this will cause unexpected data (H1L2) to be sent to the timer register instead of the intended data (H2L2). To avoid such transfer timing problems due to interrupts, the DI instruction (disable interrupts) and the EI (enable interrupts) can be executed before and after setting data in the register buffer, respectively. After a reset, TB0RG0H/L and TB0RG1H/L are undefined. If the 16-bit timer is to be used after a reset, data should be written to it beforehand. On a reset is initialized to "0", disabling the double buffer. To use the double buffer, write data to the timer register, set to "1", then write data to the register buffer 10 as shown below. TB0RG0H/L and the register buffer 0 both have the same memory addresses (0188H and 0189H) allocated to them. If = "0", the value is written to both the timer register and the register buffer 0. If = "1", the value is written to the register buffer 0 only. The addresses of the timer registers are as follows:
TMRB0
TB0RG0H/L Upper 8 bits 000189H Lower 8 bits 000188H
TB0RG1H/L Upper 8 bits 00018BH Lower 8 bits 00018AH
TMRB1
TB1RG0H/L Upper 8 bits 000199H Lower 8 bits 000198H
TB1RG1H/L Upper 8 bits 00019BH Lower 8 bits 00019AH
TMRB2
TB2RG0H/L Upper 8 bits 0001A9H Lower 8 bits 0001A8H
TB2RG1H/L Upper 8 bits 0001ABH Lower 8 bits 0001AAH
TMRB3
TB3RG0H/L Upper 8 bits 0001B9H Lower 8 bits 0001B8H
TB3RG1H/L Upper 8 bits 0001BBH Lower 8 bits 0001BAH
TMRB4
TB4RG0H/L Upper 8 bits 0001C9H Lower 8 bits 0001C8H
TB4RG1H/L Upper 8 bits 0001CBH Lower 8 bits 0001CAH
Note:The timer registers are write-only registers and thus cannot be read.
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7.2.4
Capture registers (TB0CP0H/L, TB0CP1H/L)
These 16-bit registers are used to latch the values in the up counter (UC0). Data in the capture registers should be read all 16 bits. For example, using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte. (during capture is read, capture operation is prohibited. In that case, the lower 8 bits should be read first, followed by the 8 bits.) The addresses of the capture registers are as follows;
TMRB0
TB0CP0H/L
Upper 8 bits 00018DH Lower 8 bits 00018CH
TB0CP1H/L
Upper 8 bits 00018FH Lower 8 bits 00018EH
TMRB1
TB1CP0H/L
Upper 8 bits 00019DH Lower 8 bits 00019CH
TB1CP1H/L
Upper 8 bits 00019FH Lower 8 bits 00019EH
TMRB2
TB2CP0H/L
Upper 8 bits 0001ADH Lower 8 bits 0001ACH
TB2CP1H/L
Upper 8 bits 0001AFH Lower 8 bits 0001AEH
TMRB3
TB3CP0H/L
Upper 8 bits 0001BDH Lower 8 bits 0001BCH
TB3CP1H/L
Upper 8 bits 0001BFH Lower 8 bits 0001BEH
TMRB4
TB4CP0H/L
Upper 8 bits 0001CDH Lower 8 bits 0001CCH
TB4CP1H/L
Upper 8 bits 0001CFH Lower 8 bits 0001CEH
Note:The capture registers are read-only registers and thus cannot be written to.
7.2.5
Capture Input Control and External Interrupt Control
This circuit controls the timing to latch the value of up-counter UC0 into TB0CP0H/L and TB0CP1H/L, and generates external interrupt.The latch timing of capture register and selection of edge for external interrupt is controlled by TB0MOD. The value in the up-counter (UC0) can be loaded into a capture register by software. Whenever 0 is written to TB0MOD, the current value in the up counter (UC0) is loaded into capture register TB0CP0H/ L. It is necessary to keep the prescaler in RUN mode (e.g., TB0RUN must be held at a value of 1).
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7.2.6
Comparators (CP00, CP01)
CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC0 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively).
7.2.7
Timer flip-flops (TB0FF0, TB0FF1)
These flip-flops are inverted by the match detect signals from the comparators and the latch signals to the capture registers. Inversion can be enabled and disabled for each element using TB0FFCR. After a reset the value of TB0FF0 is undefined. If "00" is written to TB0FFCR or , TB0FF0 will be inverted. If "01" is written to the capture registers, the value of TB0FF0 will be set to "1". If "10" is written to the capture registers, the value of TB0FF0 will be set to "0".
Note:If an inversion by the match-detect signal and a setting change via the TB0FFCR register occurs simultaneously, the resultant operation varies depending on the situation, as shown below. * If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the flip-flop will be inverted only once. * If an inversion by the match-detect signal and an attempt to set the flip-flop to 1 via the register occur simultaneously, the flip-flop will be set to 1. * If an inversion by the match-detect signal and an attempt to clear the flip-flop to 0 via the register occur simultaneously, the flip-flop will be cleared to 0. If an inversion by match-detect signal and inversion disable setting occur simultaneously, two case (it is inverted and it is not inverted) are occurred. Therefore, if changing inversion control (inversion enable/disable), stop timer operation beforehand.
The values of TB0FF0 and TB0FF1 can be output via the timer output pins TB0OUT0 (which is shared with P82 and TB0OUT1 (which is shared with P83). Timer output should be specified using the port P function register.
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7.3 SFR
TMRB Run Register
7 Bit symbol TB0RUN (0180H) Read/Write After reset TB0RDE R/W 0 Double Buffer 0: Disable 1: Enable TB1RDE R/W 0 Double Buffer 0: Disable 1: Enable TB2RDE R/W 0 Double Buffer 0: Disable 1: Enable TB3RDE R/W 0 Double Buffer 0: Disable 1: Enable TB4RDE R/W 0 Double Buffer 0: Disable 1: Enable 6 - R/W 0 5 - - 4 - - 3 I2TB0 R/W 0 IDLE2 0: Stop 1: Operate - - I2TB1 R/W 0 IDLE2 0: Stop 1: Operate - - I2TB2 R/W 0 IDLE2 0: Stop 1: Operate - - I2TB3 R/W 0 IDLE2 0: Stop 1: Operate - - I2TB4 R/W 0 IDLE2 0: Stop 1: Operate 2 TB0PRUN R/W 0 TMRB0 prescaler 0: Stop and Clear 1: Run (count up) TB1PRUN R/W 0 TMRB1 prescaler 0: Stop and Clear 1: Run (count up) TB2PRUN R/W 0 TMRB2 prescaler 0: Stop and Clear 1: Run (count up) TB3PRUN R/W 0 TMRB3 prescaler 0: Stop and Clear 1: Run (count up) TB4PRUN R/W 0 TMRB4 prescaler 0: Stop and Clear 1: Run (count up) - - - UC4 TB4RUN R/W 0 - - - UC3 TB3RUN R/W 0 - - - UC2 TB2RUN R/W 0 - - - UC1 TB1RUN R/W 0 1 - - - UC0 0 TB0RUN R/W 0
Function
Always write 0.
Not in use
Bit symbol TB1RUN (0190H) Read/Write After reset
- R/W 0
- -
Function
Always write 0.
Not in use
Bit symbol TB2RUN (01A0H) Read/Write After reset
- R/W 0
- -
Function
Always write 0.
Not in use
Bit symbol TB3RUN (01B0H) Read/Write After reset
- R/W 0
- -
Function
Always write 0.
Not in use
Bit symbol TB4RUN (01C0H) Read/Write After reset
- R/W 0
- -
Function
Always write 0.
Not in use
Operation
I2TB0, I2TB1, I2TB2, I2TB3, I2TB4: Operation of IDLE2 mode TB0PRUN, TB1PRUN, TB2PRUN, TB3PRUN, TB4PRUN: Operation of prescaler TB0RUN, TB1RUN, TB2RUN, TB3RUN, TB4RUN: Operation of TMRB 0 1 Stop and Clear Count
Note: Bits 1, 4 and 5 of TB0RUN/TB1RUN/TB2RUN/TB3RUN/TB4RUN are "1" when read.
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TMRB Mode Register (Read-modify-write instructions are prohibited.) (1/2)
7 Bit symbol TB0MOD (0182H) Read/Write After reset 0 TB0CT1 R/W 0 6 TB0ET1 5 TB0CP0I W* 1 0 0 4 TB0CPM1 3 TB0CPM0 2 TB0CLE R/W 0 0 0 1 TB0CLK1 0 TB0CLK0
TB0FF1 inversion trigger 0: Trigger disable 1: Trigger enable Function Invert when UC0 is loaded into TB0CP1H/L Bit symbol TB1MOD (0192H) Read/Write After reset 0 TB1CT1 R/W 0 Invert when UC0 matches with TB0RG1H/L TB1ET1
Software capture control 0: Software capture 1: Undefined
Capture timing 00: Disable INT5 occurs at rising edge 01: TB0IN0 TB0IN1 INT5 occurs at rising edge 10: TB0IN0 TB0IN0 INT5 occurs at falling edge 11: TA1OUT TA1OUT INT5 occurs at rising edge
Up counter control 0: Clear disable 1: Clear enable
TMRB0 input clock select 00: TB0IN0 pin input 01: T1 10: T4 11: T16
TB1CP0I W* 1
TB1CPM1
TB1CPM0
TB1CLE R/W
TB1CLK1
TB1CLK0
0
0
0
0
0
TB1FF1 inversion trigger 0: Trigger disable 1: Trigger enable Function Invert when UC1 is loaded into TB1CP1H/L Bit symbol TB2MOD (01A2H) Read/Write After reset 0 TB2CT1 R/W 0 Invert when UC1 matches with TB1RG1H/L TB2ET1
Software capture control 0: Software capture 1: Undefined
Capture timing 00: Disable INT7 occurs at rising edge 01: TB1IN0 TB1IN1 INT7 occurs at rising edge 10: TB1IN0 TB1IN0 INT7 occurs at falling edge 11: TA1OUT TA1OUT INT7 occurs at rising edge
Up counter control 0: Clear disable 1: Clear enable
TMRB1 input clock select 00: TB1IN0 pin input 01: T1 10: T4 11: T16
TB2CP0I W* 1
TB2CPM1
TB2CPM0
TB2CLE R/W
TB2CLK1
TB2CLK0
0
0
0
0
0
TB2FF1 inversion trigger 0: Trigger disable 1: Trigger enable Function Invert when UC2 is loaded into TB2CP1H/L Bit symbol TB3MOD (01B2H) Read/Write After reset 0 TB3CT1 R/W 0 Invert when UC2 matches with TB2RG1H/L TB3ET1
Software capture control 0: Software capture 1: Undefined
Capture timing 00: Disable INT1 occurs at rising edge 01: TB2IN0 TB2IN1 INT1 occurs at rising edge 10: TB2IN0 TB2IN0 INT1 occurs at falling edge 11: TA1OUT TA1OUT INT1 occurs at rising edge
Up counter control 0: Clear disable 1: Clear enable
TMRB2 input clock select 00: TB2IN0 pin input 01: T1 10: T4 11: T16
TB3CP0I W* 1
TB3CPM1
TB3CPM0
TB3CLE R/W
TB3CLK1
TB3CLK0
0
0
0
0
0
TB3FF1 inversion trigger 0: Trigger disable 1: Trigger enable Function Invert when UC3 is loaded into TB3CP1H/L Invert when UC3 matches with TB3RG1H/L
Software capture control 0: Software capture 1: Undefined
Capture timing 00: Disable INT3 occurs at rising edge 01: TB3IN0 TB3IN1 INT3 occurs at rising edge 10: TB3IN0 TB3IN0 INT3 occurs at falling edge 11: TA3OUT TA3OUT INT3 occurs at rising edge
Up counter control 0: Clear disable 1: Clear enable
TMRB3 input clock select 00: TB3IN0 pin input 01: T1 10: T4 11: T16
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TMRB Mode Register (Read-modify-write instructions are prohibited.) (2/2)
7 Bit symbol TB4MOD (01C2H) Read/Write After reset 0 TB4CT1 R/W 0 6 TB4ET1 5 TB4CP0I W* 1 0 0 4 TB4CPM1 3 TB4CPM0 2 TB4CLE R/W 0 0 0 1 TB4CLK1 0 TB4CLK0
TB4FF1 inversion trigger 0: Trigger disable 1: Trigger enable Function Invert when UC4 is loaded into TB4CP1H/L Invert when UC4 matches with TB4RG1H/L
Software capture control 0: Software capture 1: Undefined
Capture timing 00: Disable INT9 occurs at rising edge 01: TB4IN0 TB4IN1 INT9 occurs at rising edge 10: TB4IN0 TB4IN0 INT9 occurs at falling edge 11: TA5OUT TA5OUT INT9 occurs at rising edge
Up counter control 0: Clear disable 1: Clear enable
TMRB4 input clock select 00: TB4IN0 pin input 01: T1 10: T4 11: T16
TMRB source clock
00 01 10 11 External input clock (TBnIN0 pin input) T1 T4 T16
Up counter clear control (UCn)
0 1 Clear by match with TBnRG1H/L Disable to clear up counter
Capture/Interrupt timing
Capture control 00 01 10 Disable capture Capture to TBnCP0H/L at rising edge of TBnIN0 Capture to TBnCP1H/L at rising edge of TBnIN1 Capture to TBnCP0H/L at rising edge of TBnIN0 Capture to TBnCP1H/L at falling edge of TBnIN0 Capture to TBnCP0H/L at rising edge of TAzOUT Capture to TBnCP1H/L at falling edge of TAzOUT INT generate at rising edge of TBnIN0 INT generate at falling edge of TBnIN0 INT generate at rising edge of TBnIN0 INT5 control
11
Software capture
0 1 Undefined (Note 3) Capture value of up counter to TBnCP0H/L.
Note 1: n=0,1,2,3,4 Note 2: z=1,3,5 Note 3: As described above, whenever 0 is written to TBnMOD, the current value in the up counter is loaded into capture register TBnCP0H/L. However, note that the current value in the up counter is also loaded into capture register TBnCP0H/L when 1 is written to TBnMOD while this bit is holding 0.
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TMRB Flip-Flop Control Register (Read-modify-write instructions are prohibited.) (1/2)
7 Bit symbol TB0FFCR (0183H) Read/Write After reset 1 TB0FF1 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. Bit symbol TB1FFCR (0193H) Read/Write After reset 1 TB1FF1 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. Bit symbol TB2FFCR (01A3H) Read/Write After reset 1 TB2FF1 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. Bit symbol TB3FFCR (01B3H) Read/Write After reset 1 TB3FF1 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. TB3FF1C1 W* 1 0 0 TB3FF1C0 TB2FF1C1 W* 1 0 0 TB2FF1C0 TB1FF1C1 W* 1 0 0 TB1FF1C0 TB0FF1C1 W* 1 0 0 6 TB0FF1C0 5 TB0C1T1 4 TB0C0T1 R/W 0 0 1 TB0FF0 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. TB1FF0C1 W* 0 0 1 TB1FF0 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. TB2FF0C1 W* 0 0 1 TB2FF0 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. TB3FF0C1 W* 0 0 1 TB3FF0 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. 1 TB3FF0C0 1 TB2FF0C0 1 TB1FF0C0 3 TB0E1T1 2 TB0E0T1 1 TB0FF0C1 W* 1 0 TB0FF0C0
TB0FF0 inversion trigger 0: Disable 1: Enable Invert when UC0 is loaded into TB0CP1H/L. TB1C1T1 Invert when UC0 is loaded into TB0CP0H/L. TB1C0T1 R/W Invert when UC0 matches TB0RG1H/L. TB1E1T1 Invert when UC0 matches TB0RG0H/L. TB1E0T1
Function
TB1FF0 inversion trigger 0: Disable 1: Enable Invert when UC1 is loaded into TB1CP1H/L. TB2C1T1 Invert when UC1 is loaded into TB1CP0H/L. TB2C0T1 R/W Invert when UC1 matches TB1RG1H/L. TB2E1T1 Invert when UC1 matches TB1RG0H/L. TB2E0T1
Function
TB2FF0 inversion trigger 0: Disable 1: Enable Invert when UC2 is loaded into TB2CP1H/L. TB3C1T1 Invert when UC2 is loaded into TB2CP0H/L. TB3C0T1 R/W Invert when UC2 matches TB2RG1H/L. TB3E1T1 Invert when UC2 matches TB2RG0H/L. TB3E0T1
Function
TB3FF0 inversion trigger 0: Disable 1: Enable Invert when UC3 is loaded into TB3CP1H/L. Invert when UC3 is loaded into TB3CP0H/L. Invert when UC3 matches TB3RG1H/L. Invert when UC3 matches TB3RG0H/L.
Function
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TMRB Flip-Flop Control Register (Read-modify-write instructions are prohibited.) (2/2)
7 Bit symbol TB4FFCR (01C3H) Read/Write After reset 1 TB4FF1 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. TB4FF1C1 W* 1 0 0 6 TB4FF1C0 5 TB4C1T1 4 TB4C0T1 R/W 0 0 1 TB4FF0 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. 3 TB4E1T1 2 TB4E0T1 1 TB4FF0C1 W* 1 0 TB4FF0C0
TB4FF0 inversion trigger 0: Disable 1: Enable Invert when UC4 is loaded into TB4CP1H/L. Invert when UC4 is loaded into TB4CP0H/L. Invert when UC4 matches TB4RG1H/L. Invert when UC4 matches TB4RG0H/L.
Function
Timer flip-flop (TBnFF0) control
00 01 10 11 Clear TBnFF0 to 0. Don't care Invert TBnFF0. Set TBnFF0 to 1.
TBnFF0 inversion when UCn matches TBnRG0H/L
0 1 Enable trigger (enable inversion). Disable trigger (disable inversion).
TBnFF0 inversion when UCn matches TBnRG1H/L
0 1 Enable trigger (enable inversion). Disable trigger (disable inversion).
TBnFF0 inversion when UCn is loaded into TBnCP0H/L
0 1 Enable trigger (enable inversion). Disable trigger (disable inversion).
TBnFF0 inversion when UCn is loaded into TBnCP1H/L
0 1 Enable trigger (enable inversion). Disable trigger (disable inversion).
Timer flip-flop (TBnFF1) control
00 01 10 11 Clear TBnFF1 to 0. Don't care Invert TBnFF1. Set TBnFF1 to 1.
Note: n=0,1,2,3,4
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7.4 Operation in Each Mode
7.4.1 16-Bit Interval Timer Mode
Generating interrupts at fixed intervals In this example the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1H/L.
7 TB0RUN INTETB0 TB0FFCR TB0MOD 0 X 1 0
6 0 1 1 0
5 X 0 0 1
4 X 0 0 0
3 - X 0 0
2 0 0 0 1
1 X 0 1 *
0 0 0 1 * Select internal clock for input and disable the capture function. Stop TMRB0. Enable INTTB01 and set it to interrupt level 4. Disable INTTB00. Disable trigger.
(**=01, 10, 11) TB0RG1 * * TB0RUN 0 * * 0 * * X * * X * * - * * 1 * * X * * 1 Start TMRB0. Set interval time (16 bits).
Note:X: Don't care, -: No change
7.4.2
16-Bit Event Counter Mode
If the external clock (TB0IN0 pin input) is selected as the input clock in 16-bit timer mode, the timer can be used as an event counter. The up-counter counts up on the rising edge of TB0IN0 input. To read the value of the counter, first perform software capture once, then read the captured value.
6 TB0RUN P8CR P8FC INTETB0 TB0FFCR TB0MOD TB0RG1 0 - - X 1 0 * * TB0RUN 0 0 - - 1 1 0 * * 0
5 X - - 0 0 1 * * X
4 X - - 0 0 0 * * X
3 - - - X 0 0 * * -
2 0 - - 0 0 1 * * 1
1 X - - 0 1 0 * * X
0 0 0 1 0 1 0 * * 1 Start TMRB0. Stop TMRB0. Set port to input mode. Set port to input mode. Enable INTTB01 and set interrupt level 4. Disable INTTB00. Disable trigger. Select TB0IN0 as the input clock. Set the number of counts (16 bits).
Note 1: X: Don't care, -: No change Note 2: When the timer is used as an event counter, set the prescaler to run mode (TB0RUN = 1).
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7.4.3
16-Bit Programmable Pulse Generation (PPG) Output Mode
Square wave pulses can be generated at any frequency and duty ratio. The output pulse may be either activeLow or active-High. In PPG mode a match between the value of the up-counter UC0 and either timer register TB0RG0 or TB0RG1 inverts the output value for timer flip-flop TB0FF0. The TB0FF0 output value is output on TB0OUT0. In this mode the following conditions must be satisfied. (value set in TB0RG0) < (value set in TB0RG1)
Match with TB0RG0 (INTTB00 interrupt) Match with TB0RG1 (INTTB01 interrupt) TB0OUT0 pin
Figure 7-2
Programmable Pulse Generation (PPG) Output Waveforms
When the TB0RG0 double buffer is enabled in this mode, the value of register buffer 0 will be shifted into TB0RG0 when the up-counter value matches TB0RG1. This feature facilitates the handling of low-duty waves.
Match with TB0RG0
Up-counter = Q1 Up-counter = Q2
Match with TB0RG1 Shift into TB0RG1 TB0RG0 (value to be compared) Register buffer Q1 Q2 Q2 Q3
Write to TB0RG0
Figure 7-3 Operation of Register Buffer
Note:The values that can be set in TBxRGx range from 0001h to 0000h (equivalent to 10000h). If the maximum value 0000h is set, the match-detect signal goes active when the up-counter overflows.
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The following block diagram illustrates this mode.
TB0OUT0 (PPG TB0RUN )
Selector
TB0IN0 T1 T4 T16
16-bit up counter (UC0)
F/F (TB0FF0)
Clear
Match 16 16
Selector TB0RG0-WR
TB0RG0H/L
0 TB0RUN
TB0RG1H/L
Internal data bus
Figure 7-4
Block Diagram of 16-Bit PPG Mode
The following example shows how to set 16-bit PPG output mode:
7 TB0RUN TB0RG0 0 * * TB0RG1 * * TB0RUN 1
6 0 * * * * 0
5 X * * * * X
4 X * * * * X
3 - * * * * -
2 0 * * * * 0
1 X * * * * X
0 0 * * * * 0 Disable the TB0RGH/L double buffer and stop TMRB0. Set the duty ratio. (16 bits) Set the frequency. (16 bits) Enable the TB0RG0H/L double buffer. (The duty and frequency are changed on an INTTB01 interrupt.) Set the mode to invert TB0FF0 at the match with TB0RG0H/L, TB0RG1H/L. Clear TB0FF0 to "0". Select prescaler output as input clock and disable the capture function. Set P82 to function as TB0OUT0.
TB0FFCR TB0MOD
1 0
1 0
0 1
0 0
1 0
1 1
1 *
0 *
(**=01, 10, 11) P8CR P8FC TB0RUN - - 1 - - 0 - - X - - X - - - 1 1 1 - - X - - 1
Start TMRB0.
Note:X: Don't care, -: No change
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7.4.4
Capture function examples
Used capture function, they can be applicable in many ways, for example: 1. One-shot pulse output from external trigger pulse 2. Frequency measurement 3. Pulse width measurement 4. Time difference measurement
7.4.4.1
One-shot pulse output from external trigger pulse
Set the up counter UC0 in free-running mode with the internal input clock, input the external trigger pulse from TB0IN0 pin, and load the value of up-counter into capture register TB0CP0H/L at the rise edge of the TB0IN0 pin. When the interrupt INT5 is generated at the rise edge of TB0IN0 input, set the TB0CP0H/L value (c) plus a delay time (d) to TB0RG0H/L (= c + d), and set the above set value (c + d) plus a one-shot width (p) to TB0RG1H/L (= c + d + p). And, set "11" to timer flip-flop control register TB0FFCR. Set to trigger enable for be inverted timer flip-flop TB0FF0 by UC0 matching with TB0RG0H/L and with TB0RG1H/L. When interrupt INTTB01 occurs, this inversion will be disabled after one-shot pulse is output. The (c), (d) and (p) correspond to c, d and p Figure 7-5.
Set the counter in free-running mode.
Count clock (Prescaler output clock)
c c+d c+d+p
TB0IN0 pin input (External trigger pulse) Match with TB0RG0H/L
Load to capture register 0 (TB0CP0H/L) INT5 occurred
Match with TB0RG1H/L Timer output pin TB0OUT0
Disables inversion caused by loading into TB0CP1H/L.
Inversion enable Inversion enable
INTTB01 occurred
Delay time d
Pulse width p
Figure 7-5 One-shot Pulse Output (with delay)
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Example: To output a 2-ms one-shot pulse with a 3-ms delay to the external trigger pulse to the TB0IN0 pin.
* Clock state
System clock: Clock gear: Prescaler clock:
High frequency (fc) 1 (fc) fFPH
TB0MOD TB0FFCR P8CR P8FC INTE56 INTETB0 TB0RUN

X X - - X X -
X X - - - 0 0
1 0 - - - 0 X
0 0 - - - 0 X
1 0 - - X X -
0 0 1 1 1 0 1
0 1 - - 0 0 X
1 0 - - 0 0 1
Set free running. Count with T1. Load the up counter value into TB0CP0H/L at the rising edge of TB0IN0 pin input. Clear TB0FF0 to 0. Disable inversion of TB0FF0. Set P82 to function as the TB0OUT0 pin. Set P80 to TB0IN0 input mode. Enable INT5. Disable INTTB00 and INTTB01. Start TMRB0.
TB0RG0 TB0RG1 TB0FFCR INTETB0

TB0CP0 + 3 ms/T1 TB0RG0 + 2 ms/T1 X X X 1 - 0 - 0 1 X 1 - - - - - Enable TB0FF0 inversion when the up counter value match with TB0RG0H/L or TB0RG1H/L. Enable INTTB01.
TB0FFCR INTETB0

X X
X 0
- 0
- 0
0 X
0 -
- -
- -
Disable inversion of TB0FF0 when the up counter value match with value of TB0RG0H/L or TB0RG1H/L. Disable INTTB01.
Note: X: Don't care, -: No change
When delay time is unnecessary, invert timer flip-flop TB0FF0 when up-counter value is loaded into capture register (TB0CP0H/L), and set the TB0CP0H/L value (c) plus the one-shot pulse width (p) to TB0RG1H/L when the interrupt INT5 occurs. The TB0FF0 inversion should be enable when the up counter (UC10) value matches TB0RG1H/L, and disabled when generating the interrupt INTTB01.
Count clock (Prescaler output clock)
c c+p Load into capture register 0 (TB0CP0H/L). INT5 occurred. INTTB01 occurred. Load the up counter value in capture register 1 (TB0CP1
TB0IN0 pin input (External trigger pulse) Match with TB0RG1H/L
Inversion enable
Timer output TB0OUT0
Enables inversion caused by loading into TB0CP0H/L.
Pulse width p Disable inversion caused by loading into TB0CP1H/L.
Figure 7-6
One-shot Pulse Output (without delay)
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7.4.4.2
Frequency measurement
The frequency of the external clock can be measured in this mode. The clock is input through the TB0IN0 pin, and its frequency is measured by the 8-bit timers TMRA01 and the 16-bit timer/event counter (TMRB0). (TMRA01 is used to setting of measurement time by inversion TA1FF.) The TB0IN0 pin input should be for the input clock of TMRB0. Set to TB0MOD = "11". The value of the up counter (UC10) is loaded into the capture register TB0CP0H/L at the rise edge of the timer flip-flop TA1FF of 8-bit timers (TMRA01), and into TB0CP1H/L at its fall edge. The frequency is calculated by difference between the loaded values in TB0CP0H/L and TB0CP1H/L when the interrupt (INTTA0 or INTTA1) is generates by either 8-bit timer.
Count clock (TB0IN0 pin input)
C1 C2
TA1FF
Load to TB0CP0H/L
C1
C1
Load to TB0CP1H/L
C2
C2
INTTA0/INTTA1
Figure 7-7 Frequency Measurement
For example, if the value for the level 1 width of TA1FF of the 8-bit timer is set to 0.5 s and the difference between the values in TB0CP0H/L and TB0CP1H/L is 100, the frequency is 100 / 0.5 s = 200 Hz.
Note: The frequency in this example is calculated with 50 duty.
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7.4.4.3
Pulse width measurement
This mode allows to measure the high-level width of an external pulse. While keeping the 16-bit timer/ event counter counting (Free running) with the internal clock input, external pulse is input through the TB0IN0 pin. Then the capture function is used to load the UC0 values into TB0CP0H/L and TB0CP1H/L at the rising edge and falling edge of the external trigger pulse respectively. The interrupt INT5 occurs at the falling edge of TB0IN0. The pulse width is obtained from the difference between the values of TB0CP0H/L and TB0CP1H/L and the internal clock cycle. For example, if the internal clock is 0.8 s and the difference between TB0CP0H/L and TB0CP1H/L is 100, the pulse width will be 100 x 0.8 s = 80 s. Additionally, the pulse width which is over the UC0 maximum count time specified by the clock source, can be measured by changing software.
Count clock (Prescaler output clock)
C1 C2
TB0IN0 pin input (External pulse) Load to TB0CP0H/L
C1 C1
Load to TB0CP1H/L
C2
C2
INT5
Figure 7-8 Pulse Width Measurement
Note: Only in this pulse width measuring mode (TB0MOD = 10), external interrupt INT5 occurs at the falling edge of TB0IN0 pin input. In other modes, it occurs at the rising edge.
The width of low-level can be measured from the difference between the first C2 and the second C1 at the second INT5 interrupt.
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7.4.4.4
Time Difference Measurement
This mode is used to measure the difference in time between the rising edges of external pulses input through TB0IN0 and TB0IN1. Keep the 16-bit timer/event counter (TMRB0) counting (Free running) with the internal clock, and load the UC0 value into TB0CP0H/L at the rising edge of the input pulse to TB0IN0. Then the interrupt INT5 is generated. Similarly, the UC0 value is loaded into TB0CP1H/L at the rising edge of the input pulse to TB0IN1, generating the interrupt INT6. The time difference between these pulses can be obtained by multiplying the value subtracted TB0CP0H/L from TB0CP1H/L and the internal clock cycle together at which loading the up counter value into TB0CP0H/L and TB0CP1H/L has been done.
Count clock (Prescaler output clock)
C1 C2
TB0IN0 pin input
TB0IN1 pin input
Load to TB0CP0H/L Load to TB0CP1H/L
INT5
INT6
Time difference
Figure 7-9 Time Difference Measurement
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8. Serial Channels (SIO)
TMP91FW60 includes 3 serial I/O channels. For both channels either UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. 1. I/O interface mode * Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O. 2. UART mode * Mode 1: 7-bit data * Mode 1: 8-bit data * Mode 1: 9-bit data In mode 1 and mode 2, a parity bit can be added. Mode 3 has a wakeup function for the master controller to start slave controllers via a serial link (A multi-controller system). Figure 8-2 are block diagrams for each channel. SIO is compounded mainly prescaler, serial clock generation circuit, receiving buffer and control circuit, transmission buffer and control circuit. Both channels operate in the same function except for the following points; hence only the operation of channel 0 is explained below. Table 8-1 Differences in Serial Channel Specifications
SIO0 TXD0 (P90) RXD0 (P91) CTS0/SCLK0 (P92) SIO1 TXD1 (P93) RXD1 (P94) CTS1/SCLK1 (P95) SIO2 TXD2 (P41) RXD2 (P42) CTS2/SCLK2 (P43)
Pin name
Mode 0 (I/O interface mode Bit 0 1 2 3 4 5 6 7
Transfer direction Mode 1 (7-bit UART mode)
No parity
Start
Bit 0
1
2
3
4
5
6
Stop
Parity
Start
Bit 0
1
2
3
4
5
6
Parity Stop
Mode 2 (8-bit UART mode)
No parity
Start
Bit 0
1
2
3
4
5
6
7
Stop
Parity
Start
Bit 0
1
2
3
4
5
6
7
Parity Stop
Mode 3 (9-bit UART mode Start Bit 0 1 2 3 4 5 6 7 8 Stop
Wakeup function
Start
Bit 0
1
2
3
4
5
6
7
Bit 8
Stop
When bit8 = 1, address (Select code) is denoted. When bit8 = 0, data is denoted.
Figure 8-1 Data Formats
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8.1 Block Diagrams
Prescaler 4 8 16 32 64 T2
BRnCR BRnCR
T0
2
T8
T32
Serial clock generation circuit
TA0TRG (from TMRA0) BRnADD
Prescaler
Selector
Selector
T0 T2 T8 T32
Selector
UART mode
SIOCLK
BRnCR Baud date generator
SCnMOD0
SCnMOD0
fSYS 2
SCLKn
Selector
I/O interface mode
I/O interface mode SCLKn
SC0CR INT request INTRXn INTTXn
Receive counter (UART only 16) RXDCLK SCnMOD0 Receive control
SCnMOD0
Serial channel interrupt control
Transmission counter (UART only 16)
TXDCLK
Transmission SCnCR control SCnMOD0 CTSn
RXDn
Receive buffer 1 (Shift register)
Parity control
RB8
Receive buffer 2 (SCnBUF)
Error flag
TB8
Transmission buffer (SCnBUF)
TXDn
SCnCR
Internal data bus
Figure 8-2 Block Diagram of the Serial Channel 0/1/2
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8.2 Operation of Each Circuit
8.2.1 Prescaler
A 6-bit prescaler generates an operation clock for SIO0. The prescaler is acteve only when a baud rate generator is specified as a serial transfer clock. As an input clock of the prescaler, be sure to set SYSCR0 to "0" and then specify fFPH. This clock is used for T0 with being divided by 4. Table 8-2 shows prescaler clock resolution into the baud rate generator. Table 8-2 Prescaler Clock Resolution to Baud Rate Generator
Gear Value XXX 000 (fc) 001 (fc/2) 0 (fc) 010 (fc/4) 011 (fc/8) 100 (fc/16) 0 (1/1) fFPH Select Prescaler Clock Prescaler Output Clock Resolution T0 22/fs 22/fc 23/fc 24/fc 25/fc 26/fc T2 24/fs 24/fc 25/fc 26/fc 27/fc 28/fc T8 26/fs 26/fc 27/fc 28/fc 29/fc 210/fc T32 28/fs 28/fc 29/fc 210/fc 211/fc 212/fc
Select System Clock 1 (fs)
The baud rate generator selects between 4 clock inputs: T0, T2, T8, and T32 among the prescaler outputs.
8.2.2
Baud rate generator
The baud rate generator is a circuit which generates transmission and receiving clocks which determine the transmission rate of the serial channels. The input clock to the baud rate generator, T0, T2, T8 or T32, is generated by the 6-bit prescaler which is shared by the timers. One of these input clocks is selected using the BR0CR field in the baud rate generator control register. The baud rate generator includes a frequency divider, which divides the frequency by 1, N + (16 - K)/16 or 16 values, determining the transmission rate. The transmission rate is determined by the settings of BR0CR and BR0ADD.
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8.2.2.1
In UART mode
(1) When BR0CR = 0 The settings BR0ADD are ignored. The baud rate generator divides the selected prescaler clock by N, which is set in BR0CK. (N = 1, 2, 3 ... 16)
(2)
When BR0CR = 1 The N + (16 - K)/16 division function is enabled. The baud rate generator divides the selected prescaler clock by N + (16 - K)/16 using the value of N set in BR0CR (N = 2, 3 ... 15) and the value of K set in BR0ADD (K = 1, 2, 3 ... 15)
Note: If N = 1 and N = 16, the N + (16 - K)/16 division function is disabled. Set BR0CR to "0".
8.2.2.2
In I/O interface mode
The N + (16 - K)/16 division function is not available in I/O interface mode. Set BR0CR to "0" before dividing by N. The method for calculating the transmission rate when the baud rate generator is used is explained below.
(1)
In UART mode Input clock of baud rate generator Baud rate = --------------------------------------------------------------------------------------------------- / 16 Frequency divider for baud rate generator
(2)
In I/O interface mode Input clock of baud rate generator Baud rate = --------------------------------------------------------------------------------------------------- / 2 Frequency divider for baud rate generator
8.2.2.3
Integer divider (N divider)
For example, when the source clock frequency (fc) =19.6608 MHz, the input clock frequency = T2 (fc/ 16), the frequency divider N (BR0CR) = 8, and BR0CR = 0, the baud rate in UART mode is as follows:
*Clock state
System clock: Clock gear: Prescaler clock:
High frequency (fc) 1 (fc) fFPH
fc 16 Baudrate = ------------- / 16 8 = 19.6608 x 106 / 16 / 8 / 16 = 9600 (bps)
Note: The + (16 - K)/16 division function is disabled and setting BR0ADD is invalid.
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8.2.2.4 N + (16 - K)/16 divider (UART mode only)
Accordingly, when the source clock frequency (fc) = 15.9744 MHz, the input clock frequency = T2, the frequency divider N (BR0CR) = 6, K (BR0ADD) = 8, and BR0CR = 1, the baud rate in UART mode is as follows:
*Clock state
System clock: Clock gear: Prescaler clock:
High frequency (fc) 1 (fc) fFPH
fc/16 Baudrate= ---------------------------- / 16 ( 16 - 8 ) 6 + ------------------ 16 6 8 = 15.9744 x 10 / 16 / 6 + ----- / 16 = 9600(bps) 16
Table 8-3 show examples of UART mode transfer rates. Additionally, the external clock input is available in the serial clock. The method for calculating the baud rate is explained below: * In UART mode Baud rate = External clock input frequency / 16 It is necessary to satisfy (External clock input cycle) 4/fSYS * In I/O interface mode Baud rate = External clock input frequency It is necessary to satisfy (External clock input cycle) 16/fSYS Table 8-3 UART Baud Rate Selection
(When baud rate generator is used and BR0CR=0, SYSCR0=0)
Input Clock fc [MHz] Frequency Divider N 7.3728 9.8304 1 3 6 A C F 1 2 4 5 8 10 T0 (fc/4) 115.200 38.400 19.200 11.520 9.600 7.680 153.600 76.800 38.400 30.720 19.200 9.600 T2 (fc/16) 28.800 9.600 4.800 2.880 2.400 1.920 38.400 19.200 9.600 7.680 4.800 2.400 T8 (fc/64) 7.200 2.400 1.200 0.720 0.600 0.480 9.600 4.800 2.400 1.920 1.200 0.600 T32 (fc/256) 1.800 0.600 0.300 0.180 0.150 0.120 2.400 1.200 0.600 0.480 0.300 0.150
Unit (kbps)
Note: Transmission rates in I/O interface mode are eight times faster than the values given above.
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Timer out clock (TA0TRG) can be used for source clock of UART mode only. Calculation method the frequency of TA0TRG Frequency of TA0TRG = Baud rate x 16
Note: In case of I/O interface mode, prohibit to use TA0TRG for source clock.
8.2.3
Serial clock generation circuit
This circuit generates the basic clock for transmission and receiving data.
8.2.3.1
In I/O interface mode
In SCLK output mode with the setting SC0CR = "0", the basic clock is generated by dividing the output of the baud rate generator by 2, as described previously. In SCLK input mode with the setting SC0CR = "1", the rising edge or falling edge will be detected according to the setting of the SC0CR register to generate the basic clock.
8.2.3.2
In UART mode
The SC0MOD0 setting determines whether the baud rate generator clock, the internal system clock fSYS, the match detect signal from timer TMRA0 or the external clock (SCLK0) is used to generate the basic clock SIOCLK.
8.2.4
Receiving counter
The receiving counter is a 4-bit binary counter used in UART mode which counts up the pulses of the SIOCLK clock. It takes 16 SIOCLK pulses to receive 1 bit of data; each data bit is sampled three times - on the 7th, 8th and 9th clock cycles. The value of the data bit is determined from these three samples using the majority rule. For example, if the data bit is sampled respectively as "1", "0" and "1" on 7th, 8th and 9th clock cycles, the received data bit is taken to be "1". A data bit sampled as "0", "0" and "1" is taken to be "0".
8.2.5
Receiving control
In I/O interface mode
In SCLK output mode with the setting SC0CR = "0", the RXD0 signal is sampled on the rising or falling edge of the shift clock which is output on the SCLK0 pin, according to the SC0CR setting. In SCLK input mode with the setting SC0CR = "1", the RXD0 signal is sampled on the rising or falling edge of the SCLK0 input, according to the SC0CR setting.
8.2.5.1
8.2.5.2
In UART mode
The receiving control block has a circuit which detects a start bit using the majority rule. Received bits are sampled three times; when two or more out of three samples are "0", the bit is recognized as the start bit and the receiving operation commences. The values of the data bits that are received are also determined using the majority rule. Page 145
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TMP91FW60 8.2.6 Receiving buffers
To prevent overrun errors, the receiving buffers are arranged in a double-buffer structure. Received data is stored one bit at a time in receiving buffer 1 (which is a shift register). When 7 or 8 bits of data have been stored in receiving buffer 1, the stored data is transmitted to receiving buffer 2 (SC0BUF); this causes an INTRX0 interrupt to be generated. The CPU only reads receiving buffer 2 (SC0BUF). Even before the CPU reads receiving buffer 2 (SC0BUF), the received data can be stored in receiving buffer 1. However, unless receiving buffer 2 (SC0BUF) is read before all bits of the next data are received by receiving buffer 1, an overrun error occurs. If an overrun error occurs, the contents of receiving buffer 1 will be lost, although the contents of receiving buffer 2 and SC0CR will be preserved. SC0CR is used to store either the parity bit - added in 8-bit UART mode - or the most significant bit (MSB) - in 9-bit UART mode. In 9-bit UART mode the wakeup function for the slave controller is enabled by setting SC0MOD0 to "1"; in this mode INTRX0 interrupts occur only when the value of SC0CR is "1".
Note 1: The double buffer structure does not support SC0CR. Note 2: If the CPU reads receive buffer 2 while data is being transferred from receive buffer 1 to receive buffer 2, the data may not be read properly. To avoid this situation, a read of receive buffer 2 should be triggered by a receive interrupt.
8.2.7
Transmission counter
The transmission counter is a 4-bit binary counter which is used in UART mode and which, like the receiving counter, counts the SIOCLK clock pulses; a TXDCLK pulse is generated every 16 SIOCLK clock pulses.
SIOCLK
15
TXDCLK
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
Figure 8-3 Generation of the Transmission Clock
8.2.8
Transmission controller
In I/O interface mode
In SCLK output mode with the setting SC0CR = "0", the data in the transmission buffer is output one bit at a time to the TXD0 pin on the rising or falling edge of the shift clock which is output on the SCLK0 pin, according to the SC0CR setting. In SCLK input mode with the setting SC0CR = "1", the data in the transmission buffer is output one bit at a time on the TXD0 pin on the rising or falling edge of the SCLK0 input, according to the SC0CR setting.
8.2.8.1
8.2.8.2
In UART mode
When transmission data sent from the CPU is written to the transmission buffer, transmission starts on the rising edge of the next TXDCLK.
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8.2.8.3
Handshake function
Use of CTS0 pin allows data can be sent in units of one frame; thus, overrun errors can be avoided. The handshake function is enabled or disabled by the SC0MOD0 setting. When the CTS0 pin goes high on completion of the current data send, data transmission is halted until the CTS0 pin goes low again. However, the INTTX0 interrupt is generated, it requests the next data send to the CPU. The next data is written in the transmission buffer and data transmission is halted. Though there is no RTS pin, a handshake function can be easily configured by setting any port assigned to be the RTS function. The RTS should be output "high" to request send data halt after data receive is completed by software in the RXD interrupt routine.
TXD CTS0
RXD RTS (Any port)
Sender
Receiver
Figure 8-4 Handshake Function
Timing to write to the transmission buffer
Transmission is suspended during this period b
CTS0
a
13 14 15 16 1
2
3
13 14 15 16 1
2
3
SIOCLK
TXDCLK Start bit
TXD
Bit 0
Note 1: If the CTS0 signal goes high during transmission, no more data will be sent after completion of the current transmission. Note 2: Transmission starts on the first falling edge of the TXDCLK clock after the CTS0 signal has fallen.
Figure 8-5 CTS0 (Clear to send) Timing
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8.2.9
Transmission buffer
The transmission buffer (SC0BUF) shifts out and sends the transmission data written from the CPU from the least significant bit (LSB) in order. When all the bits are shifted out, the transmission buffer becomes empty and generates an INTTX0 interrupt.
8.2.10 Parity control circuit
When SC0CR in the serial channel control register is set to "1", it is possible to transmit and receive data with parity. However, parity can be added only in 7-bit UART mode or 8-bit UART mode. The SC0CR field in the serial channel control register allows either even or odd parity to be selected. In the case of transmission, parity is automatically generated when data is written to the transmission buffer SC0BUF. The data is transmitted after the parity bit has been stored in SC0BUF in 7-bit UART mode or in SC0MOD0 in 8-bit UART mode. SC0CR and SC0CR must be set before the transmission data is written to the transmission buffer. In the case of receiving, data is shifted into receiving buffer 1, and the parity is added after the data has been transmitted to receiving buffer 2 (SC0BUF), and then compared with SC0BUF in 7-bit UART mode or with SC0CR in 8-bit UART mode. If they are not equal, a parity error is generated and the SC0CR flag is set.
8.2.11 Error flags
Three error flags are provided to increase the reliability of data reception.
8.2.11.1 Overrun error
If all the bits of the next data item have been received in receiving buffer 1 while valid data still remains stored in receiving buffer 2 (SC0BUF), an overrun error is generated. The below is a recommended flow when the overrun error is generated. (INTRX interrupt routine) 1. Read receiving buffer 2. Read error flag 3. if = 1 then a. Set to disable receiving (Write "0" to SC0MOD0) b. Wait to terminate current frame c. Read receiving buffer d. Read error flag e. Set to enable receiving (Write "1" to SC0MOD0) f. Request to transmit again 4. Other
Note: Overrun errors are generated only with regard to receive buffer 2 (SC0BUF). Thus, if SC0CR is not read, no overrun error will occur.
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8.2.11.2 Parity error
The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is compared with the parity bit received via the RXD pin. If they are not equal, a parity error is generated.
Note: The parity error flag is cleared every time it is read. However, if a parity error is detected twice in succession and the parity error flag is read between the two parity errors, it may seem as if the flag had not been cleared. To avoid this situation, a read of the parity error flag should be triggered by a receive interrupt.
8.2.11.3 Framing error
The stop bit for the received data is sampled three times around the center. If the majority of the samples are "0", a framing error is generated.
8.2.12 Timing generation
8.2.12.1 In UART mode
Table 8-4 Receiving
Mode Interrupt timing Framing error timing Parity error timing 9 Bits Center of last bit (Bit8) Center of stop bit - Center of last bit (Bit8) 8 Bits + Parity Center of last bit (Parity bit) Center of stop bit Center of last bit (Parity bit) Center of last bit (Parity bit) 8 Bits, 7 Bits + Parity, 7 Bits Center of stop bit Center of stop bit Center of stop bit
Overrun error timing
Center of stop bit
Note 1: In 9 Bits and 8 Bits + Parity mode, interrupts coincide with the ninth bit pulse. Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be transferred) to allow checking for a framing error. Note 2: The higher the transfer rate, the later than the middle receive interrupts and errors occur.
Table 8-5
Transmitting
Mode 9 Bits Just before stop bit is transmitted 8 Bits + Parity Just before stop bit is transmitted 8 Bits, 7 Bits + Parity, 7 Bits Just before stop bit is transmitted
Interrupt timing
8.2.12.2 I/O interface
Transmission interrupt timing
SCLK output mode
Immediately after the last bit. (See Figure 8-8) Immediately after rise of last SCLK signal rising mode, or immediately after fall in falling mode. (See Figure 8-9) Timing used to transmit received data to receive buffer 2 (SC0BUF) (e.g., immediately after last SCLK). (See Figure 8-10) Timing used to transmit received data to receive buffer 2 (SC0BUF) (e.g., immediately after last SCLK). (See Figure 8-11)
SCLK input mode
Receiving interrupt timing
SCLK output mode
SCLK input mode
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8.3 SFR
Serial Control Register (Read-modify-write instructions are prohibited.)
7 SC0CR (0201H) Bit symbol Read/Write After reset SC1CR (0209H) Function SC2CR (0211H) Received data bit8 Parity 0: Odd 1: Even RB8 R Undefined 0 6 EVEN R/W 0 0 Overrun error flag 0: Undetect error 1: Detect error 5 PE 4 OERR 3 PERR 2 FERR 1 SCLKS R/W 0 Framing error flag 0: Undetect error 1: Detect error 0 Edge selection for SCLK pin (I/ O mode) 0: SCLK 1: SCLK 0 I/O interface input clock selection 0: Baud rate generator 1: SCLK pin input 0 IOC
R (Cleared to "0" when read) 0 Parity error flag 0: Undetect error 1: Detect error
Parity addition 0: Disable 1: Enable
Note1: As all error flags are cleared after reading, do not test only a single bit with a bit-testing instruction. Note2: A baud rate generator SCnCR

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