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HFA1109
Data Sheet April 23, 2007 FN4019.5
450MHz, Low Power, Current Feedback Video Operational Amplifier
The HFA1109 is a high speed, low power, current feedback amplifier built with Intersil's proprietary complementary bipolar UHF-1 process. This amplifier features a unique combination of power and performance specifically tailored for video applications. The HFA1109 is a standard pinout op amp. It is a higher performance, drop-in replacement (no feedback resistor change required) for the CLC409. If a comparably performing op amp with an output disable function (useful for video multiplexing) is required, please refer to the HFA1149 data sheet..
Features
* Wide - 3dB Bandwidth (AV = +2) . . . . . . . . . . . . . 450MHz * Gain Flatness (To 250MHz) . . . . . . . . . . . . . . . . . . . 0.8dB * Very Fast Slew Rate (AV = +2). . . . . . . . . . . . . . 1100V/s * High Input Impedance . . . . . . . . . . . . . . . . . . . . . . 1.7M * Differential Gain/Phase . . . . . . . . . . . . . . . . . 0.02%/0.02 * Low Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . 10mA * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* Professional Video Processing * Video Switchers and Routers * Medical Imaging
Ordering Information
PART NUMBER HFA1109IB HFA1109IBZ (Note 1) PART MARKING 1109IB HFA1109 IBZ TEMP. RANGE (C) PACKAGE PKG. DWG. #
* PC Multimedia Systems * Video Distribution Amplifiers * Flash Converter Drivers * Radar/IF Processing
-40 to +85 8 Ld SOIC (150MIL) M8.15 -40 to +85 8 Ld SOIC (150MIL) M8.15 (Pb-free) -40 to +85 8 Ld SOIC (150MIL) M8.15 (Pb-free)
HFA1109IBZ96 HFA1109 (Note 1) IBZ
Pinout
HFA1109 (8 LD SOIC) TOP VIEW
HFA11XXEVAL DIP Evaluation Board for High Speed Op Amps (Note 2) NOTES: 1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 2. Requires a SOIC-to-DIP adapter. See "Evaluation Board" section inside.
NC -IN +IN V-
1 2 3 4 +
8 7 6 5
NC V+ OUT NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1999, 2004, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
HFA1109
Absolute Maximum Ratings
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8V Output Current (Note 4) . . . . . . . . . . . . . . . . . Short Circuit Protected 30mA Continuous 60mA 50% Duty Cycle ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .1400V Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . . . .2000V Machine Model (Per EIAJ ED-4701Method C-111) . . . . . . . . . .50V
Thermal Information
Thermal Resistance (Typical, Note 3) JA (C/W) 8 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Maximum Junction Temperature (Die). . . . . . . . . . . . . . . . . . +175C Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 4. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output current must not exceed 30mA for maximum reliability.
Electrical Specifications
VSUPPLY = 5V, AV = +2, RF = 250, RL = 100, Unless Otherwise Specified. (NOTE 5) TEST LEVEL
PARAMETER INPUT CHARACTERISTICS Input Offset Voltage
TEST CONDITIONS
TEMP. (C)
MIN
TYP
MAX
UNITS
A A
25 Full Full 25 Full 25 Full 25 Full Full 25 Full 25 Full Full 25 Full 25 Full 25, 85 -40 25
47 45 50 47 0.8 0.5 -
1 2 10 50 48 53 51 4 5 30 0.5 0.5 2 3 40 3 3 1.6 1.6 1.7 1.4 60
5 8 10 15 1 3 10 15 6 8 5 8 -
mV mV V/C dB dB dB dB A A nA/C A/V A/V A A nA/C A/V A/V A/V A/V M M
Average Input Offset Voltage Drift Input Offset Voltage Common-Mode Rejection Ratio Input Offset Voltage Power Supply Rejection Ratio Non-Inverting Input Bias Current DVCM = 2V
B A A DVPS = 1.25V A A A A
Non-Inverting Input Bias Current Drift Non-Inverting Input Bias Current Power Supply Sensitivity Inverting Input Bias Current DVPS = 1.25V
B A A A A
Inverting Input Bias Current Drift Inverting Input Bias Current Common-Mode Sensitivity Inverting Input Bias Current Power Supply Sensitivity Non-Inverting Input Resistance DVCM = 2V
B A A DVPS = 1.25V A A DVCM = 2V A A
Inverting Input Resistance
B
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FN4019.5 April 23, 2007
HFA1109
Electrical Specifications
VSUPPLY = 5V, AV = +2, RF = 250, RL = 100, Unless Otherwise Specified. (Continued) (NOTE 5) TEST LEVEL B A
PARAMETER Input Capacitance Input Voltage Common Mode Range (Implied by VIO CMRR, +RIN, and -IBIAS CMS tests) Input Noise Voltage Density (Note 6) Non-Inverting Input Noise Current Density (Note 4) Inverting Input Noise Current Density (Note 4) TRANSFER CHARACTERISTICS Open Loop Transimpedance Gain (Note 6) Minimum Stable Gain AC CHARACTERISTICS -3dB Bandwidth (VOUT = 0.2VP-P, Note 6)
TEST CONDITIONS
TEMP. (C) 25 Full
MIN 2
TYP 1.6 2.5
MAX -
UNITS pF V
f = 100kHz
B B
25 25 25
-
4 2.4 40
-
nV/Hz pA/Hz pA/Hz
f = 100kHz
B
B B
25 Full
-
500 1
-
k V/V
AV = -1, RF = 200
B B
25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full 25 Full
300 290 280 260 390 350 -1.0 -1.1 -1.6 -1.7 -1.9 -2.2 0.3 0.4 0.8 0.9 1.3 1.4
375 360 330 320 450 410 0 0 -0.45 -0.45 -0.75 -0.75 -0.85 -0.85 0.1 0.1 0.35 0.35 0.6 0.6
0.2 0.5 -
MHz MHz MHz MHz MHz MHz dB dB dB dB dB dB dB dB dB dB dB dB dB dB
AV = +1, +RS = 550 (PDIP), +RS = 700 (SOIC) AV = +2
B B B B
Gain Peaking
AV = +2, VOUT = 0.2VP-P
B B
Gain Flatness (AV = +2, VOUT = 0.2VP-P, Note 6)
To 125MHz
B B
To 200MHz
B B
To 250MHz
B B
Gain Flatness (AV = +1, +RS = 550 (PDIP), +RS = 700 (SOIC), VOUT = 0.2VP-P, (Note 6)
To 125MHz
B B
To 200MHz
B B
To 250MHz
B B
OUTPUT CHARACTERISTICS Output Voltage Swing, Unloaded (Note 6) Output Current (Note 6) Output Short Circuit Current Closed Loop Output Resistance (Note 6) AV = -1, RL = Infinity A A AV = -1, RL = 75 A A AV = -1 DC, AV = +1 B B 25 Full 25, 85 -40 25 25 3 2.8 33 30 3.2 3 36 33 120 0.05 V V mA mA mA W
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FN4019.5 April 23, 2007
HFA1109
Electrical Specifications
VSUPPLY = 5V, AV = +2, RF = 250, RL = 100, Unless Otherwise Specified. (Continued) (NOTE 5) TEST LEVEL B B B B B
PARAMETER Second Harmonic Distortion (VOUT = 2VP-P, Note 6) Third Harmonic Distortion (VOUT = 2VP-P, Note 6) Reverse Isolation (S12) TRANSIENT CHARACTERISTICS Rise and Fall Times
TEST CONDITIONS 20MHz 60MHz 20MHz 60MHz 30MHz
TEMP. (C) 25 25 25 25 25
MIN -
TYP -55 -57 -68 -60 -65
MAX -
UNITS dBc dBc dBc dBc dB
VOUT = 0.5VP-P
B B
25 Full 25 Full 25 Full 25 Full 25 Full 25 25 25 25
2300 2200 475 430 940 800 -
1.1 1.1 0 0.5 2600 2500 550 500 1100 950 19 23 36 5
1.3 1.4 2 5 -
ns ns % % V/s V/s V/s V/s V/s V/s ns ns ns ns
Overshoot
VOUT = 0.5VP-P
B B
Slew Rate
AV = -1, RF = 200 VOUT = 5VP-P AV = +1, VOUT = 4VP-P, +RS = 550 (PDIP), +RS = 700 (SOIC) AV = +2, VOUT = 5VP-P
B B B B B B
Settling Time (VOUT = +2V to 0V step, Note 6)
To 0.1% To 0.05% To 0.01%
B B B B
Overdrive Recovery Time VIDEO CHARACTERISTICS Differential Gain (f = 3.58MHz)
VIN = 2V
RL = 150
B B
25 Full 25 Full 25 Full 25 Full
-
0.02 0.03 0.04 0.05 0.02 0.02 0.05 0.06
0.06 0.09 0.09 0.12 0.06 0.06 0.09 0.13
% % % %
RL = 75
B B
Differential Phase (f = 3.58MHz)
RL = 150
B B
RL = 75
B B
POWER SUPPLY CHARACTERISTICS Power Supply Range Power Supply Current (Note 6) C A A NOTES: 5. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only. 6. See Typical Performance Curves for more information. 25 25 Full 4.5 9.6 10 5.5 10 11 V mA mA
4
FN4019.5 April 23, 2007
HFA1109 Application Information
Optimum Feedback Resistor
Although a current feedback amplifier's bandwidth dependency on closed loop gain isn't as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier's unique relationship between bandwidth and RF. All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF, in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier's bandwidth is inversely proportional to RF. The HFA1109 design is optimized for a 250 RF at a gain of +2. Decreasing RF decreases stability, resulting in excessive peaking and overshoot (Note: Capacitive feedback will cause the same problems due to the feedback impedance decrease at higher frequencies). At higher gains the amplifier is more stable, so RF can be decreased in a trade-off of stability for bandwidth.
TABLE 1. OPTIMUM FEEDBACK RESISTOR GAIN (ACL) -1 +1 +2 +5 +10 RF (W) 200 250 (+RS = 550W) PDIP 250 (+RS = 700W) SOIC 250 100 90 BANDWIDTH (MHz)
ground plane is a must! Attention should be given to decoupling the power supplies. A large value (10F) tantalum in parallel with a small value (0.1F) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. Care must also be taken to minimize the capacitance to ground seen by the amplifier's inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting in pulse overshoot and possible instability. Thus it is recommended that the ground plane be removed under traces connected to -IN, and connections to -IN should be kept as short as possible.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier's phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth. By decreasing RS as CL increases, the maximum bandwidth is obtained without sacrificing stability. In spite of this, bandwidth still decreases as the load capacitance increases.
400 350 450 160 70
Table 1 lists recommended RF values, and the expected bandwidth, for various closed loop gains. For a gain of +1, a resistor (+RS) in series with +IN is required to reduce gain peaking and increase stability
Evaluation Board
The performance of the HFA1105 may be evaluated using the HFA11XX Evaluation Board and a SOIC to DIP adaptor like the Aries Electronics Part Number 14-350000-10. The layout and schematic of the board are shown in Figure 1. Please contact your local sales office for information. When evaluating this amplifier, the two 510 gain setting resistors on the evaluation board should be changed to 250..
PC Board Layout
The frequency response of this amplifier depends greatly on the care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid
510
510
VH 8 7 50 +5V OUT VL GND 6 5 GND +IN 0.1F 10F
VH 1
1 50 IN 2 3 4
10F 0.1F
OUT V+ VL VGND
-5V
FIGURE 1A. BOARD SCHEMATIC
FIGURE 1B. TOP LAYOUT
FIGURE 1C. BOTTOM LAYOUT
FIGURE 1. EVALUATION BOARD SCHEMATICS AND LAYOUT
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FN4019.5 April 23, 2007
HFA1109 Typical Performance Curves
VSUPPLY = 5V, TA = +25C, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified
200 AV = +2 150 OUTPUT VOLTAGE (mV) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV)
2.0 AV = +2 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV)
FIGURE 2. SMALL SIGNAL PULSE RESPONSE
OUTPUT VOLTAGE (V)
FIGURE 3. LARGE SIGNAL PULSE RESPONSE
200 AV = +1 150 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV)
2.0 AV = +1 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV)
FIGURE 4. SMALL SIGNAL PULSE RESPONSE
FIGURE 5. LARGE SIGNAL PULSE RESPONSE
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FN4019.5 April 23, 2007
HFA1109 Typical Performance Curves
200 AV = -1 150 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 100 50 0 -50 -100 -150 -200 TIME (5ns/DIV) 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV)
VSUPPLY = 5V, TA = +25C, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified (Continued)
2.0 AV = -1
FIGURE 6. SMALL SIGNAL PULSE RESPONSE
FIGURE 7. LARGE SIGNAL PULSE RESPONSE
200 150 OUTPUT VOLTAGE (mV) OUTPUT VOLTAGE (V) 100 50 0 -50 AV = +5 -100 -150 -200 TIME (5ns/DIV.) AV = +5
2.0 1.5 1.0 0.5 AV = +10 0 AV = +10 -0.5 -1.0 -1.5 -2.0 TIME (5ns/DIV.) AV = +5 AV = +5
AV = +10
AV = +10
FIGURE 8. SMALL SIGNAL PULSE RESPONSE
FIGURE 9. LARGE SIGNAL PULSE RESPONSE
GAIN (dB)
3 0 -3
VOUT = 200mVP-P GAIN AV = +1 NORMALIZED PHASE (DEGREES)
NORMALIZED GAIN (dB)
3 0 -3
VOUT = 200mVP-P GAIN AV = +10 AV = +5 PHASE AV = +2
AV = +2
AV = +1 PHASE AV = -1 0 90 180 AV = -1 0.3M 1M 10M FREQUENCY (Hz) 100M 270 700M
0 90 180 270 700M PHASE ()
AV = +1
AV = +10 AV = +5
0.3M
1M
10M FREQUENCY (Hz)
100M
FIGURE 10. FREQUENCY RESPONSE
FIGURE 11. FREQUENCY RESPONSE
7
FN4019.5 April 23, 2007
HFA1109 Typical Performance Curves
VSUPPLY = 5V, TA = +25C, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified (Continued)
116 0.1 0 NORMALIZED GAIN (dB) -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 1M 10M FREQUENCY (Hz) 100M 500M AV = +2 VOUT = 200mVP-P AV = +1 106
( VIO ) ) I
AZOL (dB, 20 LOG
96 86 76 66 56 46 36 26 0.01M 0.1M 0.3M 1M 3M 6M10M30M 100M FREQUENCY (Hz) 0 45 PHASE () 12 15 90 135 180 500M
FIGURE 12. GAIN FLATNESS
FIGURE 13. OPEN LOOP TRANSIMPEDANCE
-30 AV = +1 -40 DISTORTION (dBc) -50 50MHz -60 20MHz -70 10MHz 100MHz
-20 AV = +1 -30 100MHz -40 DISTORTION (dBc) -50 -60 -70 -80 -90 -6 -3 0 3 6 OUTPUT POWER (dBm) 9 12 -100 -6 -3 0 3 6 OUTPUT POWER (dBm) 9 50MHz
20MHz
10MHz
-80
-90
FIGURE 14. 2nd HARMONIC DISTORTION vs POUT
FIGURE 15. 3rd HARMONIC DISTORTION vs POUT
-30 AV = +2 -40 100MHz DISTORTION (dBc) -50 50MHz -60 10MHz -70 20MHz -80 DISTORTION (dBc)
-30 AV = +2 -40 100MHz -50 50MHz -60 20MHz -70 10MHz -80
-90
-6
-3
0
3 6 9 OUTPUT POWER (dBm)
12
15
-90
-6
-3
0
3 6 9 OUTPUT POWER (dBm)
12
FIGURE 16. 2nd HARMONIC DISTORTION vs POUT
FIGURE 17. 3rd HARMONIC DISTORTION vs POUT
8
FN4019.5 April 23, 2007
HFA1109 Typical Performance Curves
-20 VOUT = 2VP-P -30 DISTORTION (dBc) -30 AV = +1 -40 DISTORTION (dBc) -40 AV = -1 AV = +2
VSUPPLY = 5V, TA = +25C, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified (Continued)
-20 VOUT = 2VP-P
-50 AV = +2, -1 -60 AV = +1
-50
-60
-70
-70 AV = +1
-80 0M
10M 20M 30M 40M 50M 60M 70M 80M 90M 100M FREQUENCY (Hz)
-80 0M
10M 20M 30M 40M 50M 60M 70M 80M 90M 100M FREQUENCY (Hz)
FIGURE 18. 2nd HARMONIC DISTORTION vs FREQUENCY
FIGURE 19. 3rd HARMONIC DISTORTION vs FREQUENCY
3.6 AV = +2 OUTPUT RESISTANCE () 1k OUTPUT VOLTAGE (V) 100 10 1 0.1 0.01 3.4 3.2 3.0 +VOUT (RL = 50) 2.8 2.6 2.4 2.2 2.0 1.8 0.3 1M 10M FREQUENCY (Hz) 100M 1000M 1.6 -75 -50 -25 0 25 50 75 100 125 |-VOUT| (RL = 50) |-VOUT| (RL = 100) +VOUT (RL = 50) +VOUT (RL = 100) |-VOUT| (RL = 100)
TEMPERATURE (C)
FIGURE 20. CLOSED LOOP OUTPUT RESISTANCE
FIGURE 21. OUTPUT VOLTAGE vs TEMPERATURE
14.0 13.5 13.0 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 12.5 12.0 11.5 11.0 10.5 10.0 9.50 9.00 8.50 4 4.5 5 5.5 6.5 6 SUPPLY VOLTAGE (V) 7 7.5 8
17 16 15 14 13 12 11 10 9 8 7 6 5 4 -75 -50 -25 0 25 50 TEMPERATURE (C) 75 100 125 VS = 4V VS = 5V VS = 8V
FIGURE 22. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 23. SUPPLY CURRENT vs TEMPERATURE
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FN4019.5 April 23, 2007
HFA1109 Typical Performance Curves
100
VSUPPLY = 5V, TA = +25C, RF = Value From the Optimum Feedback Resistor Table, RL = 100, Unless Otherwise Specified (Continued)
100 0.1 AV = +2 VOUT = 2V
NOISE VOLTAGE (nV/Hz)
NOISE CURRENT (pA/Hz)
SETTLING ERROR (%)
INIINI+ 10 ENI 10
0.05 0.025 0 -0.025 -0.05
INI+ 1 0.1k 1k 10k FREQUENCY (Hz) 1 100k
-0.1
10
20
30
40
50
60
70
80
90
100
TIME (ns)
FIGURE 24. INPUT NOISE CHARACTERISTICS
FIGURE 25. SETTLING RESPONSE
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FN4019.5 April 23, 2007
HFA1109 Die Characteristics
DIE DIMENSIONS: 59milsx80milsx19mils 1500mx2020mx483m METALLIZATION: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kA 0.4kA Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kA 0.8kA
HFA1109
GLASSIVATION: Type: Nitride Thickness: 4kA 0.5kA TRANSISTOR COUNT: 130 SUBSTRATE POTENTIAL (POWERED UP): Floating (Recommend Connection to V-)
Metallization Mask Layout
NC
NC
NC NC
V+ -IN OUT
NC
NC
+IN
V-
NC
NC
11
FN4019.5 April 23, 2007
HFA1109 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45 H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 8 0 8 MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 NOTES 9 3 4 5 6 7 Rev. 1 6/05
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050
B C D E e H
C
A1 0.10(0.004)
0.050 BSC
1.27 BSC
e
B 0.25(0.010) M C AM BS
h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN4019.5 April 23, 2007

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