 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ADJD-S312-CR999 Miniature Surface-Mount RGB Digital Color Sensor Data Sheet Description The ADJD-S312-CR999 is a cost effective, CMOS digital output RGB color sensor in miniature surface-mount package with a mere size of 3x3x0.77mm. The IC comes with integrated RGB filters, an analog-to-digital converter and a digital core for communication and sensitivity control. The output allows direct interface to micro-controller or other logic control for further signal processing without the need of any additional components. This device is designed to cater for wide dynamic range of illumination level and is ideal for applications like portable or mobile devices which demand higher integration, smaller size and low power consumption. Sensitivity control is performed by the serial interface and can be optimized individually for the different color channel. The sensor can also be used in conjunction with a white LED for reflective color management. Features * * * * * * * * * * * * Fully integrated RGB digital color sensor Digital I/O via 2-wire serial interface Industry's smallest form factor - CSP 3x3x0.77mm Adjustable sensitivity for different levels of illumination Uniformly distributed RGB photodiode array 7 bit resolution per channel output Built in internal oscillator Sleep function when not in use No external components Low supply voltage (VDD) 2.6V 0C to 70C operating temperature Lead free package Applications * General color detection and measurement * Mobile appliances such as mobile phones, PDAs, MP3 players,etc * Consumer appliances * Portable medical equipments * Portable color detector/reader ESD WARNING: Standard CMOS handling precautions should be observed to avoid static discharge. AVAGO TECHNOLOGIES' PRODUCTS AND SOFTWARE ARE NOT SPECIFICALLY DESIGNED, MANUFACTURED OR AUTHORIZED FOR SALE AS PARTS, COMPONENTS OR ASSEMBLIES FOR THE PLANNING, CONSTRUCTION, MAINTENANCE OR DIRECT OPERATION OF A NUCLEAR FACILITY OR FOR USE IN MEDICAL DEVICES OR APPLICATIONS. CUSTOMER IS SOLELY RESPONSIBLE, AND WAIVES ALL RIGHTS TO MAKE CLAIMS AGAINST AVAGO TECHNOLOGIES OR ITS SUPPLIERS, FOR ALL LOSS, DAMAGE, EXPENSE OR LIABILITY IN CONNECTION WITH SUCH USE. General Specifications Feature Interface Supply Value 100kHz serial interface 2.6V digital (nominal), 2.6V analog (nominal) Powering the Device No voltage must be applied to IO's during power-up and power-down ramp time VDDD / VDDA 0V tVDD_RAMP ESD Protection Diode Turn-On During Power-Up and Power-Down A particular power-up and power-down sequence must be used to prevent any ESD diode from turning on inadvertently. The figure above describes the sequence. In general, AVDD and DVDD should power-up and powerdown together to prevent ESD diodes from turning on inadvertently. During this period, no voltage should be applied to the IO's for the same reason. Ground Connection AGND and DGND must both be set to 0V and preferably star-connected to a central power source as shown in the application diagram. A potential difference between AGND and DGND may cause the ESD diodes to turn on inadvertently. Block Diagram SDASLV SCLSLV XRST SLEEP Control Core Gain Selection RGB PHOTOSENSOR ARRAY PHOTOCURRENT TO VOLTAGE CONVERSION RED PHOTOCURRENT TO VOLTAGE CONVERSION GREEN PHOTOCURRENT TO VOLTAGE CONVERSION BLUE ANALOG TO DIGITAL CONVERSION Electrical Specifications Absolute Maximum Ratings (Notes 1 & 2) Parameter Storage temperature Digital supply voltage, DVDD to DVSS Analog supply voltage, AVDD to AVSS Input voltage Solder Reflow Peak temperature Human Body Model ESD rating Symbol TSTG_ABS Minimum -40 Maximum 85 3.7 3.7 VDDD+0.5 245 2 Units C V V V C kV Notes VDDD_ABS -0.5 VDDA_ABS -0.5 VIN_ABS TL_ABS ESDHBM_ ABS -0.5 All I/O pins All pins, human body model per JESD22-A114-B Recommended Operating Conditions Parameter Free air operating temperature Digital supply voltage, DVDD to DVSS Analog supply voltage, AVDD to AVSS Output current load high Output current load low Input voltage high level (Note 4) Input voltage low level (Note 4) Symbol TA VDDD VDDA IOH IOL VIH VIL Minimum 0 2.5 2.5 Maximum 25 2.6 2.6 Units 70 3.6 3.6 3 3 Notes C V V mA mA V V 0.7 VDDD 0 VDDD 0.3 VDDD DC Electrical Specifications Over Recommended Operating Conditions (unless otherwise specified) Parameter Output voltage high level (Note 5) Output voltage low level (Note 6) Dynamic supply current (Note 7,8) Static supply current (Note 8) Sleep-mode supply current (Note 8) Input leakage current Symbol VOH VOL IDD_DYN IDD_STATIC IDD_SLP ILEAK Conditions IOH = 3mA IOL = 3mA (Note 9) (Note 9) (Note 9) Minimum VDDD-0.8 Typical (Note 3) Maximum VDDD-0.4 0.2 9.4 2.7 0.2 15 10 0.4 14 Units V V mA mA uA uA -10 AC Electrical Specifications Parameter Internal clock frequency Symbol fCLK Conditions Minimum 16 Typical (Note 3) 26 Maximum 38 Units MHz Optical Specification Parameter Dark offset* *code is from dark code to (dark code + 128LSB) Symbol VD Conditions Ee = 0 Minimum Typical (Note 3) 65 Maximum Units LSB Minimum sensitivity (note 3) Parameter Symbol Conditions lP = 460 nm Refer Note 10 Irradiance Responsivity Re lP = 542 nm Refer Note 11 lP = 645 nm Refer Note 12 B G R Minimum Typical (Note 3) 36 52 79 Maximum Units LSB/ (mWcm-2) Maximum sensitivity (note 3) Parameter Symbol Conditions lP = 460 nm Refer Note 10 Irradiance Responsivity Re lP = 542 nm Refer Note 11 lP = 645 nm Refer Note 12 B G R Minimum Typical (Note 3) 1150 1640 2310 Maximum Units LSB/ (mWcm-2) Minimum sensitivity (note 13) Parameter Symbol Conditions lP = 460 nm Refer Note 10 Saturation Irradiance lP = 542 nm Refer Note 11 lP = 645 nm Refer Note 12 B G R Minimum Typical (Note 3) 4.17 2.88 1.90 Maximum Units mWcm-2 Maximum sensitivity (note 13) Parameter Symbol Conditions lP = 460 nm Refer Note 10 Saturation Irradiance lP = 542 nm Refer Note 11 lP = 645 nm Refer Note 12 B G R Minimum Typical (Note 3) 0.13 0.09 0.06 Maximum Units mWcm-2 Notes: 1. The "Absolute Maximum Ratings" are those values beyond which damage to the device may occur. The device should not be operated at these limits. The parametric values defined in the "Electrical Specifications" table are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. 2. Unless otherwise specified, all voltages are referenced to ground. 3. Specified at room temperature (25C) and VDDD = VDDA = 2.6V. 4. Applies to all DI pins. 5. Applies to all DO pins. SDASLV go tri-state when output logic high. Minimum VOH depends on the pull-up resistor value. 6. Applies to all DO and DIO pins. 7. Dynamic testing is performed with the IC operating in a mode representative of typical operation. 8. Refers to total device current consumption. 9. Output and bidirectional pins are not loaded. 10. Test condition is blue light of peak wavelength (lP) 460 nm and spectral half width (l1/2) 25 nm. 11. Test condition is green light of peak wavelength (lP) 542 nm and spectral half width (l1/2) 35 nm 12. Test condition is red light of peak wavelength (lP) 645 nm and spectral half width (l1/2) 20 nm 13. Saturation irradiance = (MSB)/(Irradiance responsivity) 1 Relative sensitivity 0.8 0.6 0.4 0.2 0 400 Spectral response 500 600 700 Wavelength (nm) Typical spectral response when the gains for all the color channels are set at equal. Serial Interface Timing Information Parameter SCL clock frequency (Repeated) START condition hold time Data hold time SCL clock low period SCL clock high period Repeated START condition setup time Data setup time STOP condition setup time Bus free time between START and STOP conditions Symbol fscl tHD:STA tHD:DAT tLOW tHIGH tSU:STA tSU:DAT tSU:STO tBUF tSU:STA Minimum 0 0 . .0 . 0 .0 . Maximum 100 . - Units kHz s s s s s ns s s tBUF tHD:STA tHIGH tSU:DAT SDA SCL S tLOW tHD:DAT Sr tHD:STA P tSU:STO S Figure 1. Serial Interface Bus Timing Waveforms High Level Description The sensor needs to be configured before it can be used. The gain selection needs to be set for optimum performance depending on light levels. The flowcharts below describe the different procedures required. SENSOR GAIN OPTIMIZATION Step 1 Hardware Reset Step 2 Device Initialization Step 3 - 4 Select sensor gain settings Step 5 Acquire ADC readings SENSOR OPERATION Step 1 Hardware Reset Step 2 Device Initialization Step 3 - 4 Select sensor gain settings Step 5 Acquire dark offset and store current offset values No ADC readings optimum? Yes Step 6 Acquire ADC readings Step 7 Compute sensor values STOP STOP Sensor gain optimization flowchart Sensor operation flowchart * Please refer to application note for more detailed information. Detail Description A hardware reset (by asserting XRST) should be performed before starting any operation. The user controls and configures the device by programming a set of internal registers through a serial interface. At the start of application, the following setup data must be written to the setup registers: Address (Hex) 03 04 0C 0D 0E Setup Value for Integration Time The following value can be written to each of the integration time registers to adjust the gain of the sensor. The default value after reset for these registers is 07H. Value (Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F Integration Time Slot 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Register SETUP0 SETUP1 SETUP2 SETUP3 SETUP4 Setup Data (Hex) 01 01 01 01 01 Sensor Gain Settings The sensor gain can be adjusted by varying the photodiode size and integration time of the sensor manually through the following registers. Sensor Sensitivity ~ Photodiode Size x Integration Time Slot Address (Hex) 0B 0A 09 11 10 0F Register PDASR PDASG PDASB TINTR TINTG TINTB Description Red Channel Photodiode Size Green Channel Photodiode Size Blue Channel Photodiode Size Red Channel Integration Time Green Channel Integration Time Blue Channel Integration Time Sensor ADC Output Registers To obtain sensor ADC value, `02' Hex must be written to ACQ register before reading the Sensor ADC Output Registers. Address (Hex) 02 Register ACQ Description Acquire sensor analog to digital converter (ADC) values when 02H is written. Reset to 00H when sensor acquisition is completed Sensor Red channel ADC value. Sensor Green channel ADC value. Sensor Blue channel ADC value. Setup Value for Photodiode Size The following value can be written to each of the photodiode size registers to adjust the gain of the sensor. The default value after reset for these registers is 07H. Value (Hex) 01 03 07 0F 44 ADCR ADCG ADCB Photodiode Size 1/4 1/2 3/4 Full 43 42 Serial Interface Reference Description The programming interface to the ADJD-S312 is a 2-wire serial bus. The bus consists of a serial clock (SCL) and a serial data (SDA) line. The SDA line is bi-directional on ADJD-S312 and must be connected through a pull-up resistor to the positive power supply. When the bus is free, both lines are HIGH. The 2-wire serial bus on ADJD-S312 requires one device to act as a master while all other devices must be slaves. A master is a device that initiates a data transfer on the bus, generates the clock signal and terminates the data transfer while a device addressed by the master is called a slave. Slaves are identified by unique device addresses. Both master and slave can act as a transmitter or a receiver but the master controls the direction for data transfer. A transmitter is a device that sends data to the bus and a receiver is a device that receives data from the bus. The ADJD-S312 serial bus interface always operates as a slave transceiver with a data transfer rate of up to 100kbit/s. START/STOP Condition The master initiates and terminates all serial data transfers. To begin a serial data transfer, the master must send a unique signal to the bus called a START condition. This is defined as a HIGH to LOW transition on the SDA line while SCL is HIGH. The master terminates the serial data transfer by sending another unique signal to the bus called a STOP condition. This is defined as a LOW to HIGH transition on the SDA line while SCL is HIGH. The bus is considered to be busy after a START (S) condition. It will be considered free a certain time after the STOP (P) condition. The bus stays busy if a repeated START (Sr) is sent instead of a STOP condition. The START and repeated START conditions are functionally identical. Data Transfer The master initiates data transfer after a START condition. Data is transferred in bits with the master generating one clock pulse for each bit sent. For a data bit to be valid, the SDA data line must be stable during the HIGH period of the SCL clock line. Only during the LOW period of the SCL clock line can the SDA data line change state to either HIGH or LOW. SDA SCL Data valid Figure 2: Data Bit Transfer Data change The SCL clock line synchronizes the serial data transmission on the SDA data line. It is always generated by the master. The frequency of the SCL clock line may vary throughout the transmission as long as it still meets the minimum timing requirements. The master by default drives the SDA data line. The slave drives the SDA data line only when sending an acknowledge bit after the master writes data to the slave or when the master requests the slave to send data. The SDA data line driven by the master may be implemented on the negative edge of the SCL clock line. The master may sample data driven by the slave on the positive edge of the SCL clock line. Figure shows an example of a master implementation and how the SCL clock line and SDA data line can be synchronized. SDA data sampled on the positive edge of SCL SDA SCL SDA data driven on the negative edge of SCL Figure 3: Data Bit Synchronization SDA SCL S START condition P STOP condition Figure 1: START/STOP Condition A complete data transfer is 8-bits long or 1-byte. Each byte is sent most significant bit (MSB) first followed by an acknowledge or not acknowledge bit. Each data transfer can send an unlimited number of bytes (depending on the data format). See Figure 4. Acknowledge/Not acknowledge The receiver must always acknowledge each byte sent in a data transfer. In the case of the slave-receiver and master-transmitter, if the slave-receiver does not send an acknowledge bit, the master-transmitter can either STOP the transfer or generate a repeated START to start a new transfer. See Figure 5. In the case of the master-receiver and slave-transmitter, the master generates a not acknowledge to signal the end of the data transfer to the slave-transmitter. The master can then send a STOP or repeated START condition to begin a new data transfer. In all cases, the master generates the acknowledge or not acknowledge SCL clock pulse. See Figure 6. P SDA MSB LSB ACK MSB LSB NO ACK 9 Sr Sr or P SCL S or Sr 1 2 8 9 1 2 8 START or repeated START condition Figure 4: Data Byte Transfer STOP or repeated START condition SDA pulled LOW by receiver SDA (SLAVE-RECEIVER) SDA Acknowledge (MASTER-TRANSMITTER) LSB SDA left HIGH by transmitter 9 Acknowledge clock pulse SCL (MASTER) 8 Figure 5: Slave-Receiver Acknowledge SDA (SLAVE-TRANSMITTER) SDA (MASTER-RECEIVER) SCL (MASTER) LSB SDA left HIGH by transmitter P SDA left HIGH by receiver Not acknowledge 9 Acknowledge clock pulse Sr 8 Figure 6: Master-Receiver Acknowledge STOP or repeated START condition 10 Addressing Each slave device on the serial bus needs to have a unique address. This is the first byte that is sent by the master-transmitter after the START condition. The address is defined as the first seven bits of the first byte. The eighth bit or least significant bit (LSB) determines the direction of data transfer. A `one' in the LSB of the first byte indicates that the master will read data from the addressed slave (master-receiver and slave-transmitter). A `zero' in this position indicates that the master will write data to the addressed slave (master-transmitter and slave-receiver). A device whose address matches the address sent by the master will respond with an acknowledge for the first byte and set itself up as a slave-transmitter or slave-receiver depending on the LSB of the first byte. The slave address on ADJD-S312 is 0x58 (7-bits). MSB A6 1 A5 0 A4 1 A3 1 A2 0 A1 0 A0 0 LSB R/W Data format ADJD-S312 uses a register-based programming architecture. Each register has a unique address and controls a specific function inside the chip. To write to a register, the master first generates a START condition. Then it sends the slave address for the device it wants to communicate with. The least significant bit (LSB) of the slave address must indicate that the master wants to write to the slave. The addressed device will then acknowledge the master. The master writes the register address it wants to access and waits for the slave to acknowledge. The master then writes the new register data. Once the slave acknowledges, the master generates a STOP condition to end the data transfer. See figure 8. To read from a register, the master first generates a START condition. Then it sends the slave address for the device it wants to communicate with. The least significant bit (LSB) of the slave address must indicate that the master wants to write to the slave. The addressed device will then acknowledge the master. The master writes the register address it wants to access and waits for the slave to acknowledge. The master then generates a repeated START condition and resends the slave address sent previously. The least significant bit (LSB) of the slave address must indicate that the master wants to read from the slave. The addressed device will then acknowledge the master. The master reads the register data sent by the slave and sends a no acknowledge signal to stop reading. The master then generates a STOP condition to end the data transfer. See figure 9. Slave address Figure 7: Slave Addressing Start condition S Master will write data A D7 D6 D5 D4 D3 D2 D1 D0 A Stop condition D7 D6 D5 D4 D3 D2 D1 D0 A P A6 A5 A4 A3 A2 A1 A0 W Master sends slave address Master writes register address Slave acknowledge Master writes register data Slave acknowledge Slave acknowledge Figure 8: Register Byte Write Protocol Start condition S Master will write data A Repeated start condition A Sr Master will read data A Stop condition A P A6 A5 A4 A3 A2 A1 A0 W D7 D6 D5 D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 A1 A0 R D7 D6 D5 D4 D3 D2 D1 D0 Master sends slave address Master writes register address Slave acknowledge Slave acknowledge Master sends slave address Master reads register data Slave acknowledge Master not acknowledge Figure 9: Register Byte Read Protocol 11 Powering the Device Ground Connection AGND and DGND must both be set to 0V and preferably star-connected to a central power source as shown in the application diagram. A potential difference between AGND and DGND may cause the ESD diodes to turn on inadvertently. Application Diagrams HOST SYSTEM 10k DVDD 10k 10k 10k XRST SDA SCL HOST SYSTEM AVDD A1 Voltage Regulator AGND A2, A3, D2 DGND C2 DVDD D1 Voltage Regulator Star-connected ground D4 C4 C3 XRST SDASLV SCLSLV A4 SLEEP Pin Information Pin A1 A2 A3 A4 Name AVDD AGND AGND SLEEP Type Power Ground Ground Input Description Analog power pin. Tie to analog ground. Tie to analog ground. When SLEEP=1, the device goes into sleep mode. In sleep mode, all analog circuits are powered down and the clock signal is gated away from the core logic resulting in very low current consumption. No connect. Leave floating. No connect. Leave floating. No connect. Leave floating. No connect. Leave floating. No connect. Leave floating Tie to digital ground. SDASLV and SCLSLV are the serial interface communications pins. SDASLV is the bidirectional data pin and SCLSLV is the interface clock. A pull-up resistor should be tied to SDASLV because it goes tri-state to output logic 1. Digital power pin. Tie to analog ground. No connect. Leave floating. Global, asynchronous, active-low system reset. When asserted low, XRST resets all registers. Minimum reset pulse low is 1 us and must be provided by external circuitry. B1 B2 B3 B4 C1 C2 C3 C4 NC NC NC NC NC DGND SCLSLV SDASLV No connect No connect No connect No connect No connect Ground Input Input/ Output(tri-state high) Power Ground No connect Input D1 D2 D3 D4 DVDD AGND NC XRST 1 Pin Configuration 1 A B C D AVDD NC NC DVDD 2 AGND NC DGND AGND 3 AGND NC SCLSLV NC 4 SLEEP NC SDASLV XRST Package Dimensions Note: 1. Dimensions are in milimeters (mm) 2. Standard tolerances (unless otherwise specified) a. Linear tolerance = +/-0.1mm b. Angular tolerance = +/-1 1 Recommended Underfill Type and Characteristic * Low moisture absorption type * Total height of underfill from PCB plane to cover up 70 - 85 % * Underfill to cover all 4 side of the package Height 70 ~ 85% Underfill PCB Recommended Reflow Profile It is recommended that Henkel Pb-free solder paste LF310 be used for soldering ADJD-S312-CR999. Below is the recommended reflow profile. T-peak T-reflow 240 5C 217~220 C Delta-Flux max. 2 C/sec. T-max. 180C 160C TEMPERATURE Delta-Cooling max. 2 C/sec. T-min. Delta-Ramp max. 1 C/sec. 100 ~ 140 sec. t-comp t-pre 90 ~ 120 sec. t-reflow TIME 1 Recommended PCB land pad design * NiAu flash over copper pad * Pad Diameter (C)= 0.20 mm * NSMD Diameter (D)= 0.25 ~ 0.30 mm After soldering or mounting precaution Please ensure that all soldered or reflowed CSP package that is mounted on the PCB is not exposed to compression or loading force directly perpendicular to the flat top surface. Precaution: NSMD Excessive loading force directly perpendicular to the flat top surface may cause pre-mature failure. Loading Force PCB Recommended Stencil Design * * * * * Stencil thickness Stencil type Stencil Aperture Type Stencil Aperture Additional Feature 5 mils Ni Electroforming Square 310 um Rounded square edge 310 um 560 um 1 Recommendations for Handling and Storage of ADJD-S312 This product is qualified as Moisture Sensitive Level 3 per Jedec J-STD-020. Precautions when handling this moisture sensitive product is important to ensure the reliability of the product. Do refer to Avago Application Note AN5305 Handling Of Moisture Sensitive Surface Mount Devices for details. A. Storage before use * Unopened moisture barrier bag (MBB) can be stored at 30C and 90%RH or less for maximum 1 year * It is not recommended to open the MBB prior to assembly (e.g. for IQC) * It should also be sealed with a moisture absorbent material (Silica Gel) and an indicator card (cobalt chloride) to indicate the moisture within the bag B. Control after opening the MBB * The humidity indicator card (HIC) shall be read immediately upon opening of MBB * The components must be kept at <30C/60%RH at all time and all high temperature related process including soldering, curing or rework need to be completed within 168hrs C. Control for unfinished reel * For any unused components, they need to be stored in sealed MBB with desiccant or desiccator at <5%RH D. Control of assembled boards * If the PCB soldered with the components is to be subjected to other high temperature processes, the PCB need to be stored in sealed MBB with desiccant or desiccator at <5%RH to ensure no components have exceeded their floor life of 168hrs E. Baking is required if: * * * * "10%" or "15%" HIC indicator turns pink The components are exposed to condition of >30C/60%RH at any time. The components floor life exceeded 168hrs Recommended baking condition (in component form): 125C for 24hrs 1 Package Tape and Reel Dimensions Carrier Tape Dimensions 4.00 0.10 SEE NOTE #2 2.00 0.05 SEE NOTE #2 B 1.55 0.05 R 0.50 TYP. 1.75 0.10 5.50 0.05 Bo A Ko SECTION B-B Ao Ao: Bo: Ko : PITCH: WIDTH: 3.30 3.30 1.10 8.00 12.00 A 12.00 0.10 B 8.00 0.10 1.50 (MIN.) 0.30 0.05 SECTION A-A NOTES: 1. Ao AND Bo MEASURED AT 0.3 mm ABOVE BASE OF POCKET. 2. 10 PITCHES CUMULATIVE TOLERANCE IS 0.2 mm. 3. DIMENSIONS ARE IN MILLIMETERS (mm). Reel Dimensions 65 R10.65 45 +1.5* 12.4 - 0.0 R5.2 45 55.0 0.5 178.0 0.5 176.0 EMBOSSED RIBS RAISED: 0.25 mm WIDTH: 1.25 mm BACK VIEW 512 18.0 MAX.* NOTES: 1. *MEASURED AT HUB AREA. 2. ALL FLANGE EDGES TO BE ROUNDED. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright (c) 2007 Avago Technologies Limted. All rights reserved. Obsoletes AV01-0687EN AV02-0637EN - July 30, 2007 |
Price & Availability of ADJD-S312-CR999
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |