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ASAHI KASEI
[AKD4552-A]
AKD4552-A
Evaluation board Rev.0 for AK4552
GENERAL DESCRIPTION AKD4552-A is an evaluation board for the digital audio 24bit A/D and D/A converter, AK4552. The AKD4552-A can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D D/A). The A/D section can be evaluated by interfacing with AKM's DAC evaluation boards directly. The AKD4552-A has the interface with AKM's ADC evaluation boards. Therefore, it's easy to evaluate the D/A section. The AKD4552-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD4552-A --Evaluation board for AK4552
FUNCTION * DIT/DIR with optical input/output * BNC connector for an external clock input
2.4 ~ 4.0V GND
LIN RIN AK4112B (DIR) Opt In
AK4552
LOUT ROUT AK4103A (DIT) Opt Out
A/D, D/A Data 10pin Header
Clock Generator
Figure 1. AKD4552-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
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ASAHI KASEI
[AKD4552-A]
Analog Input Circuit
External analog signal fed through the BNC connector is terminated by a resistor of 560 ohms. The resistor value should be properly selected in order to meet the output impedance of the signal source.
J4(J2) LIN(RIN) C4(C2) 10u LIN(RIN)pin +
R6(R4) 560
Figure 2. Input buffer circuit on board * AKM assumes no responsibility for the trouble when using the circuit examples.
Analog Output Circuit
The AK4552 includes a combination of switched-capacitor filter (SCF) and continuous-time filter (CTF), so any external filters are not required.
Operation sequence
1) Set up the power supply lines. [VA] (orange) = 2.4 4.0V : for VA of AK4552 (typ. 3.0V) [D2V] (orange) = 2.4 4.0V : for D2V of 74LVC541 (typ. 3.0V) [VCC] (red) = 3.6 5.0V : for logic [AGND] (black) = 0V : for analog ground (including VSS of AK4552) [DGND] (black) = 0V : for logic ground Each supply line should be distributed from the power supply unit. D2V and VA must be same voltage level. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK4552 should be reset once bringing SW1 (PDN) "L" upon power-up.
Evaluation mode
Applicable Evaluation Mode (1) Evaluation of A/D using DIT (Optical Link) (2) Evaluation of D/A using DIR (Optical Link) (3) Evaluation of loopback mode (default) (4) Evaluation of D/A using A/D converted data (5) Evaluation of A/D using D/A converted data (6) All interface signals including master clock are fed externally.
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ASAHI KASEI
[AKD4552-A]
(1) Evaluation of A/D using DIT (Optical Link) PORT2 (DIT) and X2 (X'tal) is used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX176). It is possible to connect AKM's D/A converter evaluation boards on the digital-amplifier which equips DIR input. Nothing should be connected to PORT1 (DIR), PORT3 (ROM). In case of using external clock through a BNC connector (J5), select EXT on JP11 (CLK) and short JP8 (XTE) and open JP13 (EXT). AK4112B should be powered down.
JP3 LRCK JP4 BCLK JP6 SDTI JP8 XTE JP13 EXT
ADC
DIR
ADC
DIR
ADC
DIR
* Clock example 1-1) Normal speed of ADC (MCLK=256fs) Master clock frequency example of X2 : X2 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL X1 X4 JP12 LRFS
1-2) Normal speed of ADC (MCLK=512fs) Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL X1 X4 JP12 LRFS
1-3) Double speed of ADC (MCLK=256fs) Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL X1 X4 JP12 LRFS
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[AKD4552-A]
(2) Evaluation of D/A using DIR (Optical Link) PORT1 (DIR) is used. DIR generates MCLK, BCLK, LRCK and SDATA from the received data through optical connector (TORX176). Used for the evaluation using CD test disk. Nothing should be connected to PORT3 (ROM). Set up "H" (AK4112B : PLL mode) for SW2-5 (CM0).
JP3 LRCK JP4 BCLK JP6 SDTI JP8 XTE JP13 EXT
ADC
DIR
ADC
DIR
ADC
DIR
* Clock example 2-1) Normal speed of DAC (MCLK=256fs) Input fs example for PORT1 : fs = 32kHz, 44.1kHz, 48kHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL DEM0 X1 X4 JP12 LRFS 12 H L DEM1 SW2 MODE 3 L OCKS0 4 L OCKS1 4 H L OCKS0 OCKS1 4 L OCKS1 L CM0 5 L CM0 5 L CM0 5
2-2) Normal speed of DAC (MCLK=512fs) Input fs example for PORT1 : fs = 32kHz, 44.1kHz, 48kHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL DEM0 X1 X4 JP12 LRFS 12 H L DEM1 L DEM0 DEM1 SW2 MODE 3
2-3) Double speed of DAC (MCLK=256fs) Input fs example for PORT1 : fs = 64kHz, 88.2kHz, 96kHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL X1 X4 JP12 LRFS 12 H SW2 MODE 3 L OCKS0
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[AKD4552-A]
2-4) 1/2 decimation of DAC (MCLK=128fs) Input fs example for PORT1 : fs = 64kHz, 88.2kHz, 96kHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL DEM0 X1 X4 JP12 LRFS 12 H L OCKS0 DEM1 SW2 MODE 3 H L OCKS1 4 L OCKS1 4 OCKS1 CM0 5 CM0 L CM0 5 H L OCKS0 3 L OCKS0 4 5
(3) Evaluation of loopback mode (default) Using U4 (AK4112B) and X1 (X'tal). Nothing should be connected to PORT1 (DIR), PORT3 (ROM). Set up "H" (AK4112B : X'tal mode) for SW2-5 (CM0).
JP3 LRCK JP4 BCLK JP6 SDTI JP8 XTE JP13 EXT
ADC
DIR
ADC
DIR
ADC
DIR
* Clock example 3-1) Normal speed (MCLK=256fs) Master clock frequency example of X1 : X1 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL DEM0 JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL DEM0 X1 X4 JP12 LRFS 12 H L DEM1 X1 X4 JP12 LRFS 12 H L DEM1 SW2 MODE 3
3-2) Normal speed (MCLK=512fs) Master clock frequency example of X1 : X1 = 16.384MHz, 22.5792MHz, 24.576MHz
SW2 MODE HH
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ASAHI KASEI
[AKD4552-A]
3-3) Double speed (MCLK=256fs) Master clock frequency example of X1 : X1 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL DEM0 X1 X4 JP12 LRFS 12 H L DEM1 SW2 MODE 3 L OCKS0 4 L OCKS1 4 L OCKS1 4 L OCKS1 CM0 5 L CM0 5 L CM0 5 H
(4) Evaluation of D/A using A/D converted data It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM's A/D evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR). In case of using external clock through a BNC connector (J5), select EXT on JP11 (CLK) and short JP8 (XTE) and open JP13 (EXT). This mode corresponds to normal speed only.
JP3 LRCK JP4 BCLK JP6 SDTI JP8 XTE JP13 EXT
ADC
DIR
ADC
DIR
ADC
DIR
* Clock example 4-1) Normal speed of DAC (MCLK=256fs) Master clock frequency example of X2 : X2 = 8.192MHz, 11.2896MHz, 12.288MHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL DEM0 X1 X4 JP12 LRFS 12 H L DEM1 L DEM0 DEM1 SW2 MODE 3 L OCKS0 3 L OCKS0
4-2) Normal speed of DAC (MCLK=512fs) Master clock frequency example of X2 : X2 = 16.384MHz, 22.5792MHz, 24.576MHz
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL X1 X4 JP12 LRFS 12 H SW2 MODE
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ASAHI KASEI
[AKD4552-A]
(5) Evaluation of A/D using D/A converted data It is possible to make evaluation in the form of analog inputs and analog outputs by interfacing with various AKM's D/A evaluation boards with PORT3 (ROM). Nothing should be connected to PORT1 (DIR).
JP3 LRCK JP4 BCLK JP6 SDTI JP8 XTE JP13 EXT
ADC
DIR
ADC
DIR
ADC
DIR
* Clock example 5-1) Normal speed of ADC (MCLK=256fs) Do not use X2.
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL X1 X4 JP12 LRFS
5-2) Normal speed of ADC (MCLK=512fs) Do not use X2.
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL X1 X4 JP12 LRFS
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ASAHI KASEI
[AKD4552-A]
(6) All interface signals including master clock are fed externally. Under the following set-up, all external signals needed for the AK4552 to operate could be fed through PORT3 (ROM). In case of interfacing external sources to D/A converter, JP6 (SDTI) should be open. And in case of using A/D data to externally, JP6 (SDTI) is set ADC side. When JP6 (SDTI) is open, the A/D data can be output from the SDTO pin of PORT3 (ROM) at the same time if JP5 (SDTO) is short.
JP3 LRCK JP4 BCLK JP6 SDTI JP8 XTE JP13 EXT
ADC
DIR
ADC
DIR
ADC
DIR
* Clock example 6-1) Normal speed, Double speed, 4 times speed of ADC and DAC Do not use X2.
JP2 MCKO JP7 SPEED X4 M1 M2 X2 X1 X1 X2 X1 X4 JP9 MCLK JP10 BCFS JP11 CLK DIR EXT XTL DEM0 X1 X4 JP12 LRFS 12 H L DEM1 SW2 MODE 3 L OCKS0 4 L OCKS1 5 L CM0
DIP switch set up
Upper-side is "H" and lower-side is "L". [SW2] (MODE) : Sets the de-emphasis filter of AK4552 and clock mode of U4 (AK4112B). No. 1 2 3 4 5 Pin Name Mode DEM0 See Table 2. DEM1 OCKS0 See Table 3. OCKS1 CM0 L : X'tal mode, H : PLL mode Table 1. Set up SW2
DEM1 DEM0 Mode L L 44.1kHz default L H OFF H L 48kHz H H 32kHz Table 2. Set up of DEM0/1 of AK4552 No. 0 1 OCKS1 L H OCKS0 MCKO1 MCKO2 L 256fs 256fs L 512fs 128fs Table 3. Set up of OCKS0/1 for AK4112B fs (kHz) 32, 44.1, 48, 96 32, 44.1, 48
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ASAHI KASEI
[AKD4552-A]
Other jumper pins set up
[JP1] (GND): Analog ground and digital ground open: separated short: common (The connector "DGND" can be open.) [JP5] (SDTO): SDTO of AK4552 Always open. It is possible to short for evaluation mode 6.
The function of the toggle SW
Upper-side is "H" and lower-side is "L". [SW1] (PDN): Resets the AK4552. Keep "H" during normal operation. [SW3] (DIR): Resets the AK4112B. Keep "H" during normal operation. [SW4] (DIT): Resets the AK4103A. Keep "H" during normal operation.
Indication for LED
[LED1] (ERF): Monitor ERF pin of the AK4112B. LED turns on when some error has occurred to AK4112B.
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[AKD4552-A]
MEASUREMENT RESULTS
[Measurement condition] * Measurement unit * MCLK * BCLK * fs * Bit * Band width * Measurement Filter * Power Supply * Interface * Temperature
: Audio Precision, System two Cascade : 256fs : 64fs : 32kHz, 44.1kHz, 48kHz, 96kHz : 24bit : ADC : 10Hz 20kHz (Normal Speed), 10Hz 48kHz (Double Speed) : DAC : 10Hz 20kHz (Normal Speed), 10Hz 40kHz (Double Speed) : VA = VD = 3.0V : DIT/DIR : Room
Parameter ADC Analog Input Characteristics fs=32kHz S/(N+D) (-0.5dB Input) fs=44.1kHz fs=48kHz fs=96kHz fs=32kHz, A-weighted D-Range (-60dB Input) fs=44.1kHz, A-weighted fs=48kHz, A-weighted fs=96kHz S/N fs=32kHz, A-weighted fs=44.1kHz, A-weighted fs=48kHz, A-weighted fs=96kHz Interchannel Isolation DAC Analog Output Characteristics fs=32kHz S/(N+D) (0dB Output) fs=44.1kHz fs=48kHz fs=96kHz D-Range (-60dB Output) fs=32kHz, A-weighted fs=44.1kHz, A-weighted fs=48kHz, A-weighted fs=96kHz fs=32kHz, A-weighted S/N fs=44.1kHz, A-weighted fs=48kHz, A-weighted fs=96kHz Interchannel Isolation
Result (Lch / Rch) 87.8 / 87.9 88.5 / 88.5 89.2 / 89.2 89.5 / 89.4 96.1 / 96.1 97.1 / 97.1 97.5 / 97.5 93.3 / 93.3 96.1 / 96.1 97.1 / 97.1 97.6 / 97.6 93.3 / 93.3 118.5 / 118.7 88.3 / 89.2 88.1 / 88.8 88.3 / 89.2 85.6 / 86.3 100.0 / 100.0 100.4 / 100.4 100.6 / 100.6 95.6 / 95.6 100.9 / 100.9 101.6 / 101.6 101.6 / 101.6 96.0 / 96.0 116.2 / 116.4
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
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[AKD4552-A]
1. ADC (Normal Speed)
AKM AK4552 AD C THD+N vs. Input Level VA=VD =3.0V, fs=44.1kHz, fin=1kHz
-80
-82
-84
-86
-88 d B F S
-90
-92
-94
-96
-98
-100 -120
-110
-100
-90
-80
-70
-60 dB r
-50
-40
-30
-20
-10
Figure 1. THD+N vs. Input Level
AKM
AK4552 AD C THD+N vs. Input Frequency VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr
-80
-82
-84
-86
-88 d B F S
-90
-92
-94
-96
-98
-100 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 2. THD+N vs. Input Frequency
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ASAHI KASEI
[AKD4552-A]
AKM
AK4552 ADC Linearity VA=VD =3.0V, fs=44.1kHz, fin=1kHz
+0 -10 -20 -30 -40 -50
d B F S
-60 -70 -80 -90 -100 -110 -120 -120
-110
-100
-90
-80
-70
-60 dB r
-50
-40
-30
-20
-10
+0
Figure 3. Linearity
AKM
AK4552 ADC Frequency Response VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr
+0
-0.2
-0.4
-0.6
-0.8 d B F S
-1
-1.2
-1.4
-1.6
-1.8
-2 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 4. Frequency Response
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ASAHI KASEI
[AKD4552-A]
AKM
AK4552 AD C C rosstalk VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr
-80 -85 -90 -95 -100 -105
d B
-110 -115 -120 -125 -130 -135 -140 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 5. Crosstalk
AKM
AK4552 ADC FFT Plot VA=VD=3.0V, fs=44.1kHz, Input=-0.5dBr, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70
d B F S
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 6. FFT Plot
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ASAHI KASEI
[AKD4552-A]
AKM
AK4552 ADC FFT Plot VA=VD=3.0V, fs=44.1kHz, Input=-60dBr, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70
d B F S
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 7. FFT Plot
AKM
AK4552 ADC FFT Plot VA=VD=3.0V, fs=44.1kHz, fin=None
+0 -10 -20 -30 -40 -50 -60 -70
d B F S
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 8. FFT Plot
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ASAHI KASEI
[AKD4552-A]
2. DAC (Normal Speed)
AKM AK4552 D AC THD+N vs. Input Level VA=VD =3.0V, fs=44.1kHz, fin=1kHz
-60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -120
d B r A
-110
-100
-90
-80
-70
-60 dB FS
-50
-40
-30
-20
-10
+0
Figure 1. THD+N vs. Input Level
AKM
AK4552 D AC THD+N vs. Input Frequency VA=VD =3.0V, fs=44.1kHz, Input=0dBFS
-60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 20
d B r A
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 2. THD+N vs. Input Frequency
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ASAHI KASEI
[AKD4552-A]
AKM
AK4552 D AC Linearity VA=VD=3.0V, fs=44.1kHz, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -120
d B r A
-110
-100
-90
-80
-70
-60 dB FS
-50
-40
-30
-20
-10
+0
Figure 3. Linearity
AKM
AK4552 DAC Frequency Response VA=VD =3.0V, fs=44.1kHz, Input=0dBFS
+0.5
+0.4
+0.3
+0.2
+0.1 d B r A -0.1
+0
-0.2
-0.3
-0.4
-0.5 2k 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k
Figure 4. Frequency Response
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ASAHI KASEI
[AKD4552-A]
AKM
AK4552 D AC C rosstalk VA=VD =3.0V, fs=44.1kHz, Input=0dBFS
-80
-85
-90
-95
-100 d B
-105
-110
-115
-120
-125
-130 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 5. Crosstalk
AKM
AK4552 DAC FFT Plot VA=VD=3.0V, fs=44.1kHz, Input=0dBFS, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70
d B r A
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 6. FFT Plot
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ASAHI KASEI
[AKD4552-A]
AKM
AK4552 DAC FFT Plot VA=VD=3.0V, fs=44.1kHz, Input=-60dBFS, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70
d B r A
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 7. FFT Plot
AKM
AK4552 DAC FFT Plot VA=VD=3.0V, fs=44.1kHz, fin=None
+0 -10 -20 -30 -40 -50 -60 -70
d B r A
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k
Figure 8. FFT Plot
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ASAHI KASEI
[AKD4552-A]
3. ADC (Double Speed)
AKM AK4552 AD C THD+N vs. Input Level VA=VD=3.0V, fs=96kHz, fin=1kHz
-80
-82
-84
-86
-88 d B F S
-90
-92
-94
-96
-98
-100 -120
-110
-100
-90
-80
-70
-60 dB r
-50
-40
-30
-20
-10
Figure 1. THD+N vs. Input Level
AKM
AK4552 AD C THD+N vs. Input Frequency VA=VD =3.0V, fs=96kHz, Input=-0.5dBr
-80
-82
-84
-86
-88 d B F S
-90
-92
-94
-96
-98
-100 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
40k
Figure 2. THD+N vs. Input Frequency
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ASAHI KASEI
[AKD4552-A]
AKM
AK4552 ADC Linearity VA=VD=3.0V, fs=96kHz, fin=1kHz
+0 -10 -20 -30 -40 -50
d B F S
-60 -70 -80 -90 -100 -110 -120 -120
-110
-100
-90
-80
-70
-60 dB r
-50
-40
-30
-20
-10
+0
Figure 3. Linearity
AKM
AK4552 ADC Frequency Response VA=VD =3.0V, fs=96kHz, Input=-0.5dBr
+0
-0.2
-0.4
-0.6
-0.8 d B F S
-1
-1.2
-1.4
-1.6
-1.8
-2 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
40k
Figure 4. Frequency Response
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ASAHI KASEI
[AKD4552-A]
AKM
AK4552 AD C C rosstalk VA=VD =3.0V, fs=96kHz, Input=-0.5dBr
-90
-92.5 -95 -97.5 -100 -102.5 -105 -107.5 d B -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
40k
Figure 5. Crosstalk
AKM
AK4552 ADC FFT Plot VA=VD =3.0V, fs=96kHz, Input=-0.5dBr, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70
d B F S
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 40k
Figure 6. FFT Plot
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[AKD4552-A]
AKM
AK4552 ADC FFT Plot VA=VD=3.0V, fs=96kHz, Input=-60dBr, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70
d B F S
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 40k
Figure 7. FFT Plot
AKM
AK4552 ADC FFT Plot VA=VD=3.0V, fs=96kHz, fin=None
+0 -10 -20 -30 -40 -50 -60 -70
d B F S
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 40k
Figure 8. FFT Plot
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ASAHI KASEI
[AKD4552-A]
4. DAC (Double Speed)
AKM AK4552 D AC THD+N vs. Input Level VA=VD=3.0V, fs=96kHz, fin=1kHz
-60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 -120
d B r A
-110
-100
-90
-80
-70
-60 dB FS
-50
-40
-30
-20
-10
+0
Figure 1. THD+N vs. Input Level
AKM
AK4552 D AC THD+N vs. Input Frequency VA=VD=3.0V, fs=96kHz, Input=0dBFS
-60 -65 -70 -75 -80 -85 -90 -95 -100 -105 -110 -115 -120 20
d B r A
50
100
200
500 Hz
1k
2k
5k
10k
20k
40k
Figure 2. THD+N vs. Input Frequency
- 23 -
2005/10
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 DAC Linearity VA=VD=3.0V, fs=96kHz, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -120
d B r A
-110
-100
-90
-80
-70
-60 dB FS
-50
-40
-30
-20
-10
+0
Figure 3. Linearity
AKM
AK4552 DAC Frequency Response VA=VD=3.0V, fs=96kHz, Input=0dBFS
+0.5
+0.4
+0.3
+0.2
+0.1 d B r A -0.1
+0
-0.2
-0.3
-0.4
-0.5 2.5k 5k 7.5k 10k 12.5k 15k 17.5k 20k Hz 22.5k 25k 27.5k 30k 32.5k 35k 37.5k 40k
Figure 4. Frequency Response
- 24 -
2005/10
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 D AC C rosstalk VA=VD=3.0V, fs=96kHz, Input=0dBFS
-80
-85
-90
-95
-100 d B
-105
-110
-115
-120
-125
-130 20
50
100
200
500 Hz
1k
2k
5k
10k
20k
40k
Figure 5. Crosstalk
AKM
AK4552 DAC FFT Plot VA=VD =3.0V, fs=96kHz, Input=0dBFS, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70
d B r A
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 40k
Figure 6. FFT Plot
- 25 -
2005/10
ASAHI KASEI
[AKD4552-A]
AKM
AK4552 DAC FFT Plot VA=VD =3.0V, fs=96kHz, Input=-60dBFS, fin=1kHz
+0 -10 -20 -30 -40 -50 -60 -70
d B r A
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 40k
Figure 7. FFT Plot
AKM
AK4552 DAC FFT Plot VA=VD=3.0V, fs=96kHz, fin=None
+0 -10 -20 -30 -40 -50 -60 -70
d B r A
-80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 40k
Figure 8. FFT Plot
- 26 -
2005/10
ASAHI KASEI
[AKD4552-A]
Revision History Date 05/10/18 Manual Revision KM080600 Board Revision 0 Reason First Edition Contents
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
- 27 -
2005/10
A
B
C
D
E
E
+
R1 220
J1 ROUT
E
C1 22u
R2 10k
J2 RIN
C2 10u + +
DGND
JP1 GND
AGND + R3 220 J3 LOUT
D
D
R4 560
C3 22u
R5 10k
J4 LIN
C4 10u + +
CN1
U1
CN2
U2
R6 560
1
1
RIN
ROUT
16
16
11
Y8
A8
9
PDN
2
C
2
LIN
LOUT
15
15
12
Y7
A7
8
BCLK
C
VA L1
1 2
3
3
4
C9 47u
5
R7 10 DM0
6 6 DEM0 MCLK 11
DM1
7
R11 51 SDTO
B
8
VCC
2
1
D1 1S1588
R13 10k U3A
1 2 3
U3B
4
PDN
L
3
A
H
1
74HC14
74HC14
A
SW1 PDN
2
C14 0.1u
Title Size Document Number
A
B
C
D
+
+
+
(short)
C10 10u
+
C7 10u
C8 0.1u
4
VSS
VCOM
14
VA
PDN
13
C11 0.1u
5 VD BCLK 12
R8
R9
R10 51
7 DEM1 LRCK 10 10
R12 51
8 SDTO SDTI 9 9 18 Y1 A1 2
B
AK4552
+
C5 0.1u
C6 1u
14 13 Y6 A6 7
MCLK
13
14
Y5
A5
6
LRCK
51
12 15 Y4 A4 5
SDTI
51
11
DM1
16
Y3
A3
4
DEM1
DM0
17
Y2
A2
3
DEM0
10
C12 47u
1 2
C13 0.1u
20
GND
G2
19
VCC
G1
1
L2 10u D2V 74LVC541
AKD4552-A
AK4552
1
of Rev
A3
Date:
0 3
Monday , September 26 , 2005 Sheet
E
A
B
C
D
E
E
E
VCC
SW2
1 2 3 4 5 10 9 8 7 6
for 74HCU04, 74HC14, 74HC4040, 74HCT04, 74AC74
1
L3 10u C19 0.1u C20 0.1u
VCC
2 2
T1
GND VIN
TO92
VOUT 3
D3V C22 0.1u
MODE RP1
5 4 3 2 1
D
DEM0 DEM1 OCKS0 OCKS1 CM0
DEM0 DEM1 OCKS0 OCKS1 CM0 U4
1
C16 0.1u
C17 0.1u
C18 0.1u
+ C15 47u
C21 0.1u
D
47k D3V
1
C23 10u
DVDD
CM0/CDTO
28
CM0
+
C24 0.1u
2 DVSS CM1/CDTI 27
VCC
4
C27 5p
5
C
2
1
D2 1S1588
R14 10k U3C
5 6 9
U3D
8
C28 5p
7 PDN DAUX 22
L
3 1
H SW3 DIR
2
74HC14
74HC14
C29 0.1u D3V C30 10u
+
VCC
1
B
R16
11 RX1 ERF 18 5
L4 47u
6 5 6 5 GND VCC GND OUT 4 3 2 1 2
470
12 RX2/DIF0 FS96 17
PORT1
DIR
C32 0.1u
+ C33 10u
A
A
B
+ 18k
VCC
C25 10u
C26 0.1u
3 TVDD OCKS1/CCLK 26
OCKS1
V/TX
OCKS0/CSN
25
OCKS0 JP2 MCKO DIR_MCLK
C
XTI
MCKO1
24
X1 22.5792MHz
6 XTO MCKO2 23
M1 M2
DAUX
4
U5B
3 2
U5A
1
SDTO
R15
8 R BICK 21
74HCT04 DIR_BCLK
74HCT04
9
AVDD
SDTO
20
DIR_SDTI
C31 0.1u
10 AVSS LRCK 19
DIR_LRCK U5C
6
R17
2
LED1
1
VCC
B
74HCT04
1k
ERF
13
RX3/DIF1
P/S
16
14
RX4/DIF2
AUTO
15
AK4112B
A
Title Size Document Number
AKD4552-A
DIR
Sheet
E
Rev
A3
Date:
C D
0 2
of
Monday, September 26, 2005
3
A
B
C
D
E
VCC
2
E
1
D3 1S1588
R18 10k U3F
13 12 11
U6
E
U3E
10
1
V1
U1
24
L
3 1
H SW4 DIT
2
74HC14
74HC14
2 TRANS DIF2 23
C34 0.1u
VCC
3 RESETN DIF1 22
128FS
4
MCLK
DIF0
21
PORT2
5 SDTI TXP 20 4 3 2 1 IN VCC IF GND 5 6 5 6
D
D
X_LRCK DIR_LRCK
ADC DIR
JP3 LRCK
LRCK
6
BICK
TXN
19
C35 0.1u
7 LRCK DVSS 18
R19 1k
DIT
X_BCLK DIR_BCLK
ADC DIR
JP4 BCLK BCLK
8
FS0/CSN
DVDD
17
9
FS1/CDTI
CKS1
16
MCLK SDTI
C
MCLK BCLK LRCK SDTI ROM
PORT3
1 2 3 4 5 10 9 8 7 6
10
FS2/CCLK
CKS0
15
SDTO
JP5 SDTO
11
FS3/CDTO
BLS
14
ROM
12
R20 10k
VCC JP6 SDTI ADC DIR DIR_SDTI
C1
ANS
13
AK4103A DAUX
X2 11.2896MHz x1 x2 x4 VCC U7B
2 3 4
B
R21 1M U7A
1
JP8 XTE
74HCU04 C38 5p C39 5p
74HCU04 XTL EXT DIR
4
U9A 74AC74
Q 5
x1 x2
JP9 MCLK
10
U8
CLK RST 11 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1
JP11 CLK
D CLK
PR
2 3
CL
DIR_MCLK
Q
6
1
J5 EXT
5
A
U7C 74HCU04
6
74HC4040
JP13 EXT
Title Size Document Number
A
B
C
D
+
C36 0.1u
C37 10u
VCC
C
128FS
JP7 SPEED MCLK
B
x4 x1
JP10 BCFS X_BCLK
x4 x1 JP12 LRFS
A
X_LRCK
AKD4552-A
DIT
Sheet
E
Rev
A3
Date:
0 3
of
Monday, September 26, 2005
3

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