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CY26580
PacketClockTM Network Applications Clock
Features
* Integrated phase-locked loop (PLL) * Low-jitter, high-accuracy outputs * 3.3V operation
Benefits
* Internal PLL with precision operation * Meets critical timing requirements in complex system designs * Enables application compatibility
Frequency Table
Part Number CY26580-1 Outputs 2 Input Frequency 125MHz or 25-MHz driven Output Frequencies 100 MHz, 133.33 MHz
Logic Block Diagram
CLK OSC. Q VCO P OUTPUT MULTIPLEXER AND DIVIDERS 133.33 MHz 100 MHz
PLL
SEL_25 SEL_CLK
VDD
VDD
GND
GND
Pin Configuration
CY26580 20-pin SSOP (QSOP)
NC NC CLK VDD NC GND NC NC NC 133 MHz 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 NC SEL_CLK NC 100 MHz VDD NC GND NC NC SEL_25
Input Select Options
SEL_25 X 0 1 SEL_CLK 0 1 1 Driven Driven 125 25 Input Type Input Frequency CLK1 Do not use 133.33 133.33 100 100 MHz MHz CLK2 Unit
Cypress Semiconductor Corporation Document #: 38-07536 Rev. *B
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised June 03, 2004
CY26580
Pin Description
Pin Name NC NC CLK VDD NC GND NC NC NC 133 MHz SEL_25 NC NC GND NC VDD 100 MHz NC SEL_CLK NC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 No Connect No Connect Reference Input Voltage Supply No Connect Ground No Connect No Connect No Connect 133.33-MHz Clock Output Reference Frequency Select Input; 0 = 125 MHz, 1 = 25 MHz, weak internal pull-up No Connect No Connect Ground No Connect Voltage Supply 100-MHz Clock Output No Connect Reference Select Input; Set to 1 = Driven, weak internal pull-up No Connect Pin Description
Document #: 38-07536 Rev. *B
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CY26580
Absolute Maximum Conditions[1]
Supply Voltage (VDD) ........................................-0.5 to +7.0V DC Input Voltage........................................ -0.5V to VDD+0.5 Storage Temperature (Non-condensing)..... -55C to +125C Junction Temperature ................................ -40C to +125C Data Retention @ Tj = 125C................................> 10 years Package Power Dissipation...................................... 350 mW ESD (Human Body Model) MIL-STD-883.................... 2000V
Recommended Operating Conditions
Parameter VDD TA, I-grade CLOAD fREF Parameter[2] IOH IOL IIH IIL VIH VIL IDD RUP Parameter[2] Ferror DC ER EF t9 t10 Description Supply Voltage Ambient Temperature, Industrial Max. Load Capacitance Reference Frequency Min. 3.14 -40 - - Typ. 3.3 - - 125, 25 Max. 3.47 85 15 - Unit V C pF MHz
DC Electrical Specifications
Description Output High Current Output Low Current Input High Current Input Low Current Input High Voltage Input Low Voltage Supply Current Pull-up resistor on Inputs Conditions VOH = VDD - 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V VIH = VDD VIL = 0V CMOS levels, 70% of VDD CMOS levels, 30% of VDD VDD Current, no load VDD = 3.14 to 3.47V, measured VIN = 0V Conditions All clocks Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Edge Rate, Measured from 20% to 80% of VDD, CLOAD = 15 pF. See Figure 2. Output Clock Edge Rate, Measured from 80% to 20% of VDD, CLOAD = 15 pF. See Figure 2. CLK1, CLK2 Peak-Peak period jitter 45 0.8 0.8 - - 50 1.4 1.4 100 - Min. 12 12 - - 0.7 - - - Typ. 24 24 5 - - - 35 100 Max. - - 10 50 - 0.3 50 150 Unit mA mA A A VDD VDD mA k
AC Electrical Specifications
Description Frequency Error Output Duty Cycle Rising Edge Rate Falling Edge Rate Clock Jitter PLL Lock Time Min. Typ. Max. 0 55 2 2 - 3 Unit ppm % V/ns V/ns ps ms
Test and Measurement Set-up VDDs 0.1 F DUT Outputs CLOAD
GND
Notes: 1. Above which the useful life may be impaired. For user guidelines, not tested. 2. Guaranteed by characterization, not 100% tested.
Document #: 38-07536 Rev. *B
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CY26580
Voltage and Timing Definitions
t1 t2 VDD 50% of VDD Clock Output 0V
Figure 1. Duty Cycle Definition
t3 t4 V
DD
80% of V DD Clock Output 20% of VDD 0V
Figure 2. ER = (0.6 x VDD) /t3, EF = (0.6 x VDD) /t4
Ordering Information
Ordering Code CY26580OI-1 CY26580OI-1T Package Type 20-pin SSOP (QSOP) 20-pin SSOP (QSOP) - Tape and Reel Operating Range Industrial Industrial Operating Voltage 3.3V 3.3V
Package Drawing and Dimensions
20-lead QSOP O201
51-85054-*B
PacketClock is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07536 Rev. *B Page 4 of 5
(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress.
CY26580
Document History Page
Document Title: CY26580 PacketClockTM Network Applications Clock Document #: 38-07536 Rev. *B REV. ** *A *B ECN NO. 127357 128564 216828 Issue Date 06/17/03 09/12/03 See ECN Orig. of Change RGL IJA RGL New Data Sheet Change pin 1 to NC and pin 3 to CLK Removed Preliminary Description of Change
Document #: 38-07536 Rev. *B
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