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C9530
PCIX I/O System Clock Generator with EMI Control Features
Features
* Dedicated clock buffer power pins for reduced noise, crosstalk and jitter * Input clock frequency of 25 MHz to 33.3 MHz * Output frequencies of XINx1, XINx2, XINx3 and XINx4 * Output grouped in two banks of five clocks each * One REF XIN clock output * SMBus clock control interface for individual clock disabling and SSCG control and individual back frequency selection * Output clock duty cycle is 50% ( 5%) * < 250 ps skew between output clocks within a bank * Output jitter < 250 psec (175 psec with all outputs at the same frequency) * Spread Spectrum feature for reduced electromagnetic interference (EMI) * OE pins for entire output bank enable control and testability * 48-pin SSOP and TSSOP packages Table 1. Test Mode Logic Table[1] Input Pins OEA OEB HIGH HIGH HIGH HIGH LOW SA1 SB1 LOW LOW HIGH HIGH X SA0 SB0 LOW HIGH LOW HIGH X Output Pins CLKA CLKB XIN 2 * XIN 3 * XIN 4 * XIN Three-state REF XIN XIN XIN XIN Three-state
Block Diagram
Pin Configuration
REF VDD XIN XOUT VSS SA0 SA1 VSS CLKA0 CLKA1 VDDA CLKA2 VSS VDDA CLKA3 CLKA4 VSS AGOOD# VSS IA0 IA1 IA2 AVDD OEA 1 2 3 4 5 6 7 8 9 10 48 47 46 45 44 43 42 41 40 39 SDATA SCLK VDD VSS VDD SB0 SB1 VSS CLKB0 CLKB1 VDDB CLKB2 VSS VDDB CLKB3 CLKB4 VSS BGOOD# AVDD AVDD VSS SSCG# VSS OEB
AGOOD# SSCG#
SSCG Logic /N
1 0
CLKA0 CLKA1 CLKA2 CLKA3 CLKA4 OEA CLKB0 CLKB1 CLKB2 CLKB3 CLKB4 OEB BGOOD# REF
XIN XOUT
0
C9530
11 12 13 14 15 16 17 18 19 20 21 22 23 24
38 37 36 35 34 33 32 31 30 29 28 27 26 25
SDATA SCLK IA(0:2) SA(0,1) SB(0,1)
/N I2C Control Logic
1
Note: 1. A and B banks have separate frequency select and output enable controls. XIN is the frequency of the clock on the device's XIN pin. OEA and OEB will three-state REF.
Cypress Semiconductor Corporation Document #: 38-07033 Rev. *C
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised October 31, 2005
C9530
Pin Description[3]
Pin[2] 3 4 1 24* 25* 18 31 6*, 7* Name XIN XOUT REF OEA OEB AGOOD# BGOOD# SA(0,1) PWR[4] VDDA VDDA VDD VDD VDD VDD VDD VDD I/O I O O I I O O I Description Crystal Buffer input pin. Connects to a crystal, or an external clock source. Serves as input clock TCLK, in Test mode. Crystal Buffer output pin. Connects to a crystal only. When a Can Oscillator is used or in Test mode, this pin is kept unconnected. Buffered inverted outputs of the signal applied at Xin, typically 33.33 or 25.0 MHz Output Enable for clock bank A. Causes the CLKA output clocks to be in a three-state condition when driven to a logic low level. Output Enable for clock bank B. Causes the CLKB output clocks to be in a three-state condition when driven to a logic low level. When this output signal is a logic low level, it indicates that the output clocks of the A bank are locked to the input reference clock. This output is latched. When this output signal is at a logic low level, it indicates that the output clocks of the B bank are locked to the input reference clock. This output is latched. Clock Bank A selection bits. These control the clock frequency that will be present on the outputs of the A bank of buffers. See Table 1 for frequency codes and selection values. Clock Bank B selection bits. These control the clock frequency that will be present on the outputs of the B bank of buffers. See Table 1 for frequency codes and selection values. SMBus address selection input pins. See Table 3 SMBus Address table. Enables Spread Spectrum clock modulation when at a logic low level, see Spread Spectrum Clocking on page 6. Data for the internal SMBus circuitry. Clock for the internal SMBus circuitry.
43*, 42*
SB(0,1)
VDD
I
20*, 21*, 22* 27* 48 47 11, 14 38, 35 2, 44, 46 23, 29, 30 9, 10, 12, 15, 16
IA(0:2) SSCG# SDATA SCLK VDDA VDDB VDD AVDD
VDD VDD VDD VDD - - - -
I I I/O I
PWR 3.3V common power supply pin for Bank A PCI clocks CLKA. PWR 3.3V common power supply pin for Bank B PCI clocks CLKB. PWR Power supply for internal Core logic. PWR Power for internal analog circuitry. This supply should have a separately decoupled current source from VDD. O O A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks. A bank of five XINx1, XINx2, XINx3 and XINx4 output clocks.
CLKA (0:4) VDDA
40, 39, 37, 34, CLKB (0:4) VDDB 33 5, 8, 13, 17, 19, 26, 28, 32, 36, 41, 45 VSS -
PWR Ground pins for the device.
Notes: 2. Pin numbers ending with * indicate that they contain device internal pull-up resistors that will insure that they are sensed as a logic 1 if no external circuitry is connected to them. 3. A bypass capacitor (0.1 F) should be placed as close as possible to each VDD pin. If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the trace. 4. PWR = Power connection, I = Input, O = Output and I/O = both input and output functionality of the pin(s).
Document #: 38-07033 Rev. *C
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C9530
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. Table 2. Block Read and Block Write Protocol Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits `00000000' stands for block operation Acknowledge from slave Byte Count - 8 bits Acknowledge from slave Data byte 1 - 8 bits Acknowledge from slave Data byte 2 - 8 bits Acknowledge from slave ...................... Data Byte (N-1) - 8 bits Acknowledge from slave Data Byte N - 8 bits Acknowledge from slave Stop Description
Data Protocol
The clock driver serial protocol accepts block write a operations from the controller. The bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. The C9530 does not support the Block Read function. The block write protocol is outlined in Table 2. The addresses are listed in Table 3.
Table 3. SMBus Address Selection Table SMBus Address of the Device DE DC DA D8 D6 D4 D0 D2 IA0 Bit (Pin 10) 0 1 0 1 0 1 0 1 IA1 Bit (Pin 11) 0 0 1 1 0 0 1 1 IA2 Bit (Pin 12) 0 0 0 0 1 1 1 1
Serial Control Registers
Byte 0: Function Select Register Bit 7 6 5 4 3 2 @Pup 1 0 1 0 0 0 Name TESTEN SSEN SSSEL S1 S0 Test Mode Enable. 1 = Normal operation, 0 = Test mode Spread Spectrum modulation control bit (effective only when Bit 0 of this register is set to a 0) 0 = OFF, 1= ON SSCG Spread width select. 1 = 0.5%, 0 = 1.0% See Table 4 below for clarification SB1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set to a 0) SB0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set to a 0) SA1 Bank MSB frequency control bit (effective only when Bit 0 of this register is set to a 0) Description
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C9530
Byte 0: Function Select Register (continued) Bit 1 0 @Pup 0 1 HWSEL Name Description SA0 Bank LSB frequency control bit (effective only when Bit 0 of this register is set to a 0) Hardware/SMBus frequency control. 1 = Hardware (pins 6, 7, 42, 43 and 27), 0 = SMBus Byte 0 bits 1-4, & 6
Table 4. Clarification Table for Byte0, bit 5 Byte0, bit6 0 0 1 1 Table 5. Test Table Outputs Test Function Clock Frequency CLKA XIN/6 CLKB XIN/4 REF XIN Byte0, bit5 0 1 0 1 Frequency generated from XIN Spread @ -1.0% Spread @ -0.5% Description Frequency generated from second PLL
Byte 1: A Bank and REF Clock Control Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 REFEN Name Reserved Reserved REF Output Enable 0 = Disable, 1= Enable CLKA4 Output Enable 0 = Disable, 1= Enable CLKA3 Output Enable 0 = Disable, 1= Enable CLKA2 Output Enable 0 = Disable, 1= Enable CLKA1 Output Enable 0 = Disable, 1= Enable CLKA0 Output Enable 0 = Disable, 1= Enable Description
Byte 2: PCI Register Bit 7 6 5 4 3 2 1 0 @Pup 1 1 1 1 1 1 1 1 18 19 22 23 24 Name Reserved Reserved Reserved CLKB4 Output Enable 0 = Disable, 1= Enable CLKB3 Output Enable 0 = Disable, 1= Enable CLKB2 Output Enable 0 = Disable, 1= Enable CLKB1 Output Enable 0 = Disable, 1= Enable CLKB0 Output Enable 0 = Disable, 1= Enable Description
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C9530
Table 6. Suggested Oscillator Crystal Parameters Parameter Fo TC TS TA Operating Mode CXTAL RESR Load Capacitance Effective Series Resistance (ESR) Frequency Tolerance See Note 5 Stability (TA -10 to +60C) Note 5 Aging (first year @ 25C) Note 5 Parallel Resonant, Note 5 The crystal's rated load. Note 5 Note 6 Description Conditions Min 33.0 - - - - - - Typ. 33.33 - - - - 20 40 Max. 33.5 100 100 5 - - - pF Ohms Unit MHz PPM PPM PPM
Internal Crystal Oscillator
This device will operate in two input reference clock configurations. In its simplest mode a 33.33-MHz fundamental cut parallel resonant crystal is attached to the XIN and XOUT pins. In the second mode a 33.33-MHz input reference clock is driven in on the IN clock from an external source. In this application the XOUT pin must be left disconnected.
Output Clock Frequency Control
All of the output clocks have their frequency selected by the logic state of the S0 and S1 control bits. The source of these control signals is determined by the SMBus register Byte 0 bit 0. At initial power-up this bit is set of a logic 1 state and thus the frequency selections are controlled by the logic levels present on the device's S(0,1) pins. If the application does not use an SMBus interface then hardware frequency selection S(0,1) must be used. If it is desired to control the output clocks using an SMBus interface, then this bit (B0b0) must first be set to a low state. After this is done the device will use the contents of the internal SMBus register Bytes 0 Bits 3 and 4 to control the output clock's frequency. The following formula and schematic may be used to understand and calculate either the loading specification of a crystal for a design or the additional discrete load capacitance that must be used to provide the correct load to a known load rated crystal
Output Clock Three-state Control
All of the clocks in Bank A (CLKA) and Bank B (CLKB) may be placed in a three-state condition by bringing their relevant OE pins (OEA and OEB) to a logic LOW state. This transition to and from a state and active condition is a totally asynchronous event and clock glitching may occur during the transitioning states. This function is intended as a board level testing feature. When the output clocks are being enabled and disabled in active environments the SMBus control register bits are the preferred mechanism to control these signals in an orderly and predictable manner.
CL =
where: CXTAL CXINFTG CXOUTFTG CXINPCB CXINDISC
(CXINPCB + CXINFTG + CXINDISC) x (CXOUTPCB) + CXOUTFTG) + CXOUTDISC) (CXINPCB + CXINFTG + CXINDISC) + (CXOUTPCB) + CXOUTFTG) + CXOUTDISC)
= The load rating of the crystal. = The clock generators XIN pin effective device internal capacitance to ground. = The clock generators XOUT pin effective device internal capacitance to ground. = The effective capacitance to ground of the crystal to device PCB trace. = Any discrete capacitance that is placed between the XIn pin and ground.
CXOUTPCB = The effective capacitance to ground of the crystal to device PCB trace. CXOUTDISC = Any discrete capacitance that is placed between the XIn pin and ground.
Notes: 5. For best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these specifications. 6. Larger values may cause this device to exhibit oscillator startup problems.
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C9530
Spread Spectrum Clocking
CXINPCB CXOUTPCB CXINDISC CXOUTDISC XOUT XIN CXINFTG CXOUTFTG
Down Spread Description Spread Spectrum is a modulation technique for distributing clock period over a certain bandwidth (called Spread Bandwidth). This technique allows the distribution of the undesirable electromagnetic energy (EMI) over a wide range of frequencies therefore reducing the average radiated energy present at any frequency over a given time period. As the spread is specified as a percentage of the resting (non-spread) frequency value, it is effective at the fundamental and, to a greater extent, at all it's harmonics. In this device, Spread Spectrum is enabled externally through pin 27 (SSCG#) or internally via SMBus Byte 0 Bit 0 and 6. Spread spectrum is enabled externally when the SSCG# pin is low. This pin has an internal device pull up resistor, which causes its state to default to a high (Spread Spectrum disabled) unless externally forced to a low. It may also be enabled by programming SMBus Byte 0 Bit 0 LOW (to enable SMBus control of the function) and then programming SMBus Byte 0 Bit 6 LOW to set the feature active.
Clock Generator
As an example and using this formula for this data sheet's device, a design that has no discrete loading capacitors (CDISC) and each of the crystal device PCB traces has a capacitance (CPCB) to ground of 4 pF (typical value) would calculate as follows. Therefore, to obtain output frequencies that are as close to this data sheets specified values as possible, in this design example, you should specify a parallel cut crystal that is designed to work into a load of 20 pF.
CL = = (4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF) (4 pF + 36 pF + 0 pF) x (4 pF + 36 pF + 0 pF) 40 x 40 40 x 40 1600 80 20 pF
= =
S p re a d o ff
S p re a d o n
C e n te r F re q u e n c y , S p re a d o n
C e n te r F re q u e n c y , S p re a d o ff
Figure 1. Spread Spectrum Table 7. Spectrum Spreading Selection Output Clock Frequency 33.3 MHz (XIN) 66.6 MHz (XIN*2) 100.0 MHz (XIN*3) 133.3 MHz (XIN*4) Table[7] % of Frequency Spreading SMBus Byte 0 Bit 5 = 0 1.0% (-1.0% + 0%) 1.0% (-1.0% + 0%) 1.0% (-1.0% + 0%) 1.0% (-1.0% + 0%) SMBus Byte 0 Bit 5 = 1 0.5% (-0.5% + 0%) 0.5% (-0.5% + 0%) 0.5% (-0.5% + 0%) 0.5% (-0.5% + 0%) Mode Down Spread Down Spread Down Spread Down Spread
Note: 7. When SSCG is enabled, the device will down spread the clock over a range that is 1% of its resting frequency. This means that for a 100-MHz output clock frequency will sweep through a spectral range from 99 to 100 MHz.
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C9530
Absolute Maximum Conditions
Parameter VDD,VDDP VDDA VIN TS TA TJ ESDHBM OJC OJA UL-94 MSL Description Core Supply Voltage Analog Supply Voltage Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Relative to V SS Non Functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) At 1/8 in. Condition Min. -0.5 -0.5 -0.5 -65 0 - 2000 15 45 V-0 1 Max. 4.6 4.6 VDD + 0.5 +150 70 150 - Unit V V VDC C C C V C/W C/W
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
DC Electrical Specifications
Parameter VDD, VDDA, VDDB VILI2C VIHI2C VIL VIH IIL VOL VOH IOZ CIN COUT LIN CXTAL VXIH VXIL IDD IPD Description 3.3 Operating Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Leakage Current Output Low Voltage Output High Voltage High-Impedance Output Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Crystal Pin Capacitance Xin High Voltage Xin Low Voltage Dynamic Supply Current Power-down Supply Current At 133 MHz and all outputs loaded per Table 8 PD# Asserted From XIN and XOUT pins to ground except pull-ups or pull-downs 0 < VIN < VDD IOL = 1 mA IOH = -1 mA 3.3V 5% SDATA, SCLK SDATA, SCLK S(A,B)O, S(A,B)1, OE(A,B) Condition Min. 3.135 - 2.2 VSS - 0.5 2.0 -5 - 2.4 -10 2 3 - 32 0.7VDD 0 - - Max. 3.465 1.0 - 0.8 VDD + 0. 5 5 0.4 - 10 5 6 7 38 VDD 0.3VDD 300 1 Unit V V - V V A V V A pF pF nH pF V V mA mA
AC Electrical Specifications
Parameter Crystal TDC Description XIN Duty Cycle Condition The device will operate reliably with input duty cycles up to 30/70%. When Xin is driven from an external clock source Min. 45 Max. 55 Unit %
XINFREQ
XIN Frequency
25
33.3
MHz
Document #: 38-07033 Rev. *C
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C9530
AC Electrical Specifications (continued)
Parameter TR / TF TCCJ LACC CLK TDC TPERIOD33 TPERIOD66 TPERIOD100 TPERIOD133 TR / TF TSKEW TCCJ REF TDC TR / TF TCCJ Description XIN Rise and Fall Times XIN Cycle to Cycle Jitter Long-term Accuracy CLK Duty Cycle 33MHz CLK Period 66MHz CLK Period 100MHz CLK Period 133MHz CLK Period CLK Rise and Fall Times Any CLK to Any CLK Clock Skew CLK Cycle to Cycle Jitter REF Duty Cycle REF Rise and Fall Times REF Cycle to Cycle Jitter Condition Measured between 0.3VDD and 0.7VDD As an average over 1s duration Over 150 ms Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V Measurement at 1.5V Measurement at 1.5V Measured between 0.4V and 2.4V Measurement at 1.5V 45 29.5 14.5 9.5 7.0 0.5 - - 45 1.0 - - - - Min. - - Max. 10.0 500 300 55 30.5 15.5 10.5 8.0 2.0 250 175 55 4.0 750 10.0 10.0 3.0 Unit ns ps ppm % ns ns ns ns ns ps ps % ns ps ns ns ms
ENABLE/DISABLE and SET-UP tpZL,tpZH Output Enable Delay (all outputs) tpLZ,tpZH TSTABLE Output Disable Delay (all outputs) Clock Stabilization from Power-up
Test and Measurement Set-up
3 . 3 V S ig n a ls
tD C
-
Output under Test Probe
2 .4 V
3 .3 V
Load Cap
1 .5 V
0 .4 V 0V
Tr
Tf
Lumped Load Figure 2. Test and Measurement Set-up Table 8. Loading Output Name CLK5 REF Max Load (in pF) 30 20
LVTTL Signaling
Document #: 38-07033 Rev. *C
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C9530
Ordering Information
Part Number IMIC9530CY IMIC9530CYT IMIC9530CT IMIC9530CTT Lead-free CYI9530ZXC CYI9530ZXCT Package Type 48-Pin SSOP 48-Pin SSOP - Tape and Reel 48-Pin TSSOP 48-Pin TSSOP - Tape and Reel 48-Pin TSSOP 48-Pin TSSOP - Tape and Reel Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C Commercial, 0 to 70C
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C9530
Package Diagrams
48-lead Shrunk Small Outline Package O48
51-85061-*C
48-lead (240-mil) TSSOP II Z4824
0.500[0.019]
24 1
DIMENSIONS IN MM[INCHES] MIN. MAX.
7.950[0.313] 8.255[0.325] 5.994[0.236] 6.198[0.244]
REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.33gms PART # Z4824 STANDARD PKG. ZZ4824 LEAD FREE PKG.
25
48
12.395[0.488] 12.598[0.496]
1.100[0.043] MAX.
GAUGE PLANE
0.25[0.010]
0.20[0.008]
0.851[0.033] 0.950[0.037] 0.500[0.020] BSC 0.170[0.006] 0.279[0.011] 0.051[0.002] 0.152[0.006] SEATING PLANE 0-8
0.508[0.020] 0.762[0.030] 0.100[0.003] 0.200[0.008]
51-85059-*C
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07033 Rev. *C
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
C9530
Document History Page
Document Title: C9530 PCIX I/O System Clock Generator with EMI Control Features Document #: 38-07033 REV. ** *A *B ECN NO. 106961 122726 126595 Issue Date 06/12/02 12/17/02 05/14/03 Orig. of Change IKA RBI RGL Description of Change Convert from IMI to Cypress Added power-up requirements to maximum ratings information Converted from Word to FrameMaker Fixed AC and DC tables to match char data Added 25-MHz Operation. Added Pb-free devices for TSSOP
*C
404563
See ECN
RGL
Document #: 38-07033 Rev. *C
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