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ISL54004
Data Sheet October 30, 2007 FN6513.2
Integrated Audio Amplifier Systems
The Intersil ISL54004 device is an integrated audio power amplifier system that combines a mono BTL amplifier and stereo headphone amplifiers in a single device. It can operate from a single +2.7V to +5V power supply and is offered in a 20 Ld 4x4 TQFN package. Targeted applications include handheld equipment such as cell-phones, MP3 players, and games/toys. The ISL54004 part contains one class AB BTL type power amplifier for driving an 8 mono speaker and two class AB headphone amplifiers for driving 16 or 32 headphone speakers. The BTL when using a 5V supply is capable of delivering 800mW (typ) with 0.4% THD+N and 941mW (typ) with 1% THD+N of continuous average power into an 8 BTL speaker load. Each headphone amplifier when using a 5V supply is capable of delivering 50mW (typ) with 0.3% THD+N and 94mW (typ) with 1% THD+N of continuous average power into a 32 headphone speaker. When in Mono mode the part automatically mixes the left and right audio inputs and sends the combined signal to the BTL driver. In Headphone Mode, the active right channel input is sent to the right headphone speaker and the active left channel is sent to the left headphone speaker. The ISL54004 has a four-level programmable gain stage to boost the audio signal. The part requires no external gain setting resistors. The ISL54004 part features headphone sense input circuitry that detects when a headphone jack has been inserted and automatically switches the audio inputs from the mono BTL output driver to the headphone drivers. The part also has a logic control pin that can override the headphone sense input circuitry. The part also features low power shutdown, thermal overload protection and click and pop suppression. The click and pop circuitry prevents click and pops at the speakers when transitioning in and out of shutdown.
Features
* Class AB 94mW Headphone Amplifiers and 941mW Mono BTL Speaker Amplifier * THD+N at 1kHz, 800mW into 8 BTL . . . . . . . . . . . . . .0.4% * THD+N at 1kHz, 15mW into 32 Headphone . . . . . . .0.07% * THD+N at 1kHz, 50mW into 32 Headphone . . . . . . . .0.3% * Single Supply Operation . . . . . . . . . . . . . . . . .+2.7V to +5.5V * Headphone Sense Input and Low Power Shutdown * Thermal Shutdown Protection * "Click and Pop" Suppression Circuitry * Selectable Gain Settings * TTL Logic-Compatible * Available in 20 Ld 4x4 TQFN * Pb-Free (RoHS Compliant)
Applications
* Battery-powered, Handheld, and Portable Equipment - Cellular/mobile Phones - PDA's, MP3 Players, DVD Players, Cameras - Laptops, Notebooks, Palmtops - Handheld Games and Toys * Desktop Computers
Simplified Block Diagram
VDD
R L GAIN ROUTER/ SWITCHER
CLICK AND POP SD GS0 GS1 HO
BIAS
LOGIC CONTROL
THERMAL SHUTDOWN
ISL54004
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54004 Pinout
ISL54004 (20 LD 4X4 TQFN) TOP VIEW
GSO GND GS1 INR NC
Pin Descriptions
PIN 3, 6, 12 4, 9, 20 11 17
SPKSPK+ VDD GND HpR 1 2 3 4 5 6 VDD 7 HpL 8 HD 9 GND 10 REF 15 HO 14 SD 13 NC 12 VDD 11 INL
NAME VDD GND INL INR HpR HpL SPK+ SPKSD HD
FUNCTION System Power Supply Ground Connection Left Channel Audio Input 1 Right Channel Audio Input 1 Headphone Right Ouput Headphone Left Ouput Positive Speaker Output Negative Speaker Output Shutdown, High to disable amplifiers, Low for normal operation. Headphone Detection, Internally pulled up to VDD, Low in Mono Mode, High in Headphone Mode if HO = Low Headphone Override, High in Mono Mode, Low in Headphone Mode if HD = High Gain Select Common-mode Bias Voltage, By-pass with a 1F capacitor to GND. No Connect
20
19
18
17
16
5 7 2 1 14 8
15
HO GS_ REF NC
Ordering Information
PART NUMBER PART MARKING TEMP. RANGE (C) PACKAGE PKG. DWG. #
16, 18 10 13, 19
ISL54004IRTZ* 540 04IRTZ -40 to +85 20 Ld 4x4 TQFN L20.4x4A (Note) Tape and Reel (Pb-free) *Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
ISL54004 Truth Table
SD GS1 GS0 HD HO 1 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 0 0 0 1 1 1 1 1 1 X 0 0 0 1 1 1 0 0 0 1 1 1 X 0 1 1 0 1 1 0 1 1 0 1 1 X X 0 1 X 0 1 X 0 1 X 0 1 SPK+/SPKDisabled INR + INL INR + INL 1.2 x (INR + INL) 1.2 x (INR + INL) 2 x (INR + INL) 2 x (INR + INL) 4 x (INR + INL) 4 x (INR + INL) HpR HpL Disabled Disabled INR INL -
1.2 x INR 1.2 x INL 2 x INR 4 x INR 2 x INL 4 x INL -
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FN6513.2 October 30, 2007
ISL54004
Absolute Maximum Ratings
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V Input Voltages InR, InL, SD, HD, HO, GSO, GS1. . . . . . . -0.3V to (VDD + 0.3V) Output Voltages SPK+, SPK-, HpL, HpR . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V) Continuous Current (VDD, SPK_, Hp_, GND) . . . . . . . . . . . 750mA ESD Rating Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >2kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >200kV Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >1kV
Thermal Information
Thermal Resistance (Typical, Note 1, 2) JA (C/W) JC (C/W) 20 Ld 4x4 TQFN Package . . . . . . . . . . 45 6.5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTE: 1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 5V Supply
Test Conditions: VDD = +5V, GND = 0V, VINH = 2.4V, VINL = 0.8V, SD = GSO = GS1 = VINL, CREF = 1F, RL is terminated between SPK+ and SPK- for BTL driver and between Hp_ and GND for SE drivers, Unless Otherwise Specified (Note 3). TEST CONDITIONS TEMP MIN (C) (Notes 4, 5) TYP MAX (Notes 4, 5) UNITS
PARAMETER GENERAL Power Supply Range, VDD Quiescent Supply Current, IDD
Full HO = VINL or VINH, HD = VINL, RL = None, Inputs AC coupled to GND (0.1F) SD = VINH, HO = VINL or VINH, HD = VINL, RL = 8 (BTL) and RL = 32 (SE), Inputs AC coupled to GND (0.1F) INS = 0V or VDD INS = MIX = 0V or VDD 25 Full 25 Full 25 25 25 Full Input referred minimum gain GS0 = GS1 = VINL, RL = 32 Input referred maximum gain GS0 = GS1 = VINH, RL = 32 Input referred minimum gain GS0 = GS1 = VINL, RL = 8 Input referred maximum gain GS0 = GS1 = VINH, RL = 8 SE Amplifiers HD = VINH HO = VINL 25 25 25 25
2.7 -0.4 11.4 5.2 17.2
4.6 5.5 28 31 100 150 10 1 0 12 6 18
5.5 12 50 0.6 12.6 6.6 18.6
V mA mA mA mA k C C ms dB dB dB dB
Shutdown Supply Current, ISD
Input Resistance, RIN Thermal Shutdown, TSD Thermal Shutdown Hysteresis SD to Full Operation, tSD(ON) Gain Selection Range
BTL Amplifier HD = VINH HO = VINH
BTL AMPLIFIER DRIVER, HD = VINH, HO = VINH, UNLESS OTHERWISE SPECIFIED Output Offset Voltage, VOS Measured between SPK+ and SPK-, Inputs AC coupled to GND (0.1F) FRIPPLE = 217Hz FRIPPLE = 1kHz 25 Full 25 25 25 25 38 49 49 47 941 1.23 mV mV dB dB mW W
Power Supply Rejection Ratio, PSRR VRIPPLE = 200MVP-P, HD = VINL, RL = 8, Inputs AC coupled to GND (0.1F) Output Power, POUT RL = 8, THD+N = 1%, f = 1kHz
RL = 8, THD+N = 10%, f = 1kHz
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ISL54004
Electrical Specifications - 5V Supply
Test Conditions: VDD = +5V, GND = 0V, VINH = 2.4V, VINL = 0.8V, SD = GSO = GS1 = VINL, CREF = 1F, RL is terminated between SPK+ and SPK- for BTL driver and between Hp_ and GND for SE drivers, Unless Otherwise Specified (Note 3). (Continued) TEST CONDITIONS RL = 8, POUT = 800mW, f = 1kHz RL = 8, POUT = 800mW, f = 20Hz to 20kHz RL = 8, VSIGNAL = 5VP-P, f = 1kHz RL = 8, POUT = 900mW, f = 1kHz A - Weight filter, BW = 22Hz to 22kHz RL = 8, POUT = 800mW, f = 1kHz, Signal coupled from the input of active amplifier to the output of an adjacent amplifier with its input AC coupled to GND. SD = VDD, POUT = 800mW, f = 10kHz, Signal coupled from input to output of a disabled amplifier. TEMP MIN (C) (Notes 4, 5) 25 25 25 25 25 25 7.2 TYP 0.4 0.7 7.7 85 140 80 MAX (Notes 4, 5) UNITS % % VP-P dB mVRMS dB
PARAMETER Total Harmonic Distortion + Noise, THD+N Max Output Voltage Swing, VOUT Signal to Noise Ratio, SNR Output Noise, NOUT Crosstalk RCH to LCH, LCH to RCH Off-Isolation
25
-
130
-
dB
SINGLE ENDED AMPLIFIER DRIVERS, HD = VINH, HO = VINL, UNLESS OTHERWISE SPECIFIED Power Supply Rejection Ratio, PSRR VRIPPLE = 200MVP-P, HD = 0V, RL = 32, Input AC coupled to GND (0.1F) Output Power, POUT FRIPPLE = 217Hz FRIPPLE = 1kHz 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 25 3.6 48 47 170 94 215 116 0.07 0.09 0.3 0.4 4.7 75 120 83 0.2 1.3 dB dB mW mW mW mW % % % % VP-P dB dB dB dB
RL = 16, THD+N = 1%, f = 1kHz RL = 32, THD+N = 1%, f = 1kHz RL = 16, THD+N = 10%, f = 1kHz RL = 32, THD+N = 10%, f = 1kHz
Total Harmonic Distortion + Noise, THD+N
RL = 32, POUT = 15mW, f = 1kHz RL = 32, POUT = 15mW, f = 20Hz to 20kHz RL = 32, POUT = 50mW, f = 1kHz RL = 32, POUT = 50mW, f = 20Hz to 20kHz
Max Output Voltage Swing, VOUT Crosstalk RCH to LCH, LCH to RCH Off-Isolation Signal to Noise Ratio, SNR Channel Gain Matching RCH to LCH Channel Phase Matching RCH to LCH LOGIC INPUT Input Leakage Current, ISD, IHD, IGSx, IHO Input Leakage Current, ISD, IGSx, IHD, IHO VINH VINL
RL = 32, VSIGNAL = 5VP-P, f = 1kHz RL = 32, POUT = 15mW, f = 1kHz SD = VDD, RL = 32W, POUT = 15mW, f = 10kHz RL = 32, POUT = 50mW, f = 1kHz RL = 32, VINR = VINL = 1.3VRMS (Connect to the same source) RL = 32, VINR = VINL = 1.3VRMS (Connect to the same source)
VDD = 5V, SD = 0V, INS = 0V, GSx = 0V, HD = 0V, HO = 0V VDD = 5V, SD = VDD, INS = VDD, GSx = VDD, HD = VDD, HO = VDD
25 Full 25 Full Full Full
-3 -1 2.4 -
1.9 1.9 0.02 0.02 -
3 1 0.8
A A A A V V
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FN6513.2 October 30, 2007
ISL54004
Electrical Specifications - 3.6V Supply Test Conditions: VDD = +3.6V, GND = 0V, VINH = 1.4V. VINL = 0.4V, SD = GSO = GS1 = VINL,
CREF = 1F, RL is terminated between SPK+ and SPK- for BTL driver and between Hp_ and GND for SE drivers, Unless Otherwise Specified (Note 3) TEST CONDITIONS TEMP MIN (C) (Notes 4, 5) TYP
PARAMETER GENERAL Quiescent Supply Current, IDD
MAX (Notes 4, 5) UNITS
HO = VINL or VINH, HD = VINL, RL = None, Input AC coupled to GND (0.1F) SD = VINH, HO = VINL or VINH, HD = VINL, RL = 8 (BTL) and RL = 32 (SE), Input AC coupled to GND (0.1F)
25 Full 25 Full
-
2.7 3 13 15
12 50 -
mA mA mA mA
Shutdown Supply Current, ISD
BTL AMPLIFIER DRIVER, HD = VINH, HO = VINH, UNLESS OTHERWISE SPECIFIED Output Offset Voltage, VOS Measured between SPK+ and SPK-, Input AC coupled to GND (0.1F) FRIPPLE = 217Hz FRIPPLE = 1kHz 25 Full 25 25 25 25 25 25 25 25 40 49 47 310 528 0.4 0.4 5.8 mV mV dB dB mW mW % % VP-P
Power Supply Rejection Ratio, PSRR VRIPPLE = 200mVP-P HD = 0V, RL = 8, Input AC coupled to GND (0.1F) Output Power, POUT RL = 8, THD+N = 1%, f = 1kHz RL = 8, THD+N =10%, f = 1kHz Total Harmonic Distortion + Noise, THD+N Max Output Voltage Swing, VOUT
RL = 8, POUT = 200mW, f = 1kHz RL = 8, POUT = 200mW, f = 20Hz to 20kHz RL = 8, VSIGNAL = 3.6VP-P, f = 1kHz
SINGLE ENDED AMPLIFIER DRIVERS, HD = VINH, HO = VINL, UNLESS OTHERWISE SPECIFIED Power Supply Rejection Ratio, PSRR VRIPPLE = 200MVP-P, HD = 0V, RL = 32, Input AC coupled to GND (0.1F) Output Power, POUT RL = 16, THD+N =1%, f = 1kHz RL = 32, THD+N =1%, f = 1kHz RL = 16, THD+N = 10%, f = 1kHz RL = 32, THD+N = 10%, f =1kHz Total Harmonic Distortion + Noise, THD+N Max Output Voltage Swing, VOUT LOGIC INPUT Input Leakage Current, ISD, IGSx, IHD, IHO Input Leakage Current, ISD, IGSx, IHD, IHO VINH VINL NOTES: 3. VIN = input voltage to perform proper function. 4. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 5. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested VDD = 3.6V, SD = 0V, GSx = 0V, HD = 0V , HO = 0V, 25 Full VDD = 3.6V, SD = VDD, GSx = VDD, HD = VDD, HO = VDD 25 Full Full Full 1.4 1.9 1.9 0.02 0.02 0.4 A A A A V V RL = 32, POUT = 15mW, f = 1kHz RL = 32, POUT = 15mW, f = 20Hz to 20kHz RL = 32, VSIGNAL = 3.6VP-P, f = 1kHz FRIPPLE = 217Hz FRIPPLE = 1kHz 25 25 25 25 25 25 25 25 25 48 47 80 47 107 58 0.15 0.15 3.2 dB dB mW mW mW mW % % VP-P
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FN6513.2 October 30, 2007
ISL54004 ISL54004 Typical Application Circuit and Block Diagram
0.1F VDD 0.22F RIGHT AUDIO INR SPK+ BTL SPK100k GAIN 0.22F LEFT AUDIO INL ROUTER/ SWITCHER SE HpR HD SE HpL HEADPHONE JACK VDD 10k
CLICK AND POP
THERMAL PROTECTION
BIAS
REF SD HO MICRO CONTROLLER GSO GS1 GND LOGIC CONTROL
CREF 1F
Detailed Description
The Intersil ISL54004 device is an integrated audio power amplifier system designed to provide quality audio, while requiring minimal external components. Low 0.4% THD+N ensures clean, low distortion amplification of the audio signals. It is designed to operate from a single +2.7V to +5V power supply. It is offered in a 20 Ld 4x4 TQFN package. Targeted applications include battery powered equipment such as cell-phones, MP3 players, and games/toys. The ISL54004 part contains one class AB BTL type power amplifier for driving an 8 mono speaker and two class AB single-ended (SE) type amplifiers for driving 16 or 32 headphones. The BTL when using a 5V supply is capable of delivering 800mW (typ) with 0.4% THD+N and 941mW (typ) with 1% THD+N of continuous average power into a stereo 8 BTL speaker load. When the speaker load is connected across the positive and negative terminals of the BTL driver the voltage is doubled across the load and the power is quadrupled. Each SE amplifier when using a 5V supply is capable of delivering 15mW (typ) with 0.07% THD+N and 50mW (typ) with 0.3% THD+N of continuous average power into a 32 headphone speaker. When in Mono Mode (BTL driver active) the part automatically mixes the left and right audio inputs and sends the combined
signal to the BTL driver. In Headphone Mode the right channel input is sent to the right headphone speaker and the left channel is sent to the left headphone speaker. The ISL54004 features headphone sense input circuitry that detects when a headphone jack has been inserted and automatically switches the audio inputs from the mono BTL output driver to the headphone drivers. It also has a logic control pin (HO) that can override the sense input circuitry. The ISL54004 has a four-level programmable gain stage to boost the audio signal. The part requires no external gain setting resistors. When GSO = GS1 = Low a driver will have a gain of 1V/V (0dB). When GSO = High, GS1 = Low a driver will have a gain of 1.2V/V (1.5dB). When GSO = Low, GS1 = High a driver will have a gain of 2V/V (6dB). When GSO = High, GS1 = High a driver will have a gain of 4V/V (12dB). When the speaker is connected across the SPK+ terminal and SPK- terminal of the mono BTL driver you get an additional gain of 2V/V (6dB) due to the BTL configuration. The overall gain will be 2 times the values discussed above. For example with GS1 = GS0 = High the overall gain will be 2 x 4 = 8V/V (18dB). The part features low power shutdown, thermal overload protection and click and pop suppression. The click and pop circuitry prevents click and pops at the speakers when transitioning in and out of shutdown.
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FN6513.2 October 30, 2007
ISL54004
The "Typical Application Circuit and Block Diagram" for this device is provided on page 6. The "Truth Table" for the device is provided on page 2. The audio signal at the output of each SE driver is biased at VDD/2 and unlike the BTL driver that cancels this offset due to its differential connection, a capacitor is required at the output of each SE drivers to remove this DC voltage from the headphone load. This coupling capacitor along with the resistance of the speaker load creates a high pass filter that sets the amplifier's lower bandpass frequency limit. The value of this AC coupling capacitor depends on the low frequency range required for the application. The formula required to calculate the capacitor value is shown in Equation 2:
1 C ------------------------------------------------------------[ ( 6.28 ) ( f ) ( Rspeaker ) ] (EQ. 2)
DC Bias Voltage
The ISL54004 has internal DC bias circuitry which DC offsets the incoming audio signal at VDD/2. When using a 5V supply, the DC offset will be 2.5V. When using a 3.6V supply the DC offset will be 1.8V. Since the signal gets biased internally at VDD/2 the audio signals need to be AC coupled to the inputs of the device. The value of the AC coupling capacitor depends on the low frequency range required for the application. A capacitor of 0.22F will pass a signal as low as 7.2Hz. The formula required to calculate the capacitor value is shown in Equation 1:
1 C ---------------------------------------------[ ( 6.28 ) ( f ) ( 100k ) ] (EQ. 1)
For an application driving a 32 headphone with a lower frequency requirement of 150Hz the required capacitor value is shown in Equation 3:
1 C ----------------------------------------------- = 33F [ ( 6.28 ) ( 150 ) ( 32 ) ] (EQ. 3)
The 100k is the impedance looking into the input of the ISL54004 device.
Use the closest standard value.
BTL Speaker Amplifier
The ISL54004 contains one bridge-tied load (BTL) amplifier designed to drive an 8 speaker load differentially. The output to the BTL amplifier are SPK+ and SPK-. The speaker load gets connected across these terminals. A single BTL driver consists of an inverting and non-inverting power op amps. The AC signal out of each op amp are equal in magnitude but 180 out-of-phase, so the AC signal at SPK+ and SPK- have the same amplitude but are 180 out-of-phase. Driving the load differentially using a BTL configuration doubles the output voltage across the speaker load and quadruples the power to the load. In effect you get a gain of two due to this configuration at the load as compared to driving the load with a single-ended amplifier with its load connected between a single amplifier's output and GND. The outputs of the BTL are biased at VDD/2. When the load gets connected across the + and - terminal of the BTL the mid supply DC bias voltage at each output gets cancelled out eliminating the need for large bulky output coupling capacitors.
Headphone Sense Function
With a logic "1" at the HP control pin while the HO control pin is low will activate the headphone drivers and disable the BTL driver. The "ISL54004 Typical Application Circuit and Block Diagram" on page 6 shows the implementation of the headphone control function using a common headphone jack. The HP pin gets connected to the mechanical wiper blade of the headphone jack. Two external resistors are required for proper operation. A 100k pull-up resistor from the HP pin to VDD and a 10k pull-down resistor from the jack's audio signal pin to GND of the jack signal pin to which the wiper is connected. See "ISL54004 Typical Application Circuit and Block Diagram" on page 6. When no headphone plug is inserted into the jack the voltage at the HP pin gets set at a low voltage level due to the 10k resistor and 100k resistor divider network connection to VDD. When a headphone is inserted into the jack the 10k resistor gets disconnected from the HP control pin and the HP pin gets pulled up to VDD. Since the HP pin is now high the headphone drivers are activated. A microprocessor or a switch can be used to drive the HP pin rather than using the headphone jack contact pin. Note: With a logic "1" at the HO pin the BTL driver remains active regardless of the voltage level at the HD pin. This allows a headphone to be plugged into the headphone jack without activating the HP drivers. Music will continue to play through the internal 8 speaker rather than the headphones.
Headphone (Single-Ended) Amplifiers
The ISL54004 contains two single-ended (SE) headphone amplifiers for driving the left and right channels of a 32 or 16 headphone speakers. One SE amplifier drives the right speaker of the headphone and other SE amplifier drives the left speaker of the headphone. The speaker load gets connected between the output of the amplifier and ground.
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FN6513.2 October 30, 2007
ISL54004 Low Power Shutdown
With a logic "1" at the SD control pin the device enters the low power shutdown state. When in shutdown the BTL and headphone amplifiers go into an high impedance state and IDD supply current is reduced to 26A (typ). In shutdown mode before the amplifiers enter the high impedance/low current drive state, the bias voltage of VDD/2 remains connected at the output of the amplifiers through a 100k resistor. This resistor is not present during active operation of the drivers but gets switched in when the SD pin goes high. It gets removed when the SD pin goes low. Leaving the DC bias voltage connected through a 100k resistor while going into and out of shutdown reduces the transient at the speakers to a small level preventing clicking or popping in the speakers. Note: When the SD pin is High it overrides all other logic pins. large copper pad and multiple vias to the GND plane. The vias should be plugged and tented with plating and solder mask to ensure good thermal conductivity. Best thermal performance is achieved with the largest practical copper ground plane area.
PCB Layout Considerations and Power Supply Bypassing
To maintain the highest load dissipation and widest output voltage swing the power supply PCB traces and the traces that connect the output of the drivers to the speaker loads should be made as wide as possible to minimize losses due to parasitic trace resistance. Proper supply bypassing is necessary for high power supply rejection and low noise performance. A filter network consisting of a 10F capacitor in parallel with a 0.1F capacitor is recommended at the voltage regulator that is providing the power to the ISL54004 IC. Local bypass capacitors of 0.1F should be put at each VDD pin of the ISL54004 device. They should be located as close as possible to the pin, keeping the length of leads and traces as short as possible. A 1F capacitor from the REF pin (pin 10) to GND is needed for optimum PSRR and internal bias voltage stability.
QFN Die Attach Paddle Considerations
The QFN package features an exposed thermal pad on its underside. This pad lowers the package's thermal resistance by providing a direct heat conduction path from the die to the PCB. Connect the exposed thermal pad to GND by using a
Typical Performance Curves TA = +25C, Unless Otherwise Specified
1.0 0.9 0.8 0.7 0.6 0.5 THD+N (%) 0.4 0.3 VDD = 5V BTL RL = 8 PO = 800mW THD+N (%) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 VDD = 3.6V BTL RL = 8 PO = 200mW
0.2
0.2
0.1 20
50
100
200
500
1k
2k
5k
10k
20k
0.1 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 1. THD+N vs FREQUENCY
FIGURE 2. THD+N vs FREQUENCY
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FN6513.2 October 30, 2007
ISL54004 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
10.0 5.00 2.00 1.00 THD+N (%) 0.50 0.20 0.10 0.05 0.02 0.01 10m 20m 50m 100m 200m OUTPUT POWER (W) 500m 1 VDD = 5V BTL RL = 8 f = 1kHz THD+N (%) 10.0 5.00 2.00 1.00 0.50 0.20 0.10 0.05 0.02 0.01 10m 20m 40m 70m 100m OUTPUT POWER (W) 200m 600m VDD = 3.6V BTL RL = 8 f = 1kHz
FIGURE 3. THD+N vs OUTPUT POWER
0.20 VDD = 5V SE RL = 32 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.02 PO = 15mW 0.10 THD+N (%) 0.40 0.30 0.20
FIGURE 4. THD+N vs OUTPUT POWER
VDD = 3.6V SE RL = 32 PO = 15mW
THD+N (%)
0.05 0.04 0.03
0.01
20
50
100
200
500
1k
2k
5k
10k 20k
0.01
20
50
100
200
500
1k
2k
5k
10k 20k
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 5. THD+N vs FREQUENCY
1.0 0.9 0.8 0.7 0.6 0.5 THD+N (%) THD+N (%) 0.4 0.3 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3
FIGURE 6. THD+N vs FREQUENCY
VDD = 5V SE RL = 32 PO = 50mW
VDD = 5V SE RL = 16 PO = 50mW
0.2
0.2
0.1 20 50 100 200 500 1k 2k FREQUENCY (Hz) 5k 10k 20k
0.1 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz)
FIGURE 7. THD+N vs FREQUENCY
FIGURE 8. THD+N vs FREQUENCY
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FN6513.2 October 30, 2007
ISL54004 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
1.00 VDD = 3.6V SE RL = 32 PO = 30mW THD+N (%) 1.00 0.50 VDD = 3.6V SE RL = 16 PO = 60mW 0.20 0.10 0.05
0.50
0.20 THD+N (%)
0.10
0.05
0.02
0.02 0.01 50 100 200 500 1k 2k FREQUENCY (Hz) 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz)
0.01 20
FIGURE 9. THD+N vs FREQUENCY
0.20 VDD = 5V SE RL = 32 f = 1kHz THD+N (%) 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03
FIGURE 10. THD+N vs FREQUENCY
THD+N (%)
0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03
VDD = 5V SE RL = 16 f = 1kHz
0.02 0.02
0.01 2 3 4 5 6 7 8 9 10 OUTPUT POWER (mW) 20
0.01 2 3 4 5 6 7 8 9 10 20 OUTPUT POWER (mW)
FIGURE 11. THD+N vs OUTPUT POWER
FIGURE 12. THD+N vs OUTPUT POWER
0.30 0.20 0.10 0.09 0.08 THD+N (%) 0.07 0.06 0.05 0.04 0.03 0.02 0.01 2 3 4 5 6 7 8 9 10 20 OUTPUT POWER (mW) THD+N (%) VDD = 3.6V SE RL = 32 f = 1kHz
0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 VDD = 3.6V SE RL = 16 f = 1kHz
0.02
0.01
2
3
4
5
6
7 8 9 10
20
OUTPUT POWER (mW)
FIGURE 13. THD+N vs OUTPUT POWER
FIGURE 14. THD+N vs OUTPUT POWER
10
FN6513.2 October 30, 2007
ISL54004 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
10.0 VDD = 5V 5.00 SE RL = 32 2.00 f = 1kHz THD+N (%) THD+N (%) 1.00 0.50 0.20 0.10 0.05 0.02 0.01 10m 20m 30m 40m 50m 70m 100m 10.0 5.00 2.00 1.00 0.50 0.20 0.10 0.05 0.02 0.01 10m 20m 30m 50m 70m 100m 200m VDD = 5V SE
RL = 16 f = 1kHz
OUTPUT POWER (W)
OUTPUT POWER (W)
FIGURE 15. THD+N vs OUTPUT POWER
FIGURE 16. THD+N vs OUTPUT POWER
10.0 5.00 2.00 1.00 THD+N (%) 0.50 0.20 0.10 0.05 0.02 0.01 10m 12m 15m 20m 25m 35m OUTPUT POWER (W) 45m 55m THD+N (%) VDD = 3.6V SE RL = 32 f = 1kHz
10.0 5.00 2.00 1.00 0.50 0.20 0.10 0.05 0.02 0.01 10m 20m 30m 40m 50m OUTPUT POWER (W) 70m 100m VDD = 3.6V SE RL = 16 f = 1kHz
FIGURE 17. THD+N vs OUTPUT POWER
FIGURE 18. THD+N vs OUTPUT POWER
-50 -55 -60 -65 CROSSTALK (dB) -70 -75 -80 -85 -90 -95 -100 -105 -110 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) INxL TO HPR INxR TO HPL OFF ISOLATION (dB) VDD = 5V PO = 15mW
-80 -85 -90 -95 -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 -155 -160 20 50 100 200 500 1k
HPR AND HPL
BTL
2k
5k
10k 20k
FREQUENCY (Hz)
FIGURE 19. CROSSTALK vs FREQUENCY
FIGURE 20. OFF ISOLATION vs FREQUENCY
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FN6513.2 October 30, 2007
ISL54004 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
-20 -22 -24 -26 -28 -30 -32 -34 -36 -38 -40 -42 -44 -46 -48 -50 -52 -54 -56 -58 -60 -62 -64 -66 -68 -70 VDD = 5V BTL VRIPPLE = 200MVP-P -20 VDD = 5V -25 SE -30 VRIPPLE = 200mVP-P -35 -40 -45 PSRR (dB) -50 -55 -60 -65 -70 -75 -80 -85 10 20 50 100 200 500 1k 2k 5k 10k 20k -90 10 20 50 100 200 500 1k 2k 5k 10k 20k FREQUENCY (Hz) HPL
PSRR (dB)
HPR
FREQUENCY (Hz)
FIGURE 21. PSRR vs FREQUENCY
FIGURE 22. PSRR vs FREQUENCY
700 VDD = 5V BTL 600 RL = 8 POWER DISSIPATION (mW) POWER DISSIPATION (mW) 500 400 300 200 100 0 0
400 VDD = 3.6V 350 300 250 200 150 100 50 0 250 500 POUT (mW) 750 1000 0 100 200 300 POUT (mW) 400 500 BTL RL = 8
FIGURE 23. POWER DISSIPATION vs OUTPUT POWER
FIGURE 24. POWER DISSIPATION vs OUTPUT POWER
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP): GND PROCESS: Submicron CMOS
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FN6513.2 October 30, 2007
ISL54004 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead FramePlastic Package (TMLFP)
L20.4x4A
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WGGD-1 ISSUE I) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P 0.20 0.35 1.95 1.95 0.18 MIN 0.70 NOMINAL 0.75 0.02 0.55 0.20 REF 0.25 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.50 BSC 0.60 20 5 5 0.60 12 0.75 2.25 2.25 0.30 MAX 0.80 0.05 0.80 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 2 3 3 9 9 Rev. 0 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN6513.2 October 30, 2007

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